From patchwork Wed Jul 21 08:39:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 12390317 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7B463C07E9B for ; Wed, 21 Jul 2021 08:39:39 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1339261221 for ; Wed, 21 Jul 2021 08:39:39 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1339261221 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=o8yMHDD5s7irtc/UzNb1sBqoTc4p6Q/jq7WJGfzmpnE=; b=gp6Eiv6traE2ZK Rga9PcKSk9CgAzli0sKu0lrAqZmbMPZpBjZV7DD6ATYcZlzt88PuJ3f/6mScBUk/yRzZfjw2jSy/V QoJpAmhKMZTfJqouurY2en9IXKRKdaqHrJA/+USAWaB9+r6d1es225zRzZFucuh8Xw4U3EzUUNiMr 7mXnB3/1akIcGEH5Oz5wsCGggO1n9uZiBH/aFno4AhEXDKVsSNQ9rHBx7I7u6+izeZaSvUsohn3ld OPjt8oy6m4g3DsO27OOHUfde7z8Pd7WJQrURbwgfBlZukGNgnvRBbkWS8dWARys9NxFdrO/9mS1nI TEib1pTCLsJk9DdMr4/g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1m67lS-00EwL4-J2; Wed, 21 Jul 2021 08:39:38 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1m67lA-00EwD3-Ku for linux-phy@lists.infradead.org; Wed, 21 Jul 2021 08:39:22 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id 7BC6D6120D; Wed, 21 Jul 2021 08:39:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1626856759; bh=eT62F16m4fmnu9+ZtQ5I8OSRvrVJgO8LuBY471amLVk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Br++L+BMZpXlfIiTwaiiu5mB4JjjUqyv6G64sI0V1bbQyS9c+PeZ0m7ZhzDuddfcf w3au81XBOfLEPCPavw40MZC1PdGN922M25MJaMAvcw4w/3WoRxzPh0iVbbN4oAMebN bvwpBsPghVG1CtVYDrwfuNXJdeNwOyMCvQEmEdObHqx07TDW72HWe7vILxB9qrARCm d6P+AS3tsD3qBsyu1mfKn/vihaIU2hB/tQMVLU4htAVv3sVz4tbOP7uSrbnxciigJ6 FUaKlhcQIweW7Aay5dm6UnwsNqO0BMHjNTozFZIFvwCvilYRnKBRBy7BEu4acJrYZx dzQzuwCB6hyKQ== Received: by mail.kernel.org with local (Exim 4.94.2) (envelope-from ) id 1m67l5-0022de-GT; Wed, 21 Jul 2021 10:39:15 +0200 From: Mauro Carvalho Chehab To: Vinod Koul , Bjorn Helgaas , Rob Herring Cc: linuxarm@huawei.com, mauro.chehab@huawei.com, Mauro Carvalho Chehab , Kishon Vijay Abraham I , Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH v7 06/10] dt-bindings: phy: Add bindings for HiKey 970 PCIe PHY Date: Wed, 21 Jul 2021 10:39:08 +0200 Message-Id: <946f2426bc542638240980931eae924c57f2ba27.1626855713.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210721_013920_758412_106AAC18 X-CRM114-Status: GOOD ( 11.46 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org Document the bindings for HiKey 970 (hi3670) PCIe PHY interface, supported via the pcie-kirin driver. Signed-off-by: Mauro Carvalho Chehab Signed-off-by: Mauro Carvalho Chehab --- .../phy/hisilicon,phy-hi3670-pcie.yaml | 95 +++++++++++++++++++ 1 file changed, 95 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml diff --git a/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml b/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml new file mode 100644 index 000000000000..a5ea13332cac --- /dev/null +++ b/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml @@ -0,0 +1,95 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/hisilicon,phy-hi3670-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: HiSilicon Kirin970 PCIe PHY + +maintainers: + - Mauro Carvalho Chehab + +description: |+ + Bindings for PCIe PHY on HiSilicon Kirin 970. + +properties: + compatible: + const: hisilicon,hi970-pcie-phy + + "#phy-cells": + const: 0 + + reg: + maxItems: 1 + description: PHY Control registers + + phy-supply: + description: The PCIe PHY power supply + + clocks: + items: + - description: PCIe PHY clock + - description: PCIe AUX clock + - description: PCIe APB PHY clock + - description: PCIe APB SYS clock + - description: PCIe ACLK clock + + clock-names: + items: + - const: phy_ref + - const: aux + - const: apb_phy + - const: apb_sys + - const: aclk + + reset-gpios: + description: PCI PERST reset GPIOs + maxItems: 4 + + clkreq-gpios: + description: Clock request GPIOs + maxItems: 3 + + hisilicon,eye-diagram-param: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: Eye diagram for phy. + +required: + - "#phy-cells" + - compatible + - reg + - clocks + - clock-names + - reset-gpios + - clkreq-gpios + - hisilicon,eye-diagram-param + - phy-supply + +additionalProperties: false + +examples: + - | + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + pcie_phy: pcie-phy@fc000000 { + compatible = "hisilicon,hi970-pcie-phy"; + reg = <0x0 0xfc000000 0x0 0x80000>; + #phy-cells = <0>; + phy-supply = <&ldo33>; + clocks = <&crg_ctrl HI3670_CLK_GATE_PCIEPHY_REF>, + <&crg_ctrl HI3670_CLK_GATE_PCIEAUX>, + <&crg_ctrl HI3670_PCLK_GATE_PCIE_PHY>, + <&crg_ctrl HI3670_PCLK_GATE_PCIE_SYS>, + <&crg_ctrl HI3670_ACLK_GATE_PCIE>; + clock-names = "phy_ref", "aux", + "apb_phy", "apb_sys", "aclk"; + reset-gpios = <&gpio7 0 0 >, <&gpio25 2 0 >, + <&gpio3 1 0 >, <&gpio27 4 0 >; + clkreq-gpios = <&gpio20 6 0 >, <&gpio27 3 0 >, <&gpio17 0 0 >; + hisilicon,eye-diagram-param = <0xFFFFFFFF 0xFFFFFFFF + 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF>; + }; + }; From patchwork Wed Jul 21 08:39:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 12390323 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 09DF4C07E9B for ; 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h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=MQX34jk8AS9pIpgJJehA0rneWaOuCbDWYp6YkPcML+uu8m3EZ384iEAFf9At4LLsP dVliD+jpXsK1SL1ZXYMX7BJcMRnfx4k42dWmD9klADMoQwPB8VMenzZ6O9iOpVJnGZ /Vv3Ud2mrKXvxyHcARiv28EiqLkRvkG2X4zXHdZoE2ca2Ss1rUdkNcqBuhaAybshyO 6x9P3m1VJwVlwuU2pUk1fFY86D46xp/ad3Utuw6lkYbF+DfwDPou2BW8XELJjbrq2a yxUHaqEfPzGofUjg/9X10WYLyevbLSRkX+53L66P4Gyf7bNGQR6FH45nuLA3s4Vks7 vIMm6BIuRZaKw== Received: by mail.kernel.org with local (Exim 4.94.2) (envelope-from ) id 1m67l5-0022di-Iu; Wed, 21 Jul 2021 10:39:15 +0200 From: Mauro Carvalho Chehab To: Vinod Koul , Bjorn Helgaas , Rob Herring Cc: linuxarm@huawei.com, mauro.chehab@huawei.com, Mauro Carvalho Chehab , =?utf-8?q?Krzysztof_Wilc?= =?utf-8?q?zy=C5=84ski?= , Binghui Wang , Greg Kroah-Hartman , Kishon Vijay Abraham I , Lorenzo Pieralisi , Manivannan Sadhasivam , Xiaowei Song , linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH v7 07/10] phy: HiSilicon: Add driver for Kirin 970 PCIe PHY Date: Wed, 21 Jul 2021 10:39:09 +0200 Message-Id: <5234b208155ce7696df1c682f04b0b770ebf3970.1626855713.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210721_013921_055176_91701CE8 X-CRM114-Status: GOOD ( 23.45 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org The Kirin 970 PHY is somewhat similar to the Kirin 960, but it does a lot more. Add the needed bits for PCIe to start working on HiKey 970 boards. Co-developed-by: Manivannan Sadhasivam Signed-off-by: Manivannan Sadhasivam Signed-off-by: Mauro Carvalho Chehab --- drivers/pci/controller/dwc/pcie-kirin.c | 4 + drivers/phy/hisilicon/Kconfig | 10 + drivers/phy/hisilicon/Makefile | 1 + drivers/phy/hisilicon/phy-hi3670-pcie.c | 898 ++++++++++++++++++++++++ 4 files changed, 913 insertions(+) create mode 100644 drivers/phy/hisilicon/phy-hi3670-pcie.c diff --git a/drivers/pci/controller/dwc/pcie-kirin.c b/drivers/pci/controller/dwc/pcie-kirin.c index a32f7f36461c..bfc0513f7b15 100644 --- a/drivers/pci/controller/dwc/pcie-kirin.c +++ b/drivers/pci/controller/dwc/pcie-kirin.c @@ -550,6 +550,10 @@ static const struct of_device_id kirin_pcie_match[] = { .compatible = "hisilicon,kirin960-pcie", .data = (void *)PCIE_KIRIN_INTERNAL_PHY }, + { + .compatible = "hisilicon,kirin970-pcie", + .data = (void *)PCIE_KIRIN_EXTERNAL_PHY + }, {}, }; diff --git a/drivers/phy/hisilicon/Kconfig b/drivers/phy/hisilicon/Kconfig index 4d008cfc279c..d3b92c288554 100644 --- a/drivers/phy/hisilicon/Kconfig +++ b/drivers/phy/hisilicon/Kconfig @@ -33,6 +33,16 @@ config PHY_HI3670_USB To compile this driver as a module, choose M here. +config PHY_HI3670_PCIE + tristate "hi3670 PCIe PHY support" + depends on (ARCH_HISI && ARM64) || COMPILE_TEST + select GENERIC_PHY + select MFD_SYSCON + help + Enable this to support the HiSilicon hi3670 PCIe PHY. + + To compile this driver as a module, choose M here. + config PHY_HISTB_COMBPHY tristate "HiSilicon STB SoCs COMBPHY support" depends on (ARCH_HISI && ARM64) || COMPILE_TEST diff --git a/drivers/phy/hisilicon/Makefile b/drivers/phy/hisilicon/Makefile index 51729868145b..4029d3813b1e 100644 --- a/drivers/phy/hisilicon/Makefile +++ b/drivers/phy/hisilicon/Makefile @@ -2,6 +2,7 @@ obj-$(CONFIG_PHY_HI6220_USB) += phy-hi6220-usb.o obj-$(CONFIG_PHY_HI3660_USB) += phy-hi3660-usb3.o obj-$(CONFIG_PHY_HI3670_USB) += phy-hi3670-usb3.o +obj-$(CONFIG_PHY_HI3670_PCIE) += phy-hi3670-pcie.o obj-$(CONFIG_PHY_HISTB_COMBPHY) += phy-histb-combphy.o obj-$(CONFIG_PHY_HISI_INNO_USB2) += phy-hisi-inno-usb2.o obj-$(CONFIG_PHY_HIX5HD2_SATA) += phy-hix5hd2-sata.o diff --git a/drivers/phy/hisilicon/phy-hi3670-pcie.c b/drivers/phy/hisilicon/phy-hi3670-pcie.c new file mode 100644 index 000000000000..0bc0203e9140 --- /dev/null +++ b/drivers/phy/hisilicon/phy-hi3670-pcie.c @@ -0,0 +1,898 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PCIe phy driver for Kirin 970 + * + * Copyright (C) 2017 HiSilicon Electronics Co., Ltd. + * https://www.huawei.com + * Copyright (C) 2021 Huawei Technologies Co., Ltd. + * https://www.huawei.com + * + * Authors: + * Mauro Carvalho Chehab + * Manivannan Sadhasivam + * + * Based on: + * https://lore.kernel.org/lkml/4c9d6581478aa966698758c0420933f5defab4dd.1612335031.git.mchehab+huawei@kernel.org/ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define AXI_CLK_FREQ 207500000 +#define REF_CLK_FREQ 100000000 + +/* PCIe CTRL registers */ +#define SOC_PCIECTRL_CTRL0_ADDR 0x000 +#define SOC_PCIECTRL_CTRL1_ADDR 0x004 +#define SOC_PCIECTRL_CTRL7_ADDR 0x01c +#define SOC_PCIECTRL_CTRL12_ADDR 0x030 +#define SOC_PCIECTRL_CTRL20_ADDR 0x050 +#define SOC_PCIECTRL_CTRL21_ADDR 0x054 +#define SOC_PCIECTRL_STATE0_ADDR 0x400 + +/* PCIe PHY registers */ +#define SOC_PCIEPHY_CTRL0_ADDR 0x000 +#define SOC_PCIEPHY_CTRL1_ADDR 0x004 +#define SOC_PCIEPHY_CTRL2_ADDR 0x008 +#define SOC_PCIEPHY_CTRL3_ADDR 0x00c +#define SOC_PCIEPHY_CTRL38_ADDR 0x0098 +#define SOC_PCIEPHY_STATE0_ADDR 0x400 + +#define PCIE_LINKUP_ENABLE (0x8020) +#define PCIE_ELBI_SLV_DBI_ENABLE (0x1 << 21) +#define PCIE_LTSSM_ENABLE_BIT (0x1 << 11) +#define PCIEPHY_RESET_BIT (0x1 << 17) +#define PCIEPHY_PIPE_LINE0_RESET_BIT (0x1 << 19) + +#define PORT_MSI_CTRL_ADDR 0x820 +#define PORT_MSI_CTRL_UPPER_ADDR 0x824 +#define PORT_MSI_CTRL_INT0_ENABLE 0x828 + +#define EYEPARAM_NOCFG 0xFFFFFFFF +#define RAWLANEN_DIG_PCS_XF_TX_OVRD_IN_1 0x3001 +#define SUP_DIG_LVL_OVRD_IN 0xf +#define LANEN_DIG_ASIC_TX_OVRD_IN_1 0x1002 +#define LANEN_DIG_ASIC_TX_OVRD_IN_2 0x1003 + +/* hi3670 pciephy register */ +#define SOC_PCIEPHY_MMC1PLL_CTRL1 0xc04 +#define SOC_PCIEPHY_MMC1PLL_CTRL16 0xC40 +#define SOC_PCIEPHY_MMC1PLL_CTRL17 0xC44 +#define SOC_PCIEPHY_MMC1PLL_CTRL20 0xC50 +#define SOC_PCIEPHY_MMC1PLL_CTRL21 0xC54 +#define SOC_PCIEPHY_MMC1PLL_STAT0 0xE00 + +#define CRGPERIPH_PEREN12 0x470 +#define CRGPERIPH_PERDIS12 0x474 +#define CRGPERIPH_PCIECTRL0 0x800 + +/* define ie,oe cfg */ +#define IO_IE_EN_HARD_BYPASS (0x1 << 27) +#define IO_OE_EN_HARD_BYPASS (0x1 << 11) +#define IO_HARD_CTRL_DEBOUNCE_BYPASS (0x1 << 10) +#define IO_OE_GT_MODE (0x2 << 7) +#define DEBOUNCE_WAITCFG_IN (0xf << 20) +#define DEBOUNCE_WAITCFG_OUT (0xf << 13) + +/* noc power domain */ +#define NOC_POWER_IDLEREQ_1 0x38c +#define NOC_POWER_IDLE_1 0x394 +#define NOC_PW_MASK 0x10000 +#define NOC_PW_SET_BIT 0x1 + +/* Number of GPIOs required by PHY */ +#define MAX_GPIO_RESETS 4 +#define MAX_GPIO_CLKREQ 3 +#define NUM_EYEPARAM 5 + +/* info located in sysctrl */ +#define SCTRL_PCIE_CMOS_OFFSET 0x60 +#define SCTRL_PCIE_CMOS_BIT 0x10 +#define SCTRL_PCIE_ISO_OFFSET 0x44 +#define SCTRL_PCIE_ISO_BIT 0x30 +#define SCTRL_PCIE_HPCLK_OFFSET 0x190 +#define SCTRL_PCIE_HPCLK_BIT 0x184000 +#define SCTRL_PCIE_OE_OFFSET 0x14a +#define PCIE_DEBOUNCE_PARAM 0xF0F400 +#define PCIE_OE_BYPASS (0x3 << 28) + +/* peri_crg ctrl */ +#define CRGCTRL_PCIE_ASSERT_OFFSET 0x88 +#define CRGCTRL_PCIE_ASSERT_BIT 0x8c000000 + +/* Time for delay */ +#define REF_2_PERST_MIN 20000 +#define REF_2_PERST_MAX 25000 +#define PERST_2_ACCESS_MIN 10000 +#define PERST_2_ACCESS_MAX 12000 +#define PIPE_CLK_WAIT_MIN 550 +#define PIPE_CLK_WAIT_MAX 600 +#define TIME_CMOS_MIN 100 +#define TIME_CMOS_MAX 105 +#define TIME_PHY_PD_MIN 10 +#define TIME_PHY_PD_MAX 11 + +struct hi3670_pcie_phy { + struct device *dev; + void __iomem *base; + struct regmap *apb; + struct regmap *crgctrl; + struct regmap *sysctrl; + struct regmap *pmctrl; + struct clk *apb_sys_clk; + struct clk *apb_phy_clk; + struct clk *phy_ref_clk; + struct clk *aclk; + struct clk *aux_clk; + int n_gpio_resets; + int n_gpio_clkreq; + int gpio_id_reset[MAX_GPIO_RESETS]; + const char *reset_names[MAX_GPIO_RESETS]; + int gpio_id_clkreq[MAX_GPIO_CLKREQ]; + const char *clkreq_names[MAX_GPIO_CLKREQ]; + u32 eye_param[NUM_EYEPARAM]; +}; + + +/* Registers in PCIePHY */ +static inline void hi3670_apb_phy_writel(struct hi3670_pcie_phy *phy, + u32 val, u32 reg) +{ + writel(val, phy->base + 0x40000 + reg); +} + +static inline u32 hi3670_apb_phy_readl(struct hi3670_pcie_phy *phy, u32 reg) +{ + return readl(phy->base + 0x40000 + reg); +} + +static inline void kirin_apb_natural_phy_writel(struct hi3670_pcie_phy *phy, + u32 val, u32 reg) +{ + writel(val, phy->base + reg * 4); +} + +static inline u32 kirin_apb_natural_phy_readl(struct hi3670_pcie_phy *phy, + u32 reg) +{ + return readl(phy->base + reg * 4); +} + +static void hi3670_pcie_phy_oe_enable(struct hi3670_pcie_phy *phy) +{ + u32 val; + + regmap_read(phy->sysctrl, SCTRL_PCIE_OE_OFFSET, &val); + val |= PCIE_DEBOUNCE_PARAM; + val &= ~PCIE_OE_BYPASS; + regmap_write(phy->sysctrl, SCTRL_PCIE_OE_OFFSET, val); +} + +static void hi3670_pcie_get_eyeparam(struct hi3670_pcie_phy *phy) +{ + struct device *dev = phy->dev; + struct device_node *np; + int ret, i; + + np = dev->of_node; + + ret = of_property_read_u32_array(np, "hisilicon,eye-diagram-param", + phy->eye_param, NUM_EYEPARAM); + if (!ret) + return; + + /* There's no optional eye_param property. Set array to default */ + for (i = 0; i < NUM_EYEPARAM; i++) + phy->eye_param[i] = EYEPARAM_NOCFG; +} + +static void hi3670_pcie_set_eyeparam(struct hi3670_pcie_phy *phy) +{ + u32 val; + + val = kirin_apb_natural_phy_readl(phy, RAWLANEN_DIG_PCS_XF_TX_OVRD_IN_1); + + if (phy->eye_param[1] != EYEPARAM_NOCFG) { + val &= (~0xf00); + val |= (phy->eye_param[1] << 8) | (0x1 << 12); + } + kirin_apb_natural_phy_writel(phy, val, RAWLANEN_DIG_PCS_XF_TX_OVRD_IN_1); + + val = kirin_apb_natural_phy_readl(phy, LANEN_DIG_ASIC_TX_OVRD_IN_2); + val &= (~0x1FBF); + if (phy->eye_param[2] != EYEPARAM_NOCFG) + val |= (phy->eye_param[2]<< 0) | (0x1 << 6); + + if (phy->eye_param[3] != EYEPARAM_NOCFG) + val |= (phy->eye_param[3] << 7) | (0x1 << 13); + + kirin_apb_natural_phy_writel(phy, val, LANEN_DIG_ASIC_TX_OVRD_IN_2); + + val = kirin_apb_natural_phy_readl(phy, SUP_DIG_LVL_OVRD_IN); + if (phy->eye_param[0] != EYEPARAM_NOCFG) { + val &= (~0x1C0); + val |= (phy->eye_param[0] << 6) | (0x1 << 9); + } + kirin_apb_natural_phy_writel(phy, val, SUP_DIG_LVL_OVRD_IN); + + val = kirin_apb_natural_phy_readl(phy, LANEN_DIG_ASIC_TX_OVRD_IN_1); + if (phy->eye_param[4] != EYEPARAM_NOCFG) { + val &= (~0x7E00); + val |= (phy->eye_param[4] << 9) | (0x1 << 15); + } + kirin_apb_natural_phy_writel(phy, val, LANEN_DIG_ASIC_TX_OVRD_IN_1); +} + +static int hi3670_pcie_gpio_request(struct hi3670_pcie_phy *phy, + struct device *dev) +{ + int ret, i; + + for (i = 0; i < phy->n_gpio_resets; i++) { + if (!gpio_is_valid(phy->gpio_id_reset[i])) { + dev_err(dev, "unable to get a valid %s gpio\n", + phy->reset_names[i]); + return -ENODEV; + } + + ret = devm_gpio_request(dev, phy->gpio_id_reset[i], + phy->reset_names[i]); + if (ret) + return ret; + } + + for (i = 0; i < phy->n_gpio_clkreq; i++) { + if (!gpio_is_valid(phy->gpio_id_clkreq[i])) { + dev_err(dev, "unable to get a valid %s gpio\n", + phy->clkreq_names[i]); + return -ENODEV; + } + + ret = devm_gpio_request(dev, phy->gpio_id_clkreq[i], + phy->clkreq_names[i]); + if (ret) + return ret; + } + + return ret; +} + +static void hi3670_pcie_natural_cfg(struct hi3670_pcie_phy *phy) +{ + u32 val; + + /* change 2p mem_ctrl */ + regmap_write(phy->apb, SOC_PCIECTRL_CTRL20_ADDR, 0x02605550); + + /* pull up sys_aux_pwr_det */ + regmap_read(phy->apb, SOC_PCIECTRL_CTRL7_ADDR, &val); + val |= (0x1 << 10); + regmap_write(phy->apb, SOC_PCIECTRL_CTRL7_ADDR, val); + + /* output, pull down */ + regmap_read(phy->apb, SOC_PCIECTRL_CTRL12_ADDR, &val); + val &= ~(0x3 << 2); + val |= (0x1 << 1); + val &= ~(0x1 << 0); + regmap_write(phy->apb, SOC_PCIECTRL_CTRL12_ADDR, val); + + /* Handle phy_reset and lane0_reset to HW */ + val = hi3670_apb_phy_readl(phy, SOC_PCIEPHY_CTRL1_ADDR); + val |= PCIEPHY_RESET_BIT; + val &= ~PCIEPHY_PIPE_LINE0_RESET_BIT; + hi3670_apb_phy_writel(phy, val, SOC_PCIEPHY_CTRL1_ADDR); + + /* fix chip bug: TxDetectRx fail */ + val = hi3670_apb_phy_readl(phy, SOC_PCIEPHY_CTRL38_ADDR); + val |= (0x1 << 2); + hi3670_apb_phy_writel(phy, val, SOC_PCIEPHY_CTRL38_ADDR); +} + +static void hi3670_pcie_pll_init(struct hi3670_pcie_phy *phy) +{ + u32 val; + + /* choose FNPLL */ + val = hi3670_apb_phy_readl(phy, SOC_PCIEPHY_MMC1PLL_CTRL1); + val |= (0x1 << 27); + hi3670_apb_phy_writel(phy, val, SOC_PCIEPHY_MMC1PLL_CTRL1); + + val = hi3670_apb_phy_readl(phy, SOC_PCIEPHY_MMC1PLL_CTRL16); + val &= 0xF000FFFF; + /* fnpll fbdiv = 0xD0 */ + val |= (0xd0 << 16); + hi3670_apb_phy_writel(phy, val, SOC_PCIEPHY_MMC1PLL_CTRL16); + + val = hi3670_apb_phy_readl(phy, SOC_PCIEPHY_MMC1PLL_CTRL17); + val &= 0xFF000000; + /* fnpll fracdiv = 0x555555 */ + val |= (0x555555 << 0); + hi3670_apb_phy_writel(phy, val, SOC_PCIEPHY_MMC1PLL_CTRL17); + + val = hi3670_apb_phy_readl(phy, SOC_PCIEPHY_MMC1PLL_CTRL20); + val &= 0xF5FF88FF; + /* fnpll dll_en = 0x1 */ + val |= (0x1 << 27); + /* fnpll postdiv1 = 0x5 */ + val |= (0x5 << 8); + /* fnpll postdiv2 = 0x4 */ + val |= (0x4 << 12); + /* fnpll pll_mode = 0x0 */ + val &= ~(0x1 << 25); + hi3670_apb_phy_writel(phy, val, SOC_PCIEPHY_MMC1PLL_CTRL20); + + hi3670_apb_phy_writel(phy, 0x20, SOC_PCIEPHY_MMC1PLL_CTRL21); +} + +static int hi3670_pcie_pll_ctrl(struct hi3670_pcie_phy *phy, bool enable) +{ + struct device *dev = phy->dev; + u32 val; + int time = 200; + + if (enable) { + /* pd = 0 */ + val = hi3670_apb_phy_readl(phy, SOC_PCIEPHY_MMC1PLL_CTRL16); + val &= ~(0x1 << 0); + hi3670_apb_phy_writel(phy, val, SOC_PCIEPHY_MMC1PLL_CTRL16); + + val = hi3670_apb_phy_readl(phy, SOC_PCIEPHY_MMC1PLL_STAT0); + + /* choose FNPLL */ + while (!(val & 0x10)) { + if (!time) { + dev_err(dev, "wait for pll_lock timeout\n"); + return -1; + } + time --; + udelay(1); + val = hi3670_apb_phy_readl(phy, SOC_PCIEPHY_MMC1PLL_STAT0); + } + + /* pciepll_bp = 0 */ + val = hi3670_apb_phy_readl(phy, SOC_PCIEPHY_MMC1PLL_CTRL20); + val &= ~(0x1 << 16); + hi3670_apb_phy_writel(phy, val, SOC_PCIEPHY_MMC1PLL_CTRL20); + + } else { + /* pd = 1 */ + val = hi3670_apb_phy_readl(phy, SOC_PCIEPHY_MMC1PLL_CTRL16); + val |= (0x1 << 0); + hi3670_apb_phy_writel(phy, val, SOC_PCIEPHY_MMC1PLL_CTRL16); + + /* pciepll_bp = 1 */ + val = hi3670_apb_phy_readl(phy, SOC_PCIEPHY_MMC1PLL_CTRL20); + val |= (0x1 << 16); + hi3670_apb_phy_writel(phy, val, SOC_PCIEPHY_MMC1PLL_CTRL20); + } + + return 0; +} + +static void hi3670_pcie_hp_debounce_gt(struct hi3670_pcie_phy *phy, bool open) +{ + if (open) + /* gt_clk_pcie_hp/gt_clk_pcie_debounce open */ + regmap_write(phy->crgctrl, CRGPERIPH_PEREN12, 0x9000); + else + /* gt_clk_pcie_hp/gt_clk_pcie_debounce close */ + regmap_write(phy->crgctrl, CRGPERIPH_PERDIS12, 0x9000); +} + +static void hi3670_pcie_phyref_gt(struct hi3670_pcie_phy *phy, bool open) +{ + unsigned int val; + + regmap_read(phy->crgctrl, CRGPERIPH_PCIECTRL0, &val); + + if (open) + val &= ~(0x1 << 1); //enable hard gt mode + else + val |= (0x1 << 1); //disable hard gt mode + + regmap_write(phy->crgctrl, CRGPERIPH_PCIECTRL0, val); + + /* disable soft gt mode */ + regmap_write(phy->crgctrl, CRGPERIPH_PERDIS12, 0x4000); +} + +static void hi3670_pcie_oe_ctrl(struct hi3670_pcie_phy *phy, bool en_flag) +{ + unsigned int val; + + regmap_read(phy->crgctrl , CRGPERIPH_PCIECTRL0, &val); + + /* set ie cfg */ + val |= IO_IE_EN_HARD_BYPASS; + + /* set oe cfg */ + val &= ~IO_HARD_CTRL_DEBOUNCE_BYPASS; + + /* set phy_debounce in&out time */ + val |= (DEBOUNCE_WAITCFG_IN | DEBOUNCE_WAITCFG_OUT); + + /* select oe_gt_mode */ + val |= IO_OE_GT_MODE; + + if (en_flag) + val &= ~IO_OE_EN_HARD_BYPASS; + else + val |= IO_OE_EN_HARD_BYPASS; + + regmap_write(phy->crgctrl, CRGPERIPH_PCIECTRL0, val); +} + +static void hi3670_pcie_ioref_gt(struct hi3670_pcie_phy *phy, bool open) +{ + unsigned int val; + + if (open) { + regmap_write(phy->apb, SOC_PCIECTRL_CTRL21_ADDR, 0x20000070); + + hi3670_pcie_oe_ctrl(phy, true); + + /* en hard gt mode */ + regmap_read(phy->crgctrl, CRGPERIPH_PCIECTRL0, &val); + val &= ~(0x1 << 0); + regmap_write(phy->crgctrl, CRGPERIPH_PCIECTRL0, val); + + /* disable soft gt mode */ + regmap_write(phy->crgctrl, CRGPERIPH_PERDIS12, 0x2000); + + } else { + /* disable hard gt mode */ + regmap_read(phy->crgctrl, CRGPERIPH_PCIECTRL0, &val); + val |= (0x1 << 0); + regmap_write(phy->crgctrl, CRGPERIPH_PCIECTRL0, val); + + /* disable soft gt mode */ + regmap_write(phy->crgctrl, CRGPERIPH_PERDIS12, 0x2000); + + hi3670_pcie_oe_ctrl(phy, false); + } +} + +static int hi3670_pcie_allclk_ctrl(struct hi3670_pcie_phy *phy, bool clk_on) +{ + struct device *dev = phy->dev; + u32 val; + int ret = 0; + + if (!clk_on) + goto close_clocks; + + /* choose 100MHz clk src: Bit[8]==1 pad, Bit[8]==0 pll */ + val = hi3670_apb_phy_readl(phy, SOC_PCIEPHY_CTRL1_ADDR); + val &= ~(0x1 << 8); + hi3670_apb_phy_writel(phy, val, SOC_PCIEPHY_CTRL1_ADDR); + + hi3670_pcie_pll_init(phy); + + ret = hi3670_pcie_pll_ctrl(phy, true); + if (ret) { + dev_err(dev, "Failed to enable pll\n"); + return -1; + } + hi3670_pcie_hp_debounce_gt(phy, true); + hi3670_pcie_phyref_gt(phy, true); + hi3670_pcie_ioref_gt(phy, true); + + ret = clk_set_rate(phy->aclk, AXI_CLK_FREQ); + if (ret) { + dev_err(dev, "Failed to set rate\n"); + goto close_clocks; + } + + return 0; + +close_clocks: + hi3670_pcie_ioref_gt(phy, false); + hi3670_pcie_phyref_gt(phy, false); + hi3670_pcie_hp_debounce_gt(phy, false); + + hi3670_pcie_pll_ctrl(phy, false); + + return ret; +} + +static bool is_pipe_clk_stable(struct hi3670_pcie_phy *phy) +{ + struct device *dev = phy->dev; + u32 val; + u32 time = 100; + u32 pipe_clk_stable = 0x1 << 19; + + val = hi3670_apb_phy_readl(phy, SOC_PCIEPHY_STATE0_ADDR); + while (val & pipe_clk_stable) { + mdelay(1); + if (time == 0) { + dev_err(dev, "PIPE clk is not stable\n"); + return false; + } + time--; + val = hi3670_apb_phy_readl(phy, SOC_PCIEPHY_STATE0_ADDR); + } + + return true; +} + +static int hi3670_pcie_noc_power(struct hi3670_pcie_phy *phy, bool enable) +{ + struct device *dev = phy->dev; + u32 time = 100; + unsigned int val = NOC_PW_MASK; + int rst; + + if (enable) + val = NOC_PW_MASK | NOC_PW_SET_BIT; + else + val = NOC_PW_MASK; + rst = enable ? 1 : 0; + + regmap_write(phy->pmctrl, NOC_POWER_IDLEREQ_1, val); + + time = 100; + regmap_read(phy->pmctrl, NOC_POWER_IDLE_1, &val); + while((val & NOC_PW_SET_BIT) != rst) { + udelay(10); + if (!time) { + dev_err(dev, "Failed to reverse noc power-status\n"); + return -1; + } + time--; + regmap_read(phy->pmctrl, NOC_POWER_IDLE_1, &val); + } + + return 0; +} + +static int hi3670_pcie_get_apb(struct hi3670_pcie_phy *phy) +{ + struct device_node *pcie_port; + struct device *dev = phy->dev; + struct device *pcie_dev; + + pcie_port = of_get_child_by_name(dev->parent->of_node, "pcie"); + if (!pcie_port) { + dev_err(dev, "no pcie node found in %s\n", + dev->parent->of_node->full_name); + return -ENODEV; + } + + pcie_dev = bus_find_device_by_of_node(&platform_bus_type, pcie_port); + if (!pcie_dev) { + dev_err(dev, "Didn't find pcie device\n"); + return -ENODEV; + } + + /* + * We might just use NULL instead of the APB name, as the + * pcie-kirin currently registers directly just one regmap (although + * the DWC driver register other regmaps). + * + * Yet, it sounds safer to warrant that it will be accessing the + * right regmap. So, let's use the named version. + */ + phy->apb = dev_get_regmap(pcie_dev, "kirin_pcie_apb"); + if (!phy->apb) { + dev_err(dev, "Failed to get APB regmap\n"); + return -ENODEV; + } + + return 0; +} + + +static int kirin_pcie_clk_ctrl(struct hi3670_pcie_phy *phy, bool enable) +{ + int ret = 0; + + if (!enable) + goto close_clk; + + ret = clk_set_rate(phy->phy_ref_clk, REF_CLK_FREQ); + if (ret) + return ret; + + ret = clk_prepare_enable(phy->phy_ref_clk); + if (ret) + return ret; + + ret = clk_prepare_enable(phy->apb_sys_clk); + if (ret) + goto apb_sys_fail; + + ret = clk_prepare_enable(phy->apb_phy_clk); + if (ret) + goto apb_phy_fail; + + ret = clk_prepare_enable(phy->aclk); + if (ret) + goto aclk_fail; + + ret = clk_prepare_enable(phy->aux_clk); + if (ret) + goto aux_clk_fail; + + return 0; + +close_clk: + clk_disable_unprepare(phy->aux_clk); +aux_clk_fail: + clk_disable_unprepare(phy->aclk); +aclk_fail: + clk_disable_unprepare(phy->apb_phy_clk); +apb_phy_fail: + clk_disable_unprepare(phy->apb_sys_clk); +apb_sys_fail: + clk_disable_unprepare(phy->phy_ref_clk); + + return ret; +} + +static int hi3670_pcie_phy_init(struct phy *generic_phy) +{ + struct hi3670_pcie_phy *phy = phy_get_drvdata(generic_phy); + struct device *dev = phy->dev; + int ret; + + /* + * The code under hi3670_pcie_get_apb() need to access the + * DWC APB registers. So, get them from + * the pcie driver's regmap (see pcie-kirin regmap). + * + * Such kind of resource can only be obtained during the PCIe + * power_on sequence, as the code inside pcie-kirin needs to + * be already probed, as it needs to register the APB regmap. + */ + + ret = hi3670_pcie_get_apb(phy); + if (ret) + return ret; + + /* phy regulator needs to be powered on before calling it */ + return hi3670_pcie_gpio_request(phy, dev); +} + +static int hi3670_pcie_phy_power_on(struct phy *generic_phy) +{ + struct hi3670_pcie_phy *phy = phy_get_drvdata(generic_phy); + int val, ret, i; + + /* Power supply for Host */ + regmap_write(phy->sysctrl, + SCTRL_PCIE_CMOS_OFFSET, SCTRL_PCIE_CMOS_BIT); + usleep_range(TIME_CMOS_MIN, TIME_CMOS_MAX); + + hi3670_pcie_phy_oe_enable(phy); + + for (i = 0; i < phy->n_gpio_clkreq; i++) { + ret = gpio_direction_output(phy->gpio_id_clkreq[i], 0); + if (ret) + return ret; + } + + ret = kirin_pcie_clk_ctrl(phy, true); + if (ret) + return ret; + + /* ISO disable, PCIeCtrl, PHY assert and clk gate clear */ + regmap_write(phy->sysctrl, + SCTRL_PCIE_ISO_OFFSET, SCTRL_PCIE_ISO_BIT); + regmap_write(phy->crgctrl, + CRGCTRL_PCIE_ASSERT_OFFSET, CRGCTRL_PCIE_ASSERT_BIT); + regmap_write(phy->sysctrl, + SCTRL_PCIE_HPCLK_OFFSET, SCTRL_PCIE_HPCLK_BIT); + + hi3670_pcie_natural_cfg(phy); + + ret = hi3670_pcie_allclk_ctrl(phy, true); + if (ret) + goto disable_clks; + + /* pull down phy_test_powerdown signal */ + val = hi3670_apb_phy_readl(phy, SOC_PCIEPHY_CTRL0_ADDR); + val &= ~(0x1 << 22); + hi3670_apb_phy_writel(phy, val, SOC_PCIEPHY_CTRL0_ADDR); + + /* deassert controller perst_n */ + regmap_read(phy->apb, SOC_PCIECTRL_CTRL12_ADDR, &val); + val |= (0x1 << 2); + regmap_write(phy->apb, SOC_PCIECTRL_CTRL12_ADDR, val); + udelay(10); + + /* perst assert Endpoints */ + usleep_range(21000, 23000); + for (i = 0; i < phy->n_gpio_resets; i++) { + ret = gpio_direction_output(phy->gpio_id_reset[i], 1); + if (ret) + return ret; + } + usleep_range(10000, 11000); + + ret = is_pipe_clk_stable(phy); + if (!ret) + goto disable_clks; + + hi3670_pcie_set_eyeparam(phy); + + ret = hi3670_pcie_noc_power(phy, false); + if (ret) + goto disable_clks; + + return 0; + +disable_clks: + kirin_pcie_clk_ctrl(phy, false); + return ret; +} + +static int hi3670_pcie_phy_power_off(struct phy *generic_phy) +{ + struct hi3670_pcie_phy *phy = phy_get_drvdata(generic_phy); + + /* Drop power supply for Host */ + regmap_write(phy->sysctrl, SCTRL_PCIE_CMOS_OFFSET, 0x00); + + kirin_pcie_clk_ctrl(phy, false); + + return 0; +} + +static const struct phy_ops hi3670_phy_ops = { + .init = hi3670_pcie_phy_init, + .power_on = hi3670_pcie_phy_power_on, + .power_off = hi3670_pcie_phy_power_off, + .owner = THIS_MODULE, +}; + +static int hi3670_pcie_phy_get_resources(struct hi3670_pcie_phy *phy, + struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + char name[32]; + int i; + + /* syscon */ + phy->crgctrl = syscon_regmap_lookup_by_compatible("hisilicon,hi3670-crgctrl"); + if (IS_ERR(phy->crgctrl)) + return PTR_ERR(phy->crgctrl); + + phy->sysctrl = syscon_regmap_lookup_by_compatible("hisilicon,hi3670-sctrl"); + if (IS_ERR(phy->sysctrl)) + return PTR_ERR(phy->sysctrl); + + phy->pmctrl = syscon_regmap_lookup_by_compatible("hisilicon,hi3670-pmctrl"); + if (IS_ERR(phy->sysctrl)) + return PTR_ERR(phy->sysctrl); + + /* clocks */ + phy->phy_ref_clk = devm_clk_get(dev, "phy_ref"); + if (IS_ERR(phy->phy_ref_clk)) + return PTR_ERR(phy->phy_ref_clk); + + phy->aux_clk = devm_clk_get(dev, "aux"); + if (IS_ERR(phy->aux_clk)) + return PTR_ERR(phy->aux_clk); + + phy->apb_phy_clk = devm_clk_get(dev, "apb_phy"); + if (IS_ERR(phy->apb_phy_clk)) + return PTR_ERR(phy->apb_phy_clk); + + phy->apb_sys_clk = devm_clk_get(dev, "apb_sys"); + if (IS_ERR(phy->apb_sys_clk)) + return PTR_ERR(phy->apb_sys_clk); + + phy->aclk = devm_clk_get(dev, "aclk"); + if (IS_ERR(phy->aclk)) + return PTR_ERR(phy->aclk); + + /* registers */ + phy->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(phy->base)) + return PTR_ERR(phy->base); + + /* perst reset gpios */ + phy->n_gpio_resets = of_gpio_named_count(np, "reset-gpios"); + if (phy->n_gpio_resets > MAX_GPIO_RESETS) { + dev_err(dev, "Too many GPIO resets!\n"); + return -EINVAL; + } + for (i = 0; i < phy->n_gpio_resets; i++) { + phy->gpio_id_reset[i] = of_get_named_gpio(dev->of_node, + "reset-gpios", i); + if (phy->gpio_id_reset[i] < 0) + return phy->gpio_id_reset[i]; + + sprintf(name, "pcie_perst_%d", i); + + phy->reset_names[i] = devm_kstrdup_const(dev, name, + GFP_KERNEL); + if (!phy->reset_names[i]) + return -ENOMEM; + } + + /* clock request gpios */ + phy->n_gpio_clkreq = of_gpio_named_count(np, "clkreq-gpios"); + if (phy->n_gpio_clkreq > MAX_GPIO_CLKREQ) { + dev_err(dev, "Too many GPIO clock requests!\n"); + return -EINVAL; + } + for (i = 0; i < phy->n_gpio_clkreq; i++) { + phy->gpio_id_clkreq[i] = of_get_named_gpio(dev->of_node, + "clkreq-gpios", i); + if (phy->gpio_id_clkreq[i] < 0) + return phy->gpio_id_clkreq[i]; + + sprintf(name, "pcie_clkreq_%d", i); + phy->clkreq_names[i] = devm_kstrdup_const(dev, name, + GFP_KERNEL); + if (!phy->clkreq_names[i]) + return -ENOMEM; + } + + hi3670_pcie_get_eyeparam(phy); + + return 0; +} + +static int hi3670_pcie_phy_probe(struct platform_device *pdev) +{ + struct phy_provider *phy_provider; + struct device *dev = &pdev->dev; + struct hi3670_pcie_phy *phy; + struct phy *generic_phy; + int ret; + + phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); + if (!phy) + return -ENOMEM; + + phy->dev = dev; + + ret = hi3670_pcie_phy_get_resources(phy, pdev); + if (ret) + return ret; + + generic_phy = devm_phy_create(dev, dev->of_node, &hi3670_phy_ops); + if (IS_ERR(generic_phy)) { + dev_err(dev, "failed to create PHY\n"); + return PTR_ERR(generic_phy); + } + + phy_set_drvdata(generic_phy, phy); + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + + return PTR_ERR_OR_ZERO(phy_provider); +} + +static const struct of_device_id hi3670_pcie_phy_match[] = { + { + .compatible = "hisilicon,hi970-pcie-phy", + }, + {}, +}; + +static struct platform_driver hi3670_pcie_phy_driver = { + .probe = hi3670_pcie_phy_probe, + .driver = { + .of_match_table = hi3670_pcie_phy_match, + .name = "hi3670_pcie_phy", + .suppress_bind_attrs = true, + } +}; +builtin_platform_driver(hi3670_pcie_phy_driver); + +MODULE_DEVICE_TABLE(of, hi3670_pcie_phy_match); +MODULE_DESCRIPTION("PCIe phy driver for Kirin 970"); +MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_AUTHOR("Manivannan Sadhasivam "); +MODULE_LICENSE("GPL v2"); From patchwork Wed Jul 21 08:39:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 12390319 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-23.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, MENTIONS_GIT_HOSTING,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BD5D9C12002 for ; Wed, 21 Jul 2021 08:39:51 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7D1E3610D2 for ; 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Wed, 21 Jul 2021 10:39:15 +0200 From: Mauro Carvalho Chehab To: Vinod Koul , Bjorn Helgaas , Rob Herring Cc: linuxarm@huawei.com, mauro.chehab@huawei.com, Mauro Carvalho Chehab , Kishon Vijay Abraham I , Manivannan Sadhasivam , Rob Herring , Wei Xu , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH v7 10/10] phy-hi3670-pcie: Move reset-gpios to the PCIe DT schema Date: Wed, 21 Jul 2021 10:39:12 +0200 Message-Id: <25f0d338b301157d4b0fe8ab97db542635dff562.1626855713.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210721_013920_836236_EB827A90 X-CRM114-Status: GOOD ( 20.69 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org The PHY interface as found on HiKey 970 uses 4 reset-gpios instead of just one. That seems to be due to electrical requirements, as, on HiKey 970, the PERST# signal is provided via one GPIO per connected/available PCIe device: - GPIO 56 has a pullup logic from 1V8 to 2V5 connected to a PCIe bridge chip (PEX 8606); - GPIO 25 has a pullup logic from 1V8 to 3V3 connected to the PERST# pin at the M.2 slot; - GPIO 220 has a pullup logic from 1V8 to 3V3 connected to the PERST# pin at the PCIe mini slot; - GPIO 203 has a pullup logic from 1V8 to 3V3 connected to the PERST# pin at the Ethernet chipset. Originally, this was mapped via the PHY interface, but, as such design may also be used with different hardware, remap this to use the pcie-bus DT schema. This patch depends on a DT schema patch submitted at: https://github.com/devicetree-org/dt-schema/pull/56 Signed-off-by: Mauro Carvalho Chehab --- .../phy/hisilicon,phy-hi3670-pcie.yaml | 7 --- arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 5 +- drivers/phy/hisilicon/phy-hi3670-pcie.c | 54 ++++++++++--------- 3 files changed, 31 insertions(+), 35 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml b/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml index a5ea13332cac..86767c53bc91 100644 --- a/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml +++ b/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml @@ -42,10 +42,6 @@ properties: - const: apb_sys - const: aclk - reset-gpios: - description: PCI PERST reset GPIOs - maxItems: 4 - clkreq-gpios: description: Clock request GPIOs maxItems: 3 @@ -60,7 +56,6 @@ required: - reg - clocks - clock-names - - reset-gpios - clkreq-gpios - hisilicon,eye-diagram-param - phy-supply @@ -86,8 +81,6 @@ examples: <&crg_ctrl HI3670_ACLK_GATE_PCIE>; clock-names = "phy_ref", "aux", "apb_phy", "apb_sys", "aclk"; - reset-gpios = <&gpio7 0 0 >, <&gpio25 2 0 >, - <&gpio3 1 0 >, <&gpio27 4 0 >; clkreq-gpios = <&gpio20 6 0 >, <&gpio27 3 0 >, <&gpio17 0 0 >; hisilicon,eye-diagram-param = <0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF>; diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi index 6dfcfcfeedae..a07790c76b72 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi @@ -687,9 +687,6 @@ pcie_phy: pcie-phy@fc000000 { "apb_phy", "apb_sys", "aclk"; - reset-gpios = <&gpio7 0 0 >, <&gpio25 2 0 >, - <&gpio3 1 0 >, <&gpio27 4 0 >; - clkreq-gpios = <&gpio20 6 0 >, <&gpio27 3 0 >, <&gpio17 0 0 >; @@ -729,6 +726,8 @@ &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, <0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; + reset-gpios = <&gpio7 0 0 >, <&gpio25 2 0 >, + <&gpio3 1 0 >, <&gpio27 4 0 >; }; /* UFS */ diff --git a/drivers/phy/hisilicon/phy-hi3670-pcie.c b/drivers/phy/hisilicon/phy-hi3670-pcie.c index 0bc0203e9140..82cc5fc4eac2 100644 --- a/drivers/phy/hisilicon/phy-hi3670-pcie.c +++ b/drivers/phy/hisilicon/phy-hi3670-pcie.c @@ -553,11 +553,13 @@ static int hi3670_pcie_noc_power(struct hi3670_pcie_phy *phy, bool enable) return 0; } -static int hi3670_pcie_get_apb(struct hi3670_pcie_phy *phy) +static int hi3670_pcie_get_resources_from_pcie(struct hi3670_pcie_phy *phy) { struct device_node *pcie_port; struct device *dev = phy->dev; struct device *pcie_dev; + char name[32]; + int i; pcie_port = of_get_child_by_name(dev->parent->of_node, "pcie"); if (!pcie_port) { @@ -586,6 +588,27 @@ static int hi3670_pcie_get_apb(struct hi3670_pcie_phy *phy) return -ENODEV; } + /* perst reset gpios */ + phy->n_gpio_resets = of_gpio_named_count(pcie_dev->of_node, + "reset-gpios"); + if (phy->n_gpio_resets > MAX_GPIO_RESETS) { + dev_err(dev, "Too many GPIO resets!\n"); + return -EINVAL; + } + for (i = 0; i < phy->n_gpio_resets; i++) { + phy->gpio_id_reset[i] = of_get_named_gpio(pcie_dev->of_node, + "reset-gpios", i); + if (phy->gpio_id_reset[i] < 0) + return phy->gpio_id_reset[i]; + + sprintf(name, "pcie_perst_%d", i); + + phy->reset_names[i] = devm_kstrdup_const(dev, name, + GFP_KERNEL); + if (!phy->reset_names[i]) + return -ENOMEM; + } + return 0; } @@ -644,16 +667,17 @@ static int hi3670_pcie_phy_init(struct phy *generic_phy) int ret; /* - * The code under hi3670_pcie_get_apb() need to access the - * DWC APB registers. So, get them from - * the pcie driver's regmap (see pcie-kirin regmap). + * The code under hi3670_pcie_get_resources_from_pcie() need to + * access the reset-gpios and the APB registers, both from the + * pcie-kirin driver. * + * The APB is obtained via the pcie driver's regmap * Such kind of resource can only be obtained during the PCIe * power_on sequence, as the code inside pcie-kirin needs to * be already probed, as it needs to register the APB regmap. */ - ret = hi3670_pcie_get_apb(phy); + ret = hi3670_pcie_get_resources_from_pcie(phy); if (ret) return ret; @@ -800,26 +824,6 @@ static int hi3670_pcie_phy_get_resources(struct hi3670_pcie_phy *phy, if (IS_ERR(phy->base)) return PTR_ERR(phy->base); - /* perst reset gpios */ - phy->n_gpio_resets = of_gpio_named_count(np, "reset-gpios"); - if (phy->n_gpio_resets > MAX_GPIO_RESETS) { - dev_err(dev, "Too many GPIO resets!\n"); - return -EINVAL; - } - for (i = 0; i < phy->n_gpio_resets; i++) { - phy->gpio_id_reset[i] = of_get_named_gpio(dev->of_node, - "reset-gpios", i); - if (phy->gpio_id_reset[i] < 0) - return phy->gpio_id_reset[i]; - - sprintf(name, "pcie_perst_%d", i); - - phy->reset_names[i] = devm_kstrdup_const(dev, name, - GFP_KERNEL); - if (!phy->reset_names[i]) - return -ENOMEM; - } - /* clock request gpios */ phy->n_gpio_clkreq = of_gpio_named_count(np, "clkreq-gpios"); if (phy->n_gpio_clkreq > MAX_GPIO_CLKREQ) {