From patchwork Fri Jul 23 09:41:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christine Zhu X-Patchwork-Id: 12395773 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EDCF3C4338F for ; Fri, 23 Jul 2021 09:53:20 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BC5D360E95 for ; Fri, 23 Jul 2021 09:53:20 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org BC5D360E95 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=KEqTz+Il+TwXrHF6xECQRSWXqcASQpH9ZSjmiEa0wYE=; b=o7IEr/tl7hcqOs 6kNAS9xflLndH/XEZ86Y2orC0esrcy/Zhm64E6BS6DVUn2RaPi3aw+lczVosPNWf+3DqPQlUmmige olKdPgklowb73Iz9BEtj2JJpsWq+FNws7OPTzi9ZmYhLzkeaEzYvKbztEck5Cn/TRS4vWkIG+GNpO ScC2/MV/MYFDHVg6gbfd54xb5Vs1HIy9J8g+1KGLNeAMSnnSHivey7uePA93HHyV2yv/BsWgIVqyq J8gy0XlSVz1/dvAJtgiRY/ZXkv2yUTqWO0FsWeBTnTbD+4kp53vdeCFTRXXfGrz1vBKarjOrS7Tws XYtaD70orpT1XS2ADo0w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1m6rrj-004CYj-OW; Fri, 23 Jul 2021 09:53:11 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1m6rqq-004CIk-5l; Fri, 23 Jul 2021 09:52:17 +0000 X-UUID: 7242146d9ff943c1966a5004a81d9eca-20210723 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=prEUx4Fr36qhmRopO2EQzqqVsYFf3N6/a1ibywqMX4o=; b=jBdqpBByQE9k9vlL3xccmfHfqLaE99FlyMCetzl5hCHXk0rocYkI/dfwrEITy64prH5OBy4i0hFIY2iMNwb1vNAxU42CueH0G5XIPQoV3TUSd6TE/Nn+ciFUzx3tbK2fpFTaKPNHP/V5BV730jiNSFbcvJ2mnAaWeWd3zIscmzQ=; X-UUID: 7242146d9ff943c1966a5004a81d9eca-20210723 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 922482658; Fri, 23 Jul 2021 02:52:14 -0700 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 23 Jul 2021 02:42:13 -0700 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 23 Jul 2021 17:42:11 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 23 Jul 2021 17:42:10 +0800 From: Christine Zhu To: , , , CC: , , , , , , , , Christine Zhu Subject: [v6,1/3] dt-bindings: mediatek: mt8195: update mtk-wdt document Date: Fri, 23 Jul 2021 17:41:36 +0800 Message-ID: <20210723094138.24793-2-Christine.Zhu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210723094138.24793-1-Christine.Zhu@mediatek.com> References: <20210723094138.24793-1-Christine.Zhu@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210723_025216_230378_252E2AD3 X-CRM114-Status: UNSURE ( 7.94 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Update mtk-wdt document for MT8195 platform. Signed-off-by: Christine Zhu Acked-by: Rob Herring --- Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt index e36ba60de829..ca9b67ab7c44 100644 --- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt +++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt @@ -13,6 +13,7 @@ Required properties: "mediatek,mt8183-wdt": for MT8183 "mediatek,mt8516-wdt", "mediatek,mt6589-wdt": for MT8516 "mediatek,mt8192-wdt": for MT8192 + "mediatek,mt8195-wdt": for MT8195 - reg : Specifies base physical address and size of the registers. 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Fri, 23 Jul 2021 02:52:14 -0700 Received: from mtkmbs05n2.mediatek.inc (172.21.101.140) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 23 Jul 2021 02:42:14 -0700 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs05n2.mediatek.inc (172.21.101.140) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 23 Jul 2021 17:42:12 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 23 Jul 2021 17:42:11 +0800 From: Christine Zhu To: , , , CC: , , , , , , , , Christine Zhu Subject: [v6, 2/3] dt-bindings: reset: mt8195: add toprgu reset-controller header file Date: Fri, 23 Jul 2021 17:41:37 +0800 Message-ID: <20210723094138.24793-3-Christine.Zhu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210723094138.24793-1-Christine.Zhu@mediatek.com> References: <20210723094138.24793-1-Christine.Zhu@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210723_025215_449833_C06D7D53 X-CRM114-Status: GOOD ( 11.76 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Add toprgu reset-controller header file for MT8195 platform Signed-off-by: Christine Zhu --- .../reset-controller/mt8195-resets.h | 32 +++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 include/dt-bindings/reset-controller/mt8195-resets.h diff --git a/include/dt-bindings/reset-controller/mt8195-resets.h b/include/dt-bindings/reset-controller/mt8195-resets.h new file mode 100644 index 000000000000..8176a3e5063f --- /dev/null +++ b/include/dt-bindings/reset-controller/mt8195-resets.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ +/* + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either licens + * + * Copyright (c) 2021 MediaTek Inc. + * Author: Christine Zhu + */ + +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8195 +#define _DT_BINDINGS_RESET_CONTROLLER_MT8195 + +#define MT8195_TOPRGU_CONN_MCU_SW_RST 0 +#define MT8195_TOPRGU_INFRA_GRST_SW_RST 1 +#define MT8195_TOPRGU_APU_SW_RST 2 +#define MT8195_TOPRGU_INFRA_AO_GRST_SW_RST 6 +#define MT8195_TOPRGU_MMSYS_SW_RST 7 +#define MT8195_TOPRGU_MFG_SW_RST 8 +#define MT8195_TOPRGU_VENC_SW_RST 9 +#define MT8195_TOPRGU_VDEC_SW_RST 10 +#define MT8195_TOPRGU_IMG_SW_RST 11 +#define MT8195_TOPRGU_APMIXEDSYS_SW_RST 13 +#define MT8195_TOPRGU_AUDIO_SW_RST 14 +#define MT8195_TOPRGU_CAMSYS_SW_RST 15 +#define MT8195_TOPRGU_EDPTX_SW_RST 16 +#define MT8195_TOPRGU_ADSPSYS_SW_RST 21 +#define MT8195_TOPRGU_DPTX_SW_RST 22 +#define MT8195_TOPRGU_SPMI_MST_SW_RST 23 + +#define MT8195_TOPRGU_SW_RST_NUM 16 + +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */