From patchwork Thu Jul 29 13:30:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shai Malin X-Patchwork-Id: 12408743 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AE57CC432BE for ; Thu, 29 Jul 2021 13:31:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9332260184 for ; Thu, 29 Jul 2021 13:31:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237539AbhG2Nbo (ORCPT ); Thu, 29 Jul 2021 09:31:44 -0400 Received: from mx0b-0016f401.pphosted.com ([67.231.156.173]:1866 "EHLO mx0b-0016f401.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237459AbhG2Nbo (ORCPT ); Thu, 29 Jul 2021 09:31:44 -0400 Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 16TDVRjL017290; Thu, 29 Jul 2021 06:31:33 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=GJdtlvHcnYMSTM2wdlplrHS4MgWPR4A2CMsdY9OyLDI=; b=Onk3ar8GwAOXEs2M3Cvq/UIal8GvL0CFtd+YQ0JkbfKkSmJE6eyAWistHGmqEuz7Cqvs AuUeTzJeqaay8CypKCMFYoEZu4/93CFz6QkXD02EvMe9A8hWLPvpDehnvol1IfIGThT/ 7cT/iIJIaeCBEwJvCmtO2zwJKUx6v5kBzZser3jqouQkyWt8olwAyQYfTYUFjXEqx4hI s9A6JvskmTsTX/XRouTDpRUr7vJF/rPYAckOGh+6Q6Q3MtWVAs+6as7nBPafbbHBk56O Mcpg5upz85efBIjYJpTNjoYw8fSudeoZG0giKn3GiT+fP6DGRpc0vovxVQeXvepYl7WG 7w== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 3a35pr4yua-4 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 29 Jul 2021 06:31:32 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 29 Jul 2021 06:30:41 -0700 Received: from lbtlvb-pcie154.il.qlogic.org (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 29 Jul 2021 06:30:38 -0700 From: Shai Malin To: , , , CC: , , , , , , Subject: [PATCH for-next 1/3] qed: add get and set support for dscp priority Date: Thu, 29 Jul 2021 16:30:30 +0300 Message-ID: <20210729133032.26278-2-smalin@marvell.com> X-Mailer: git-send-email 2.16.6 In-Reply-To: <20210729133032.26278-1-smalin@marvell.com> References: <20210729133032.26278-1-smalin@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: g0W4ZgaRSngoo1yzt2gbmAkuyL182gov X-Proofpoint-GUID: g0W4ZgaRSngoo1yzt2gbmAkuyL182gov X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391,18.0.790 definitions=2021-07-29_10:2021-07-29,2021-07-29 signatures=0 Precedence: bulk List-ID: X-Mailing-List: linux-rdma@vger.kernel.org From: Prabhakar Kushwaha This patch add support of get or set priority value for a given dscp index. Signed-off-by: Shai Malin Signed-off-by: Ariel Elior Signed-off-by: Prabhakar Kushwaha --- drivers/net/ethernet/qlogic/qed/qed_dcbx.c | 65 ++++++++++++++++++++++ drivers/net/ethernet/qlogic/qed/qed_dcbx.h | 9 +++ include/linux/qed/qed_if.h | 6 ++ 3 files changed, 80 insertions(+) diff --git a/drivers/net/ethernet/qlogic/qed/qed_dcbx.c b/drivers/net/ethernet/qlogic/qed/qed_dcbx.c index e81dd34a3cac..ba9276599e72 100644 --- a/drivers/net/ethernet/qlogic/qed/qed_dcbx.c +++ b/drivers/net/ethernet/qlogic/qed/qed_dcbx.c @@ -1280,6 +1280,71 @@ int qed_dcbx_get_config_params(struct qed_hwfn *p_hwfn, return 0; } +int qed_dcbx_get_dscp_priority(struct qed_hwfn *p_hwfn, u8 dscp_index, + u8 *p_dscp_pri) +{ + struct qed_dcbx_get *p_dcbx_info; + int rc; + + if (IS_VF(p_hwfn->cdev)) { + DP_ERR(p_hwfn->cdev, + "qed rdma get dscp priority not supported for VF.\n"); + return -EINVAL; + } + + if (dscp_index >= QED_DCBX_DSCP_SIZE) { + DP_ERR(p_hwfn, "Invalid dscp index %d\n", dscp_index); + return -EINVAL; + } + + p_dcbx_info = kmalloc(sizeof(*p_dcbx_info), GFP_KERNEL); + if (!p_dcbx_info) + return -ENOMEM; + + memset(p_dcbx_info, 0, sizeof(*p_dcbx_info)); + rc = qed_dcbx_query_params(p_hwfn, p_dcbx_info, + QED_DCBX_OPERATIONAL_MIB); + if (rc) { + kfree(p_dcbx_info); + return rc; + } + + *p_dscp_pri = p_dcbx_info->dscp.dscp_pri_map[dscp_index]; + kfree(p_dcbx_info); + + return 0; +} + +int qed_dcbx_set_dscp_priority(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, + u8 dscp_index, u8 pri_val) +{ + struct qed_dcbx_set dcbx_set; + int rc; + + if (IS_VF(p_hwfn->cdev)) { + DP_ERR(p_hwfn->cdev, + "qed rdma set dscp priority not supported for VF.\n"); + return -EINVAL; + } + + if (dscp_index >= QED_DCBX_DSCP_SIZE || + pri_val >= QED_MAX_PFC_PRIORITIES) { + DP_ERR(p_hwfn, "Invalid dscp params: index = %d pri = %d\n", + dscp_index, pri_val); + return -EINVAL; + } + + memset(&dcbx_set, 0, sizeof(dcbx_set)); + rc = qed_dcbx_get_config_params(p_hwfn, &dcbx_set); + if (rc) + return rc; + + dcbx_set.override_flags = QED_DCBX_OVERRIDE_DSCP_CFG; + dcbx_set.dscp.dscp_pri_map[dscp_index] = pri_val; + + return qed_dcbx_config_params(p_hwfn, p_ptt, &dcbx_set, 1); +} + static struct qed_dcbx_get *qed_dcbnl_get_dcbx(struct qed_hwfn *hwfn, enum qed_mib_read_type type) { diff --git a/drivers/net/ethernet/qlogic/qed/qed_dcbx.h b/drivers/net/ethernet/qlogic/qed/qed_dcbx.h index e1798925b444..6d8ce9bb30bd 100644 --- a/drivers/net/ethernet/qlogic/qed/qed_dcbx.h +++ b/drivers/net/ethernet/qlogic/qed/qed_dcbx.h @@ -46,6 +46,7 @@ struct qed_dcbx_set { bool enabled; struct qed_dcbx_admin_params config; u32 ver_num; + struct qed_dcbx_dscp_params dscp; }; struct qed_dcbx_results { @@ -100,6 +101,14 @@ void qed_dcbx_info_free(struct qed_hwfn *p_hwfn); void qed_dcbx_set_pf_update_params(struct qed_dcbx_results *p_src, struct pf_update_ramrod_data *p_dest); +/* Returns priority value for a given dscp index */ +int qed_dcbx_get_dscp_priority(struct qed_hwfn *p_hwfn, u8 dscp_index, + u8 *p_dscp_pri); + +/* Sets priority value for a given dscp index */ +int qed_dcbx_set_dscp_priority(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, + u8 dscp_index, u8 pri_val); + #define QED_DCBX_DEFAULT_TC 0 u8 qed_dcbx_get_priority_tc(struct qed_hwfn *p_hwfn, u8 pri); diff --git a/include/linux/qed/qed_if.h b/include/linux/qed/qed_if.h index 850b98991670..f7ce9a923d7c 100644 --- a/include/linux/qed/qed_if.h +++ b/include/linux/qed/qed_if.h @@ -124,12 +124,18 @@ struct qed_dcbx_operational_params { u32 err; }; +struct qed_dcbx_dscp_params { + bool enabled; + u8 dscp_pri_map[QED_DCBX_DSCP_SIZE]; +}; + struct qed_dcbx_get { struct qed_dcbx_operational_params operational; struct qed_dcbx_lldp_remote lldp_remote; struct qed_dcbx_lldp_local lldp_local; struct qed_dcbx_remote_params remote; struct qed_dcbx_admin_params local; + struct qed_dcbx_dscp_params dscp; }; enum qed_nvm_images { From patchwork Thu Jul 29 13:30:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shai Malin X-Patchwork-Id: 12408741 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C3CCDC4338F for ; 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Thu, 29 Jul 2021 06:31:33 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 29 Jul 2021 06:30:45 -0700 Received: from lbtlvb-pcie154.il.qlogic.org (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 29 Jul 2021 06:30:42 -0700 From: Shai Malin To: , , , CC: , , , , , , Subject: [PATCH for-next 2/3] qedr: Consider dscp priority for vlan priority Date: Thu, 29 Jul 2021 16:30:31 +0300 Message-ID: <20210729133032.26278-3-smalin@marvell.com> X-Mailer: git-send-email 2.16.6 In-Reply-To: <20210729133032.26278-1-smalin@marvell.com> References: <20210729133032.26278-1-smalin@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: 8CebflyCZj_bGiLcf80yqeSPYoJvkuHx X-Proofpoint-GUID: 8CebflyCZj_bGiLcf80yqeSPYoJvkuHx X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391,18.0.790 definitions=2021-07-29_10:2021-07-29,2021-07-29 signatures=0 Precedence: bulk List-ID: X-Mailing-List: linux-rdma@vger.kernel.org From: Prabhakar Kushwaha if dscp is enabled, consider its priority while deciding vlan priority. Signed-off-by: Shai Malin Signed-off-by: Ariel Elior Signed-off-by: Prabhakar Kushwaha --- drivers/infiniband/hw/qedr/qedr_roce_cm.c | 11 +++++++++- drivers/net/ethernet/qlogic/qed/qed_dcbx.c | 7 ++++++ drivers/net/ethernet/qlogic/qed/qed_dcbx.h | 5 +++-- drivers/net/ethernet/qlogic/qed/qed_rdma.c | 25 ++++++++++++++++++++++ include/linux/qed/qed_rdma_if.h | 7 ++++++ 5 files changed, 52 insertions(+), 3 deletions(-) diff --git a/drivers/infiniband/hw/qedr/qedr_roce_cm.c b/drivers/infiniband/hw/qedr/qedr_roce_cm.c index 13e5e6bbec99..eb7d24742664 100644 --- a/drivers/infiniband/hw/qedr/qedr_roce_cm.c +++ b/drivers/infiniband/hw/qedr/qedr_roce_cm.c @@ -389,6 +389,7 @@ static inline int qedr_gsi_build_header(struct qedr_dev *dev, const struct ib_global_route *grh = rdma_ah_read_grh(ah_attr); const struct ib_gid_attr *sgid_attr = grh->sgid_attr; int send_size = 0; + u8 vlan_pri, dscp; u16 vlan_id = 0; u16 ether_type; int rc; @@ -437,8 +438,16 @@ static inline int qedr_gsi_build_header(struct qedr_dev *dev, ether_addr_copy(udh->eth.dmac_h, ah_attr->roce.dmac); ether_addr_copy(udh->eth.smac_h, dev->ndev->dev_addr); if (has_vlan) { - udh->eth.type = htons(ETH_P_8021Q); + dscp = GET_FIELD(grh->traffic_class, QED_RDMA_TC_TOS_DSCP); + + /* get the vlan priority associated with the dscp value */ + if (!dev->ops->rdma_get_dscp_priority(dev->rdma_ctx, dscp, + &vlan_pri)) + vlan_id |= vlan_pri << VLAN_PRIO_SHIFT; + udh->vlan.tag = htons(vlan_id); + + udh->eth.type = htons(ETH_P_8021Q); udh->vlan.type = htons(ether_type); } else { udh->eth.type = htons(ether_type); diff --git a/drivers/net/ethernet/qlogic/qed/qed_dcbx.c b/drivers/net/ethernet/qlogic/qed/qed_dcbx.c index ba9276599e72..cec4b890e69a 100644 --- a/drivers/net/ethernet/qlogic/qed/qed_dcbx.c +++ b/drivers/net/ethernet/qlogic/qed/qed_dcbx.c @@ -973,6 +973,13 @@ void qed_dcbx_set_pf_update_params(struct qed_dcbx_results *p_src, qed_dcbx_update_protocol_data(p_dcb_data, p_src, DCBX_PROTOCOL_ETH); } +bool qed_dcbx_get_dscp_state(struct qed_hwfn *p_hwfn) +{ + struct qed_dcbx_get *p_dcbx_info = &p_hwfn->p_dcbx_info->get; + + return p_dcbx_info->dscp.enabled; +} + u8 qed_dcbx_get_priority_tc(struct qed_hwfn *p_hwfn, u8 pri) { struct qed_dcbx_get *dcbx_info = &p_hwfn->p_dcbx_info->get; diff --git a/drivers/net/ethernet/qlogic/qed/qed_dcbx.h b/drivers/net/ethernet/qlogic/qed/qed_dcbx.h index 6d8ce9bb30bd..86a374c3ed86 100644 --- a/drivers/net/ethernet/qlogic/qed/qed_dcbx.h +++ b/drivers/net/ethernet/qlogic/qed/qed_dcbx.h @@ -102,8 +102,7 @@ void qed_dcbx_set_pf_update_params(struct qed_dcbx_results *p_src, struct pf_update_ramrod_data *p_dest); /* Returns priority value for a given dscp index */ -int qed_dcbx_get_dscp_priority(struct qed_hwfn *p_hwfn, u8 dscp_index, - u8 *p_dscp_pri); +int qed_dcbx_get_dscp_priority(struct qed_hwfn *p_hwfn, u8 dscp_index, u8 *pri); /* Sets priority value for a given dscp index */ int qed_dcbx_set_dscp_priority(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, @@ -112,4 +111,6 @@ int qed_dcbx_set_dscp_priority(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, #define QED_DCBX_DEFAULT_TC 0 u8 qed_dcbx_get_priority_tc(struct qed_hwfn *p_hwfn, u8 pri); + +bool qed_dcbx_get_dscp_state(struct qed_hwfn *p_hwfn); #endif diff --git a/drivers/net/ethernet/qlogic/qed/qed_rdma.c b/drivers/net/ethernet/qlogic/qed/qed_rdma.c index da864d12916b..e904ba2e6242 100644 --- a/drivers/net/ethernet/qlogic/qed/qed_rdma.c +++ b/drivers/net/ethernet/qlogic/qed/qed_rdma.c @@ -32,6 +32,7 @@ #include "qed_rdma.h" #include "qed_roce.h" #include "qed_sp.h" +#include "qed_dcbx.h" int qed_rdma_bmap_alloc(struct qed_hwfn *p_hwfn, @@ -1965,6 +1966,29 @@ static void qed_rdma_remove_user(void *rdma_cxt, u16 dpi) spin_unlock_bh(&p_hwfn->p_rdma_info->lock); } +#ifdef CONFIG_DCB +static int qed_rdma_get_dscp_priority(void *rdma_cxt, u8 dscp_index, u8 *pri) +{ + struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; + int rc = -EINVAL; + + if (qed_dcbx_get_dscp_state(p_hwfn)) { + rc = qed_dcbx_get_dscp_priority(p_hwfn, dscp_index, pri); + if (rc) + DP_INFO(p_hwfn, + "Failed to get priority val for dscp idx %d\n", + dscp_index); + } + + return rc; +} +#else +static int qed_rdma_get_dscp_priority(void *rdma_cxt, u8 dscp_index, u8 *pri) +{ + return -EINVAL; +} +#endif + static int qed_roce_ll2_set_mac_filter(struct qed_dev *cdev, u8 *old_mac_address, u8 *new_mac_address) @@ -2045,6 +2069,7 @@ static const struct qed_rdma_ops qed_rdma_ops_pass = { .rdma_create_srq = &qed_rdma_create_srq, .rdma_modify_srq = &qed_rdma_modify_srq, .rdma_destroy_srq = &qed_rdma_destroy_srq, + .rdma_get_dscp_priority = &qed_rdma_get_dscp_priority, .ll2_acquire_connection = &qed_ll2_acquire_connection, .ll2_establish_connection = &qed_ll2_establish_connection, .ll2_terminate_connection = &qed_ll2_terminate_connection, diff --git a/include/linux/qed/qed_rdma_if.h b/include/linux/qed/qed_rdma_if.h index aeb242cefebf..cd98e95ec2e3 100644 --- a/include/linux/qed/qed_rdma_if.h +++ b/include/linux/qed/qed_rdma_if.h @@ -363,6 +363,10 @@ struct qed_rdma_modify_qp_in_params { u32 dest_qp; bool lb_indication; u16 mtu; +#define QED_RDMA_TC_TOS_ECN_SHIFT 0 +#define QED_RDMA_TC_TOS_ECN_MASK 0x3 +#define QED_RDMA_TC_TOS_DSCP_SHIFT 2 +#define QED_RDMA_TC_TOS_DSCP_MASK 0x3f u8 traffic_class_tos; u8 hop_limit_ttl; u32 flow_label; @@ -639,6 +643,9 @@ struct qed_rdma_ops { int (*rdma_modify_srq)(void *rdma_cxt, struct qed_rdma_modify_srq_in_params *iparams); + int (*rdma_get_dscp_priority)(void *rdma_cxt, u8 dscp_index, + u8 *p_dscp_pri); + int (*ll2_acquire_connection)(void *rdma_cxt, struct qed_ll2_acquire_data *data); From patchwork Thu Jul 29 13:30:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shai Malin X-Patchwork-Id: 12408737 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C3455C4338F for ; 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Thu, 29 Jul 2021 06:31:23 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 29 Jul 2021 06:30:49 -0700 Received: from lbtlvb-pcie154.il.qlogic.org (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 29 Jul 2021 06:30:46 -0700 From: Shai Malin To: , , , CC: , , , , , , Subject: [PATCH for-next 3/3] qedr: Use grh layer traffic_class as RDMA CM TOS Date: Thu, 29 Jul 2021 16:30:32 +0300 Message-ID: <20210729133032.26278-4-smalin@marvell.com> X-Mailer: git-send-email 2.16.6 In-Reply-To: <20210729133032.26278-1-smalin@marvell.com> References: <20210729133032.26278-1-smalin@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: 4cUGCO3tFGFXkm6YJXtTaO4VKrWETWgQ X-Proofpoint-ORIG-GUID: 4cUGCO3tFGFXkm6YJXtTaO4VKrWETWgQ X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391,18.0.790 definitions=2021-07-29_10:2021-07-29,2021-07-29 signatures=0 Precedence: bulk List-ID: X-Mailing-List: linux-rdma@vger.kernel.org From: Prabhakar Kushwaha Instead of grh flow label use grh layer traffic_class as RDMA CM TOS. Signed-off-by: Shai Malin Signed-off-by: Ariel Elior Signed-off-by: Prabhakar Kushwaha --- drivers/infiniband/hw/qedr/qedr_roce_cm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/infiniband/hw/qedr/qedr_roce_cm.c b/drivers/infiniband/hw/qedr/qedr_roce_cm.c index eb7d24742664..1fa7415117e5 100644 --- a/drivers/infiniband/hw/qedr/qedr_roce_cm.c +++ b/drivers/infiniband/hw/qedr/qedr_roce_cm.c @@ -477,7 +477,7 @@ static inline int qedr_gsi_build_header(struct qedr_dev *dev, u32 ipv4_addr; udh->ip4.protocol = IPPROTO_UDP; - udh->ip4.tos = htonl(grh->flow_label); + udh->ip4.tos = grh->traffic_class; udh->ip4.frag_off = htons(IP_DF); udh->ip4.ttl = grh->hop_limit;