From patchwork Thu Jul 29 21:51:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 12409963 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D3ED4C4320E for ; Thu, 29 Jul 2021 22:34:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B32D961019 for ; Thu, 29 Jul 2021 22:34:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232810AbhG2Weq (ORCPT ); Thu, 29 Jul 2021 18:34:46 -0400 Received: from Galois.linutronix.de ([193.142.43.55]:49056 "EHLO galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229707AbhG2Weq (ORCPT ); Thu, 29 Jul 2021 18:34:46 -0400 Message-ID: <20210729222542.344136412@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1627598080; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: references:references; bh=RUg7tFwxeXr+VQq+Rk54Zo4rNFwgWvVbGs+FETqcpGc=; b=v/V6sFKxNS7wkJnFjx1m1UKY6VIyqRNxfaAzeezZcb0a2/cgjl621ydMKMnGMKNqAq4t+E FQxOH5NoSowRlSBpkdNVvOcRNxb9068youWaUFHmbw0daG+AXLI7Qw019zeVZcm/wGDmGc K2sEZh5snqL+6RL8RzCbOgdy0XGiKVjIhZhZyUrytvXwH9kcm9xrvRBb66Oml70I/RqDsK O8AeK39Vbgl6P7mFm7KzXEVPGiGBZLEPMnmfVRXN6xx1zC8tGY18eBukW58HTZCjvv4rzr LDpCy6CNk3jtXrU3ECr7vXX8Rhz978io0VnO2jQx93QWYzW6UQYRE4VMDwPufg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1627598080; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: references:references; bh=RUg7tFwxeXr+VQq+Rk54Zo4rNFwgWvVbGs+FETqcpGc=; b=qsVaEGKJ8uJ0I8xtbnhOcO0+zAnZtuYkUKzaHduCQ5tMiiuvKZTwwg5GRtm1iEBBKP4qx3 zbn8NYlav4McN5Aw== Date: Thu, 29 Jul 2021 23:51:40 +0200 From: Thomas Gleixner To: LKML Cc: Alex Williamson , "Raj, Ashok" , "David S. Miller" , Bjorn Helgaas , linux-pci@vger.kernel.org, Kevin Tian , Marc Zyngier , Ingo Molnar , x86@kernel.org, linux-s390@vger.kernel.org, Niklas Schnelle , Gerald Schaefer , Heiko Carstens , Christian Borntraeger Subject: [patch V2 01/19] PCI/MSI: Enable and mask MSI-X early References: <20210729215139.889204656@linutronix.de> MIME-Version: 1.0 Content-transfer-encoding: 8-bit Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Thomas Gleixner The ordering of MSI-X enable in hardware is dysfunctional: 1) MSI-X is disabled in the control register 2) Various setup functions 3) pci_msi_setup_msi_irqs() is invoked which ends up accessing the MSI-X table entries 4) MSI-X is enabled and masked in the control register with the comment that enabling is required for some hardware to access the MSI-X table Step #4 obviously contradicts #3. The history of this is an issue with the NIU hardware. When #4 was introduced the table access actually happened in msix_program_entries() which was invoked after enabling and masking MSI-X. This was changed in commit d71d6432e105 ("PCI/MSI: Kill redundant call of irq_set_msi_desc() for MSI-X interrupts") which removed the table write from msix_program_entries(). Interestingly enough nobody noticed and either NIU still works or it did not get any testing with a kernel 3.19 or later. Nevertheless this is inconsistent and there is no reason why MSI-X can't be enabled and masked in the control register early on, i.e. move step #4 above to step #1. This preserves the NIU workaround and has no side effects on other hardware. Fixes: d71d6432e105 ("PCI/MSI: Kill redundant call of irq_set_msi_desc() for MSI-X interrupts") Signed-off-by: Thomas Gleixner Reviewed-by: Ashok Raj Reviewed-by: Marc Zyngier Acked-by: Bjorn Helgaas --- drivers/pci/msi.c | 28 +++++++++++++++------------- 1 file changed, 15 insertions(+), 13 deletions(-) --- a/drivers/pci/msi.c +++ b/drivers/pci/msi.c @@ -772,18 +772,25 @@ static int msix_capability_init(struct p u16 control; void __iomem *base; - /* Ensure MSI-X is disabled while it is set up */ - pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0); + /* + * Some devices require MSI-X to be enabled before the MSI-X + * registers can be accessed. Mask all the vectors to prevent + * interrupts coming in before they're fully set up. + */ + pci_msix_clear_and_set_ctrl(dev, 0, PCI_MSIX_FLAGS_MASKALL | + PCI_MSIX_FLAGS_ENABLE); pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); /* Request & Map MSI-X table region */ base = msix_map_region(dev, msix_table_size(control)); - if (!base) - return -ENOMEM; + if (!base) { + ret = -ENOMEM; + goto out_disable; + } ret = msix_setup_entries(dev, base, entries, nvec, affd); if (ret) - return ret; + goto out_disable; ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX); if (ret) @@ -794,14 +801,6 @@ static int msix_capability_init(struct p if (ret) goto out_free; - /* - * Some devices require MSI-X to be enabled before we can touch the - * MSI-X registers. We need to mask all the vectors to prevent - * interrupts coming in before they're fully set up. - */ - pci_msix_clear_and_set_ctrl(dev, 0, - PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE); - msix_program_entries(dev, entries); ret = populate_msi_sysfs(dev); @@ -836,6 +835,9 @@ static int msix_capability_init(struct p out_free: free_msi_irqs(dev); +out_disable: + pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0); + return ret; } From patchwork Thu Jul 29 21:51:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 12409965 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-20.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3236DC43216 for ; Thu, 29 Jul 2021 22:34:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 17A1F60F4B for ; Thu, 29 Jul 2021 22:34:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233104AbhG2Wes (ORCPT ); Thu, 29 Jul 2021 18:34:48 -0400 Received: from Galois.linutronix.de ([193.142.43.55]:49076 "EHLO galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233017AbhG2Wer (ORCPT ); Thu, 29 Jul 2021 18:34:47 -0400 Message-ID: <20210729222542.403833459@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1627598082; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: references:references; bh=yhNFc6cu/Ud2vpLDU4lJ6f445JcsOy4OWzVjDs40Mro=; b=p3xZHaJkiOK+NZ/1XefUN0qIt2sQAS5pIiM9GjOzxbYjxy/xTAn6RdfRVP0OIiHyPUJHBM gRfHa9D1yMDhIJ4qmyQifKNiAu4Cu8pmNCvj3dJ0biJ2JbuK3Zkez5XEstn7XVOeH8zykg +MvR5DHdv+2wWYELC1F6I2iooXJRcaBDHV/+ylj0JpRWca/6IG4HHC4qY6Pn/UbJ1ePbk0 f81mJqwk8T4K88XNIO3gJkZecA/1RjZ7DKpt5CHQc/ASiQhj5DO8ONFOkirLQ3rYNkWh5x pLMEvTM3V1qOTQAJpWlxgieoSyERmJ+2t3b9ZpvsPJ7eBhMeT7MZvEi63LKweA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1627598082; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: references:references; bh=yhNFc6cu/Ud2vpLDU4lJ6f445JcsOy4OWzVjDs40Mro=; b=caphShy0MF3PngpoeM01saNrUGgl4KkkWzDGGrSzdJ7ljg4OfvWaIk35pUL9ELuyRCQzF7 tOXDBm3c1R4VhODg== Date: Thu, 29 Jul 2021 23:51:41 +0200 From: Thomas Gleixner To: LKML Cc: Alex Williamson , "Raj, Ashok" , "David S. Miller" , Bjorn Helgaas , linux-pci@vger.kernel.org, Kevin Tian , Marc Zyngier , Ingo Molnar , x86@kernel.org, linux-s390@vger.kernel.org, Niklas Schnelle , Gerald Schaefer , Heiko Carstens , Christian Borntraeger Subject: [patch V2 02/19] PCI/MSI: Mask all unused MSI-X entries References: <20210729215139.889204656@linutronix.de> MIME-Version: 1.0 Content-transfer-encoding: 8-bit Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Thomas Gleixner When MSI-X is enabled the ordering of calls is: msix_map_region(); msix_setup_entries(); pci_msi_setup_msi_irqs(); msix_program_entries(); This has a few interesting issues: 1) msix_setup_entries() allocates the MSI descriptors and initializes them except for the msi_desc:masked member which is left zero initialized. 2) pci_msi_setup_msi_irqs() allocates the interrupt descriptors and sets up the MSI interrupts which ends up in pci_write_msi_msg() unless the interrupt chip provides its own irq_write_msi_msg() function. 3) msix_program_entries() does not do what the name suggests. It solely updates the entries array (if not NULL) and initializes the masked member for each MSI descriptor by reading the hardware state and then masks the entry. Obviously this has some issues: 1) The uninitialized masked member of msi_desc prevents the enforcement of masking the entry in pci_write_msi_msg() depending on the cached masked bit. Aside of that half initialized data is a NONO in general 2) msix_program_entries() only ensures that the actually allocated entries are masked. This is wrong as experimentation with crash testing and crash kernel kexec has shown. This limited testing unearthed that when the production kernel had more entries in use and unmasked when it crashed and the crash kernel allocated a smaller amount of entries, then a full scan of all entries found unmasked entries which were in use in the production kernel. This is obviously a device or emulation issue as the device reset should mask all MSI-X table entries, but obviously that's just part of the paper specification. Cure this by: 1) Masking all table entries in hardware 2) Initializing msi_desc::masked in msix_setup_entries() 3) Removing the mask dance in msix_program_entries() 4) Renaming msix_program_entries() to msix_update_entries() to reflect the purpose of that function. As the masking of unused entries has never been done the Fixes tag refers to a commit in: git://git.kernel.org/pub/scm/linux/kernel/git/tglx/history.git Fixes: f036d4ea5fa7 ("[PATCH] ia32 Message Signalled Interrupt support") Signed-off-by: Thomas Gleixner Reviewed-by: Marc Zyngier Acked-by: Bjorn Helgaas --- drivers/pci/msi.c | 45 +++++++++++++++++++++++++++------------------ 1 file changed, 27 insertions(+), 18 deletions(-) --- a/drivers/pci/msi.c +++ b/drivers/pci/msi.c @@ -691,6 +691,7 @@ static int msix_setup_entries(struct pci { struct irq_affinity_desc *curmsk, *masks = NULL; struct msi_desc *entry; + void __iomem *addr; int ret, i; int vec_count = pci_msix_vec_count(dev); @@ -711,6 +712,7 @@ static int msix_setup_entries(struct pci entry->msi_attrib.is_msix = 1; entry->msi_attrib.is_64 = 1; + if (entries) entry->msi_attrib.entry_nr = entries[i].entry; else @@ -722,6 +724,10 @@ static int msix_setup_entries(struct pci entry->msi_attrib.default_irq = dev->irq; entry->mask_base = base; + addr = pci_msix_desc_addr(entry); + if (addr) + entry->masked = readl(addr + PCI_MSIX_ENTRY_VECTOR_CTRL); + list_add_tail(&entry->list, dev_to_msi_list(&dev->dev)); if (masks) curmsk++; @@ -732,26 +738,25 @@ static int msix_setup_entries(struct pci return ret; } -static void msix_program_entries(struct pci_dev *dev, - struct msix_entry *entries) +static void msix_update_entries(struct pci_dev *dev, struct msix_entry *entries) { struct msi_desc *entry; - int i = 0; - void __iomem *desc_addr; for_each_pci_msi_entry(entry, dev) { - if (entries) - entries[i++].vector = entry->irq; + if (entries) { + entries->vector = entry->irq; + entries++; + } + } +} - desc_addr = pci_msix_desc_addr(entry); - if (desc_addr) - entry->masked = readl(desc_addr + - PCI_MSIX_ENTRY_VECTOR_CTRL); - else - entry->masked = 0; +static void msix_mask_all(void __iomem *base, int tsize) +{ + u32 ctrl = PCI_MSIX_ENTRY_CTRL_MASKBIT; + int i; - msix_mask_irq(entry, 1); - } + for (i = 0; i < tsize; i++, base += PCI_MSIX_ENTRY_SIZE) + writel(ctrl, base + PCI_MSIX_ENTRY_VECTOR_CTRL); } /** @@ -768,9 +773,9 @@ static void msix_program_entries(struct static int msix_capability_init(struct pci_dev *dev, struct msix_entry *entries, int nvec, struct irq_affinity *affd) { - int ret; - u16 control; void __iomem *base; + int ret, tsize; + u16 control; /* * Some devices require MSI-X to be enabled before the MSI-X @@ -782,12 +787,16 @@ static int msix_capability_init(struct p pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); /* Request & Map MSI-X table region */ - base = msix_map_region(dev, msix_table_size(control)); + tsize = msix_table_size(control); + base = msix_map_region(dev, tsize); if (!base) { ret = -ENOMEM; goto out_disable; } + /* Ensure that all table entries are masked. */ + msix_mask_all(base, tsize); + ret = msix_setup_entries(dev, base, entries, nvec, affd); if (ret) goto out_disable; @@ -801,7 +810,7 @@ static int msix_capability_init(struct p if (ret) goto out_free; - msix_program_entries(dev, entries); + msix_update_entries(dev, entries); ret = populate_msi_sysfs(dev); if (ret) From patchwork Thu Jul 29 21:51:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 12409967 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-20.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 99DF1C43214 for ; Thu, 29 Jul 2021 22:34:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 82E7061019 for ; Thu, 29 Jul 2021 22:34:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233311AbhG2Wet (ORCPT ); Thu, 29 Jul 2021 18:34:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37746 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233158AbhG2Wes (ORCPT ); Thu, 29 Jul 2021 18:34:48 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2781EC061765; Thu, 29 Jul 2021 15:34:45 -0700 (PDT) Message-ID: <20210729222542.462096385@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1627598083; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: references:references; bh=2kT8gx5L4k5paCeWi2IrtDWSFtERCo0iFD5Y07fK3qA=; b=z/wjHw9b0sZrvBS0WSAQ/oCs0QVzJSXN+F1GXKNUWtY74rYlK6rr/5Df/6laBM/wfNHtZf rZXVBDVfncoi9PXh2fKmS59UFl8gIe+yQ1gtUau5e0uu9DUFM2Z/Vb13Aaq9wP4OHTi5vm MBCLTKsgAFyOILB/SaN9timh9WcIqw7oigsC7upmZLtHdR2Ijwx7TMnBVufyNy80DbhpNV ep7eLdsU618vygaSYQ1Fdus+sjkDaKCnjA/5iAB8LI3W63fh8mapdG+R0Y5dIYkvnw6Ytk CWqUJfb8G8oKZV+0I5jlaQ5zRqTlO0CEcC5fvP0G+Ng7BdNqK+4eOjFYv0g67A== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1627598083; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: references:references; bh=2kT8gx5L4k5paCeWi2IrtDWSFtERCo0iFD5Y07fK3qA=; b=m6E8c6wrpxkU+8toX89CUgIp7Lrka8nm3uT3YKgi9s1v0gnOae325HJLTS5tRw1rbgrrNO c06RzA2hqnRO1VDQ== Date: Thu, 29 Jul 2021 23:51:42 +0200 From: Thomas Gleixner To: LKML Cc: Alex Williamson , "Raj, Ashok" , "David S. Miller" , Bjorn Helgaas , linux-pci@vger.kernel.org, Kevin Tian , Marc Zyngier , Ingo Molnar , x86@kernel.org, linux-s390@vger.kernel.org, Niklas Schnelle , Gerald Schaefer , Heiko Carstens , Christian Borntraeger Subject: [patch V2 03/19] PCI/MSI: Enforce that MSI-X table entry is masked for update References: <20210729215139.889204656@linutronix.de> MIME-Version: 1.0 Content-transfer-encoding: 8-bit Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Thomas Gleixner The specification (PCIe r5.0, sec 6.1.4.5) states: For MSI-X, a function is permitted to cache Address and Data values from unmasked MSI-X Table entries. However, anytime software unmasks a currently masked MSI-X Table entry either by clearing its Mask bit or by clearing the Function Mask bit, the function must update any Address or Data values that it cached from that entry. If software changes the Address or Data value of an entry while the entry is unmasked, the result is undefined. The Linux kernel's MSI-X support never enforced that the entry is masked before the entry is modified hence the Fixes tag refers to a commit in: git://git.kernel.org/pub/scm/linux/kernel/git/tglx/history.git Enforce the entry to be masked across the update. There is no point in enforcing this to be handled at all possible call sites as this is just pointless code duplication and the common update function is the obvious place to enforce this. Fixes: f036d4ea5fa7 ("[PATCH] ia32 Message Signalled Interrupt support") Reported-by: Kevin Tian Signed-off-by: Thomas Gleixner Reviewed-by: Marc Zyngier Acked-by: Bjorn Helgaas --- drivers/pci/msi.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) --- a/drivers/pci/msi.c +++ b/drivers/pci/msi.c @@ -289,13 +289,28 @@ void __pci_write_msi_msg(struct msi_desc /* Don't touch the hardware now */ } else if (entry->msi_attrib.is_msix) { void __iomem *base = pci_msix_desc_addr(entry); + bool unmasked = !(entry->masked & PCI_MSIX_ENTRY_CTRL_MASKBIT); if (!base) goto skip; + /* + * The specification mandates that the entry is masked + * when the message is modified: + * + * "If software changes the Address or Data value of an + * entry while the entry is unmasked, the result is + * undefined." + */ + if (unmasked) + __pci_msix_desc_mask_irq(entry, PCI_MSIX_ENTRY_CTRL_MASKBIT); + writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR); writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR); writel(msg->data, base + PCI_MSIX_ENTRY_DATA); + + if (unmasked) + __pci_msix_desc_mask_irq(entry, 0); } else { int pos = dev->msi_cap; u16 msgctl; From patchwork Thu Jul 29 21:51:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 12409969 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-20.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2AAA5C4320A for ; Thu, 29 Jul 2021 22:34:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 17D1F61055 for ; Thu, 29 Jul 2021 22:34:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233341AbhG2Weu (ORCPT ); Thu, 29 Jul 2021 18:34:50 -0400 Received: from Galois.linutronix.de ([193.142.43.55]:49076 "EHLO galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233247AbhG2Wet (ORCPT ); Thu, 29 Jul 2021 18:34:49 -0400 Message-ID: <20210729222542.515188147@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1627598085; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: references:references; bh=Jk5SWiz4zixJPTPHbu/FUC3Ud8rM85M9ZKpgM4tFAHQ=; b=oynYxQGHwe7YFlYp72SfHF9qpOFMr9z+XbXN9t6LNltnPOPzI10qhsi4aVXgG3w2wBgJSa PAQorvzKkGtLMV21ukE5KZNKyGjdLOxoAVAr1RDn6aBiwPpHiQ2Jmsfp2jpvMYveco8zfK bie4iUIvUCXRaWF8/lkmMKSV7EmjoKO1fZpKCoS/hW+CUvupxFvxSWB7oDbAI9GH8Zc0oW 7qTX/uh01xpdCTnXnWSjpir/8Ko16jxp2Dz3ciiEl++oKQVKUtaH+aJqZZEMQF9SAWB3AM qtn9clB2U+S8mOMGxVLIsIn2CqjP5o+R1l4m0UfWiYprqZX1ZyxBW+xd5D2GTg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1627598085; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: references:references; bh=Jk5SWiz4zixJPTPHbu/FUC3Ud8rM85M9ZKpgM4tFAHQ=; b=PilEaf04chh3LEQY+bW6AWc6ThmBtbyWE9EHjoRe2Q3OqXNvl9VY0p/8SPsLRv1HoBpmuL zCfUVmjkMOY/WsBw== Date: Thu, 29 Jul 2021 23:51:43 +0200 From: Thomas Gleixner To: LKML Cc: Alex Williamson , "Raj, Ashok" , "David S. Miller" , Bjorn Helgaas , linux-pci@vger.kernel.org, Kevin Tian , Marc Zyngier , Ingo Molnar , x86@kernel.org, linux-s390@vger.kernel.org, Niklas Schnelle , Gerald Schaefer , Heiko Carstens , Christian Borntraeger Subject: [patch V2 04/19] PCI/MSI: Enforce MSI[X] entry updates to be visible References: <20210729215139.889204656@linutronix.de> MIME-Version: 1.0 Content-transfer-encoding: 8-bit Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Thomas Gleixner Nothing enforces the posted writes to be visible when the function returns. Flush them even if the flush might be redundant when the entry is masked already as the unmask will flush as well. This is either setup or a rare affinity change event so the extra flush is not the end of the world. While this is more a theoretical issue especially the logic in the X86 specific msi_set_affinity() function relies on the assumption that the update has reached the hardware when the function returns. Again, as this never has been enforced the Fixes tag refers to a commit in: git://git.kernel.org/pub/scm/linux/kernel/git/tglx/history.git Fixes: f036d4ea5fa7 ("[PATCH] ia32 Message Signalled Interrupt support") Signed-off-by: Thomas Gleixner Reviewed-by: Marc Zyngier Acked-by: Bjorn Helgaas --- drivers/pci/msi.c | 5 +++++ 1 file changed, 5 insertions(+) --- a/drivers/pci/msi.c +++ b/drivers/pci/msi.c @@ -311,6 +311,9 @@ void __pci_write_msi_msg(struct msi_desc if (unmasked) __pci_msix_desc_mask_irq(entry, 0); + + /* Ensure that the writes are visible in the device */ + readl(base + PCI_MSIX_ENTRY_DATA); } else { int pos = dev->msi_cap; u16 msgctl; @@ -331,6 +334,8 @@ void __pci_write_msi_msg(struct msi_desc pci_write_config_word(dev, pos + PCI_MSI_DATA_32, msg->data); } + /* Ensure that the writes are visible in the device */ + pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl); } skip: From patchwork Thu Jul 29 21:51:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 12409971 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0A315C4338F for ; Thu, 29 Jul 2021 22:34:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E181B6109D for ; Thu, 29 Jul 2021 22:34:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233413AbhG2Wey (ORCPT ); Thu, 29 Jul 2021 18:34:54 -0400 Received: from Galois.linutronix.de ([193.142.43.55]:49110 "EHLO galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233476AbhG2Wew (ORCPT ); Thu, 29 Jul 2021 18:34:52 -0400 Message-ID: <20210729222542.568173099@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1627598086; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: references:references; bh=e0Rg8yrqC6ByF4Ayj0lHWiTUdgX75JlD8npB4aXrydI=; b=PAW9Y/qOxI0ArBO+RbjV3Q6z1O7mYfJIX/7ME5tY4aCrEoT6ry0X9M0vH7GYeEoiAJgqKy 0OEbIr+DfeZD3kA5yV1Y0AidOUgXOBgag6/itAXSdzOlBqOJYIGsk1EVv/W/pmKjbIgIOG otQVZyOesyir/RmwWKUsOBbM1xlczYY7w3vReSZOtbiEzCpj2v2EZ/nhUYfWZmEhPWNOhm wSaiVbZrv5MTUtI8zv+49kh97tX/AV+BkVof4JTHW8k3HP/ehO5NJo+HFHyr9vxkyfCTIB HFLElDF9hJA/515YAgtUwLkRsouOgssBNFLJuuy9Fuk/h6QhTRGjrOL6qbUlTA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1627598086; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: references:references; bh=e0Rg8yrqC6ByF4Ayj0lHWiTUdgX75JlD8npB4aXrydI=; b=PgfzGnAC5dVd7xUw+4fdCRttRA+s0n6kcWisJrm1CCjNVx3nHonlb6PxPI61294cp8b6zE bpwZAT/b3sNUvkCA== Date: Thu, 29 Jul 2021 23:51:44 +0200 From: Thomas Gleixner To: LKML Cc: Alex Williamson , "Raj, Ashok" , "David S. Miller" , Bjorn Helgaas , linux-pci@vger.kernel.org, Kevin Tian , Marc Zyngier , Ingo Molnar , x86@kernel.org, linux-s390@vger.kernel.org, Niklas Schnelle , Gerald Schaefer , Heiko Carstens , Christian Borntraeger Subject: [patch V2 05/19] PCI/MSI: Do not set invalid bits in MSI mask References: <20210729215139.889204656@linutronix.de> MIME-Version: 1.0 Content-transfer-encoding: 8-bit Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org msi_mask_irq() takes a mask and a flags argument. The mask argument is used to mask out bits from the cached mask and the flags argument to set bits. Some places invoke it with a flags argument which sets bits which are not used by the device, i.e. when the device supports up to 8 vectors a full unmask in some places sets the mask to 0xFFFFFF00. While devices probably do not care, it's still bad practice. Fixes: 7ba1930db02f ("PCI MSI: Unmask MSI if setup failed") Signed-off-by: Thomas Gleixner --- V2: New patch --- drivers/pci/msi.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) --- a/drivers/pci/msi.c +++ b/drivers/pci/msi.c @@ -656,21 +656,21 @@ static int msi_capability_init(struct pc /* Configure MSI capability structure */ ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI); if (ret) { - msi_mask_irq(entry, mask, ~mask); + msi_mask_irq(entry, mask, 0); free_msi_irqs(dev); return ret; } ret = msi_verify_entries(dev); if (ret) { - msi_mask_irq(entry, mask, ~mask); + msi_mask_irq(entry, mask, 0); free_msi_irqs(dev); return ret; } ret = populate_msi_sysfs(dev); if (ret) { - msi_mask_irq(entry, mask, ~mask); + msi_mask_irq(entry, mask, 0); free_msi_irqs(dev); return ret; } @@ -962,7 +962,7 @@ static void pci_msi_shutdown(struct pci_ /* Return the device with MSI unmasked as initial states */ mask = msi_mask(desc->msi_attrib.multi_cap); /* Keep cached state to be restored */ - __pci_msi_desc_mask_irq(desc, mask, ~mask); + __pci_msi_desc_mask_irq(desc, mask, 0); /* Restore dev->irq to its default pin-assertion IRQ */ dev->irq = desc->msi_attrib.default_irq; From patchwork Thu Jul 29 21:51:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 12409973 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8CC98C4320A for ; Thu, 29 Jul 2021 22:34:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 75158610A0 for ; Thu, 29 Jul 2021 22:34:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234379AbhG2WfB (ORCPT ); Thu, 29 Jul 2021 18:35:01 -0400 Received: from Galois.linutronix.de ([193.142.43.55]:49134 "EHLO galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233586AbhG2Wex (ORCPT ); Thu, 29 Jul 2021 18:34:53 -0400 Message-ID: <20210729222542.621609423@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1627598088; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: references:references; bh=o7/zZ56Eqe+3Hqo1lY6fvcr08Gf8JGm1/pSYYMhs5e8=; b=g3S9BXQFyt3rvNWuWuEpt2gy02gWaWVRlb74t+2+ElrBtzTb0uqGmOVrR7yzEaHo8iaHWA l+kXpM7YHAhUABKtx6U3lPqMF8aLlSUi8ZXz3rQCuVYVfkNa9fJFCR+d/uC/CpGOxwBPFF 4DzC50Gr5R645FO0kBJu1uEIHUAFJH1plEqjbZ76+viFBKCiXLdDIEkC/JhJGz4QM+yll0 CuI+LKJzFayiDPwiPHwIqw98Qp7Pffc52zdfgcYGjr981wZeWIA6DLPIZSO9u+aWm4x8cM xIayc8CEUSJkUOOA7Ij/Q/Nt3Sr0Pycf0g+bcrLAeqqdIqu8idsK3rAZGbae7Q== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1627598088; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: references:references; bh=o7/zZ56Eqe+3Hqo1lY6fvcr08Gf8JGm1/pSYYMhs5e8=; b=IKVQjOWuih3kib5537AQMYxUhKsPIaQq1rWcg5FTro3uBqzMD0NaOW6oQtQJVaSo6+0+Sf 1MY3Oo8LvlbF7nDw== Date: Thu, 29 Jul 2021 23:51:45 +0200 From: Thomas Gleixner To: LKML Cc: Alex Williamson , "Raj, Ashok" , "David S. Miller" , Bjorn Helgaas , linux-pci@vger.kernel.org, Kevin Tian , Marc Zyngier , Ingo Molnar , x86@kernel.org, linux-s390@vger.kernel.org, Niklas Schnelle , Gerald Schaefer , Heiko Carstens , Christian Borntraeger Subject: [patch V2 06/19] PCI/MSI: Correct misleading comments References: <20210729215139.889204656@linutronix.de> MIME-Version: 1.0 Content-transfer-encoding: 8-bit Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The comments about preserving the cached state in pci_msi[x]_shutdown() are misleading as the MSI descriptors are freed right after those functions return. So there is nothing to restore. Signed-off-by: Thomas Gleixner --- V2: New patch --- drivers/pci/msi.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) --- a/drivers/pci/msi.c +++ b/drivers/pci/msi.c @@ -961,7 +961,6 @@ static void pci_msi_shutdown(struct pci_ /* Return the device with MSI unmasked as initial states */ mask = msi_mask(desc->msi_attrib.multi_cap); - /* Keep cached state to be restored */ __pci_msi_desc_mask_irq(desc, mask, 0); /* Restore dev->irq to its default pin-assertion IRQ */ @@ -1047,10 +1046,8 @@ static void pci_msix_shutdown(struct pci } /* Return the device with MSI-X masked as initial states */ - for_each_pci_msi_entry(entry, dev) { - /* Keep cached states to be restored */ + for_each_pci_msi_entry(entry, dev) __pci_msix_desc_mask_irq(entry, 1); - } pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0); pci_intx_for_msi(dev, 1); From patchwork Thu Jul 29 21:51:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 12409977 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 62E25C43214 for ; Thu, 29 Jul 2021 22:35:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4F61A61042 for ; Thu, 29 Jul 2021 22:35:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234496AbhG2WfD (ORCPT ); Thu, 29 Jul 2021 18:35:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37786 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233789AbhG2Wez (ORCPT ); Thu, 29 Jul 2021 18:34:55 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 671EDC0613D3; Thu, 29 Jul 2021 15:34:51 -0700 (PDT) Message-ID: <20210729222542.674391354@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1627598089; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: references:references; bh=UY7Ttb1P2PDak4c/kzI03Rybi1or7W0j7rcPz99XUrY=; b=Z0n2tOH7NXyi18R9oRGhVy1yctQl8ykx4HTIBIG0FHdMF/YvgKi/EpCAIzZakxfu5+8Aka 1hPbwtOVrE8uR6Gkd/ml/r8nXrcb9db6jnoVbEMQdQFDy2CLfABOvPPAN1kqdpSGVm1s8F RuKNFoJb/HCV1gDayY85O8lXUZKSS8ydVVBSDMSWiZWUIa0Fo38wUp0QvPdn7hFOBNe+px b0XiS2O4hGE0h3F4vH+RhcqLgOSQuK/uW+ZbAk1PTcp7oJlBNmKEjwYrG3XFa+rFLuLCKJ By0zK7E9pFgcEI9w5tKYSH6/YljT1bOPH91vQC5H5tID7aEjeCQLsmrxtqsC0A== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1627598089; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: references:references; bh=UY7Ttb1P2PDak4c/kzI03Rybi1or7W0j7rcPz99XUrY=; b=PuYcN3v0OZK4yT/dFu588ZKJ5xmX+Lo0rVvKzO1LrVq8zoy+ywQInBvjgoGBdgv/pQL3WV 2MdWZ/6qP7JOOmBg== Date: Thu, 29 Jul 2021 23:51:46 +0200 From: Thomas Gleixner To: LKML Cc: Alex Williamson , "Raj, Ashok" , "David S. Miller" , Bjorn Helgaas , linux-pci@vger.kernel.org, Kevin Tian , Marc Zyngier , Ingo Molnar , x86@kernel.org, linux-s390@vger.kernel.org, Niklas Schnelle , Gerald Schaefer , Heiko Carstens , Christian Borntraeger Subject: [patch V2 07/19] PCI/MSI: Use msi_mask_irq() in pci_msi_shutdown() References: <20210729215139.889204656@linutronix.de> MIME-Version: 1.0 Content-transfer-encoding: 8-bit Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org No point in using the raw write function from shutdown. Preparatory change to introduce proper serialization for the msi_desc::masked cache. Signed-off-by: Thomas Gleixner --- V2: New patch --- drivers/pci/msi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- a/drivers/pci/msi.c +++ b/drivers/pci/msi.c @@ -961,7 +961,7 @@ static void pci_msi_shutdown(struct pci_ /* Return the device with MSI unmasked as initial states */ mask = msi_mask(desc->msi_attrib.multi_cap); - __pci_msi_desc_mask_irq(desc, mask, 0); + msi_mask_irq(desc, mask, 0); /* Restore dev->irq to its default pin-assertion IRQ */ dev->irq = desc->msi_attrib.default_irq; From patchwork Thu Jul 29 21:51:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 12409975 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 54929C41537 for ; Thu, 29 Jul 2021 22:35:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3FEBD60F6F for ; Thu, 29 Jul 2021 22:35:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233017AbhG2WfE (ORCPT ); Thu, 29 Jul 2021 18:35:04 -0400 Received: from Galois.linutronix.de ([193.142.43.55]:49160 "EHLO galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233587AbhG2We4 (ORCPT ); Thu, 29 Jul 2021 18:34:56 -0400 Message-ID: <20210729222542.726833414@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1627598091; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: references:references; bh=2/+guVn6pKXxjnXZXmGYEd87x9t7hHiXlm8d23ff6Yg=; b=eNiS/2wBNtOsyWOLPdnGEu+t7rxF+oh9v8MH+zm8lskXycuA+McXaD1VY96WxnQ8KKwz+y pko9DqYyoTNHkh1wCqhzFp/ut0cCEB4AeOaYW4yeA0UFBaQHDBnARxJjlX8Bie5C8Xdnaw rty3CaJiVbdfHkUMe8CB496ALmKv1iyaECD3ketIHIXDAbfC7TGW3+pvgII/mEg7dt4fO6 vytnS5J/HIainYBcqaYLkU6ijjkPzhxI9Iu0werjSn68g6s/51ZgO1r1ltyA4SahNiKo3U QzTHZC8s4nZi1QhkLNsmgEu62DMpBfHffaCYw3r9+6nJE2R/vIQJz+Ge2LB23A== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1627598091; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: references:references; bh=2/+guVn6pKXxjnXZXmGYEd87x9t7hHiXlm8d23ff6Yg=; b=O3e3MytSFlaYzeCEMSDesSZqwMOLiuO/fWCFFR0JlJrjV9rMhexlYex8zXUcfO1vPxULkB hveEM6PY4QyG+yDg== Date: Thu, 29 Jul 2021 23:51:47 +0200 From: Thomas Gleixner To: LKML Cc: Alex Williamson , "Raj, Ashok" , "David S. Miller" , Bjorn Helgaas , linux-pci@vger.kernel.org, Kevin Tian , Marc Zyngier , Ingo Molnar , x86@kernel.org, linux-s390@vger.kernel.org, Niklas Schnelle , Gerald Schaefer , Heiko Carstens , Christian Borntraeger Subject: [patch V2 08/19] PCI/MSI: Protect msi_desc::masked for multi-MSI References: <20210729215139.889204656@linutronix.de> MIME-Version: 1.0 Content-transfer-encoding: 8-bit Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Multi-MSI uses a single MSI descriptor and there is a single mask register when the device supports per vector masking. To avoid reading back the mask register the value is cached in the MSI descriptor and updates are done by clearing and setting bits in the cache and writing it to the device. But nothing protects msi_desc::masked and the mask register from being modified concurrently on two different CPUs for two different Linux interrupts which belong to the same multi-MSI descriptor. Add a lock to struct device and protect any operation on the mask and the mask register with it. This makes the update of msi_desc::masked unconditional, but there is no place which requires a modification of the hardware register without updating the masked cache. msi_mask_irq() is now an empty wrapper which will be cleaned up in follow up changes. The problem goes way back to the initial support of multi-MSI, but picking the commit which introduced the mask cache is a valid cut off point (2.6.30). Fixes: f2440d9acbe8 ("PCI MSI: Refactor interrupt masking code") Signed-off-by: Thomas Gleixner --- drivers/base/core.c | 1 + drivers/pci/msi.c | 19 ++++++++++--------- include/linux/device.h | 1 + include/linux/msi.h | 2 +- 4 files changed, 13 insertions(+), 10 deletions(-) --- a/drivers/base/core.c +++ b/drivers/base/core.c @@ -2837,6 +2837,7 @@ void device_initialize(struct device *de device_pm_init(dev); set_dev_node(dev, -1); #ifdef CONFIG_GENERIC_MSI_IRQ + raw_spin_lock_init(&dev->msi_lock); INIT_LIST_HEAD(&dev->msi_list); #endif INIT_LIST_HEAD(&dev->links.consumers); --- a/drivers/pci/msi.c +++ b/drivers/pci/msi.c @@ -143,24 +143,25 @@ static inline __attribute_const__ u32 ms * reliably as devices without an INTx disable bit will then generate a * level IRQ which will never be cleared. */ -u32 __pci_msi_desc_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) +void __pci_msi_desc_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) { - u32 mask_bits = desc->masked; + raw_spinlock_t *lock = &desc->dev->msi_lock; + unsigned long flags; if (pci_msi_ignore_mask || !desc->msi_attrib.maskbit) - return 0; + return; - mask_bits &= ~mask; - mask_bits |= flag; + raw_spin_lock_irqsave(lock, flags); + desc->masked &= ~mask; + desc->masked |= flag; pci_write_config_dword(msi_desc_to_pci_dev(desc), desc->mask_pos, - mask_bits); - - return mask_bits; + desc->masked); + raw_spin_unlock_irqrestore(lock, flags); } static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) { - desc->masked = __pci_msi_desc_mask_irq(desc, mask, flag); + __pci_msi_desc_mask_irq(desc, mask, flag); } static void __iomem *pci_msix_desc_addr(struct msi_desc *desc) --- a/include/linux/device.h +++ b/include/linux/device.h @@ -506,6 +506,7 @@ struct device { struct dev_pin_info *pins; #endif #ifdef CONFIG_GENERIC_MSI_IRQ + raw_spinlock_t msi_lock; struct list_head msi_list; #endif #ifdef CONFIG_DMA_OPS --- a/include/linux/msi.h +++ b/include/linux/msi.h @@ -233,7 +233,7 @@ void __pci_read_msi_msg(struct msi_desc void __pci_write_msi_msg(struct msi_desc *entry, struct msi_msg *msg); u32 __pci_msix_desc_mask_irq(struct msi_desc *desc, u32 flag); -u32 __pci_msi_desc_mask_irq(struct msi_desc *desc, u32 mask, u32 flag); +void __pci_msi_desc_mask_irq(struct msi_desc *desc, u32 mask, u32 flag); void pci_msi_mask_irq(struct irq_data *data); void pci_msi_unmask_irq(struct irq_data *data); From patchwork Thu Jul 29 21:51:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 12409979 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B3A0EC43216 for ; Thu, 29 Jul 2021 22:35:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9BB9D60F6F for ; Thu, 29 Jul 2021 22:35:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233965AbhG2WfE (ORCPT ); Thu, 29 Jul 2021 18:35:04 -0400 Received: from Galois.linutronix.de ([193.142.43.55]:49186 "EHLO galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233946AbhG2We6 (ORCPT ); Thu, 29 Jul 2021 18:34:58 -0400 Message-ID: <20210729222542.779791738@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1627598093; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: references:references; bh=uXX28HYY446PuapxidtNu2nqv20CLiE7a8IJmT71Jlg=; b=k1QpCMhStWNPBZzmK5e6NGQuEeVINZ+PG5u0Dq0h4iLGawOZoZweHpM8EVE/dhTLanHlyL esO0WXVzGILcpb3tt6cI1TFKUkuI3Y11ZPgaagqOhkUecr5Yj4454PXjqt63WC2ieK/IcP J5Is0LJCtyxIM8OpDL1crQpt+e9XqFvGEnl1WDuJWIaAnW8zqWmYAAxAgCN+mQP6qCIr+V Z76yKPQ534VH9r3cFYq1IjfYwkj25ZZzyRckCc7q8waYozF0tIqJ1s7PwbHeu9hVX82arH fVbi6hYd9tX/13tbenOpnL4sWCPU5XdnRYCL7dvYuImvM/C1dgUNlybOv9+/Zw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1627598093; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: references:references; bh=uXX28HYY446PuapxidtNu2nqv20CLiE7a8IJmT71Jlg=; b=AUDZZ5yyToY3/ouqtEsRMstTXJN8tdr4OXGz7PY7miRjdijmmjF0snwv/USboisu5FaSSE OWIbbU/n4VT0YkCg== Date: Thu, 29 Jul 2021 23:51:48 +0200 From: Thomas Gleixner To: LKML Cc: Alex Williamson , "Raj, Ashok" , "David S. Miller" , Bjorn Helgaas , linux-pci@vger.kernel.org, Kevin Tian , Marc Zyngier , Ingo Molnar , x86@kernel.org, linux-s390@vger.kernel.org, Niklas Schnelle , Gerald Schaefer , Heiko Carstens , Christian Borntraeger Subject: [patch V2 09/19] genirq: Provide IRQCHIP_AFFINITY_PRE_STARTUP References: <20210729215139.889204656@linutronix.de> MIME-Version: 1.0 Content-transfer-encoding: 8-bit Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Thomas Gleixner X86 IO/APIC and MSI interrupts (when used without interrupts remapping) require that the affinity setup on startup is done before the interrupt is enabled for the first time as the non-remapped operation mode cannot safely migrate enabled interrupts from arbitrary contexts. Provide a new irq chip flag which allows affected hardware to request this. This has to be opt-in because there have been reports in the past that some interrupt chips cannot handle affinity setting before startup. Fixes: 18404756765c ("genirq: Expose default irq affinity mask (take 3)") Signed-off-by: Thomas Gleixner Reviewed-by: Marc Zyngier --- include/linux/irq.h | 2 ++ kernel/irq/chip.c | 5 ++++- 2 files changed, 6 insertions(+), 1 deletion(-) --- a/include/linux/irq.h +++ b/include/linux/irq.h @@ -569,6 +569,7 @@ struct irq_chip { * IRQCHIP_SUPPORTS_NMI: Chip can deliver NMIs, only for root irqchips * IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND: Invokes __enable_irq()/__disable_irq() for wake irqs * in the suspend path if they are in disabled state + * IRQCHIP_AFFINITY_PRE_STARTUP: Default affinity update before startup */ enum { IRQCHIP_SET_TYPE_MASKED = (1 << 0), @@ -581,6 +582,7 @@ enum { IRQCHIP_SUPPORTS_LEVEL_MSI = (1 << 7), IRQCHIP_SUPPORTS_NMI = (1 << 8), IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND = (1 << 9), + IRQCHIP_AFFINITY_PRE_STARTUP = (1 << 10), }; #include --- a/kernel/irq/chip.c +++ b/kernel/irq/chip.c @@ -265,8 +265,11 @@ int irq_startup(struct irq_desc *desc, b } else { switch (__irq_startup_managed(desc, aff, force)) { case IRQ_STARTUP_NORMAL: + if (d->chip->flags & IRQCHIP_AFFINITY_PRE_STARTUP) + irq_setup_affinity(desc); ret = __irq_startup(desc); - irq_setup_affinity(desc); + if (!(d->chip->flags & IRQCHIP_AFFINITY_PRE_STARTUP)) + irq_setup_affinity(desc); break; case IRQ_STARTUP_MANAGED: irq_do_set_affinity(d, aff, false); From patchwork Thu Jul 29 21:51:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 12409991 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 990A4C4320E for ; Thu, 29 Jul 2021 22:35:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8103D60F6F for ; Thu, 29 Jul 2021 22:35:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234520AbhG2WfR (ORCPT ); Thu, 29 Jul 2021 18:35:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37816 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234537AbhG2WfF (ORCPT ); Thu, 29 Jul 2021 18:35:05 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3A3F1C0617A5; Thu, 29 Jul 2021 15:34:56 -0700 (PDT) Message-ID: <20210729222542.832143400@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1627598094; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: references:references; bh=GHTKh4UC+3cHiKHivf/3mVjBEH0mFWprbVF8XAiQXIM=; b=jeCl9FoJl2MlO8vzlanvz1uGTg04MpSaLs31DceSx6WPAlKOx/AQdo1WjlhndrAEcvKJj4 U5ght6x3MCoIM8Z6NKJ/e0WrqFm7t1tCxeLXWjm6JNCf5FXUPTKHakYxJD+GVJZAXj9Spp jSI+fVaOYXB2PbYZ8Thk5gbMiFB6dtRc8Z7PF1hoVtUfDjYhJUP3yHuuUgsCkVnCLyr4cD ByVTJBkMXljDLVo4TgQCdvNK+LqfxlWruQTk6u96glw1YfilHLW83ZuLisuKThZeaqUCP/ QkkRitsuKVZCsZ4aFoP/WMtwQKgYlpkJ/ySJuVkMHYICVu9dYfkhVga2+F1tvg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1627598094; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: references:references; bh=GHTKh4UC+3cHiKHivf/3mVjBEH0mFWprbVF8XAiQXIM=; b=nzk+7ntFNMy11TbPDHkrvdjov5K5aeeZ1KtIaiO1RBWoIato6RaGOUJBHRlydY4nflRP2r eoqV001E73esWrAA== Date: Thu, 29 Jul 2021 23:51:49 +0200 From: Thomas Gleixner To: LKML Cc: Alex Williamson , "Raj, Ashok" , "David S. Miller" , Bjorn Helgaas , linux-pci@vger.kernel.org, Kevin Tian , Marc Zyngier , Ingo Molnar , x86@kernel.org, linux-s390@vger.kernel.org, Niklas Schnelle , Gerald Schaefer , Heiko Carstens , Christian Borntraeger Subject: [patch V2 10/19] x86/ioapic: Force affinity setup before startup References: <20210729215139.889204656@linutronix.de> MIME-Version: 1.0 Content-transfer-encoding: 8-bit Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Thomas Gleixner The IO/APIC cannot handle interrupt affinity changes safely after startup other than from an interrupt handler. The startup sequence in the generic interrupt code violates that assumption. Mark the irq chip with the new IRQCHIP_AFFINITY_PRE_STARTUP flag so that the default interrupt setting happens before the interrupt is started up for the first time. Fixes: 18404756765c ("genirq: Expose default irq affinity mask (take 3)") Signed-off-by: Thomas Gleixner Reviewed-by: Marc Zyngier --- arch/x86/kernel/apic/io_apic.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) --- a/arch/x86/kernel/apic/io_apic.c +++ b/arch/x86/kernel/apic/io_apic.c @@ -1986,7 +1986,8 @@ static struct irq_chip ioapic_chip __rea .irq_set_affinity = ioapic_set_affinity, .irq_retrigger = irq_chip_retrigger_hierarchy, .irq_get_irqchip_state = ioapic_irq_get_chip_state, - .flags = IRQCHIP_SKIP_SET_WAKE, + .flags = IRQCHIP_SKIP_SET_WAKE | + IRQCHIP_AFFINITY_PRE_STARTUP, }; static struct irq_chip ioapic_ir_chip __read_mostly = { @@ -1999,7 +2000,8 @@ static struct irq_chip ioapic_ir_chip __ .irq_set_affinity = ioapic_set_affinity, .irq_retrigger = irq_chip_retrigger_hierarchy, .irq_get_irqchip_state = ioapic_irq_get_chip_state, - .flags = IRQCHIP_SKIP_SET_WAKE, + .flags = IRQCHIP_SKIP_SET_WAKE | + IRQCHIP_AFFINITY_PRE_STARTUP, }; static inline void init_IO_APIC_traps(void) From patchwork Thu Jul 29 21:51:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 12409981 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7E292C432BE for ; Thu, 29 Jul 2021 22:35:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6C8FD61042 for ; Thu, 29 Jul 2021 22:35:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234610AbhG2WfH (ORCPT ); Thu, 29 Jul 2021 18:35:07 -0400 Received: from Galois.linutronix.de ([193.142.43.55]:49220 "EHLO galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233572AbhG2WfB (ORCPT ); Thu, 29 Jul 2021 18:35:01 -0400 Message-ID: <20210729222542.886722080@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1627598096; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: references:references; bh=jl2FVG8Tb5Gkgu6NJfnwgSDMfJ1zkBDjBBGZxXbBtkA=; b=pH0+ZcTYSAMxyeotnOP5RFC6FKF9xs9hURKzhPNKPNKJ2QXB+8bU3uaE4WKbB/vSpEBhYV 5hGKCVuPwZbBgAlAKP+3uulOPawsziBejuwvpdn66MWBDbCszPmQPqyqatH8+Bl6Lerxs5 OOpOcBUSs4O5Uhuj+SGCxruH7BUdY069vC5+eK9+V1f1+u+xZi2plOrAxZ2Dy4RNfTdlcl 0+Y5KdVpxl/PSNg5aRa8bVcCeU4yYuICsIiq0ZxDAETwo8zKNmgDwYkRStjM9FuSFKCiX0 7qFyKlWkF2l9BcyCSj3fd04q+K4RqeQzyksHWA/Y0i00FWxGmaRj+AVcqXR3tQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1627598096; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: references:references; bh=jl2FVG8Tb5Gkgu6NJfnwgSDMfJ1zkBDjBBGZxXbBtkA=; b=XtLnraXSso1tUPT2pkYzH5jJoOwaG+S6jjPbyay5e815sH8qE91jCq92G+/ELDIJ8ZawYu EJQvcHTf2maS6qAg== Date: Thu, 29 Jul 2021 23:51:50 +0200 From: Thomas Gleixner To: LKML Cc: Alex Williamson , "Raj, Ashok" , "David S. Miller" , Bjorn Helgaas , linux-pci@vger.kernel.org, Kevin Tian , Marc Zyngier , Ingo Molnar , x86@kernel.org, linux-s390@vger.kernel.org, Niklas Schnelle , Gerald Schaefer , Heiko Carstens , Christian Borntraeger Subject: [patch V2 11/19] x86/msi: Force affinity setup before startup References: <20210729215139.889204656@linutronix.de> MIME-Version: 1.0 Content-transfer-encoding: 8-bit Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Thomas Gleixner The X86 MSI mechanism cannot handle interrupt affinity changes safely after startup other than from an interrupt handler, unless interrupt remapping is enabled. The startup sequence in the generic interrupt code violates that assumption. Mark the irq chips with the new IRQCHIP_AFFINITY_PRE_STARTUP flag so that the default interrupt setting happens before the interrupt is started up for the first time. While the interrupt remapping MSI chip does not require this, there is no point in treating it differently as this might spare an interrupt to a CPU which is not in the default affinity mask. For the non-remapping case go to the direct write path when the interrupt is not yet started similar to the not yet activated case. Fixes: 18404756765c ("genirq: Expose default irq affinity mask (take 3)") Signed-off-by: Thomas Gleixner Reviewed-by: Marc Zyngier --- arch/x86/kernel/apic/msi.c | 11 ++++++++--- arch/x86/kernel/hpet.c | 2 +- 2 files changed, 9 insertions(+), 4 deletions(-) --- a/arch/x86/kernel/apic/msi.c +++ b/arch/x86/kernel/apic/msi.c @@ -58,11 +58,13 @@ msi_set_affinity(struct irq_data *irqd, * The quirk bit is not set in this case. * - The new vector is the same as the old vector * - The old vector is MANAGED_IRQ_SHUTDOWN_VECTOR (interrupt starts up) + * - The interrupt is not yet started up * - The new destination CPU is the same as the old destination CPU */ if (!irqd_msi_nomask_quirk(irqd) || cfg->vector == old_cfg.vector || old_cfg.vector == MANAGED_IRQ_SHUTDOWN_VECTOR || + !irqd_is_started(irqd) || cfg->dest_apicid == old_cfg.dest_apicid) { irq_msi_update_msg(irqd, cfg); return ret; @@ -150,7 +152,8 @@ static struct irq_chip pci_msi_controlle .irq_ack = irq_chip_ack_parent, .irq_retrigger = irq_chip_retrigger_hierarchy, .irq_set_affinity = msi_set_affinity, - .flags = IRQCHIP_SKIP_SET_WAKE, + .flags = IRQCHIP_SKIP_SET_WAKE | + IRQCHIP_AFFINITY_PRE_STARTUP, }; int pci_msi_prepare(struct irq_domain *domain, struct device *dev, int nvec, @@ -219,7 +222,8 @@ static struct irq_chip pci_msi_ir_contro .irq_mask = pci_msi_mask_irq, .irq_ack = irq_chip_ack_parent, .irq_retrigger = irq_chip_retrigger_hierarchy, - .flags = IRQCHIP_SKIP_SET_WAKE, + .flags = IRQCHIP_SKIP_SET_WAKE | + IRQCHIP_AFFINITY_PRE_STARTUP, }; static struct msi_domain_info pci_msi_ir_domain_info = { @@ -273,7 +277,8 @@ static struct irq_chip dmar_msi_controll .irq_retrigger = irq_chip_retrigger_hierarchy, .irq_compose_msi_msg = dmar_msi_compose_msg, .irq_write_msi_msg = dmar_msi_write_msg, - .flags = IRQCHIP_SKIP_SET_WAKE, + .flags = IRQCHIP_SKIP_SET_WAKE | + IRQCHIP_AFFINITY_PRE_STARTUP, }; static int dmar_msi_init(struct irq_domain *domain, --- a/arch/x86/kernel/hpet.c +++ b/arch/x86/kernel/hpet.c @@ -508,7 +508,7 @@ static struct irq_chip hpet_msi_controll .irq_set_affinity = msi_domain_set_affinity, .irq_retrigger = irq_chip_retrigger_hierarchy, .irq_write_msi_msg = hpet_msi_write_msg, - .flags = IRQCHIP_SKIP_SET_WAKE, + .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_AFFINITY_PRE_STARTUP, }; static int hpet_msi_init(struct irq_domain *domain, From patchwork Thu Jul 29 21:51:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 12409993 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 740CBC432BE for ; Thu, 29 Jul 2021 22:35:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5B9EA610A1 for ; Thu, 29 Jul 2021 22:35:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233398AbhG2WfS (ORCPT ); Thu, 29 Jul 2021 18:35:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37814 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234019AbhG2WfF (ORCPT ); Thu, 29 Jul 2021 18:35:05 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3F737C0613C1; Thu, 29 Jul 2021 15:34:59 -0700 (PDT) Message-ID: <20210729222542.939798136@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1627598097; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: references:references; bh=CWkvWsXP5joIr9x9FuJs2oTkmXN95ZjHWWuJ4EOrAb8=; b=s9d9Sv36yjh+ZyH5u1+2vJjlLuzSVEkLPeHehuLMcaLGsAG4kObUXNsC+HYP0c+J8mZtos 1+3e/Rz1y9dCe6OkZEdt2LOJd/DibOTe1Ai1s1HkIgnsAPPuG+E0FlvQHeXQC7Jnz4vylE 3AGFrD7LPSJ5EPndTbmVGK+2/URCzIOtgH8B0QkRv8qLK++ZI7xbYCcEayCykZtcAw12Hw 9/wr2r44spFddD0AUCryMEnUbDBtFkQEvNl+UFq4axmA5OPvi0f5IiphHFasXcXRFRWrie slt1FXp8S8kfQsNFj+A5ckJICQvUaIepXS0FKweYef/SUErFSPb97kp+8pTRHA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1627598097; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: references:references; bh=CWkvWsXP5joIr9x9FuJs2oTkmXN95ZjHWWuJ4EOrAb8=; b=LcaC8YufCcyzSpzgXf8ckLkdHBg7VCGyzq3yNglxvdlgVUQ7XjyMHSR+JN6YmlXX32UvCn HCoph775bw9w06Cg== Date: Thu, 29 Jul 2021 23:51:51 +0200 From: Thomas Gleixner To: LKML Cc: Alex Williamson , "Raj, Ashok" , "David S. Miller" , Bjorn Helgaas , linux-pci@vger.kernel.org, Kevin Tian , Marc Zyngier , Ingo Molnar , x86@kernel.org, linux-s390@vger.kernel.org, Niklas Schnelle , Gerald Schaefer , Heiko Carstens , Christian Borntraeger Subject: [patch V2 12/19] s390/pci: Do not mask MSI[-X] entries on teardown References: <20210729215139.889204656@linutronix.de> MIME-Version: 1.0 Content-transfer-encoding: 8-bit Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The PCI core already ensures that the MSI[-X] state is correct when MSI[-X] is disabled. For MSI the reset state is all entries unmasked and for MSI-X all vectors are masked. S390 masks all MSI entries and masks the already masked MSI-X entries again. Remove it and let the device in the correct state. Signed-off-by: Thomas Gleixner Cc: linux-s390@vger.kernel.org Cc: Niklas Schnelle Cc: Gerald Schaefer Cc: Heiko Carstens Cc: Christian Borntraeger Acked-by: Niklas Schnelle Tested-by: Niklas Schnelle --- arch/s390/pci/pci_irq.c | 4 ---- drivers/pci/msi.c | 4 ++-- include/linux/msi.h | 2 -- 3 files changed, 2 insertions(+), 8 deletions(-) --- a/arch/s390/pci/pci_irq.c +++ b/arch/s390/pci/pci_irq.c @@ -365,10 +365,6 @@ void arch_teardown_msi_irqs(struct pci_d for_each_pci_msi_entry(msi, pdev) { if (!msi->irq) continue; - if (msi->msi_attrib.is_msix) - __pci_msix_desc_mask_irq(msi, 1); - else - __pci_msi_desc_mask_irq(msi, 1, 1); irq_set_msi_desc(msi->irq, NULL); irq_free_desc(msi->irq); msi->msg.address_lo = 0; --- a/drivers/pci/msi.c +++ b/drivers/pci/msi.c @@ -143,7 +143,7 @@ static inline __attribute_const__ u32 ms * reliably as devices without an INTx disable bit will then generate a * level IRQ which will never be cleared. */ -void __pci_msi_desc_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) +static void __pci_msi_desc_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) { raw_spinlock_t *lock = &desc->dev->msi_lock; unsigned long flags; @@ -180,7 +180,7 @@ static void __iomem *pci_msix_desc_addr( * file. This saves a few milliseconds when initialising devices with lots * of MSI-X interrupts. */ -u32 __pci_msix_desc_mask_irq(struct msi_desc *desc, u32 flag) +static u32 __pci_msix_desc_mask_irq(struct msi_desc *desc, u32 flag) { u32 mask_bits = desc->masked; void __iomem *desc_addr; --- a/include/linux/msi.h +++ b/include/linux/msi.h @@ -232,8 +232,6 @@ void free_msi_entry(struct msi_desc *ent void __pci_read_msi_msg(struct msi_desc *entry, struct msi_msg *msg); void __pci_write_msi_msg(struct msi_desc *entry, struct msi_msg *msg); -u32 __pci_msix_desc_mask_irq(struct msi_desc *desc, u32 flag); -void __pci_msi_desc_mask_irq(struct msi_desc *desc, u32 mask, u32 flag); void pci_msi_mask_irq(struct irq_data *data); void pci_msi_unmask_irq(struct irq_data *data); From patchwork Thu Jul 29 21:51:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 12409989 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 90C20C432BE for ; Thu, 29 Jul 2021 22:35:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7983860F5E for ; Thu, 29 Jul 2021 22:35:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234891AbhG2WfQ (ORCPT ); Thu, 29 Jul 2021 18:35:16 -0400 Received: from Galois.linutronix.de ([193.142.43.55]:49160 "EHLO galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233247AbhG2WfE (ORCPT ); Thu, 29 Jul 2021 18:35:04 -0400 Message-ID: <20210729222542.992849326@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1627598099; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: references:references; bh=jjGNcCOmrTWZsysH9SrPCPLLXLLNsn5HmBKnKwQMdV0=; b=eGxF3/2rYX/oxGIsP5E1+vdSZLJQVIffwL2BHmA8k9+fdshGxN3kg+EjVyV0QedGGeLQcJ NDiJE2MertOtUmA6shOwfMr4h6tnWwgJbi8ioDdZ8pU75g3FQ04QXp/djLCp5X986PZP1f lzniFm2iIKSJDV1I4QlW+xYdJrrmlHvv2KDLWd9dc3ez9OCvJVrp9OfC+hPihzT7dL78fp RHkz+rGOYdlyOzFgnRL/kaNhnxgV2G+qz3/I4G4TadVI1Eo7e2Y6CaYQJJoffLd0+9FHq3 sbz7cgJk994eINShWlB2Ttk8GNcDDmu5Sus8BC24CIObnM1TFH4xw2WufZ5jcg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1627598099; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: references:references; bh=jjGNcCOmrTWZsysH9SrPCPLLXLLNsn5HmBKnKwQMdV0=; b=9rQAG6I7Q7FtxAZayHgKu164PZPVg3RTBmzS/kpfojkkPIEy81kSYSD1I6YvR7Sy3moAWK FWGBWWrJUO17SbDQ== Date: Thu, 29 Jul 2021 23:51:52 +0200 From: Thomas Gleixner To: LKML Cc: Alex Williamson , "Raj, Ashok" , "David S. Miller" , Bjorn Helgaas , linux-pci@vger.kernel.org, Kevin Tian , Marc Zyngier , Ingo Molnar , x86@kernel.org, linux-s390@vger.kernel.org, Niklas Schnelle , Gerald Schaefer , Heiko Carstens , Christian Borntraeger Subject: [patch V2 13/19] PCI/MSI: Simplify msi_verify_entries() References: <20210729215139.889204656@linutronix.de> MIME-Version: 1.0 Content-transfer-encoding: 8-bit Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Thomas Gleixner No point in looping over all entries when 64bit addressing mode is enabled for nothing. Signed-off-by: Thomas Gleixner Reviewed-by: Marc Zyngier Acked-by: Bjorn Helgaas --- drivers/pci/msi.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) --- a/drivers/pci/msi.c +++ b/drivers/pci/msi.c @@ -613,8 +613,11 @@ static int msi_verify_entries(struct pci { struct msi_desc *entry; + if (!dev->no_64bit_msi) + return 0; + for_each_pci_msi_entry(entry, dev) { - if (entry->msg.address_hi && dev->no_64bit_msi) { + if (entry->msg.address_hi) { pci_err(dev, "arch assigned 64-bit MSI address %#x%08x but device only supports 32 bits\n", entry->msg.address_hi, entry->msg.address_lo); return -EIO; From patchwork Thu Jul 29 21:51:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 12410001 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D63F2C4320A for ; Thu, 29 Jul 2021 22:35:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C166060F4B for ; Thu, 29 Jul 2021 22:35:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234758AbhG2Wfc (ORCPT ); Thu, 29 Jul 2021 18:35:32 -0400 Received: from Galois.linutronix.de ([193.142.43.55]:49220 "EHLO galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234157AbhG2WfG (ORCPT ); Thu, 29 Jul 2021 18:35:06 -0400 Message-ID: <20210729222543.045993608@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1627598101; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: references:references; bh=G8gQA2Hvd9tJ7CHOY+IkR1yc+vWQ4JZgR6mssB9yHa4=; b=w33s6zt0+y7ZqR3NSyKuA8XtQ2UFBIfomm87N2PPX2DshaTKExLdy9yPkdm2IuWDZ/eFAY KH3LujTG1wiJVTqG2zDXUYfP5+UY7OjtxZQ5Rw+/63I5LpDgid1ZeXy+CNF77fHT8hNGo+ DZol6qZPtFpDigXe+pPHtkWNuDnEWKzakrFNfIkYWChJS080TGDKHrRxpjCsbAsUzEZ5Ik iYX4bY1Om2ZHOFq2rVVy+D5ewymJp0jwgLUY9yxw5Y2SJoiKJUga0HE3E2jffStSbVTBUj RXfgunZ0KHdiI6ScoJNkvbj4h6+8LVyIFPsRqt75HlGEVkbhYE4JD1z1EONLfw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1627598101; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: references:references; bh=G8gQA2Hvd9tJ7CHOY+IkR1yc+vWQ4JZgR6mssB9yHa4=; b=ShafdiCyyOvmkxcq0R3499rKzklPUgxI9y9kkvRgYEGYJsx8KQAfQ2fgixc6ea4Cp5OAY3 V9/Sm46v7MExXvDQ== Date: Thu, 29 Jul 2021 23:51:53 +0200 From: Thomas Gleixner To: LKML Cc: Alex Williamson , "Raj, Ashok" , "David S. Miller" , Bjorn Helgaas , linux-pci@vger.kernel.org, Kevin Tian , Marc Zyngier , Ingo Molnar , x86@kernel.org, linux-s390@vger.kernel.org, Niklas Schnelle , Gerald Schaefer , Heiko Carstens , Christian Borntraeger Subject: [patch V2 14/19] PCI/MSI: Rename msi_desc::masked References: <20210729215139.889204656@linutronix.de> MIME-Version: 1.0 Content-transfer-encoding: 8-bit Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org msi_desc::masked is a misnomer. For MSI it's used to cache the MSI mask bits when the device supports per vector masking. For MSI-X it's used to cache the content of the vector control word which contains the mask bit for the vector. Replace it with a union of msi_mask and msix_ctrl to make the purpose clear and fix up the usage sites. No functional change Signed-off-by: Thomas Gleixner --- V2: New patch --- drivers/pci/msi.c | 30 +++++++++++++++--------------- include/linux/msi.h | 8 ++++++-- 2 files changed, 21 insertions(+), 17 deletions(-) --- a/drivers/pci/msi.c +++ b/drivers/pci/msi.c @@ -152,10 +152,10 @@ static void __pci_msi_desc_mask_irq(stru return; raw_spin_lock_irqsave(lock, flags); - desc->masked &= ~mask; - desc->masked |= flag; + desc->msi_mask &= ~mask; + desc->msi_mask |= flag; pci_write_config_dword(msi_desc_to_pci_dev(desc), desc->mask_pos, - desc->masked); + desc->msi_mask); raw_spin_unlock_irqrestore(lock, flags); } @@ -182,7 +182,7 @@ static void __iomem *pci_msix_desc_addr( */ static u32 __pci_msix_desc_mask_irq(struct msi_desc *desc, u32 flag) { - u32 mask_bits = desc->masked; + u32 ctrl = desc->msix_ctrl; void __iomem *desc_addr; if (pci_msi_ignore_mask) @@ -192,18 +192,18 @@ static u32 __pci_msix_desc_mask_irq(stru if (!desc_addr) return 0; - mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT; - if (flag & PCI_MSIX_ENTRY_CTRL_MASKBIT) - mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT; + ctrl &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT; + if (ctrl & PCI_MSIX_ENTRY_CTRL_MASKBIT) + ctrl |= PCI_MSIX_ENTRY_CTRL_MASKBIT; - writel(mask_bits, desc_addr + PCI_MSIX_ENTRY_VECTOR_CTRL); + writel(ctrl, desc_addr + PCI_MSIX_ENTRY_VECTOR_CTRL); - return mask_bits; + return ctrl; } static void msix_mask_irq(struct msi_desc *desc, u32 flag) { - desc->masked = __pci_msix_desc_mask_irq(desc, flag); + desc->msix_ctrl = __pci_msix_desc_mask_irq(desc, flag); } static void msi_set_mask_bit(struct irq_data *data, u32 flag) @@ -290,7 +290,7 @@ void __pci_write_msi_msg(struct msi_desc /* Don't touch the hardware now */ } else if (entry->msi_attrib.is_msix) { void __iomem *base = pci_msix_desc_addr(entry); - bool unmasked = !(entry->masked & PCI_MSIX_ENTRY_CTRL_MASKBIT); + bool unmasked = !(entry->msix_ctrl & PCI_MSIX_ENTRY_CTRL_MASKBIT); if (!base) goto skip; @@ -430,7 +430,7 @@ static void __pci_restore_msi_state(stru pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); msi_mask_irq(entry, msi_mask(entry->msi_attrib.multi_cap), - entry->masked); + entry->msi_mask); control &= ~PCI_MSI_FLAGS_QSIZE; control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE; pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); @@ -461,7 +461,7 @@ static void __pci_restore_msix_state(str arch_restore_msi_irqs(dev); for_each_pci_msi_entry(entry, dev) - msix_mask_irq(entry, entry->masked); + msix_mask_irq(entry, entry->msix_ctrl); pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0); } @@ -602,7 +602,7 @@ msi_setup_entry(struct pci_dev *dev, int /* Save the initial mask status */ if (entry->msi_attrib.maskbit) - pci_read_config_dword(dev, entry->mask_pos, &entry->masked); + pci_read_config_dword(dev, entry->mask_pos, &entry->msi_mask); out: kfree(masks); @@ -750,7 +750,7 @@ static int msix_setup_entries(struct pci addr = pci_msix_desc_addr(entry); if (addr) - entry->masked = readl(addr + PCI_MSIX_ENTRY_VECTOR_CTRL); + entry->msix_ctrl = readl(addr + PCI_MSIX_ENTRY_VECTOR_CTRL); list_add_tail(&entry->list, dev_to_msi_list(&dev->dev)); if (masks) --- a/include/linux/msi.h +++ b/include/linux/msi.h @@ -107,7 +107,8 @@ struct ti_sci_inta_msi_desc { * address or data changes * @write_msi_msg_data: Data parameter for the callback. * - * @masked: [PCI MSI/X] Mask bits + * @msi_mask: [PCI MSI] MSI cached mask bits + * @msix_ctrl: [PCI MSI-X] MSI-X cached per vector control bits * @is_msix: [PCI MSI/X] True if MSI-X * @multiple: [PCI MSI/X] log2 num of messages allocated * @multi_cap: [PCI MSI/X] log2 num of messages supported @@ -139,7 +140,10 @@ struct msi_desc { union { /* PCI MSI/X specific data */ struct { - u32 masked; + union { + u32 msi_mask; + u32 msix_ctrl; + }; struct { u8 is_msix : 1; u8 multiple : 3; From patchwork Thu Jul 29 21:51:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 12409999 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8D2E4C4338F for ; Thu, 29 Jul 2021 22:35:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6BE0D60F4B for ; Thu, 29 Jul 2021 22:35:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235028AbhG2Wf1 (ORCPT ); Thu, 29 Jul 2021 18:35:27 -0400 Received: from Galois.linutronix.de ([193.142.43.55]:49282 "EHLO galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234607AbhG2WfH (ORCPT ); Thu, 29 Jul 2021 18:35:07 -0400 Message-ID: <20210729222543.098828720@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1627598102; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: references:references; bh=6Hlz9b+gfajEt7fjlrTSAgtd7anX3wLVI1HqGJ1v/ZE=; b=1eQY5WI6T8vk8Is8/rdugbsg8/M8i3OlzgWpApUVPOHK27VqtdHGXq2SSSiN/s/Kj+too8 M/a6E0SE+dLKoqmbbqjGnv8sh1QDnXmGolpfP6aiTeOOwHUztPotFqDkWXOsfrYT+imhX8 AwU3SGZmh4XC0v+/4ne5DkDSakDCQxAkN+/vwuLg8RLFDgbIFUaUvBS0Z5jMmrCHDe/UYA oWwdPYUtK7imf28U7zxUGCQp2AXuVtqvP9R2w9HjMZbk8hIKZRjX02UU60c4bRtL/Y+V93 qapxcwjK0QrPPRfQ1BJHyMbnapDJliNWMhXKd+ep/cjA60W3u/JPIF6Haw6oHA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1627598102; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: references:references; bh=6Hlz9b+gfajEt7fjlrTSAgtd7anX3wLVI1HqGJ1v/ZE=; b=ar5xjcPRfN+qCCD6kJ6f+TNGmtzFvu534AEiUL76KoIvLBzo2LbIsjg3LUwcB9kmk719en cUpUbk6Lzzyp7JBA== Date: Thu, 29 Jul 2021 23:51:54 +0200 From: Thomas Gleixner To: LKML Cc: Alex Williamson , "Raj, Ashok" , "David S. Miller" , Bjorn Helgaas , linux-pci@vger.kernel.org, Kevin Tian , Marc Zyngier , Ingo Molnar , x86@kernel.org, linux-s390@vger.kernel.org, Niklas Schnelle , Gerald Schaefer , Heiko Carstens , Christian Borntraeger Subject: [patch V2 15/19] PCI/MSI: Consolidate error handling in msi_capability_init() References: <20210729215139.889204656@linutronix.de> MIME-Version: 1.0 Content-transfer-encoding: 8-bit Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Three error exits doing exactly the same ask for a common error exit point. Signed-off-by: Thomas Gleixner --- V2: New patch --- drivers/pci/msi.c | 26 +++++++++++--------------- 1 file changed, 11 insertions(+), 15 deletions(-) --- a/drivers/pci/msi.c +++ b/drivers/pci/msi.c @@ -659,25 +659,16 @@ static int msi_capability_init(struct pc /* Configure MSI capability structure */ ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI); - if (ret) { - msi_mask_irq(entry, mask, 0); - free_msi_irqs(dev); - return ret; - } + if (ret) + goto err; ret = msi_verify_entries(dev); - if (ret) { - msi_mask_irq(entry, mask, 0); - free_msi_irqs(dev); - return ret; - } + if (ret) + goto err; ret = populate_msi_sysfs(dev); - if (ret) { - msi_mask_irq(entry, mask, 0); - free_msi_irqs(dev); - return ret; - } + if (ret) + goto err; /* Set MSI enabled bits */ pci_intx_for_msi(dev, 0); @@ -687,6 +678,11 @@ static int msi_capability_init(struct pc pcibios_free_irq(dev); dev->irq = entry->irq; return 0; + +err: + msi_mask_irq(entry, mask, 0); + free_msi_irqs(dev); + return ret; } static void __iomem *msix_map_region(struct pci_dev *dev, unsigned nr_entries) From patchwork Thu Jul 29 21:51:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 12409997 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A6416C432BE for ; Thu, 29 Jul 2021 22:35:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 936D760FD7 for ; Thu, 29 Jul 2021 22:35:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234733AbhG2WfX (ORCPT ); Thu, 29 Jul 2021 18:35:23 -0400 Received: from Galois.linutronix.de ([193.142.43.55]:49294 "EHLO galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234650AbhG2WfI (ORCPT ); Thu, 29 Jul 2021 18:35:08 -0400 Message-ID: <20210729222543.151522318@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1627598103; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: references:references; bh=4d6jpf7VvfSCC5wDxxTlQqDwmyplaLXi1z26YEo5c+g=; b=k6cqmo7oDAI9dn6SAtLHM3xOJ7YfIzaMmn0zYmaLHw8+p+JOOHFdrCAr6dsrZHxEA1JlJX sbJYdL2Uarh0flzsFzbUZB/4/VnJ8zAiY579QdYjtC+9mxCKr7QCbrQzvd7FUr85XHQMld /xHqtjAm9EFpYv6MizgR7Kk12Q9N1XWQH+AYSQSJdUPv8KTTRk+j1P2hylaYrpuquAroVF oBkcEq1m8m05yWIvLjcgYAMHMA3aWVVlMyLbfXs+VaOX8nMau77j/mI97WP5lJ5lNCwNOe DoJjfS/7jdplfOJ3rAFwF/FoLMcqV0Ac1qLStBZy2h1LkSiA9EINHchL02tS3A== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1627598103; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: references:references; bh=4d6jpf7VvfSCC5wDxxTlQqDwmyplaLXi1z26YEo5c+g=; b=qlyKSNm+nB2ii1MzIVL8ZeVE1LmzcDswofdWBSGQHuwVaSpjYrZgbOWS9UizJCyT5ohuVH 7cFjIru2/Z4UjLBQ== Date: Thu, 29 Jul 2021 23:51:55 +0200 From: Thomas Gleixner To: LKML Cc: Alex Williamson , "Raj, Ashok" , "David S. Miller" , Bjorn Helgaas , linux-pci@vger.kernel.org, Kevin Tian , Marc Zyngier , Ingo Molnar , x86@kernel.org, linux-s390@vger.kernel.org, Niklas Schnelle , Gerald Schaefer , Heiko Carstens , Christian Borntraeger Subject: [patch V2 16/19] PCI/MSI: Deobfuscate virtual MSI-X References: <20210729215139.889204656@linutronix.de> MIME-Version: 1.0 Content-transfer-encoding: 8-bit Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Handling of virtual MSI-X is obfuscated by letting pci_msix_desc_addr() return NULL and checking the pointer. Just use msi_desc::msi_attrib.is_virtual at the call sites and get rid of that pointer check. No functional change. Signed-off-by: Thomas Gleixner --- V2: New patch --- drivers/pci/msi.c | 25 ++++++++----------------- 1 file changed, 8 insertions(+), 17 deletions(-) --- a/drivers/pci/msi.c +++ b/drivers/pci/msi.c @@ -166,11 +166,7 @@ static void msi_mask_irq(struct msi_desc static void __iomem *pci_msix_desc_addr(struct msi_desc *desc) { - if (desc->msi_attrib.is_virtual) - return NULL; - - return desc->mask_base + - desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; + return desc->mask_base + desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; } /* @@ -182,14 +178,10 @@ static void __iomem *pci_msix_desc_addr( */ static u32 __pci_msix_desc_mask_irq(struct msi_desc *desc, u32 flag) { + void __iomem *desc_addr = pci_msix_desc_addr(desc); u32 ctrl = desc->msix_ctrl; - void __iomem *desc_addr; - - if (pci_msi_ignore_mask) - return 0; - desc_addr = pci_msix_desc_addr(desc); - if (!desc_addr) + if (pci_msi_ignore_mask || desc->msi_attrib.is_virtual) return 0; ctrl &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT; @@ -256,10 +248,8 @@ void __pci_read_msi_msg(struct msi_desc if (entry->msi_attrib.is_msix) { void __iomem *base = pci_msix_desc_addr(entry); - if (!base) { - WARN_ON(1); + if (WARN_ON_ONCE(entry->msi_attrib.is_virtual)) return; - } msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR); msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR); @@ -292,7 +282,7 @@ void __pci_write_msi_msg(struct msi_desc void __iomem *base = pci_msix_desc_addr(entry); bool unmasked = !(entry->msix_ctrl & PCI_MSIX_ENTRY_CTRL_MASKBIT); - if (!base) + if (entry->msi_attrib.is_virtual) goto skip; /* @@ -744,9 +734,10 @@ static int msix_setup_entries(struct pci entry->msi_attrib.default_irq = dev->irq; entry->mask_base = base; - addr = pci_msix_desc_addr(entry); - if (addr) + if (!entry->msi_attrib.is_virtual) { + addr = pci_msix_desc_addr(entry); entry->msix_ctrl = readl(addr + PCI_MSIX_ENTRY_VECTOR_CTRL); + } list_add_tail(&entry->list, dev_to_msi_list(&dev->dev)); if (masks) From patchwork Thu Jul 29 21:51:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 12409995 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1192EC4338F for ; Thu, 29 Jul 2021 22:35:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id ED77A60F6F for ; Thu, 29 Jul 2021 22:35:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234812AbhG2WfW (ORCPT ); Thu, 29 Jul 2021 18:35:22 -0400 Received: from Galois.linutronix.de ([193.142.43.55]:49312 "EHLO galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233789AbhG2WfK (ORCPT ); Thu, 29 Jul 2021 18:35:10 -0400 Message-ID: <20210729222543.203905260@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1627598105; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: references:references; bh=uZuaut2JpvGfn2gpCKX+rCbymLOSgSIekmfYPWe2CMk=; b=nqOaLIUOaTou1DdTA5UvWBfb6j3F1E4jjCsClod7GaYzSXZ4LA/RTex8nTet6F44vLEoPi P/wrf2wzvGC6kTvQO5rkJJl/kVPeuqhGHeBMORRTYYffUaVF6z9FALexoQo1Tpc+IXPNi6 lOFgbKV7fSj4cvLAfqUy0zClZk3Z49K6o62bIaRsyiQOQbs71sAQfEf5tSrRct7umuDii8 QfAXTpiptOzUFqOSL9SYWacCITKpmjIcWsQp/dBeVBhvnrOWXpNSn74YVuFugN+ElhkbKN uoJinNE56XZ6srDKlBLuU/XEt0FrJfh2giY/AXAgy+oNyLgTsLVIqD1DZuj3Gg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1627598105; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: references:references; bh=uZuaut2JpvGfn2gpCKX+rCbymLOSgSIekmfYPWe2CMk=; b=QlTuqPb25LezbZyhxPwNdR0kY61X5X2sJJGk373lsnIIUq02gvWjIcWoq38Ge2Yke+qGCq 3Mf6AI2iHqpBJbBg== Date: Thu, 29 Jul 2021 23:51:56 +0200 From: Thomas Gleixner To: LKML Cc: Alex Williamson , "Raj, Ashok" , "David S. Miller" , Bjorn Helgaas , linux-pci@vger.kernel.org, Kevin Tian , Marc Zyngier , Ingo Molnar , x86@kernel.org, linux-s390@vger.kernel.org, Niklas Schnelle , Gerald Schaefer , Heiko Carstens , Christian Borntraeger Subject: [patch V2 17/19] PCI/MSI: Cleanup msi_mask() References: <20210729215139.889204656@linutronix.de> MIME-Version: 1.0 Content-transfer-encoding: 8-bit Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org msi_mask() is calculating the possible mask bits for MSI per vector masking. Rename it to msi_multi_mask() and hand the MSI descriptor pointer into it to simplify the call sites. Signed-off-by: Thomas Gleixner --- V2: New patch --- drivers/pci/msi.c | 25 +++++++++++-------------- 1 file changed, 11 insertions(+), 14 deletions(-) --- a/drivers/pci/msi.c +++ b/drivers/pci/msi.c @@ -129,14 +129,6 @@ void __weak arch_restore_msi_irqs(struct return default_restore_msi_irqs(dev); } -static inline __attribute_const__ u32 msi_mask(unsigned x) -{ - /* Don't shift by >= width of type */ - if (x >= 5) - return 0xffffffff; - return (1 << (1 << x)) - 1; -} - /* * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to * mask all MSI interrupts by clearing the MSI enable bit does not work @@ -211,6 +203,14 @@ static void msi_set_mask_bit(struct irq_ } } +static inline __attribute_const__ u32 msi_multi_mask(struct msi_desc *desc) +{ + /* Don't shift by >= width of type */ + if (desc->msi_attrib.multi_cap >= 5) + return 0xffffffff; + return (1 << (1 << desc->msi_attrib.multi_cap)) - 1; +} + /** * pci_msi_mask_irq - Generic IRQ chip callback to mask PCI/MSI interrupts * @data: pointer to irqdata associated to that interrupt @@ -419,8 +419,7 @@ static void __pci_restore_msi_state(stru arch_restore_msi_irqs(dev); pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); - msi_mask_irq(entry, msi_mask(entry->msi_attrib.multi_cap), - entry->msi_mask); + msi_mask_irq(entry, msi_multi_mask(entry), entry->msi_mask); control &= ~PCI_MSI_FLAGS_QSIZE; control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE; pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); @@ -642,7 +641,7 @@ static int msi_capability_init(struct pc return -ENOMEM; /* All MSIs are unmasked by default; mask them all */ - mask = msi_mask(entry->msi_attrib.multi_cap); + mask = msi_multi_mask(entry); msi_mask_irq(entry, mask, mask); list_add_tail(&entry->list, dev_to_msi_list(&dev->dev)); @@ -938,7 +937,6 @@ EXPORT_SYMBOL(pci_msi_vec_count); static void pci_msi_shutdown(struct pci_dev *dev) { struct msi_desc *desc; - u32 mask; if (!pci_msi_enable || !dev || !dev->msi_enabled) return; @@ -951,8 +949,7 @@ static void pci_msi_shutdown(struct pci_ dev->msi_enabled = 0; /* Return the device with MSI unmasked as initial states */ - mask = msi_mask(desc->msi_attrib.multi_cap); - msi_mask_irq(desc, mask, 0); + msi_mask_irq(desc, msi_multi_mask(desc), 0); /* Restore dev->irq to its default pin-assertion IRQ */ dev->irq = desc->msi_attrib.default_irq; From patchwork Thu Jul 29 21:51:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 12410003 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.0 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, UNWANTED_LANGUAGE_BODY,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 01A50C4320E for ; Thu, 29 Jul 2021 22:35:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E1BB1610A1 for ; Thu, 29 Jul 2021 22:35:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234819AbhG2Wfu (ORCPT ); Thu, 29 Jul 2021 18:35:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37888 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234449AbhG2WfM (ORCPT ); Thu, 29 Jul 2021 18:35:12 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F30ECC06179E; Thu, 29 Jul 2021 15:35:08 -0700 (PDT) Message-ID: <20210729222543.257079238@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1627598107; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: references:references; bh=qCOSKfEnl3o4/mZfiuDpWaLIrkNMwSoGIlOo9G4CfEE=; b=YbzP5MrRXs1pMhsPQrfSBxalc/mCCCJnrFrY22Zhg5CqXFXtjQX42T9rLthXL0zTb/m3A2 4s+X188gD48e3u42Km39KjwsntsGurGCgnY8tLIdbRI79T042bLGaF8jKVuvtOJJbRhHeU h63gNh+jDPaHN52tQmPRCIYJa97VkGMakDnq3kDzvZaTJVqideMtMbafrt7fhnGbrdUvy4 bsq7O1ZtyFmWLofnhPcoRKqCXE6ZzXMAt2sswRS6xYkU0h12efgLroVqq1jchTVk4V3d6z FZc53M8DXQ0pcqVlEQVQYw6gJfps4SCSCpHdAxJULLmsPoRD4z0/Ua0lu74dww== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1627598107; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: references:references; bh=qCOSKfEnl3o4/mZfiuDpWaLIrkNMwSoGIlOo9G4CfEE=; b=3LHWmLNrasrWI5g7TAO4i8R1vj9nIw0rSzMKCNKf7KD/DC6bl9itmjLN13QMOfgUa9HrM6 iudZJmtq19TM3GBQ== Date: Thu, 29 Jul 2021 23:51:57 +0200 From: Thomas Gleixner To: LKML Cc: Alex Williamson , "Raj, Ashok" , "David S. Miller" , Bjorn Helgaas , linux-pci@vger.kernel.org, Kevin Tian , Marc Zyngier , Ingo Molnar , x86@kernel.org, linux-s390@vger.kernel.org, Niklas Schnelle , Gerald Schaefer , Heiko Carstens , Christian Borntraeger Subject: [patch V2 18/19] PCI/MSI: Provide a new set of mask and unmask functions References: <20210729215139.889204656@linutronix.de> MIME-Version: 1.0 Content-transfer-encoding: 8-bit Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The existing mask/unmask functions are convoluted and generate suboptimal assembly code. Provide a new set of functions which will be used in later patches to replace the exisiting ones. Signed-off-by: Thomas Gleixner --- V2: New patch --- drivers/pci/msi.c | 72 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) --- a/drivers/pci/msi.c +++ b/drivers/pci/msi.c @@ -211,6 +211,78 @@ static inline __attribute_const__ u32 ms return (1 << (1 << desc->msi_attrib.multi_cap)) - 1; } +static noinline void pci_msi_update_mask(struct msi_desc *desc, u32 clear, u32 set) +{ + raw_spinlock_t *lock = &desc->dev->msi_lock; + unsigned long flags; + + raw_spin_lock_irqsave(lock, flags); + desc->msi_mask &= ~clear; + desc->msi_mask |= set; + pci_write_config_dword(msi_desc_to_pci_dev(desc), desc->mask_pos, + desc->msi_mask); + raw_spin_unlock_irqrestore(lock, flags); +} + +static inline void pci_msi_mask(struct msi_desc *desc, u32 mask) +{ + pci_msi_update_mask(desc, 0, mask); +} + +static inline void pci_msi_unmask(struct msi_desc *desc, u32 mask) +{ + pci_msi_update_mask(desc, mask, 0); +} + +/* + * This internal function does not flush PCI writes to the device. All + * users must ensure that they read from the device before either assuming + * that the device state is up to date, or returning out of this file. + * It does not affect the msi_desc::msix_ctrl cache either. Use with care! + */ +static void pci_msix_write_vector_ctrl(struct msi_desc *desc, u32 ctrl) +{ + void __iomem *desc_addr = pci_msix_desc_addr(desc); + + writel(ctrl, desc_addr + PCI_MSIX_ENTRY_VECTOR_CTRL); +} + +static inline void pci_msix_mask(struct msi_desc *desc) +{ + desc->msix_ctrl |= PCI_MSIX_ENTRY_CTRL_MASKBIT; + pci_msix_write_vector_ctrl(desc, desc->msix_ctrl); + /* Flush write to device */ + readl(desc->mask_base); +} + +static inline void pci_msix_unmask(struct msi_desc *desc) +{ + desc->msix_ctrl &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT; + pci_msix_write_vector_ctrl(desc, desc->msix_ctrl); +} + +static void __pci_msi_mask_desc(struct msi_desc *desc, u32 mask) +{ + if (pci_msi_ignore_mask || desc->msi_attrib.is_virtual) + return; + + if (desc->msi_attrib.is_msix) + pci_msix_mask(desc); + else if (!desc->msi_attrib.maskbit) + pci_msi_mask(desc, mask); +} + +static void __pci_msi_unmask_desc(struct msi_desc *desc, u32 mask) +{ + if (pci_msi_ignore_mask || desc->msi_attrib.is_virtual) + return; + + if (desc->msi_attrib.is_msix) + pci_msix_unmask(desc); + else if (!desc->msi_attrib.maskbit) + pci_msi_unmask(desc, mask); +} + /** * pci_msi_mask_irq - Generic IRQ chip callback to mask PCI/MSI interrupts * @data: pointer to irqdata associated to that interrupt From patchwork Thu Jul 29 21:51:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 12410005 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 608B8C43216 for ; Thu, 29 Jul 2021 22:35:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3DD4C60F4B for ; Thu, 29 Jul 2021 22:35:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235249AbhG2Wfw (ORCPT ); Thu, 29 Jul 2021 18:35:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37844 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234445AbhG2WfQ (ORCPT ); Thu, 29 Jul 2021 18:35:16 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 78AE3C0617A0; Thu, 29 Jul 2021 15:35:10 -0700 (PDT) Message-ID: <20210729222543.311207034@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1627598108; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: references:references; bh=0EFERMseOgGp4ED8VGrniueRywqbBbmEkuB4rNqG78M=; b=iK0/YPv7B6vrRwygNr/aWJnd4VVkL1ZKn2kQxcI/dQnLtz4ft5VuCOlaqUc0kIiEGBJBBN GugXI1BpHhXUee/zOtQ3QYIkQtoADzIgpO66fLYCUXA99uL/eVGkBU8+FjaNVFSDh90xOx ttbd4eCIlG4LzZPnOdODCjUZEAUmpm+A5ttd92ox6GYtcI6rILn2yd0kYasy8M2/MzGZlQ dfb4A1+oNObxX+o9RjZR7UwxskIYDhgotxxjBsMZqaUjFq4GsXZMIsJSGzhxRk56UP4dbb G+YAA0m5fmB2uw21y2YeLNLkVrTZio7gl7BtTbjZmL4b7s52vrzu9mgn4SGYXw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1627598108; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: references:references; bh=0EFERMseOgGp4ED8VGrniueRywqbBbmEkuB4rNqG78M=; b=rAEPIoE0COfVWKBOWFxx8T9/cGARQwv/RBsWXCm3fq8hcG1iXWzNzYxnWm4W/QkhcApOdC uLZsHfb3XCaAhiCA== Date: Thu, 29 Jul 2021 23:51:58 +0200 From: Thomas Gleixner To: LKML Cc: Alex Williamson , "Raj, Ashok" , "David S. Miller" , Bjorn Helgaas , linux-pci@vger.kernel.org, Kevin Tian , Marc Zyngier , Ingo Molnar , x86@kernel.org, linux-s390@vger.kernel.org, Niklas Schnelle , Gerald Schaefer , Heiko Carstens , Christian Borntraeger Subject: [patch V2 19/19] PCI/MSI: Use new mask/unmask functions References: <20210729215139.889204656@linutronix.de> MIME-Version: 1.0 Content-transfer-encoding: 8-bit Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Switch the PCI/MSI core to use the new mask/unmask functions. No functional change. Signed-off-by: Thomas Gleixner --- V2: New patch --- drivers/pci/msi.c | 102 +++++++++++------------------------------------------- 1 file changed, 21 insertions(+), 81 deletions(-) --- a/drivers/pci/msi.c +++ b/drivers/pci/msi.c @@ -135,74 +135,6 @@ void __weak arch_restore_msi_irqs(struct * reliably as devices without an INTx disable bit will then generate a * level IRQ which will never be cleared. */ -static void __pci_msi_desc_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) -{ - raw_spinlock_t *lock = &desc->dev->msi_lock; - unsigned long flags; - - if (pci_msi_ignore_mask || !desc->msi_attrib.maskbit) - return; - - raw_spin_lock_irqsave(lock, flags); - desc->msi_mask &= ~mask; - desc->msi_mask |= flag; - pci_write_config_dword(msi_desc_to_pci_dev(desc), desc->mask_pos, - desc->msi_mask); - raw_spin_unlock_irqrestore(lock, flags); -} - -static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) -{ - __pci_msi_desc_mask_irq(desc, mask, flag); -} - -static void __iomem *pci_msix_desc_addr(struct msi_desc *desc) -{ - return desc->mask_base + desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; -} - -/* - * This internal function does not flush PCI writes to the device. - * All users must ensure that they read from the device before either - * assuming that the device state is up to date, or returning out of this - * file. This saves a few milliseconds when initialising devices with lots - * of MSI-X interrupts. - */ -static u32 __pci_msix_desc_mask_irq(struct msi_desc *desc, u32 flag) -{ - void __iomem *desc_addr = pci_msix_desc_addr(desc); - u32 ctrl = desc->msix_ctrl; - - if (pci_msi_ignore_mask || desc->msi_attrib.is_virtual) - return 0; - - ctrl &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT; - if (ctrl & PCI_MSIX_ENTRY_CTRL_MASKBIT) - ctrl |= PCI_MSIX_ENTRY_CTRL_MASKBIT; - - writel(ctrl, desc_addr + PCI_MSIX_ENTRY_VECTOR_CTRL); - - return ctrl; -} - -static void msix_mask_irq(struct msi_desc *desc, u32 flag) -{ - desc->msix_ctrl = __pci_msix_desc_mask_irq(desc, flag); -} - -static void msi_set_mask_bit(struct irq_data *data, u32 flag) -{ - struct msi_desc *desc = irq_data_get_msi_desc(data); - - if (desc->msi_attrib.is_msix) { - msix_mask_irq(desc, flag); - readl(desc->mask_base); /* Flush write to device */ - } else { - unsigned offset = data->irq - desc->irq; - msi_mask_irq(desc, 1 << offset, flag << offset); - } -} - static inline __attribute_const__ u32 msi_multi_mask(struct msi_desc *desc) { /* Don't shift by >= width of type */ @@ -234,6 +166,11 @@ static inline void pci_msi_unmask(struct pci_msi_update_mask(desc, mask, 0); } +static inline void __iomem *pci_msix_desc_addr(struct msi_desc *desc) +{ + return desc->mask_base + desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; +} + /* * This internal function does not flush PCI writes to the device. All * users must ensure that they read from the device before either assuming @@ -289,7 +226,9 @@ static void __pci_msi_unmask_desc(struct */ void pci_msi_mask_irq(struct irq_data *data) { - msi_set_mask_bit(data, 1); + struct msi_desc *desc = irq_data_get_msi_desc(data); + + __pci_msi_mask_desc(desc, BIT(data->irq - desc->irq)); } EXPORT_SYMBOL_GPL(pci_msi_mask_irq); @@ -299,7 +238,9 @@ EXPORT_SYMBOL_GPL(pci_msi_mask_irq); */ void pci_msi_unmask_irq(struct irq_data *data) { - msi_set_mask_bit(data, 0); + struct msi_desc *desc = irq_data_get_msi_desc(data); + + __pci_msi_unmask_desc(desc, BIT(data->irq - desc->irq)); } EXPORT_SYMBOL_GPL(pci_msi_unmask_irq); @@ -352,7 +293,8 @@ void __pci_write_msi_msg(struct msi_desc /* Don't touch the hardware now */ } else if (entry->msi_attrib.is_msix) { void __iomem *base = pci_msix_desc_addr(entry); - bool unmasked = !(entry->msix_ctrl & PCI_MSIX_ENTRY_CTRL_MASKBIT); + u32 ctrl = entry->msix_ctrl; + bool unmasked = !(ctrl & PCI_MSIX_ENTRY_CTRL_MASKBIT); if (entry->msi_attrib.is_virtual) goto skip; @@ -366,14 +308,14 @@ void __pci_write_msi_msg(struct msi_desc * undefined." */ if (unmasked) - __pci_msix_desc_mask_irq(entry, PCI_MSIX_ENTRY_CTRL_MASKBIT); + pci_msix_write_vector_ctrl(entry, ctrl | PCI_MSIX_ENTRY_CTRL_MASKBIT); writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR); writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR); writel(msg->data, base + PCI_MSIX_ENTRY_DATA); if (unmasked) - __pci_msix_desc_mask_irq(entry, 0); + pci_msix_write_vector_ctrl(entry, ctrl); /* Ensure that the writes are visible in the device */ readl(base + PCI_MSIX_ENTRY_DATA); @@ -491,7 +433,7 @@ static void __pci_restore_msi_state(stru arch_restore_msi_irqs(dev); pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); - msi_mask_irq(entry, msi_multi_mask(entry), entry->msi_mask); + pci_msi_update_mask(entry, 0, 0); control &= ~PCI_MSI_FLAGS_QSIZE; control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE; pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); @@ -522,7 +464,7 @@ static void __pci_restore_msix_state(str arch_restore_msi_irqs(dev); for_each_pci_msi_entry(entry, dev) - msix_mask_irq(entry, entry->msix_ctrl); + pci_msix_write_vector_ctrl(entry, entry->msix_ctrl); pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0); } @@ -704,7 +646,6 @@ static int msi_capability_init(struct pc { struct msi_desc *entry; int ret; - unsigned mask; pci_msi_set_enable(dev, 0); /* Disable MSI during set up */ @@ -713,8 +654,7 @@ static int msi_capability_init(struct pc return -ENOMEM; /* All MSIs are unmasked by default; mask them all */ - mask = msi_multi_mask(entry); - msi_mask_irq(entry, mask, mask); + pci_msi_mask(entry, msi_multi_mask(entry)); list_add_tail(&entry->list, dev_to_msi_list(&dev->dev)); @@ -741,7 +681,7 @@ static int msi_capability_init(struct pc return 0; err: - msi_mask_irq(entry, mask, 0); + pci_msi_unmask(entry, msi_multi_mask(entry)); free_msi_irqs(dev); return ret; } @@ -1021,7 +961,7 @@ static void pci_msi_shutdown(struct pci_ dev->msi_enabled = 0; /* Return the device with MSI unmasked as initial states */ - msi_mask_irq(desc, msi_multi_mask(desc), 0); + pci_msi_unmask(desc, msi_multi_mask(desc)); /* Restore dev->irq to its default pin-assertion IRQ */ dev->irq = desc->msi_attrib.default_irq; @@ -1107,7 +1047,7 @@ static void pci_msix_shutdown(struct pci /* Return the device with MSI-X masked as initial states */ for_each_pci_msi_entry(entry, dev) - __pci_msix_desc_mask_irq(entry, 1); + pci_msix_mask(entry); pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0); pci_intx_for_msi(dev, 1);