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Fri, 30 Jul 2021 15:41:38 -0500 From: Harry Wentland To: , , , , , , CC: , , , , , , , , , , "Harry Wentland" Subject: [RFC PATCH v3 1/6] drm/doc: Color Management and HDR10 RFC Date: Fri, 30 Jul 2021 16:41:29 -0400 Message-ID: <20210730204134.21769-2-harry.wentland@amd.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210730204134.21769-1-harry.wentland@amd.com> References: <20210730204134.21769-1-harry.wentland@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 06ce0f2c-12d9-4532-ec2a-08d9539a6f89 X-MS-TrafficTypeDiagnostic: BYAPR12MB3624: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7691; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: g4NV6P1o9dtQa5He8uJliNIF0kFxTymy/piI8wpIIEdRLRI6BZT6lWLbER7GyjacJ/G7zrCCKVW4R4TEBnuTIp8htnLGBvjZbPkBrG+fCLnCeKQfYXn8+xAhjN2euxghNEc2FmqcoSqNcK8O7kmxmaWS2B/0kxsrds1XoZUbur6CQcZJjM7e8sQPuqPvpA9GC6p0FgqSQenPxhIrrnB7k2lLr78WDLqzu64pxOoqnyVHew4e72Eh/esJd47C0VCmiC1Km9yWA0v+yBAAxcUEIPO8WtmEiE01WRu33d+BZvO6jWG2/ueccGzsJev3arDYllf/YWK/brmIPBR8NrUzWXHYGSlxEFcUQKC6xjBwccGb4kPSwNOMcygn3Wo316ANZdSJqJlUEasBnT+EmqpnD4oIkufhSY2ZEg7Z+kY6FCj/N+oThcFqkEOCJIunJwCgAbrKN0Vn/BB/fYvLtPAlTpMVqhx+UqY+bP8vSNhL9W0FdHDfZPeuw5WFw+WaliXs9QWOBH9HCRdIhMirdI7BzSxN9B/coDhYY3PgN/vF5VTHI7AI/tEYk9yZjEHu3AsXHaWswm/72KggYkhkEU7P+xHOUz957Y/viyVIWdfAU68ozXkvFB1VITD5xE9brsO2EhW2JQWwZRbKm9dKD1y3YTn9lxNXiigO83RhrTU432y7+KWgA/6z9XT70YbrLmcvI3dGrUGGeypRbDUP/pUC203x4YglGFydXs2nIAJu5NqdGu1Te3QBhIn7+H7WjFxNqy2uPO7Sml/a52T2zuRDomT9I5VhXJJ38JaM8qfp9pWaF9LS5PViPIZgGaMoqo2xBP6zxsDtaSS4wSCYYQZQpzqPucfBkPk50Hai0xNBBd8= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(4636009)(39860400002)(136003)(376002)(346002)(396003)(36840700001)(46966006)(1076003)(336012)(70206006)(19627235002)(30864003)(966005)(5660300002)(2616005)(47076005)(8676002)(478600001)(2906002)(36756003)(83380400001)(7696005)(166002)(4326008)(6666004)(6636002)(8936002)(26005)(316002)(426003)(86362001)(54906003)(44832011)(82740400003)(186003)(70586007)(356005)(82310400003)(36860700001)(110136005)(81166007)(36900700001)(579004)(559001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jul 2021 20:41:40.9375 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 06ce0f2c-12d9-4532-ec2a-08d9539a6f89 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT035.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR12MB3624 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Use the new DRM RFC doc section to capture the RFC previously only described in the cover letter at https://patchwork.freedesktop.org/series/89506/ v3: * Add sections on single-plane and multi-plane HDR * Describe approach to define HW details vs approach to define SW intentions * Link Jeremy Cline's excellent HDR summaries * Outline intention behind overly verbose doc * Describe FP16 use-case * Clean up links v2: create this doc v1: n/a Signed-off-by: Harry Wentland --- Documentation/gpu/rfc/color_intentions.drawio | 1 + Documentation/gpu/rfc/color_intentions.svg | 3 + Documentation/gpu/rfc/colorpipe | 1 + Documentation/gpu/rfc/colorpipe.svg | 3 + Documentation/gpu/rfc/hdr-wide-gamut.rst | 580 ++++++++++++++++++ Documentation/gpu/rfc/index.rst | 1 + 6 files changed, 589 insertions(+) create mode 100644 Documentation/gpu/rfc/color_intentions.drawio create mode 100644 Documentation/gpu/rfc/color_intentions.svg create mode 100644 Documentation/gpu/rfc/colorpipe create mode 100644 Documentation/gpu/rfc/colorpipe.svg create mode 100644 Documentation/gpu/rfc/hdr-wide-gamut.rst diff --git a/Documentation/gpu/rfc/color_intentions.drawio b/Documentation/gpu/rfc/color_intentions.drawio new file mode 100644 index 000000000000..d62f3b24e1ec --- /dev/null +++ b/Documentation/gpu/rfc/color_intentions.drawio @@ -0,0 +1 @@ +7VhJl9owDP41OTIvC2E5DjDQvravtMybGY6GmMR9Tpw6Dkt/fZXEWUwgw1CWSy8QfbZkWfokBTRr6G8nHIXeN+Zgqpm6s9WskWaatt2HzwTYZYBhtK0McTlxJFYCM/IHS1CXaEwcHCkbBWNUkFAFlywI8FIoGOKcbdRtK0bVU0Pk4howWyJaR1+JI7z8GrpeLnzCxPXk0T1bLvgo3yyByEMO21Qg60mzhpwxkT352yGmSfDyuGR64yOrhWMcB+IUhcfJ5y/0ZUKC53AxfYnmr31j1TJkNtaIxvLG0luxy0OAHYiIFAMWwNeAszhwcGJYB4lx4TGXBYh+ZSwE0ADwFxZiJ/OJYsEA8oRP5Sr4zHdvif4DxCwH5gC09Ae9REZbeUYm7arSFHPiY4G5BDPHE2+PRkhCEYv5EjeFRTINcReLhn3dIo9QAJiBN3wHehxTJMha9QNJJrrFvkJ1ygh4aOqyavqSMXnN5AzKLWRuSaUy4/BQ8aKEUh58hBMHKNGhEIaBQ9YKNTq/44S9A4G3ooUocQPNekyKEQIOaSnW4cmV36mdKERBjo058vEiXq1SBZptG1d3VODUARU9AMV0H6GkyYWfk0Hv/bPrNpqtRmD2HKsA1i+wf/e9ElXrceMRgWchSim+gb6s1p5M1IjiVWlsjTlksblw6kSXCm2VsLm4qTTMvF961V6pH68MhdQfZbDVvk0T2xKR9TBbSvPKStm6EiHvXBdsUtdpPoatJrOWpSt3n26t+wwoDhwSuP/G+svT3OjVeV5M+yrPO9fiudG7+/Tudrv709vu3Ht69+86vot313vN736NFQeG7IKfNjZPGPfpIKkN+6mexOGd8Xm+9R/Xsz14NnWz2fe9IX3nxmR0zhvABXj5CWzXODgiUUhR4vX3WISxuBkR4T3sPxNvxUT9yNvDNagIYvnzOeue5Z8Q1tNf \ No newline at end of file diff --git a/Documentation/gpu/rfc/color_intentions.svg b/Documentation/gpu/rfc/color_intentions.svg new file mode 100644 index 000000000000..2f6b5f5813a3 --- /dev/null +++ b/Documentation/gpu/rfc/color_intentions.svg @@ -0,0 +1,3 @@ + + +
Framebuffer
  • RGB8
  • sRGB
Framebuffer...
Blending
Blending
Framebuffer
  • P010
  • PQ
  • BT2020
Framebuffer...
Display Output
  • RGB10
  • PQ
  • BT2020
Display Output...Viewer does not support full SVG 1.1 \ No newline at end of file diff --git a/Documentation/gpu/rfc/colorpipe b/Documentation/gpu/rfc/colorpipe new file mode 100644 index 000000000000..2d12490eddec --- /dev/null +++ b/Documentation/gpu/rfc/colorpipe @@ -0,0 +1 @@ +7ZpdU+IwFIZ/DTPuhUyb9AMuFZXdWZ1xBtTlMtLQdqdtOiEI7K/f1Cb9ICrdUUkclgtoTptwes7zpsmBHhylmzFFeXRDApz0gBVsevCiB4DrDvl7YdiWhgF0S0NI46A02bVhEv/BwmgJ6yoO8LJ1ISMkYXHeNs5JluE5a9kQpWTdvmxBkva35ijEimEyR4lqfYgDFgmrbVn1ie84DiPx1QNXnEiRvFgYlhEKyLphgpc9OKKEsPIo3YxwUsROxqXsd/XK2coxijPWpcPZ+MfP5H4cZ9P88fZ+OXsY2otTG5bDPKFkJe5YeMu2MgQ44BERzYxk/OOcklUW4GJgi7cIZREJSYaSa0JybrS58TdmbCvyiVaMcFPE0kSc5T7T7a+if9+VzZkY7rlxsWm1tqJVOld49GoUhGlJVnSO37p1QROiIWZvXAeqXHHGMUkx94f3ozhBLH5q+4EEbWF1XZ0QfiBy8i/5UdJzRVGKH1eLBaZKptppWUcxw5McPUdhzdXZToEYGVOGN28HU7152UGyLcRtO6K9bkhFKiVqqESK5OPj5R4tz6Ajz45OnoGSngCfzu7uywmTxhvjmK7m731MO5/GtHO0TDsdmXZ1Mq2m54RDPUZpir71gJdwx88f+WTthcXR9d3UPMaH2hn3DoP0JmYNonlr1jhT81w0tk249crA7SgDT6cM1CfvaHrTK0i74u+jycg47KGnHXv/K2DPA9ACv2/Zzh74n1u3mMY8Tnyh+uGK8DoqwtepCE9RxJQnNEV5HmehcWpw5M5cmxqg8xXUoOsh4HdEHlovp/0wzPsK8+cJzgITgXctdfqvVvtN4L1Pm/4HSrQOowD9NNvDjji/ltQD1V+GSoZMKsBUc7ExBRipnyNEuqpP70Ua6kRaDmxwDWYXa/01GEnxMWINu2KttQoD1F8yTC/DKJhrL8OA/yvwvYB3UYLWbScwvxKzS77+Sgz4EgVI3/dNq8SArvvS92pCdL0lMXexJmkw7INBCya+r+sPHKt6yd8E5aClp2KcHWwqx95BkroFNqnssys9/WUfoO6xjmVtBa2O4oFA5xMFqpu6kwbThi6v7MFOvUf78graSlAMfMhoEwPoKgat+2fppsHLq13yPe3LK/jC7szkrdluBP1PfEryZv0vwHIVUv+VEl7+BQ== \ No newline at end of file diff --git a/Documentation/gpu/rfc/colorpipe.svg b/Documentation/gpu/rfc/colorpipe.svg new file mode 100644 index 000000000000..f6b8ece2499d --- /dev/null +++ b/Documentation/gpu/rfc/colorpipe.svg @@ -0,0 +1,3 @@ + + +
Framebuffer
Framebuffer
de-YUV matrix
de-YUV matrix
(de-Gamma)
LUT
(de-Gamma)...
CTM / CSC
CTM / CSC
Tonemapping
Tonemapping
Blending
Blending
Framebuffer
Framebuffer
de-YUV matrix
de-YUV matrix
(de-Gamma)
LUT
(de-Gamma)...
CTM / CSC
CTM / CSC
Tonemapping
Tonemapping
(Tonemapping)
LUT
(Tonemapping)...
CTM / CSC
CTM / CSC
(Gamma)
LUT
(Gamma)...Viewer does not support full SVG 1.1 \ No newline at end of file diff --git a/Documentation/gpu/rfc/hdr-wide-gamut.rst b/Documentation/gpu/rfc/hdr-wide-gamut.rst new file mode 100644 index 000000000000..e463670191ab --- /dev/null +++ b/Documentation/gpu/rfc/hdr-wide-gamut.rst @@ -0,0 +1,580 @@ +============================== +HDR & Wide Color Gamut Support +============================== + +.. role:: wy-text-strike + +ToDo +==== + +* :wy-text-strike:`Reformat as RST kerneldoc` - done +* :wy-text-strike:`Don't use color_encoding for color_space definitions` - done +* :wy-text-strike:`Update SDR luminance description and reasoning` - done +* :wy-text-strike:`Clarify 3D LUT required for some color space transformations` - done +* :wy-text-strike:`Highlight need for named color space and EOTF definitions` - done +* :wy-text-strike:`Define transfer function API` - done +* :wy-text-strike:`Draft upstream plan` - done +* :wy-text-strike:`Reference to wayland plan` - done +* Reference to Chrome plans +* Sketch view of HW pipeline for couple of HW implementations + + +Upstream Plan +============= + +* Reach consensus on DRM/KMS API +* Implement support in amdgpu +* Implement IGT tests +* Add API support to Weston, ChromiumOS, or other canonical open-source project interested in HDR +* Merge user-space +* Merge kernel patches + + +History +======= + +v3: + +* Add sections on single-plane and multi-plane HDR +* Describe approach to define HW details vs approach to define SW intentions +* Link Jeremy Cline's excellent HDR summaries +* Outline intention behind overly verbose doc +* Describe FP16 use-case +* Clean up links + +v2: create this doc + +v1: n/a + + +Introduction +============ + +We are looking to enable HDR support for a couple of single-plane and +multi-plane scenarios. To do this effectively we recommend new interfaces +to drm_plane. Below I'll give a bit of background on HDR and why we +propose these interfaces. + +As an RFC doc this document is more verbose than what we would want from +an eventual uAPI doc. This is intentional in order to ensure interested +parties are all on the same page and to facilitate discussion if there +is disagreement on aspects of the intentions behind the proposed uAPI. + + +Overview and background +======================= + +I highly recommend you read `Jeremy Cline's HDR primer`_ + +Jeremy Cline did a much better job describing this. I highly recommend +you read it at [1]: + +.. _Jeremy Cline's HDR primer: https://www.jcline.org/blog/fedora/graphics/hdr/2021/05/07/hdr-in-linux-p1.html + +Defining a pixel's luminance +---------------------------- + +The luminance space of pixels in a framebuffer/plane presented to the +display is not well defined in the DRM/KMS APIs. It is usually assumed to +be in a 2.2 or 2.4 gamma space and has no mapping to an absolute luminance +value; it is interpreted in relative terms. + +Luminance can be measured and described in absolute terms as candela +per meter squared, or cd/m2, or nits. Even though a pixel value can be +mapped to luminance in a linear fashion to do so without losing a lot of +detail requires 16-bpc color depth. The reason for this is that human +perception can distinguish roughly between a 0.5-1% luminance delta. A +linear representation is suboptimal, wasting precision in the highlights +and losing precision in the shadows. + +A gamma curve is a decent approximation to a human's perception of +luminance, but the `PQ (perceptual quantizer) function`_ improves on +it. It also defines the luminance values in absolute terms, with the +highest value being 10,000 nits and the lowest 0.0005 nits. + +Using a content that's defined in PQ space we can approximate the real +world in a much better way. + +Here are some examples of real-life objects and their approximate +luminance values: + + +.. _PQ (perceptual quantizer) function: https://en.wikipedia.org/wiki/High-dynamic-range_video#Perceptual_Quantizer + +.. flat-table:: + :header-rows: 1 + + * - Object + - Luminance in nits + + * - Fluorescent light + - 10,000 + + * - Highlights + - 1,000 - sunlight + + * - White Objects + - 250 - 1,000 + + * - Typical Objects + - 1 - 250 + + * - Shadows + - 0.01 - 1 + + * - Ultra Blacks + - 0 - 0.0005 + + +Transfer functions +------------------ + +Traditionally we used the terms gamma and de-gamma to describe the +encoding of a pixel's luminance value and the operation to transfer from +a linear luminance space to the non-linear space used to encode the +pixels. Since some newer encodings don't use a gamma curve I suggest +we refer to non-linear encodings using the terms `EOTF, and OETF`_, or +simply as transfer function in general. + +The EOTF (Electro-Optical Transfer Function) describes how to transfer +from an electrical signal to an optical signal. This was traditionally +done by the de-gamma function. + +The OETF (Opto Electronic Transfer Function) describes how to transfer +from an optical signal to an electronic signal. This was traditionally +done by the gamma function. + +More generally we can name the transfer function describing the transform +between scanout and blending space as the **input transfer function**, and +the transfer function describing the transform from blending space to the +output space as **output transfer function**. + + +.. _EOTF, and OETF: https://en.wikipedia.org/wiki/Transfer_functions_in_imaging + +Mastering Luminances +-------------------- + +Even though we are able to describe the absolute luminance of a pixel +using the PQ 2084 EOTF we are presented with physical limitations of the +display technologies on the market today. Here are a few examples of +luminance ranges of displays. + +.. flat-table:: + :header-rows: 1 + + * - Display + - Luminance range in nits + + * - Typical PC display + - 0.3 - 200 + + * - Excellent LCD HDTV + - 0.3 - 400 + + * - HDR LCD w/ local dimming + - 0.05 - 1,500 + +Since no display can currently show the full 0.0005 to 10,000 nits +luminance range of PQ the display will need to tone-map the HDR content, +i.e to fit the content within a display's capabilities. To assist +with tone-mapping HDR content is usually accompanied by a metadata +that describes (among other things) the minimum and maximum mastering +luminance, i.e. the maximum and minimum luminance of the display that +was used to master the HDR content. + +The HDR metadata is currently defined on the drm_connector via the +hdr_output_metadata blob property. + +It might be useful to define per-plane hdr metadata, as different planes +might have been mastered differently. + +.. _SDR Luminance: + +SDR Luminance +------------- + +Traditional SDR content's maximum white luminance is not well defined. +Some like to define it at 80 nits, others at 200 nits. It also depends +to a large extent on the environmental viewing conditions. In practice +this means that we need to define the maximum SDR white luminance, either +in nits, or as a ratio. + +`One Windows API`_ defines it as a ratio against 80 nits. + +`Another Windows API`_ defines it as a nits value. + +The `Wayland color management proposal`_ uses Apple's definition of EDR as a +ratio of the HDR range vs SDR range. + +If a display's maximum HDR white level is correctly reported it is trivial +to convert between all of the above representations of SDR white level. If +it is not, defining SDR luminance as a nits value, or a ratio vs a fixed +nits value is preferred, assuming we are blending in linear space. + +It is our experience that many HDR displays do not report maximum white +level correctly + +.. _One Windows API: https://docs.microsoft.com/en-us/windows-hardware/drivers/ddi/dispmprt/ns-dispmprt-_dxgkarg_settargetadjustedcolorimetry2 +.. _Another Windows API: https://docs.microsoft.com/en-us/uwp/api/windows.graphics.display.advancedcolorinfo.sdrwhitelevelinnits?view=winrt-20348 +.. _Wayland color management proposal: https://gitlab.freedesktop.org/swick/wayland-protocols/-/blob/color/unstable/color-management/color.rst#id8 + +Let There Be Color +------------------ + +So far we've only talked about luminance, ignoring colors altogether. Just +like in the luminance space, traditionally the color space of display +outputs has not been well defined. Similar to how an EOTF defines a +mapping of pixel data to an absolute luminance value, the color space +maps color information for each pixel onto the CIE 1931 chromaticity +space. This can be thought of as a mapping to an absolute, real-life, +color value. + +A color space is defined by its primaries and white point. The primaries +and white point are expressed as coordinates in the CIE 1931 color +space. Think of the red primary as the reddest red that can be displayed +within the color space. Same for green and blue. + +Examples of color spaces are: + +.. flat-table:: + :header-rows: 1 + + * - Color Space + - Description + + * - BT 601 + - similar to BT 709 + + * - BT 709 + - used by sRGB content; ~53% of BT 2020 + + * - DCI-P3 + - used by most HDR displays; ~72% of BT 2020 + + * - BT 2020 + - standard for most HDR content + + + +Color Primaries and White Point +------------------------------- + +Just like displays can currently not represent the entire 0.0005 - +10,000 nits HDR range of the PQ 2084 EOTF, they are currently not capable +of representing the entire BT.2020 color Gamut. For this reason video +content will often specify the color primaries and white point used to +master the video, in order to allow displays to be able to map the image +as best as possible onto the display's gamut. + + +Displays and Tonemapping +------------------------ + +External displays are able to do their own tone and color mapping, based +on the mastering luminance, color primaries, and white space defined in +the HDR metadata. + +Some internal panels might not include the complex HW to do tone and color +mapping on their own and will require the display driver to perform +appropriate mapping. + + +How are we solving the problem? +=============================== + +Single-plane +------------ + +If a single drm_plane is used no further work is required. The compositor +will provide one HDR plane alongside a drm_connector's hdr_output_metadata +and the display HW will output this plane without further processing if +no CRTC LUTs are provided. + +If desired a compositor can use the CRTC LUTs for HDR content but without +support for PWL or multi-segmented LUTs the quality of the operation is +expected to be subpar for HDR content. + + +Multi-plane +----------- + +In multi-plane configurations we need to solve the problem of blending +HDR and SDR content. This blending should be done in linear space and +therefore requires framebuffer data that is presented in linear space +or a way to convert non-linear data to linear space. Additionally +we need a way to define the luminance of any SDR content in relation +to the HDR content. + +In order to present framebuffer data in linear space without losing a +lot of precision it needs to be presented using 16 bpc precision. + + +Defining HW Details +------------------- + +One way to take full advantage of modern HW's color pipelines is by +defining a "generic" pipeline that matches all capable HW. Something +like this, which I took `from Uma Shankar`_ and expanded on: + +.. _from Uma Shankar: https://patchwork.freedesktop.org/series/90826/ + +.. kernel-figure:: colorpipe.svg + +I intentionally put de-Gamma, and Gamma in parentheses in my graph +as they describe the intention of the block but not necessarily a +strict definition of how a userspace implementation is required to +use them. + +De-Gamma and Gamma blocks are named LUT, but they could be non-programmable +LUTs in some HW implementations with no programmable LUT available. See +the definitions for AMD's `latest dGPU generation`_ as an example. + +.. _latest dGPU generation: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c?h=v5.13#n2586 + +I renamed the "Plane Gamma LUT" and "CRTC De-Gamma LUT" to "Tonemapping" +as we generally don't want to re-apply gamma before blending, or do +de-gamma post blending. These blocks tend generally to be intended for +tonemapping purposes. + +Tonemapping in this case could be a simple nits value or `EDR`_ to describe +how to scale the :ref:`SDR luminance`. + +Tonemapping could also include the ability to use a 3D LUT which might be +accompanied by a 1D shaper LUT. The shaper LUT is required in order to +ensure a 3D LUT with limited entries (e.g. 9x9x9, or 17x17x17) operates +in perceptual (non-linear) space, so as to evenly spread the limited +entries evenly across the perceived space. + +.. _EDR: https://gitlab.freedesktop.org/swick/wayland-protocols/-/blob/color/unstable/color-management/color.rst#id8 + +Creating a model that is flexible enough to define color pipelines for +a wide variety of HW is challenging, though not impossible. Implementing +support for such a flexible definition in userspace, though, amounts +to essentially writing color pipeline drivers for each HW. + + +Defining SW Intentions +---------------------- + +An alternative to describing the HW color pipeline in enough detail to +be useful for color management and HDR purposes is to instead define +SW intentions. + +.. kernel-figure:: color_intentions.svg + +This greatly simplifies the API and lets the driver do what a driver +does best: figure out how to program the HW to achieve the desired +effect. + +The above diagram could include white point, primaries, and maximum +peak and average white levels in order to facilitate tone mapping. + +At this point I suggest to keep tonemapping (other than an SDR luminance +adjustment) out of the current DRM/KMS API. Most HDR displays are capable +of tonemapping. If for some reason tonemapping is still desired on +a plane, a shader might be a better way of doing that instead of relying +on display HW. + +In some ways this mirrors how various userspace APIs treat HDR: + * Gstreamer's `GstVideoTransferFunction`_ + * EGL's `EGL_EXT_gl_colorspace_bt2020_pq`_ extension + * Vulkan's `VkColorSpaceKHR`_ + +.. _GstVideoTransferFunction: https://gstreamer.freedesktop.org/documentation/video/video-color.html?gi-language=c#GstVideoTransferFunction +.. _EGL_EXT_gl_colorspace_bt2020_pq: https://www.khronos.org/registry/EGL/extensions/EXT/EGL_EXT_gl_colorspace_bt2020_linear.txt +.. _VkColorSpaceKHR: https://www.khronos.org/registry/vulkan/specs/1.2-extensions/html/vkspec.html#VkColorSpaceKHR + + +A hybrid approach to the API +---------------------------- + +Our current approach attempts a hybrid approach, defining API to specify +input and output transfer functions, as well as an SDR boost, and a +input color space definition. + +We would like to solicit feedback and encourage discussion around the +merits and weaknesses of these approaches. This question is at the core +of defining a good API and we'd like to get it right. + + +Input and Output Transfer functions +----------------------------------- + +We define an input transfer function on drm_plane to describe the +transform from framebuffer to blending space. + +We define an output transfer function on drm_crtc to describe the +transform from blending space to display space. + +The transfer function can be a pre-defined function, such as PQ EOTF, or +a custom LUT. A driver will be able to specify support for specific +transfer functions, including custom ones. + +Defining the transfer function in this way allows us to support in on HW +that uses ROMs to support these transforms, as well as on HW that use +LUT definitions that are complex and don't map easily onto a standard LUT +definition. + +We will not define per-plane LUTs in this patchset as the scope of our +current work only deals with pre-defined transfer functions. This API has +the flexibility to add custom 1D or 3D LUTs at a later date. + +In order to support the existing 1D de-gamma and gamma LUTs on the drm_crtc +we will include a "custom 1D" enum value to indicate that the custom gamma and +de-gamma 1D LUTs should be used. + +Possible transfer functions: + +.. flat-table:: + :header-rows: 1 + + * - Transfer Function + - Description + + * - Gamma 2.2 + - a simple 2.2 gamma function + + * - sRGB + - 2.4 gamma with small initial linear section + + * - PQ 2084 + - SMPTE ST 2084; used for HDR video and allows for up to 10,000 nit support + + * - Linear + - Linear relationship between pixel value and luminance value + + * - Custom 1D + - Custom 1D de-gamma and gamma LUTs; one LUT per color + + * - Custom 3D + - Custom 3D LUT (to be defined) + + +Describing SDR Luminance +------------------------------ + +Since many displays do no correctly advertise the HDR white level we +propose to define the SDR white level in nits. + +We define a new drm_plane property to specify the white level of an SDR +plane. + + +Defining the color space +------------------------ + +We propose to add a new color space property to drm_plane to define a +plane's color space. + +While some color space conversions can be performed with a simple color +transformation matrix (CTM) others require a 3D LUT. + + +Defining mastering color space and luminance +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +ToDo + + + +Pixel Formats +~~~~~~~~~~~~~ + +The pixel formats, such as ARGB8888, ARGB2101010, P010, or FP16 are +unrelated to color space and EOTF definitions. HDR pixels can be formatted +in different ways but in order to not lose precision HDR content requires +at least 10 bpc precision. For this reason ARGB2101010, P010, and FP16 are +the obvious candidates for HDR. ARGB2101010 and P010 have the advantage +of requiring only half the bandwidth as FP16, while FP16 has the advantage +of enough precision to operate in a linear space, i.e. without EOTF. + + +Use Cases +========= + +RGB10 HDR plane - composited HDR video & desktop +------------------------------------------------ + +A single, composited plane of HDR content. The use-case is a video player +on a desktop with the compositor owning the composition of SDR and HDR +content. The content shall be PQ BT.2020 formatted. The drm_connector's +hdr_output_metadata shall be set. + + +P010 HDR video plane + RGB8 SDR desktop plane +--------------------------------------------- +A normal 8bpc desktop plane, with a P010 HDR video plane underlayed. The +HDR plane shall be PQ BT.2020 formatted. The desktop plane shall specify +an SDR boost value. The drm_connector's hdr_output_metadata shall be set. + + +One XRGB8888 SDR Plane - HDR output +----------------------------------- + +In order to support a smooth transition we recommend an OS that supports +HDR output to provide the hdr_output_metadata on the drm_connector to +configure the output for HDR, even when the content is only SDR. This will +allow for a smooth transition between SDR-only and HDR content. In this +use-case the SDR max luminance value should be provided on the drm_plane. + +In DCN we will de-PQ or de-Gamma all input in order to blend in linear +space. For SDR content we will also apply any desired boost before +blending. After blending we will then re-apply the PQ EOTF and do RGB +to YCbCr conversion if needed. + +FP16 HDR linear planes +---------------------- + +These will require a transformation into the display's encoding (e.g. PQ) +using the CRTC LUT. Current CRTC LUTs are lacking the precision in the +dark areas to do the conversion without losing detail. + +One of the newly defined output transfer functions or a PWL or `multi-segmented +LUT`_ can be used to facilitate the conversion to PQ, HLG, or another +encoding supported by displays. + +.. _multi-segmented LUT: https://patchwork.freedesktop.org/series/90822/ + + +User Space +========== + +Gnome & GStreamer +----------------- + +See Jeremy Cline's `HDR in Linux\: Part 2`_. + +.. _HDR in Linux\: Part 2: https://www.jcline.org/blog/fedora/graphics/hdr/2021/06/28/hdr-in-linux-p2.html + + +Wayland +------- + +See `Wayland Color Management and HDR Design Goals`_. + +.. _Wayland Color Management and HDR Design Goals: https://gitlab.freedesktop.org/swick/wayland-protocols/-/blob/color/unstable/color-management/color.rst + + +ChromeOS Ozone +-------------- + +ToDo + + +HW support +========== + +ToDo, describe pipeline on a couple different HW platforms + + +Further Reading +=============== + +* https://gitlab.freedesktop.org/swick/wayland-protocols/-/blob/color/unstable/color-management/color.rst +* http://downloads.bbc.co.uk/rd/pubs/whp/whp-pdf-files/WHP309.pdf +* https://app.spectracal.com/Documents/White%20Papers/HDR_Demystified.pdf +* https://www.jcline.org/blog/fedora/graphics/hdr/2021/05/07/hdr-in-linux-p1.html +* https://www.jcline.org/blog/fedora/graphics/hdr/2021/06/28/hdr-in-linux-p2.html + + diff --git a/Documentation/gpu/rfc/index.rst b/Documentation/gpu/rfc/index.rst index 05670442ca1b..8d8430cfdde1 100644 --- a/Documentation/gpu/rfc/index.rst +++ b/Documentation/gpu/rfc/index.rst @@ -19,3 +19,4 @@ host such documentation: .. toctree:: i915_gem_lmem.rst + hdr-wide-gamut.rst From patchwork Fri Jul 30 20:41:30 2021 Content-Type: text/plain; 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Fri, 30 Jul 2021 15:41:39 -0500 From: Harry Wentland To: , , , , , , CC: , , , , , , , , , , "Harry Wentland" Subject: [RFC PATCH v3 2/6] drm/color: Add transfer functions for HDR/SDR on drm_plane Date: Fri, 30 Jul 2021 16:41:30 -0400 Message-ID: <20210730204134.21769-3-harry.wentland@amd.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210730204134.21769-1-harry.wentland@amd.com> References: <20210730204134.21769-1-harry.wentland@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 8ba9306e-05f6-4fea-c85d-08d9539a737a X-MS-TrafficTypeDiagnostic: PH0PR12MB5450: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8882; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: BEvkyRbxhDS/VCgajc8OA9fKNzzXcL2gH1j/qo4EtIAaAqvZm2aBPtS0EX1CgvU29+5rOS/7lcAUAQFpnIz80yrQbWik3p4qN8QUmL14AMDSDCrOHWojF4noP8DmqUUDPsDBl9aDcXUb5eCl+tn6i+QbcSRWpBii1ELfLNk8vJri2E4bcp7XiltDV8QOA5fwlEfMcqO6HeaGB7LckqZkq8IIaEqfguigtdC2mwbsHWFYZHv0k3A7uqF8w3xBbm3TL9MoytKPDYTMn1XJdbbwwH1Sv0PlnEhn+1Y1ld6/RMOMxLeab23Ri3PEzKm/z/JyZP8Yc3/5amLvZE2ZgNYF7J2acnvE3b0g84P4Kr00QQYdkjEKNsiKwCs14uDzjKCe5zfCVYFXSVQghv25cfQHhdy6qRdrsU1hMJ0rs3B1vZkqMbhayP8ClfaYcvaBevOv6dx7KpKM2Dhx3zyWg3UKEa+EpNo20wUqtGiYp7a1zNxu8m4apKlIzNQObvrAij8rfrKE2fgaNBs/yw8mAW0+/ES5AyLe4W7/PDucd/Z9LajwywBlQDk/+3gCCZs1Y/KM11uIyEJr73RkHOqq5Itq0D52tIySHxMQlC9bmpxKBf1iPfiIUsFskKdK3V9sGf5RlxIRzd5DZfs2Hwq7cX5e6c5dGGkaYWQCkOpENS2VVxPfSYGawDxCyplPnmYam2xpmcjbE7WDA6SvrqESmqIVNogjKjSQHBspxRTD5GUXxyA= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB03.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(4636009)(376002)(136003)(396003)(39860400002)(346002)(36840700001)(46966006)(316002)(70206006)(2906002)(6666004)(47076005)(70586007)(478600001)(83380400001)(8676002)(86362001)(54906003)(356005)(4326008)(6636002)(44832011)(81166007)(30864003)(336012)(110136005)(1076003)(8936002)(26005)(82310400003)(2616005)(82740400003)(36860700001)(5660300002)(7696005)(186003)(36756003)(426003)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jul 2021 20:41:47.6141 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8ba9306e-05f6-4fea-c85d-08d9539a737a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT053.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5450 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Bhawanpreet Lakha Due to the way displays and human vision work it is most effective to encode luminance information in a non-linear space. For SDR this non-linear mapping is assumed to roughly use a gamma 2.2 curve. This was due to the way CRTs worked and was fine for SDR content with a low luminance range. The large luminance range (0-10,000 nits) for HDR exposes some short-comings of a simple gamma curve that have been addressed through various Electro-Optical Transfer Functions (EOTFs). Rather than assuming how framebuffer content is encoded we want to make sure userspace presenting HDR content is explicit about the EOTF of the content, so a driver can decide whether the content can be supported or not. This Patch adds common transfer functions for SDR/HDR. These can be used to communicate with the driver regarding the transformation to use for a given plane. enums added: DRM_TF_UNDEFINED the legacy case where the TF in/out of blending space is undefined DRM_TF_SRGB roughly 2.4 gamma with initial linear section DRM_TF_BT709 Similar to Gamma 2.2-2.8 DRM_TF_PQ2084 most common tf used for HDR video (HDR10/Dolby). Can support up to 10,000 nits The usage is similar to color_encoding and color_range where the driver can specify the default and supported tfs and pass it into drm_plane_create_color_properties(). v2: - drop "color" from transfer function name (Harry) - add DRM_TF_UNDEFINED enum as legacy default (Harry) Signed-off-by: Bhawanpreet Lakha Signed-off-by: Harry Wentland --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 +- .../gpu/drm/arm/display/komeda/komeda_plane.c | 4 +- drivers/gpu/drm/arm/malidp_planes.c | 4 +- drivers/gpu/drm/armada/armada_overlay.c | 4 +- drivers/gpu/drm/drm_atomic_uapi.c | 4 ++ drivers/gpu/drm/drm_color_mgmt.c | 64 +++++++++++++++++-- drivers/gpu/drm/i915/display/intel_sprite.c | 4 +- .../drm/i915/display/skl_universal_plane.c | 4 +- drivers/gpu/drm/nouveau/dispnv04/overlay.c | 4 +- drivers/gpu/drm/omapdrm/omap_plane.c | 4 +- drivers/gpu/drm/sun4i/sun8i_vi_layer.c | 4 +- drivers/gpu/drm/tidss/tidss_plane.c | 6 +- include/drm/drm_color_mgmt.h | 18 +++++- include/drm/drm_plane.h | 16 +++++ 14 files changed, 128 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index b5b5ccf0ed71..63ddae9c5abe 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -7276,7 +7276,9 @@ static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, BIT(DRM_COLOR_YCBCR_BT2020), BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | BIT(DRM_COLOR_YCBCR_FULL_RANGE), - DRM_COLOR_YCBCR_BT709, DRM_COLOR_YCBCR_LIMITED_RANGE); + BIT(DRM_TF_SRGB), + DRM_COLOR_YCBCR_BT709, DRM_COLOR_YCBCR_LIMITED_RANGE, + DRM_TF_SRGB); } supported_rotations = diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_plane.c b/drivers/gpu/drm/arm/display/komeda/komeda_plane.c index d63d83800a8a..811f79ab6d32 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_plane.c +++ b/drivers/gpu/drm/arm/display/komeda/komeda_plane.c @@ -302,8 +302,10 @@ static int komeda_plane_add(struct komeda_kms_dev *kms, BIT(DRM_COLOR_YCBCR_BT2020), BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | BIT(DRM_COLOR_YCBCR_FULL_RANGE), + BIT(DRM_TF_UNDEFINED), DRM_COLOR_YCBCR_BT601, - DRM_COLOR_YCBCR_LIMITED_RANGE); + DRM_COLOR_YCBCR_LIMITED_RANGE, + DRM_TF_UNDEFINED); if (err) goto cleanup; diff --git a/drivers/gpu/drm/arm/malidp_planes.c b/drivers/gpu/drm/arm/malidp_planes.c index 8c2ab3d653b7..98d308262880 100644 --- a/drivers/gpu/drm/arm/malidp_planes.c +++ b/drivers/gpu/drm/arm/malidp_planes.c @@ -1030,7 +1030,9 @@ int malidp_de_planes_init(struct drm_device *drm) BIT(DRM_COLOR_YCBCR_BT2020), BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | \ BIT(DRM_COLOR_YCBCR_FULL_RANGE), - enc, range); + BIT(DRM_TF_UNDEFINED), + enc, range, + DRM_TF_UNDEFINED); if (!ret) /* program the HW registers */ malidp_de_set_color_encoding(plane, enc, range); diff --git a/drivers/gpu/drm/armada/armada_overlay.c b/drivers/gpu/drm/armada/armada_overlay.c index d3e3e5fdc390..f7792444cb73 100644 --- a/drivers/gpu/drm/armada/armada_overlay.c +++ b/drivers/gpu/drm/armada/armada_overlay.c @@ -596,8 +596,10 @@ int armada_overlay_plane_create(struct drm_device *dev, unsigned long crtcs) BIT(DRM_COLOR_YCBCR_BT601) | BIT(DRM_COLOR_YCBCR_BT709), BIT(DRM_COLOR_YCBCR_LIMITED_RANGE), + BIT(DRM_TF_UNDEFINED), DEFAULT_ENCODING, - DRM_COLOR_YCBCR_LIMITED_RANGE); + DRM_COLOR_YCBCR_LIMITED_RANGE, + DRM_TF_UNDEFINED); return ret; } diff --git a/drivers/gpu/drm/drm_atomic_uapi.c b/drivers/gpu/drm/drm_atomic_uapi.c index 7e48d40600ff..9582515dd12e 100644 --- a/drivers/gpu/drm/drm_atomic_uapi.c +++ b/drivers/gpu/drm/drm_atomic_uapi.c @@ -596,6 +596,8 @@ static int drm_atomic_plane_set_property(struct drm_plane *plane, state->color_encoding = val; } else if (property == plane->color_range_property) { state->color_range = val; + } else if (property == plane->transfer_function_property) { + state->transfer_function = val; } else if (property == config->prop_fb_damage_clips) { ret = drm_atomic_replace_property_blob_from_id(dev, &state->fb_damage_clips, @@ -662,6 +664,8 @@ drm_atomic_plane_get_property(struct drm_plane *plane, *val = state->color_encoding; } else if (property == plane->color_range_property) { *val = state->color_range; + } else if (property == plane->transfer_function_property) { + *val = state->transfer_function; } else if (property == config->prop_fb_damage_clips) { *val = (state->fb_damage_clips) ? state->fb_damage_clips->base.id : 0; diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c index bb14f488c8f6..daf62fb090a6 100644 --- a/drivers/gpu/drm/drm_color_mgmt.c +++ b/drivers/gpu/drm/drm_color_mgmt.c @@ -106,6 +106,11 @@ * Optional plane enum property to support different non RGB * color parameter ranges. The driver can provide a subset of * standard enum values supported by the DRM plane. + * + * "COLOR_TRANFER_FUNCTION": + * Optional plane enum property to support different + * color luminance mappings. The driver can provide a subset of + * standard enum values supported by the DRM plane. */ /** @@ -476,6 +481,11 @@ static const char * const color_range_name[] = { [DRM_COLOR_YCBCR_LIMITED_RANGE] = "YCbCr limited range", }; +static const char * const tf_name[] = { + [DRM_TF_UNDEFINED] = "undefined", + [DRM_TF_SRGB] = "sRGB", + [DRM_TF_PQ2084] = "PQ2084", +}; /** * drm_get_color_encoding_name - return a string for color encoding * @encoding: color encoding to compute name of @@ -506,30 +516,49 @@ const char *drm_get_color_range_name(enum drm_color_range range) return color_range_name[range]; } +/** + * drm_get_transfer_function - return a string for transfer function + * @tf: transfer function to compute name of + * + * In contrast to the other drm_get_*_name functions this one here returns a + * const pointer and hence is threadsafe. + */ +const char *drm_get_transfer_function_name(enum drm_transfer_function tf) +{ + if (WARN_ON(tf >= ARRAY_SIZE(tf_name))) + return "unknown"; + + return tf_name[tf]; +} /** * drm_plane_create_color_properties - color encoding related plane properties * @plane: plane object * @supported_encodings: bitfield indicating supported color encodings * @supported_ranges: bitfileld indicating supported color ranges + * @supported_tfs: bitfield indicating supported transfer functions * @default_encoding: default color encoding * @default_range: default color range + * @default_tf: default color transfer function * - * Create and attach plane specific COLOR_ENCODING and COLOR_RANGE - * properties to @plane. The supported encodings and ranges should - * be provided in supported_encodings and supported_ranges bitmasks. + * Create and attach plane specific COLOR_ENCODING, COLOR_RANGE and TRANSFER_FUNCTION + * properties to @plane. The supported encodings, ranges and tfs should + * be provided in supported_encodings, supported_ranges and supported_tfs bitmasks. * Each bit set in the bitmask indicates that its number as enum * value is supported. */ int drm_plane_create_color_properties(struct drm_plane *plane, u32 supported_encodings, u32 supported_ranges, + u32 supported_tfs, enum drm_color_encoding default_encoding, - enum drm_color_range default_range) + enum drm_color_range default_range, + enum drm_transfer_function default_tf) { struct drm_device *dev = plane->dev; struct drm_property *prop; struct drm_prop_enum_list enum_list[max_t(int, DRM_COLOR_ENCODING_MAX, - DRM_COLOR_RANGE_MAX)]; + max_t(int, DRM_COLOR_RANGE_MAX, + DRM_TF_MAX))]; int i, len; if (WARN_ON(supported_encodings == 0 || @@ -542,6 +571,11 @@ int drm_plane_create_color_properties(struct drm_plane *plane, (supported_ranges & BIT(default_range)) == 0)) return -EINVAL; + if (WARN_ON(supported_tfs == 0 || + (supported_tfs & -BIT(DRM_TF_MAX)) != 0 || + (supported_tfs & BIT(default_tf)) == 0)) + return -EINVAL; + len = 0; for (i = 0; i < DRM_COLOR_ENCODING_MAX; i++) { if ((supported_encodings & BIT(i)) == 0) @@ -580,6 +614,26 @@ int drm_plane_create_color_properties(struct drm_plane *plane, if (plane->state) plane->state->color_range = default_range; + + len = 0; + for (i = 0; i < DRM_TF_MAX; i++) { + if ((supported_tfs & BIT(i)) == 0) + continue; + + enum_list[len].type = i; + enum_list[len].name = tf_name[i]; + len++; + } + + prop = drm_property_create_enum(dev, 0, "TRANSFER_FUNCTION", + enum_list, len); + if (!prop) + return -ENOMEM; + plane->transfer_function_property = prop; + drm_object_attach_property(&plane->base, prop, default_tf); + if (plane->state) + plane->state->transfer_function = default_tf; + return 0; } EXPORT_SYMBOL(drm_plane_create_color_properties); diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c index 4ae9a7455b23..b3f7aca3795b 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c @@ -1850,8 +1850,10 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, BIT(DRM_COLOR_YCBCR_BT709), BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | BIT(DRM_COLOR_YCBCR_FULL_RANGE), + BIT(DRM_TF_UNDEFINED), DRM_COLOR_YCBCR_BT709, - DRM_COLOR_YCBCR_LIMITED_RANGE); + DRM_COLOR_YCBCR_LIMITED_RANGE, + DRM_TF_UNDEFINED); zpos = sprite + 1; drm_plane_create_zpos_immutable_property(&plane->base, zpos); diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index 92a4fd508e92..df596431151d 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -2160,8 +2160,10 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, supported_csc, BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | BIT(DRM_COLOR_YCBCR_FULL_RANGE), + BIT(DRM_TF_UNDEFINED), DRM_COLOR_YCBCR_BT709, - DRM_COLOR_YCBCR_LIMITED_RANGE); + DRM_COLOR_YCBCR_LIMITED_RANGE, + DRM_TF_UNDEFINED); drm_plane_create_alpha_property(&plane->base); drm_plane_create_blend_mode_property(&plane->base, diff --git a/drivers/gpu/drm/nouveau/dispnv04/overlay.c b/drivers/gpu/drm/nouveau/dispnv04/overlay.c index 37e63e98cd08..64e1793212b4 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/overlay.c +++ b/drivers/gpu/drm/nouveau/dispnv04/overlay.c @@ -345,8 +345,10 @@ nv10_overlay_init(struct drm_device *device) BIT(DRM_COLOR_YCBCR_BT601) | BIT(DRM_COLOR_YCBCR_BT709), BIT(DRM_COLOR_YCBCR_LIMITED_RANGE), + BIT(DRM_TF_UNDEFINED), DRM_COLOR_YCBCR_BT601, - DRM_COLOR_YCBCR_LIMITED_RANGE); + DRM_COLOR_YCBCR_LIMITED_RANGE, + DRM_TF_UNDEFINED); plane->set_params = nv10_set_params; nv10_set_params(plane); diff --git a/drivers/gpu/drm/omapdrm/omap_plane.c b/drivers/gpu/drm/omapdrm/omap_plane.c index 801da917507d..ca7559824dcd 100644 --- a/drivers/gpu/drm/omapdrm/omap_plane.c +++ b/drivers/gpu/drm/omapdrm/omap_plane.c @@ -325,8 +325,10 @@ struct drm_plane *omap_plane_init(struct drm_device *dev, BIT(DRM_COLOR_YCBCR_BT709), BIT(DRM_COLOR_YCBCR_FULL_RANGE) | BIT(DRM_COLOR_YCBCR_LIMITED_RANGE), + BIT(DRM_TF_UNDEFINED), DRM_COLOR_YCBCR_BT601, - DRM_COLOR_YCBCR_FULL_RANGE); + DRM_COLOR_YCBCR_FULL_RANGE, + DRM_TF_UNDEFINED); return plane; diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c index 1c86c2dd0bbf..eda8f51bafd7 100644 --- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c +++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c @@ -600,8 +600,10 @@ struct sun8i_vi_layer *sun8i_vi_layer_init_one(struct drm_device *drm, ret = drm_plane_create_color_properties(&layer->plane, supported_encodings, supported_ranges, + BIT(DRM_TF_UNDEFINED), DRM_COLOR_YCBCR_BT709, - DRM_COLOR_YCBCR_LIMITED_RANGE); + DRM_COLOR_YCBCR_LIMITED_RANGE, + DRM_TF_UNDEFINED); if (ret) { dev_err(drm->dev, "Couldn't add encoding and range properties!\n"); return ERR_PTR(ret); diff --git a/drivers/gpu/drm/tidss/tidss_plane.c b/drivers/gpu/drm/tidss/tidss_plane.c index 1acd15aa4193..a1336ecd5fd5 100644 --- a/drivers/gpu/drm/tidss/tidss_plane.c +++ b/drivers/gpu/drm/tidss/tidss_plane.c @@ -186,8 +186,10 @@ struct tidss_plane *tidss_plane_create(struct tidss_device *tidss, BIT(DRM_COLOR_YCBCR_BT709)); u32 color_ranges = (BIT(DRM_COLOR_YCBCR_FULL_RANGE) | BIT(DRM_COLOR_YCBCR_LIMITED_RANGE)); + u32 transfer_functions = BIT(DRM_TF_UNDEFINED; u32 default_encoding = DRM_COLOR_YCBCR_BT601; u32 default_range = DRM_COLOR_YCBCR_FULL_RANGE; + u32 default_tf = DRM_TF_UNDEFINED;; u32 blend_modes = (BIT(DRM_MODE_BLEND_PREMULTI) | BIT(DRM_MODE_BLEND_COVERAGE)); int ret; @@ -217,8 +219,10 @@ struct tidss_plane *tidss_plane_create(struct tidss_device *tidss, ret = drm_plane_create_color_properties(&tplane->plane, color_encodings, color_ranges, + transfer_functions, default_encoding, - default_range); + default_range, + default_tf); if (ret) goto err; diff --git a/include/drm/drm_color_mgmt.h b/include/drm/drm_color_mgmt.h index 81c298488b0c..370bbc55b744 100644 --- a/include/drm/drm_color_mgmt.h +++ b/include/drm/drm_color_mgmt.h @@ -87,11 +87,27 @@ enum drm_color_range { DRM_COLOR_RANGE_MAX, }; +/** + * enum drm_transfer_function - common transfer function used for sdr/hdr formats + * + * DRM_TF_UNDEFINED - The legacy case where a TF in and out of the blending + * space is undefined + * DRM_TF_SRGB - Based on gamma curve and is used for printer/monitors/web + * DRM_TF_PQ2084 - Used for HDR and allows for up to 10,000 nit support. +*/ +enum drm_transfer_function { + DRM_TF_UNDEFINED, + DRM_TF_SRGB, + DRM_TF_PQ2084, + DRM_TF_MAX, +}; int drm_plane_create_color_properties(struct drm_plane *plane, u32 supported_encodings, u32 supported_ranges, + u32 supported_tf, enum drm_color_encoding default_encoding, - enum drm_color_range default_range); + enum drm_color_range default_range, + enum drm_transfer_function default_tf); /** * enum drm_color_lut_tests - hw-specific LUT tests to perform diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h index 1294610e84f4..cff56994513f 100644 --- a/include/drm/drm_plane.h +++ b/include/drm/drm_plane.h @@ -179,6 +179,14 @@ struct drm_plane_state { */ enum drm_color_range color_range; + /** + * @transfer_function: + * + * Transfer function for HDR color/luminance mapping. This will allow the + * driver to know what transfer function should be used to for the current + * format for a proper HDR color/luminance output. + */ + enum drm_transfer_function transfer_function; /** * @fb_damage_clips: * @@ -741,6 +749,14 @@ struct drm_plane { * See drm_plane_create_color_properties(). */ struct drm_property *color_range_property; + /** + * @transfer_function_property: + * + * Optional "TRANSFER_FUNCTION" enum property for specifying + * color transfer function for non RGB formats, mostly used for HDR. + * See drm_plane_create_color_properties(). + */ + struct drm_property *transfer_function_property; /** * @scaling_filter_property: property to apply a particular filter while From patchwork Fri Jul 30 20:41:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Harry Wentland X-Patchwork-Id: 12411929 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.0 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, UNWANTED_LANGUAGE_BODY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EF8A7C4338F for ; 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Fri, 30 Jul 2021 15:41:40 -0500 From: Harry Wentland To: , , , , , , CC: , , , , , , , , , , "Harry Wentland" Subject: [RFC PATCH v3 3/6] drm/color: Add output transfer function to crtc Date: Fri, 30 Jul 2021 16:41:31 -0400 Message-ID: <20210730204134.21769-4-harry.wentland@amd.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210730204134.21769-1-harry.wentland@amd.com> References: <20210730204134.21769-1-harry.wentland@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: e9502cc0-2de0-4f2f-9b98-08d9539a73cb X-MS-TrafficTypeDiagnostic: MN2PR12MB4567: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:353; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: jJlPypesbJmD41xUsFJdVc+dEYXOTlsygIMVSlqcXhzWrKclSnjlTEaHGr11S1SXKj8h8H6wzbd2/eLOPT88DXXweHJJ3k5Qr4CCBYLxeUfuh0lPgELAwIIyreoj9J7Q94ZEy6se9QXHh8W9b+IPc0rVyWW37+fAqARt64iCpkdSprSglV6ZLejacNJYNLyWd/gSTr0G4gi7haTjeI490DkVfEI1hy/xNh8oBkp+lKLRnlIl/V1gtJUeIm593uzp9DiCQAu5E3yuJwNacnY+tYQDIceVFPITqqAu3XOVGgcDx2ko0mbKyk/30jR7V/uRbvnGsgqWeyG3eZ/z54eIDFOOWlrxlcr4Nv19lLG6HJSIWaGT1VBo+Vu3KzIU1klkz0F7kzqxYrqzt8GTcvlPqvWZ57aMPHzY1ZaKWF1VV3UrPA51fL/FsefO7HLzaFEGMacq9KOS48YHjJo0WlxKeNHXM6AHJ9iQS/3xWTcLul1Ac7JYgZ9NZGvTZSmpZ/SfLn1ick/SXgEGLv2+j7NadYcmfs/1oWcEhjXPeI76bxr2piiH4Vcz6lfcFv+SwLZ3OeMOPPoLqMgeFq+OWO0AcgUXEGy3lqChWOF4JJZ1eYMwRc5MzN5mytwM1zcds6jdYxJgm3bTaHEeZCdYfAbMf5epGRNioDzkuLKkMHAfEW3xfhZXqXpK9XYnZbWaTadEpLnMuypp7CHMO/JfoH6yoGNGU6Da91oG77vzziD14fg= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB03.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(4636009)(136003)(376002)(346002)(39850400004)(396003)(46966006)(36840700001)(426003)(6666004)(26005)(30864003)(8676002)(36756003)(186003)(356005)(4326008)(82310400003)(47076005)(44832011)(70586007)(336012)(70206006)(7696005)(316002)(86362001)(5660300002)(478600001)(82740400003)(83380400001)(1076003)(81166007)(8936002)(2906002)(6636002)(36860700001)(2616005)(54906003)(110136005)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jul 2021 20:41:48.1428 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e9502cc0-2de0-4f2f-9b98-08d9539a73cb X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT053.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4567 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" We currently have 1D LUTs to define output transfer function but using a 1D LUT is not always the best way to define a transfer function for HW that has ROMs for certain transfer functions, or for HW that has complex PWL definition for accurate LUT definitions. For this reason we're introducing named transfer functions. The original LUT behavior is preserved with the default "1D LUT" transfer function. Signed-off-by: Harry Wentland --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 11 +++- .../gpu/drm/arm/display/komeda/komeda_crtc.c | 7 ++- drivers/gpu/drm/arm/malidp_crtc.c | 7 ++- drivers/gpu/drm/armada/armada_crtc.c | 5 +- .../gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c | 7 ++- drivers/gpu/drm/drm_color_mgmt.c | 54 ++++++++++++++++--- drivers/gpu/drm/i915/display/intel_color.c | 11 ++-- drivers/gpu/drm/i915/display/intel_color.h | 2 +- drivers/gpu/drm/i915/display/intel_crtc.c | 4 +- drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 9 +++- drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 8 ++- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 9 +++- drivers/gpu/drm/nouveau/dispnv50/head.c | 13 +++-- drivers/gpu/drm/omapdrm/omap_crtc.c | 10 +++- drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 7 ++- drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 5 +- drivers/gpu/drm/stm/ltdc.c | 8 ++- drivers/gpu/drm/tidss/tidss_crtc.c | 9 +++- drivers/gpu/drm/vc4/vc4_crtc.c | 16 +++++- include/drm/drm_color_mgmt.h | 37 +++++++------ include/drm/drm_crtc.h | 20 +++++++ 21 files changed, 208 insertions(+), 51 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 63ddae9c5abe..b6d072211bf9 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -7343,8 +7343,15 @@ static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, acrtc->otg_inst = -1; dm->adev->mode_info.crtcs[crtc_index] = acrtc; - drm_crtc_enable_color_mgmt(&acrtc->base, MAX_COLOR_LUT_ENTRIES, - true, MAX_COLOR_LUT_ENTRIES); + + res = drm_crtc_enable_color_mgmt(&acrtc->base, MAX_COLOR_LUT_ENTRIES, + true, MAX_COLOR_LUT_ENTRIES, + BIT(DRM_TF_1D_LUT), DRM_TF_1D_LUT); + if (res) { + drm_crtc_cleanup(&acrtc->base); + goto fail; + } + drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES); return 0; diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c index 59172acb9738..f364d37232b5 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c +++ b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c @@ -626,7 +626,12 @@ static int komeda_crtc_add(struct komeda_kms_dev *kms, crtc->port = kcrtc->master->of_output_port; - drm_crtc_enable_color_mgmt(crtc, 0, true, KOMEDA_COLOR_LUT_SIZE); + err = drm_crtc_enable_color_mgmt(crtc, 0, true, KOMEDA_COLOR_LUT_SIZE, + BIT(DRM_TF_1D_LUT), DRM_TF_1D_LUT); + if (err) { + drm_crtc_cleanup(crtc); + return err; + } return err; } diff --git a/drivers/gpu/drm/arm/malidp_crtc.c b/drivers/gpu/drm/arm/malidp_crtc.c index 494075ddbef6..7af87002c375 100644 --- a/drivers/gpu/drm/arm/malidp_crtc.c +++ b/drivers/gpu/drm/arm/malidp_crtc.c @@ -552,7 +552,12 @@ int malidp_crtc_init(struct drm_device *drm) drm_crtc_helper_add(&malidp->crtc, &malidp_crtc_helper_funcs); drm_mode_crtc_set_gamma_size(&malidp->crtc, MALIDP_GAMMA_LUT_SIZE); /* No inverse-gamma: it is per-plane. */ - drm_crtc_enable_color_mgmt(&malidp->crtc, 0, true, MALIDP_GAMMA_LUT_SIZE); + ret = drm_crtc_enable_color_mgmt(&malidp->crtc, 0, true, MALIDP_GAMMA_LUT_SIZE, + BIT(DRM_TF_1D_LUT), DRM_TF_1D_LUT); + if (ret) { + drm_crtc_cleanup(&malidp->crtc); + return ret; + } malidp_se_set_enh_coeffs(malidp->dev); diff --git a/drivers/gpu/drm/armada/armada_crtc.c b/drivers/gpu/drm/armada/armada_crtc.c index b7bb90ae787f..d44a1d4fa475 100644 --- a/drivers/gpu/drm/armada/armada_crtc.c +++ b/drivers/gpu/drm/armada/armada_crtc.c @@ -992,7 +992,10 @@ static int armada_drm_crtc_create(struct drm_device *drm, struct device *dev, if (ret) return ret; - drm_crtc_enable_color_mgmt(&dcrtc->crtc, 0, false, 256); + ret = drm_crtc_enable_color_mgmt(&dcrtc->crtc, 0, false, , + BIT(DRM_TF_1D_LUT), DRM_TF_1D_LUT); + if (ret) + return ret; return armada_overlay_plane_create(drm, 1 << dcrtc->num); diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c index 05ad75d155e8..e5911826d002 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c @@ -528,8 +528,11 @@ int atmel_hlcdc_crtc_create(struct drm_device *dev) drm_crtc_helper_add(&crtc->base, &lcdc_crtc_helper_funcs); drm_mode_crtc_set_gamma_size(&crtc->base, ATMEL_HLCDC_CLUT_SIZE); - drm_crtc_enable_color_mgmt(&crtc->base, 0, false, - ATMEL_HLCDC_CLUT_SIZE); + ret = drm_crtc_enable_color_mgmt(&crtc->base, 0, false, + ATMEL_HLCDC_CLUT_SIZE, + BIT(DRM_TF_1D_LUT), DRM_TF_1D_LUT); + if (ret) + goto fail; dc->crtc = &crtc->base; diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c index daf62fb090a6..196544951ab7 100644 --- a/drivers/gpu/drm/drm_color_mgmt.c +++ b/drivers/gpu/drm/drm_color_mgmt.c @@ -147,12 +147,21 @@ u64 drm_color_ctm_s31_32_to_qm_n(u64 user_input, u32 m, u32 n) } EXPORT_SYMBOL(drm_color_ctm_s31_32_to_qm_n); +static const char * const tf_name[] = { + [DRM_TF_UNDEFINED] = "undefined", + [DRM_TF_SRGB] = "sRGB", + [DRM_TF_PQ2084] = "PQ2084", + [DRM_TF_1D_LUT] = "1D LUT", +}; + /** * drm_crtc_enable_color_mgmt - enable color management properties * @crtc: DRM CRTC * @degamma_lut_size: the size of the degamma lut (before CSC) * @has_ctm: whether to attach ctm_property for CSC matrix * @gamma_lut_size: the size of the gamma lut (after CSC) + * @supported_tfs: bitfield indicating supported transfer functions + * @default_tf: default output transfer function * * This function lets the driver enable the color correction * properties on a CRTC. This includes 3 degamma, csc and gamma @@ -162,13 +171,27 @@ EXPORT_SYMBOL(drm_color_ctm_s31_32_to_qm_n); * their size is not 0 and ctm_property is only attached if has_ctm is * true. */ -void drm_crtc_enable_color_mgmt(struct drm_crtc *crtc, +bool drm_crtc_enable_color_mgmt(struct drm_crtc *crtc, uint degamma_lut_size, bool has_ctm, - uint gamma_lut_size) + uint gamma_lut_size, + u32 supported_tfs, + enum drm_transfer_function default_tf) { struct drm_device *dev = crtc->dev; struct drm_mode_config *config = &dev->mode_config; + struct drm_property *prop; + struct drm_prop_enum_list enum_list[DRM_TF_MAX]; + int i, len; + + if (WARN_ON(supported_tfs == 0 || + (supported_tfs & -BIT(DRM_TF_MAX)) != 0 || + (supported_tfs & BIT(default_tf)) == 0)) + return -EINVAL; + + if (!!(supported_tfs & BIT(DRM_TF_1D_LUT)) != + !!(degamma_lut_size || gamma_lut_size)) + return -EINVAL; if (degamma_lut_size) { drm_object_attach_property(&crtc->base, @@ -189,6 +212,28 @@ void drm_crtc_enable_color_mgmt(struct drm_crtc *crtc, config->gamma_lut_size_property, gamma_lut_size); } + + len = 0; + for (i = 0; i < DRM_TF_MAX; i++) { + if ((supported_tfs & BIT(i)) == 0) + continue; + + enum_list[len].type = i; + enum_list[len].name = tf_name[i]; + len++; + } + + prop = drm_property_create_enum(dev, 0, "OUT TRANSFER_FUNCTION", + enum_list, len); + if (!prop) + return -ENOMEM; + crtc->out_transfer_function_property = prop; + drm_object_attach_property(&crtc->base, prop, default_tf); + if (crtc->state) + crtc->state->out_transfer_function = default_tf; + + return 0; + } EXPORT_SYMBOL(drm_crtc_enable_color_mgmt); @@ -481,11 +526,6 @@ static const char * const color_range_name[] = { [DRM_COLOR_YCBCR_LIMITED_RANGE] = "YCbCr limited range", }; -static const char * const tf_name[] = { - [DRM_TF_UNDEFINED] = "undefined", - [DRM_TF_SRGB] = "sRGB", - [DRM_TF_PQ2084] = "PQ2084", -}; /** * drm_get_color_encoding_name - return a string for color encoding * @encoding: color encoding to compute name of diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index dab892d2251b..a9332080efe5 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -2093,7 +2093,7 @@ static void icl_read_luts(struct intel_crtc_state *crtc_state) } } -void intel_color_init(struct intel_crtc *crtc) +bool intel_color_init(struct intel_crtc *crtc) { struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); bool has_ctm = INTEL_INFO(dev_priv)->color.degamma_lut_size != 0; @@ -2150,8 +2150,9 @@ void intel_color_init(struct intel_crtc *crtc) } } - drm_crtc_enable_color_mgmt(&crtc->base, - INTEL_INFO(dev_priv)->color.degamma_lut_size, - has_ctm, - INTEL_INFO(dev_priv)->color.gamma_lut_size); + return drm_crtc_enable_color_mgmt(&crtc->base, + INTEL_INFO(dev_priv)->color.degamma_lut_size, + has_ctm, + INTEL_INFO(dev_priv)->color.gamma_lut_size, + BIT(DRM_TF_1D_LUT), DRM_TF_1D_LUT); } diff --git a/drivers/gpu/drm/i915/display/intel_color.h b/drivers/gpu/drm/i915/display/intel_color.h index 173727aaa24d..a8e015acc60c 100644 --- a/drivers/gpu/drm/i915/display/intel_color.h +++ b/drivers/gpu/drm/i915/display/intel_color.h @@ -12,7 +12,7 @@ struct intel_crtc_state; struct intel_crtc; struct drm_property_blob; -void intel_color_init(struct intel_crtc *crtc); +bool intel_color_init(struct intel_crtc *crtc); int intel_color_check(struct intel_crtc_state *crtc_state); void intel_color_commit(const struct intel_crtc_state *crtc_state); void intel_color_load_luts(const struct intel_crtc_state *crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c index 95ff1707b4bd..0846fb4ef14e 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc.c +++ b/drivers/gpu/drm/i915/display/intel_crtc.c @@ -340,7 +340,9 @@ int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe) BIT(DRM_SCALING_FILTER_DEFAULT) | BIT(DRM_SCALING_FILTER_NEAREST_NEIGHBOR)); - intel_color_init(crtc); + ret = intel_color_init(crtc); + if (ret) + goto fail; intel_crtc_crc_init(crtc); diff --git a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c index 5244f4763477..f21fdd7e5f2a 100644 --- a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c +++ b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c @@ -1017,8 +1017,13 @@ static int ingenic_drm_bind(struct device *dev, bool has_components) return ret; } - drm_crtc_enable_color_mgmt(&priv->crtc, 0, false, - ARRAY_SIZE(priv->dma_hwdescs->palette)); + ret = drm_crtc_enable_color_mgmt(&priv->crtc, 0, false, + ARRAY_SIZE(priv->dma_hwdescs->palette), + BIT(DRM_TF_1D_LUT), DRM_TF_1D_LUT); + if (ret) { + dev_err(dev, "Failed to init color management: %i\n", ret); + return ret; + } if (soc_info->has_osd) { drm_plane_helper_add(&priv->f0, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c index 474efb844249..d2496ad16931 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c @@ -827,7 +827,13 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev, if (gamma_lut_size) drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size); - drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size); + ret = drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size, + BIT(DRM_TF_1D_LUT), DRM_TF_1D_LUT); + if (ret) { + drm_crtc_cleanup(mtk_crtc->base); + kfree(mtk_crtc); + return ret; + priv->num_pipes++; mutex_init(&mtk_crtc->hw_lock); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index 9a5c70c87cc8..9b7e947e8c8b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -1337,6 +1337,7 @@ struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane, struct drm_crtc *crtc = NULL; struct dpu_crtc *dpu_crtc = NULL; int i; + int ret = 0; dpu_crtc = kzalloc(sizeof(*dpu_crtc), GFP_KERNEL); if (!dpu_crtc) @@ -1365,7 +1366,13 @@ struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane, drm_crtc_helper_add(crtc, &dpu_crtc_helper_funcs); - drm_crtc_enable_color_mgmt(crtc, 0, true, 0); + ret = drm_crtc_enable_color_mgmt(crtc, 0, true, 0, + BIT(DRM_TF_UNDEFINED), DRM_TF_UNDEFINED); + if (ret) { + drm_crtc_cleanup(crtc); + kfree(dpu_crtc); + return ERR_PTR(ret); + } /* save user friendly CRTC name for later */ snprintf(dpu_crtc->name, DPU_CRTC_NAME_SIZE, "crtc%u", crtc->base.id); diff --git a/drivers/gpu/drm/nouveau/dispnv50/head.c b/drivers/gpu/drm/nouveau/dispnv50/head.c index ec361d17e900..f97b3f70152b 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head.c @@ -589,9 +589,16 @@ nv50_head_create(struct drm_device *dev, int index) drm_crtc_helper_add(crtc, &nv50_head_help); /* Keep the legacy gamma size at 256 to avoid compatibility issues */ drm_mode_crtc_set_gamma_size(crtc, 256); - drm_crtc_enable_color_mgmt(crtc, base->func->ilut_size, - disp->disp->object.oclass >= GF110_DISP, - head->func->olut_size); + ret = drm_crtc_enable_color_mgmt(crtc, base->func->ilut_size, + disp->disp->object.oclass >= GF110_DISP, + head->func->olut_size, + BIT(DRM_TF_1D_LUT), DRM_TF_1D_LUT); + if (ret) { + drm_crtc_cleanup(crtc); + kfree(head); + return ERR_PTR(ret); + } + if (head->func->olut_set) { ret = nv50_lut_init(disp, &drm->client.mmu, &head->olut); diff --git a/drivers/gpu/drm/omapdrm/omap_crtc.c b/drivers/gpu/drm/omapdrm/omap_crtc.c index 06a719c104f4..a618b3338c38 100644 --- a/drivers/gpu/drm/omapdrm/omap_crtc.c +++ b/drivers/gpu/drm/omapdrm/omap_crtc.c @@ -839,7 +839,15 @@ struct drm_crtc *omap_crtc_init(struct drm_device *dev, if (dispc_mgr_gamma_size(priv->dispc, channel)) { unsigned int gamma_lut_size = 256; - drm_crtc_enable_color_mgmt(crtc, gamma_lut_size, true, 0); + ret = drm_crtc_enable_color_mgmt(crtc, gamma_lut_size, true, 0, + BIT(DRM_TF_1D_LUT), DRM_TF_1D_LUT); + if (ret) { + dev_err(dev->dev, "$s(): could not init color management for: %s\n", + __func__, pipe->output->name); + drm_crtc_cleanup(crtc); + kfree(omap_crtc); + return ERR_PTR(ret); + } drm_mode_crtc_set_gamma_size(crtc, gamma_lut_size); } diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c index ea7e39d03545..02d8737e6603 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c @@ -1263,7 +1263,12 @@ int rcar_du_crtc_create(struct rcar_du_group *rgrp, unsigned int swindex, rgrp->cmms_mask |= BIT(hwindex % 2); drm_mode_crtc_set_gamma_size(crtc, CM2_LUT_SIZE); - drm_crtc_enable_color_mgmt(crtc, 0, false, CM2_LUT_SIZE); + ret = drm_crtc_enable_color_mgmt(crtc, 0, false, CM2_LUT_SIZE, + BIT(DRM_TF_1D_LUT), DRM_TF_1D_LUT); + if (ret) { + drm_crtc_cleanup(crtc); + return ret; + } } drm_crtc_helper_add(crtc, &crtc_helper_funcs); diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index f5b9028a16a3..68d3a7b1f041 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c @@ -1817,7 +1817,10 @@ static int vop_create_crtc(struct vop *vop) drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs); if (vop->lut_regs) { drm_mode_crtc_set_gamma_size(crtc, vop_data->lut_size); - drm_crtc_enable_color_mgmt(crtc, 0, false, vop_data->lut_size); + ret = drm_crtc_enable_color_mgmt(crtc, 0, false, vop_data->lut_size, + BIT(DRM_TF_1D_LUT), DRM_TF_1D_LUT); + if (ret) + goto err_cleanup_crtc; } /* diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c index 08b71248044d..ffdf7114f50a 100644 --- a/drivers/gpu/drm/stm/ltdc.c +++ b/drivers/gpu/drm/stm/ltdc.c @@ -1035,7 +1035,13 @@ static int ltdc_crtc_init(struct drm_device *ddev, struct drm_crtc *crtc) drm_crtc_helper_add(crtc, <dc_crtc_helper_funcs); drm_mode_crtc_set_gamma_size(crtc, CLUT_SIZE); - drm_crtc_enable_color_mgmt(crtc, 0, false, CLUT_SIZE); + ret = drm_crtc_enable_color_mgmt(crtc, 0, false, CLUT_SIZE, + BIT(DRM_TF_1D_LUT), DRM_TF_1D_LUT); + if (ret) { + DRM_ERROR("Can not initialize color management\n"); + drm_crtc_cleanup(crtc); + goto cleanup; + } DRM_DEBUG_DRIVER("CRTC:%d created\n", crtc->base.id); diff --git a/drivers/gpu/drm/tidss/tidss_crtc.c b/drivers/gpu/drm/tidss/tidss_crtc.c index 2218da3b3ca3..34ed098887bc 100644 --- a/drivers/gpu/drm/tidss/tidss_crtc.c +++ b/drivers/gpu/drm/tidss/tidss_crtc.c @@ -439,7 +439,14 @@ struct tidss_crtc *tidss_crtc_create(struct tidss_device *tidss, if (tidss->feat->vp_feat.color.gamma_size) gamma_lut_size = 256; - drm_crtc_enable_color_mgmt(crtc, 0, has_ctm, gamma_lut_size); + ret = drm_crtc_enable_color_mgmt(crtc, 0, has_ctm, gamma_lut_size, + BIT(DRM_TF_1D_LUT), DRM_TF_1D_LUT); + if (ret) { + drm_crtc_cleanup(crtc); + kfree(tcrtc); + return ERR_PTR(ret); + } + if (gamma_lut_size) drm_mode_crtc_set_gamma_size(crtc, gamma_lut_size); diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c index 18f5009ce90e..3bb2c0dba09a 100644 --- a/drivers/gpu/drm/vc4/vc4_crtc.c +++ b/drivers/gpu/drm/vc4/vc4_crtc.c @@ -1118,12 +1118,24 @@ int vc4_crtc_init(struct drm_device *drm, struct vc4_crtc *vc4_crtc, if (!vc4->hvs->hvs5) { drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r)); - drm_crtc_enable_color_mgmt(crtc, 0, false, crtc->gamma_size); + ret = drm_crtc_enable_color_mgmt(crtc, 0, false, crtc->gamma_size, + BIT(DRM_TF_1D_LUT), DRM_TF_1D_LUT); + if (ret) { + dev_err(drm->dev, "failed to enable color management\n"); + drm_crtc_cleanup(crtc); + return ret; + } /* We support CTM, but only for one CRTC at a time. It's therefore * implemented as private driver state in vc4_kms, not here. */ - drm_crtc_enable_color_mgmt(crtc, 0, true, crtc->gamma_size); + ret = drm_crtc_enable_color_mgmt(crtc, 0, true, crtc->gamma_size, + BIT(DRM_TF_1D_LUT), DRM_TF_1D_LUT); + if (ret) { + dev_err(drm->dev, "failed to enable color management\n"); + drm_crtc_cleanup(crtc); + return ret; + } } for (i = 0; i < crtc->gamma_size; i++) { diff --git a/include/drm/drm_color_mgmt.h b/include/drm/drm_color_mgmt.h index 370bbc55b744..408561acdb3d 100644 --- a/include/drm/drm_color_mgmt.h +++ b/include/drm/drm_color_mgmt.h @@ -54,10 +54,29 @@ static inline u32 drm_color_lut_extract(u32 user_input, int bit_precision) u64 drm_color_ctm_s31_32_to_qm_n(u64 user_input, u32 m, u32 n); -void drm_crtc_enable_color_mgmt(struct drm_crtc *crtc, +/** + * enum drm_transfer_function - common transfer function used for sdr/hdr formats + * + * DRM_TF_UNDEFINED - The legacy case where a TF in and out of the blending + * space is undefined + * DRM_TF_SRGB - Based on gamma curve and is used for printer/monitors/web + * DRM_TF_PQ2084 - Used for HDR and allows for up to 10,000 nit support. + * DRM_TF_1D_LUT - Use 1D gamma/degamma LUTs (currently only defined on crtc) +*/ +enum drm_transfer_function { + DRM_TF_UNDEFINED, + DRM_TF_SRGB, + DRM_TF_PQ2084, + DRM_TF_1D_LUT, + DRM_TF_MAX, +}; + +bool drm_crtc_enable_color_mgmt(struct drm_crtc *crtc, uint degamma_lut_size, bool has_ctm, - uint gamma_lut_size); + uint gamma_lut_size, + u32 supported_tfs, + enum drm_transfer_function default_tf); int drm_mode_crtc_set_gamma_size(struct drm_crtc *crtc, int gamma_size); @@ -87,20 +106,6 @@ enum drm_color_range { DRM_COLOR_RANGE_MAX, }; -/** - * enum drm_transfer_function - common transfer function used for sdr/hdr formats - * - * DRM_TF_UNDEFINED - The legacy case where a TF in and out of the blending - * space is undefined - * DRM_TF_SRGB - Based on gamma curve and is used for printer/monitors/web - * DRM_TF_PQ2084 - Used for HDR and allows for up to 10,000 nit support. -*/ -enum drm_transfer_function { - DRM_TF_UNDEFINED, - DRM_TF_SRGB, - DRM_TF_PQ2084, - DRM_TF_MAX, -}; int drm_plane_create_color_properties(struct drm_plane *plane, u32 supported_encodings, u32 supported_ranges, diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index 13eeba2a750a..35580dd36294 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -288,6 +288,15 @@ struct drm_crtc_state { */ struct drm_property_blob *gamma_lut; + /** + * @out_transfer_function: + * + * Transfer function for conversion from blending space to + * display space. DRM_TF_1D_LUT can be specified to use the + * gamma/degamma LUTs from mode_config instead. + */ + enum drm_transfer_function out_transfer_function; + /** * @target_vblank: * @@ -1096,6 +1105,17 @@ struct drm_crtc { */ struct drm_property *scaling_filter_property; + /** + * @out_transfer_function_property: + * + * Optional "OUT TRANSFER FUNCTION" enum property for specifying + * an output transfer function, i.e. a TF to convert from + * blending space to luminance space. Use DRM_TF_1D_LUT to + * indicate using the 1D gamma/degamma LUTs instead of a + * named transfer function. + */ + struct drm_property *out_transfer_function_property; + /** * @state: * From patchwork Fri Jul 30 20:41:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Harry Wentland X-Patchwork-Id: 12411935 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1AD15C432BE for ; Fri, 30 Jul 2021 20:42:01 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DEAB560EE6 for ; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; Received: from SATLEXMB03.amd.com (165.204.84.17) by DM6NAM11FT032.mail.protection.outlook.com (10.13.173.93) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4373.18 via Frontend Transport; Fri, 30 Jul 2021 20:41:48 +0000 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2242.12; Fri, 30 Jul 2021 15:41:42 -0500 Received: from hwentlanryzen.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2242.12 via Frontend Transport; Fri, 30 Jul 2021 15:41:41 -0500 From: Harry Wentland To: , , , , , , CC: , , , , , , , , , , "Harry Wentland" Subject: [RFC PATCH v3 4/6] drm/color: Add sdr boost property Date: Fri, 30 Jul 2021 16:41:32 -0400 Message-ID: <20210730204134.21769-5-harry.wentland@amd.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210730204134.21769-1-harry.wentland@amd.com> References: <20210730204134.21769-1-harry.wentland@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a0f21661-8a38-4f96-bdda-08d9539a73df X-MS-TrafficTypeDiagnostic: BY5PR12MB4999: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:9508; 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CAT:NONE; SFS:(4636009)(396003)(39860400002)(346002)(136003)(376002)(46966006)(36840700001)(2906002)(83380400001)(26005)(1076003)(4326008)(54906003)(2616005)(336012)(8936002)(86362001)(44832011)(426003)(81166007)(7696005)(478600001)(82740400003)(5660300002)(186003)(316002)(6666004)(356005)(70586007)(36756003)(8676002)(70206006)(6636002)(110136005)(82310400003)(47076005)(36860700001)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jul 2021 20:41:48.2808 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a0f21661-8a38-4f96-bdda-08d9539a73df X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT032.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4999 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Bhawanpreet Lakha SDR is typically mastered at 200 nits and HDR is mastered at up to 10,000 nits. Due to this luminance range difference if we blend a SDR and HDR plane together, we can run into problems where the HDR plane is too bright or the SDR plane is too dim A common solution to this problem is to boost the SDR plane so that its not too dim. This patch introduces a "sdr_white_level" property, this property can be used by the userspace to boost the SDR content luminance. The boost value is an explicit luminance value in nits. This allows the userspace to set the maximum white level for the SDR plane. v2: - fix type in description Signed-off-by: Bhawanpreet Lakha Signed-off-by: Harry Wentland --- drivers/gpu/drm/drm_atomic_uapi.c | 4 ++++ drivers/gpu/drm/drm_color_mgmt.c | 17 +++++++++++++++++ include/drm/drm_color_mgmt.h | 6 ++++++ include/drm/drm_plane.h | 15 ++++++++++++++- 4 files changed, 41 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/drm_atomic_uapi.c b/drivers/gpu/drm/drm_atomic_uapi.c index 9582515dd12e..e5a193657f7d 100644 --- a/drivers/gpu/drm/drm_atomic_uapi.c +++ b/drivers/gpu/drm/drm_atomic_uapi.c @@ -598,6 +598,8 @@ static int drm_atomic_plane_set_property(struct drm_plane *plane, state->color_range = val; } else if (property == plane->transfer_function_property) { state->transfer_function = val; + } else if (property == plane->sdr_white_level_property) { + state->sdr_white_level = val; } else if (property == config->prop_fb_damage_clips) { ret = drm_atomic_replace_property_blob_from_id(dev, &state->fb_damage_clips, @@ -666,6 +668,8 @@ drm_atomic_plane_get_property(struct drm_plane *plane, *val = state->color_range; } else if (property == plane->transfer_function_property) { *val = state->transfer_function; + } else if (property == plane->sdr_white_level_property) { + *val = state->sdr_white_level; } else if (property == config->prop_fb_damage_clips) { *val = (state->fb_damage_clips) ? state->fb_damage_clips->base.id : 0; diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c index 196544951ab7..44842ba0454d 100644 --- a/drivers/gpu/drm/drm_color_mgmt.c +++ b/drivers/gpu/drm/drm_color_mgmt.c @@ -556,6 +556,23 @@ const char *drm_get_color_range_name(enum drm_color_range range) return color_range_name[range]; } +int drm_plane_create_sdr_white_level_property(struct drm_plane *plane){ + + struct drm_property *prop; + + prop = drm_property_create_range(plane->dev, 0, "SDR_WHITE_LEVEL", 0, UINT_MAX); + + if (!prop) + return -ENOMEM; + + plane->sdr_white_level_property = prop; + drm_object_attach_property(&plane->base, prop, DRM_DEFAULT_SDR_WHITE_LEVEL); + + if (plane->state) + plane->state->sdr_white_level = DRM_DEFAULT_SDR_WHITE_LEVEL; + + return 0; +} /** * drm_get_transfer_function - return a string for transfer function * @tf: transfer function to compute name of diff --git a/include/drm/drm_color_mgmt.h b/include/drm/drm_color_mgmt.h index 408561acdb3d..2a356a9601df 100644 --- a/include/drm/drm_color_mgmt.h +++ b/include/drm/drm_color_mgmt.h @@ -26,6 +26,12 @@ #include #include +/** + * Default SDR white level in nits. Although there is no standard SDR nit level, 200 + * is chosen as the default since that is the generally accepted value. + */ +#define DRM_DEFAULT_SDR_WHITE_LEVEL 200 + struct drm_crtc; struct drm_plane; diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h index cff56994513f..93ee308a46af 100644 --- a/include/drm/drm_plane.h +++ b/include/drm/drm_plane.h @@ -187,6 +187,11 @@ struct drm_plane_state { * format for a proper HDR color/luminance output. */ enum drm_transfer_function transfer_function; + /** + * @sdr_white_level: + * SDR white level boost for HDR+SDR multi plane usecases. max white level in nits + */ + unsigned int sdr_white_level; /** * @fb_damage_clips: * @@ -757,7 +762,15 @@ struct drm_plane { * See drm_plane_create_color_properties(). */ struct drm_property *transfer_function_property; - + /** + * @sdr_white_level: + * + * Optional sdr_white_level. When HDR and SDR are combined in multi plane + * overlay cases, the sdr plane will be very dim. This property allows + * the driver to boost the sdr plane's white level. The value should be + * max white level in nits. + */ + struct drm_property *sdr_white_level_property; /** * @scaling_filter_property: property to apply a particular filter while * scaling. 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Fri, 30 Jul 2021 15:41:43 -0500 From: Harry Wentland To: , , , , , , CC: , , , , , , , , , , "Harry Wentland" Subject: [RFC PATCH v3 5/6] drm/color: Add color space plane property Date: Fri, 30 Jul 2021 16:41:33 -0400 Message-ID: <20210730204134.21769-6-harry.wentland@amd.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210730204134.21769-1-harry.wentland@amd.com> References: <20210730204134.21769-1-harry.wentland@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: bb9de49d-7975-48dd-1890-08d9539a746c X-MS-TrafficTypeDiagnostic: MN2PR12MB3856: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6430; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: xPz4y6EcWbYuUYKQ773kp2hQGAoq/xr7opcc0TjAYUWcOXF7rfHy81+u8kHYSEv0OncANRD5epJXHJCwhXFeu349Iyj5ZlRE1D7WRkZkUNzNizcb6A0PENQOSYlL7N+ZuNxqie6mXM6OEcbMld5Npz0xvJQcsu4azu41pBjqcEC7tAHZTKkO7B3TSXNFZjUsv+Bxui0FhSdmTEBkoSJLp7RHnNFFIHW/Zk1u83fcb7o2B9Sri5xL8sOzVjhJnjHiYXaGN0hiQOO3T087JmtE+8IMAEYN4/Hqf4Mdi3Zjh/3z9AeNQoUwEvK0p9f2QKUEo11yFkl1iD1IDFvSYSj8S0b655OXj+CNwC6N5EWMFMEvlujOkXJapztATv0VqTZFwd1k7JMXT9tIwZswVtr+PahqzNl3xwLZ2S1YMMDoimRx6/VPRoFiB+yyi9rLfypsiO1VH/rK6wwxTe8YtUcX/3nid2+EMO87q1+7lOjt4S4UeL/B0FFyu5HN0yByFM2DGFurY6fQQF0mwzwHJ9hWwg6YywP5EKrnuNc9DfLi/Jxc0nS0NAptJAHy2qrMDQrq+qRJXDxEqGmSvN6jF0PA5ETmzgnyEMt1+Q1EwGO0LQqjqOmdShR0fTw3Od4nHwiKbhtkWk5Qsp1CvuzOFkg37a21Q5+9u9CCno0W7PCgcAW7ZSPfOV0JLKbdGeKNqKQRovPGsZYn4vLEND4i2UsESLd/JqyPXykluFhQL6f92Vo= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(4636009)(346002)(376002)(396003)(39860400002)(136003)(36840700001)(46966006)(478600001)(82310400003)(36756003)(316002)(26005)(2906002)(6636002)(1076003)(81166007)(82740400003)(5660300002)(30864003)(6666004)(186003)(44832011)(2616005)(336012)(70206006)(36860700001)(356005)(4326008)(110136005)(47076005)(8676002)(70586007)(8936002)(426003)(54906003)(83380400001)(86362001)(7696005)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jul 2021 20:41:49.1366 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bb9de49d-7975-48dd-1890-08d9539a746c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT019.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB3856 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Bhawanpreet Lakha Add color space definitions for BT601, BT709, BT2020, and DCI-P3. Default to BT709, the sRGB color space. Signed-off-by: Bhawanpreet Lakha Signed-off-by: Harry Wentland --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 + .../gpu/drm/arm/display/komeda/komeda_plane.c | 2 + drivers/gpu/drm/arm/malidp_planes.c | 4 +- drivers/gpu/drm/armada/armada_overlay.c | 2 + drivers/gpu/drm/drm_color_mgmt.c | 58 ++++++++++++++++++- drivers/gpu/drm/i915/display/intel_sprite.c | 2 + .../drm/i915/display/skl_universal_plane.c | 2 + drivers/gpu/drm/nouveau/dispnv04/overlay.c | 2 + drivers/gpu/drm/omapdrm/omap_plane.c | 2 + drivers/gpu/drm/sun4i/sun8i_vi_layer.c | 6 +- drivers/gpu/drm/tidss/tidss_plane.c | 4 ++ include/drm/drm_color_mgmt.h | 16 +++++ include/drm/drm_plane.h | 16 +++++ 13 files changed, 113 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index b6d072211bf9..a6dbf1f26787 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -7276,8 +7276,10 @@ static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, BIT(DRM_COLOR_YCBCR_BT2020), BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | BIT(DRM_COLOR_YCBCR_FULL_RANGE), + BIT(DRM_COLOR_SPACE_BT709), BIT(DRM_TF_SRGB), DRM_COLOR_YCBCR_BT709, DRM_COLOR_YCBCR_LIMITED_RANGE, + DRM_COLOR_SPACE_BT709, DRM_TF_SRGB); } diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_plane.c b/drivers/gpu/drm/arm/display/komeda/komeda_plane.c index 811f79ab6d32..4fb3ad4c691e 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_plane.c +++ b/drivers/gpu/drm/arm/display/komeda/komeda_plane.c @@ -302,9 +302,11 @@ static int komeda_plane_add(struct komeda_kms_dev *kms, BIT(DRM_COLOR_YCBCR_BT2020), BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | BIT(DRM_COLOR_YCBCR_FULL_RANGE), + BIT(DRM_COLOR_SPACE_BT709), BIT(DRM_TF_UNDEFINED), DRM_COLOR_YCBCR_BT601, DRM_COLOR_YCBCR_LIMITED_RANGE, + DRM_COLOR_SPACE_BT709, DRM_TF_UNDEFINED); if (err) goto cleanup; diff --git a/drivers/gpu/drm/arm/malidp_planes.c b/drivers/gpu/drm/arm/malidp_planes.c index 98d308262880..0bc809435555 100644 --- a/drivers/gpu/drm/arm/malidp_planes.c +++ b/drivers/gpu/drm/arm/malidp_planes.c @@ -1023,6 +1023,7 @@ int malidp_de_planes_init(struct drm_device *drm) /* default encoding for YUV->RGB is BT601 NARROW */ enum drm_color_encoding enc = DRM_COLOR_YCBCR_BT601; enum drm_color_range range = DRM_COLOR_YCBCR_LIMITED_RANGE; + enum drm_color_space space = DRM_COLOR_SPACE_BT709; ret = drm_plane_create_color_properties(&plane->base, BIT(DRM_COLOR_YCBCR_BT601) | \ @@ -1030,8 +1031,9 @@ int malidp_de_planes_init(struct drm_device *drm) BIT(DRM_COLOR_YCBCR_BT2020), BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | \ BIT(DRM_COLOR_YCBCR_FULL_RANGE), + BIT(DRM_COLOR_SPACE_BT709), BIT(DRM_TF_UNDEFINED), - enc, range, + enc, range, space, DRM_TF_UNDEFINED); if (!ret) /* program the HW registers */ diff --git a/drivers/gpu/drm/armada/armada_overlay.c b/drivers/gpu/drm/armada/armada_overlay.c index f7792444cb73..e66f2fa72830 100644 --- a/drivers/gpu/drm/armada/armada_overlay.c +++ b/drivers/gpu/drm/armada/armada_overlay.c @@ -596,9 +596,11 @@ int armada_overlay_plane_create(struct drm_device *dev, unsigned long crtcs) BIT(DRM_COLOR_YCBCR_BT601) | BIT(DRM_COLOR_YCBCR_BT709), BIT(DRM_COLOR_YCBCR_LIMITED_RANGE), + BIT(DRM_COLOR_SPACE_BT709), BIT(DRM_TF_UNDEFINED), DEFAULT_ENCODING, DRM_COLOR_YCBCR_LIMITED_RANGE, + DRM_COLOR_SPACE_BT709, DRM_TF_UNDEFINED); return ret; diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c index 44842ba0454d..75e6dbbd0081 100644 --- a/drivers/gpu/drm/drm_color_mgmt.c +++ b/drivers/gpu/drm/drm_color_mgmt.c @@ -526,6 +526,13 @@ static const char * const color_range_name[] = { [DRM_COLOR_YCBCR_LIMITED_RANGE] = "YCbCr limited range", }; +static const char * const color_space_name[] = { + [DRM_COLOR_SPACE_BT601] = "ITU-R BT.601 RGB", + [DRM_COLOR_SPACE_BT709] = "ITU-R BT.709 RGB", + [DRM_COLOR_SPACE_BT2020] = "ITU-R BT.2020 RGB", + [DRM_COLOR_SPACE_P3] = "DCI-P3", +}; + /** * drm_get_color_encoding_name - return a string for color encoding * @encoding: color encoding to compute name of @@ -556,6 +563,21 @@ const char *drm_get_color_range_name(enum drm_color_range range) return color_range_name[range]; } +/** + * drm_get_color_space_name - return a string for color space + * @space: color space to compute name of + * + * In contrast to the other drm_get_*_name functions this one here returns a + * const pointer and hence is threadsafe. + */ +const char *drm_get_color_space_name(enum drm_color_space space) +{ + if (WARN_ON(space >= ARRAY_SIZE(color_space_name))) + return "unknown"; + + return color_space_name[space]; +} + int drm_plane_create_sdr_white_level_property(struct drm_plane *plane){ struct drm_property *prop; @@ -592,23 +614,28 @@ const char *drm_get_transfer_function_name(enum drm_transfer_function tf) * @plane: plane object * @supported_encodings: bitfield indicating supported color encodings * @supported_ranges: bitfileld indicating supported color ranges + * @supported_spaces: bitfield indicating supported color spaces * @supported_tfs: bitfield indicating supported transfer functions * @default_encoding: default color encoding * @default_range: default color range + * @default_space: default color space * @default_tf: default color transfer function * - * Create and attach plane specific COLOR_ENCODING, COLOR_RANGE and TRANSFER_FUNCTION - * properties to @plane. The supported encodings, ranges and tfs should - * be provided in supported_encodings, supported_ranges and supported_tfs bitmasks. + * Create and attach plane specific COLOR_ENCODING, COLOR_RANGE, COLOR_SPACE, + * and TRANSFER_FUNCTION properties to @plane. The supported encodings, ranges, + * spaces, and tfs should be provided in supported_encodings, supported_ranges, + * supported_spaces, and supported_tfs bitmasks. * Each bit set in the bitmask indicates that its number as enum * value is supported. */ int drm_plane_create_color_properties(struct drm_plane *plane, u32 supported_encodings, u32 supported_ranges, + u32 supported_spaces, u32 supported_tfs, enum drm_color_encoding default_encoding, enum drm_color_range default_range, + enum drm_color_space default_space, enum drm_transfer_function default_tf) { struct drm_device *dev = plane->dev; @@ -628,6 +655,11 @@ int drm_plane_create_color_properties(struct drm_plane *plane, (supported_ranges & BIT(default_range)) == 0)) return -EINVAL; + if (WARN_ON(supported_spaces == 0 || + (supported_spaces & -BIT(DRM_COLOR_SPACE_MAX)) != 0 || + (supported_spaces & BIT(default_space)) == 0)) + return -EINVAL; + if (WARN_ON(supported_tfs == 0 || (supported_tfs & -BIT(DRM_TF_MAX)) != 0 || (supported_tfs & BIT(default_tf)) == 0)) @@ -672,6 +704,26 @@ int drm_plane_create_color_properties(struct drm_plane *plane, plane->state->color_range = default_range; + len = 0; + for (i = 0; i < DRM_COLOR_SPACE_MAX; i++) { + if ((supported_spaces & BIT(i)) == 0) + continue; + + enum_list[len].type = i; + enum_list[len].name = color_space_name[i]; + len++; + } + + prop = drm_property_create_enum(dev, 0, "COLOR_SPACE", + enum_list, len); + if (!prop) + return -ENOMEM; + plane->color_space_property = prop; + drm_object_attach_property(&plane->base, prop, default_space); + if (plane->state) + plane->state->color_space = default_space; + + len = 0; for (i = 0; i < DRM_TF_MAX; i++) { if ((supported_tfs & BIT(i)) == 0) diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c index b3f7aca3795b..76637b1aa5dc 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c @@ -1850,9 +1850,11 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, BIT(DRM_COLOR_YCBCR_BT709), BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | BIT(DRM_COLOR_YCBCR_FULL_RANGE), + BIT(DRM_COLOR_SPACE_BT709), BIT(DRM_TF_UNDEFINED), DRM_COLOR_YCBCR_BT709, DRM_COLOR_YCBCR_LIMITED_RANGE, + DRM_COLOR_SPACE_BT709, DRM_TF_UNDEFINED); zpos = sprite + 1; diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index df596431151d..3ed65e527dde 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -2160,9 +2160,11 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, supported_csc, BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | BIT(DRM_COLOR_YCBCR_FULL_RANGE), + BIT(DRM_COLOR_SPACE_BT709), BIT(DRM_TF_UNDEFINED), DRM_COLOR_YCBCR_BT709, DRM_COLOR_YCBCR_LIMITED_RANGE, + DRM_COLOR_SPACE_BT709, DRM_TF_UNDEFINED); drm_plane_create_alpha_property(&plane->base); diff --git a/drivers/gpu/drm/nouveau/dispnv04/overlay.c b/drivers/gpu/drm/nouveau/dispnv04/overlay.c index 64e1793212b4..dc350245c98b 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/overlay.c +++ b/drivers/gpu/drm/nouveau/dispnv04/overlay.c @@ -345,9 +345,11 @@ nv10_overlay_init(struct drm_device *device) BIT(DRM_COLOR_YCBCR_BT601) | BIT(DRM_COLOR_YCBCR_BT709), BIT(DRM_COLOR_YCBCR_LIMITED_RANGE), + BIT(DRM_COLOR_SPACE_BT709), BIT(DRM_TF_UNDEFINED), DRM_COLOR_YCBCR_BT601, DRM_COLOR_YCBCR_LIMITED_RANGE, + DRM_COLOR_SPACE_BT709, DRM_TF_UNDEFINED); plane->set_params = nv10_set_params; diff --git a/drivers/gpu/drm/omapdrm/omap_plane.c b/drivers/gpu/drm/omapdrm/omap_plane.c index ca7559824dcd..3eb52e78e08d 100644 --- a/drivers/gpu/drm/omapdrm/omap_plane.c +++ b/drivers/gpu/drm/omapdrm/omap_plane.c @@ -325,9 +325,11 @@ struct drm_plane *omap_plane_init(struct drm_device *dev, BIT(DRM_COLOR_YCBCR_BT709), BIT(DRM_COLOR_YCBCR_FULL_RANGE) | BIT(DRM_COLOR_YCBCR_LIMITED_RANGE), + BIT(DRM_COLOR_SPACE_BT709), BIT(DRM_TF_UNDEFINED), DRM_COLOR_YCBCR_BT601, DRM_COLOR_YCBCR_FULL_RANGE, + DRM_COLOR_SPACE_BT709, DRM_TF_UNDEFINED); return plane; diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c index eda8f51bafd7..c0115783c6a6 100644 --- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c +++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c @@ -543,7 +543,7 @@ struct sun8i_vi_layer *sun8i_vi_layer_init_one(struct drm_device *drm, struct sun8i_mixer *mixer, int index) { - u32 supported_encodings, supported_ranges; + u32 supported_encodings, supported_ranges, supported_spaces; unsigned int plane_cnt, format_count; struct sun8i_vi_layer *layer; const u32 *formats; @@ -597,12 +597,16 @@ struct sun8i_vi_layer *sun8i_vi_layer_init_one(struct drm_device *drm, supported_ranges = BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | BIT(DRM_COLOR_YCBCR_FULL_RANGE); + supported_spaces = BIT(DRM_COLOR_SPACE_BT709); + ret = drm_plane_create_color_properties(&layer->plane, supported_encodings, supported_ranges, + supported_spaces, BIT(DRM_TF_UNDEFINED), DRM_COLOR_YCBCR_BT709, DRM_COLOR_YCBCR_LIMITED_RANGE, + DRM_COLOR_SPACE_BT709, DRM_TF_UNDEFINED); if (ret) { dev_err(drm->dev, "Couldn't add encoding and range properties!\n"); diff --git a/drivers/gpu/drm/tidss/tidss_plane.c b/drivers/gpu/drm/tidss/tidss_plane.c index a1336ecd5fd5..367a14616756 100644 --- a/drivers/gpu/drm/tidss/tidss_plane.c +++ b/drivers/gpu/drm/tidss/tidss_plane.c @@ -186,9 +186,11 @@ struct tidss_plane *tidss_plane_create(struct tidss_device *tidss, BIT(DRM_COLOR_YCBCR_BT709)); u32 color_ranges = (BIT(DRM_COLOR_YCBCR_FULL_RANGE) | BIT(DRM_COLOR_YCBCR_LIMITED_RANGE)); + u32 color_spaces = BIT(DRM_COLOR_SPACE_BY709); u32 transfer_functions = BIT(DRM_TF_UNDEFINED; u32 default_encoding = DRM_COLOR_YCBCR_BT601; u32 default_range = DRM_COLOR_YCBCR_FULL_RANGE; + u32 default_space = DRM_COLOR_SPACE_BT709; u32 default_tf = DRM_TF_UNDEFINED;; u32 blend_modes = (BIT(DRM_MODE_BLEND_PREMULTI) | BIT(DRM_MODE_BLEND_COVERAGE)); @@ -219,9 +221,11 @@ struct tidss_plane *tidss_plane_create(struct tidss_device *tidss, ret = drm_plane_create_color_properties(&tplane->plane, color_encodings, color_ranges, + color_spaces, transfer_functions, default_encoding, default_range, + default_space, default_tf); if (ret) goto err; diff --git a/include/drm/drm_color_mgmt.h b/include/drm/drm_color_mgmt.h index 2a356a9601df..575427650542 100644 --- a/include/drm/drm_color_mgmt.h +++ b/include/drm/drm_color_mgmt.h @@ -99,6 +99,9 @@ static inline int drm_color_lut_size(const struct drm_property_blob *blob) return blob->length / sizeof(struct drm_color_lut); } +/** + * drm_color_encoding - describes the coefficient for YCbCr-RGB conversion + */ enum drm_color_encoding { DRM_COLOR_YCBCR_BT601, DRM_COLOR_YCBCR_BT709, @@ -112,12 +115,25 @@ enum drm_color_range { DRM_COLOR_RANGE_MAX, }; +/** + * drm_color_space - describes the color space (primaries & white point) + */ +enum drm_color_space { + DRM_COLOR_SPACE_BT601, + DRM_COLOR_SPACE_BT709, + DRM_COLOR_SPACE_BT2020, + DRM_COLOR_SPACE_P3, + DRM_COLOR_SPACE_MAX, +}; + int drm_plane_create_color_properties(struct drm_plane *plane, u32 supported_encodings, u32 supported_ranges, + u32 supported_spaces, u32 supported_tf, enum drm_color_encoding default_encoding, enum drm_color_range default_range, + enum drm_color_space default_space, enum drm_transfer_function default_tf); /** diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h index 93ee308a46af..8c9fe6350ead 100644 --- a/include/drm/drm_plane.h +++ b/include/drm/drm_plane.h @@ -179,6 +179,13 @@ struct drm_plane_state { */ enum drm_color_range color_range; + /** + * @color_space + * + * Color space (primaries & white point) of the plane + */ + enum drm_color_space color_space; + /** * @transfer_function: * @@ -754,6 +761,15 @@ struct drm_plane { * See drm_plane_create_color_properties(). */ struct drm_property *color_range_property; + /** + * @color_space_property: + * + * Optional "COLOR_SPACE" enum property for specifying + * the color space (i.e. primaries and white point) of + * the plane. + * See drm_plane_create_color_properties(). + */ + struct drm_property *color_space_property; /** * @transfer_function_property: * From patchwork Fri Jul 30 20:41:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Harry Wentland X-Patchwork-Id: 12411933 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9521EC4338F for ; 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Signed-off-by: Harry Wentland --- drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h | 28 +++++++++++++-------- 1 file changed, 18 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h index 00fc81431b43..345b3956425a 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h @@ -55,22 +55,30 @@ struct dpp_input_csc_matrix { static const struct dpp_input_csc_matrix __maybe_unused dpp_input_csc_matrix[] = { {COLOR_SPACE_SRGB, - {0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} }, + {0x2000, 0, 0, 0, + 0, 0x2000, 0, 0, + 0, 0, 0x2000, 0} }, {COLOR_SPACE_SRGB_LIMITED, - {0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} }, + {0x2000, 0, 0, 0, + 0, 0x2000, 0, 0, + 0, 0, 0x2000, 0} }, {COLOR_SPACE_YCBCR601, - {0x2cdd, 0x2000, 0, 0xe991, 0xe926, 0x2000, 0xf4fd, 0x10ef, - 0, 0x2000, 0x38b4, 0xe3a6} }, + {0x2cdd, 0x2000, 0, 0xe991, + 0xe926, 0x2000, 0xf4fd, 0x10ef, + 0, 0x2000, 0x38b4, 0xe3a6} }, {COLOR_SPACE_YCBCR601_LIMITED, - {0x3353, 0x2568, 0, 0xe400, 0xe5dc, 0x2568, 0xf367, 0x1108, - 0, 0x2568, 0x40de, 0xdd3a} }, + {0x3353, 0x2568, 0, 0xe400, + 0xe5dc, 0x2568, 0xf367, 0x1108, + 0, 0x2568, 0x40de, 0xdd3a} }, {COLOR_SPACE_YCBCR709, - {0x3265, 0x2000, 0, 0xe6ce, 0xf105, 0x2000, 0xfa01, 0xa7d, 0, - 0x2000, 0x3b61, 0xe24f} }, + {0x3265, 0x2000, 0, 0xe6ce, + 0xf105, 0x2000, 0xfa01, 0xa7d, + 0, 0x2000, 0x3b61, 0xe24f} }, {COLOR_SPACE_YCBCR709_LIMITED, - {0x39a6, 0x2568, 0, 0xe0d6, 0xeedd, 0x2568, 0xf925, 0x9a8, 0, - 0x2568, 0x43ee, 0xdbb2} } + {0x39a6, 0x2568, 0, 0xe0d6, + 0xeedd, 0x2568, 0xf925, 0x9a8, + 0, 0x2568, 0x43ee, 0xdbb2} } }; struct dpp_grph_csc_adjustment {