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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Aug 2021 12:58:41.0127 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ed616601-0cca-4fc9-6f89-08d955b540a6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT008.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5025 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Sanjay R Mehta This patch enables support for AMD USB4 host router. Signed-off-by: Basavaraj Natikar Signed-off-by: Sanjay R Mehta --- drivers/thunderbolt/nhi.c | 4 ++++ include/linux/pci_ids.h | 2 ++ 2 files changed, 6 insertions(+) diff --git a/drivers/thunderbolt/nhi.c b/drivers/thunderbolt/nhi.c index fa44332..d7d9c4b 100644 --- a/drivers/thunderbolt/nhi.c +++ b/drivers/thunderbolt/nhi.c @@ -1338,6 +1338,10 @@ static struct pci_device_id nhi_ids[] = { { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADL_NHI1), .driver_data = (kernel_ulong_t)&icl_nhi_ops }, + /* AMD USB4 host */ + { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_USB4_HIA0) }, + { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_USB4_HIA1) }, + /* Any USB4 compliant host */ { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_USB4, ~0) }, diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h index 4bac183..6d50019 100644 --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h @@ -604,6 +604,8 @@ #define PCI_DEVICE_ID_AMD_HUDSON2_SMBUS 0x780b #define PCI_DEVICE_ID_AMD_HUDSON2_IDE 0x780c #define PCI_DEVICE_ID_AMD_KERNCZ_SMBUS 0x790b +#define PCI_DEVICE_ID_AMD_USB4_HIA0 0x162e +#define PCI_DEVICE_ID_AMD_USB4_HIA1 0x162f #define PCI_VENDOR_ID_TRIDENT 0x1023 #define PCI_DEVICE_ID_TRIDENT_4DWAVE_DX 0x2000 From patchwork Mon Aug 2 12:58:18 2021 Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Aug 2021 12:58:45.9417 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2403fd50-9f82-415e-73e7-08d955b54397 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT038.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR12MB1398 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Sanjay R Mehta when the "Disable ISR Auto-Clear" bit is set, the Tx/Rx ring interrupt status is not cleared. Hence handling it by setting the "Interrupt status clear" register to clear the corresponding Tx/Rx ring interrupt. Signed-off-by: Basavaraj Natikar Signed-off-by: Sanjay R Mehta --- drivers/thunderbolt/nhi.c | 26 +++++++++++++++++++++++++- include/linux/thunderbolt.h | 1 + 2 files changed, 26 insertions(+), 1 deletion(-) diff --git a/drivers/thunderbolt/nhi.c b/drivers/thunderbolt/nhi.c index d7d9c4b..63bbabf 100644 --- a/drivers/thunderbolt/nhi.c +++ b/drivers/thunderbolt/nhi.c @@ -74,7 +74,11 @@ static void ring_interrupt_active(struct tb_ring *ring, bool active) if (!(misc & REG_DMA_MISC_INT_AUTO_CLEAR)) { misc |= REG_DMA_MISC_INT_AUTO_CLEAR; iowrite32(misc, ring->nhi->iobase + REG_DMA_MISC); - } + misc = ioread32(ring->nhi->iobase + REG_DMA_MISC); + if (misc & REG_DMA_MISC_INT_AUTO_CLEAR) + ring->nhi->is_intr_autoclr = true; + } else + ring->nhi->is_intr_autoclr = true; ivr_base = ring->nhi->iobase + REG_INT_VEC_ALLOC_BASE; step = index / REG_INT_VEC_ALLOC_REGS * REG_INT_VEC_ALLOC_BITS; @@ -377,11 +381,31 @@ void tb_ring_poll_complete(struct tb_ring *ring) } EXPORT_SYMBOL_GPL(tb_ring_poll_complete); +static void check_and_clear_intr_status(struct tb_ring *ring, int int_pos) +{ + u32 value; + + if (!ring->nhi->is_intr_autoclr) { + value = ioread32(ring->nhi->iobase + + REG_RING_NOTIFY_BASE + + 4 * (int_pos / 32)); + iowrite32(value, ring->nhi->iobase + + (REG_RING_NOTIFY_BASE + 8) + + 4 * (int_pos / 32)); + } +} + static irqreturn_t ring_msix(int irq, void *data) { struct tb_ring *ring = data; spin_lock(&ring->nhi->lock); + + if (ring->is_tx) + check_and_clear_intr_status(ring, 0); + else + check_and_clear_intr_status(ring, ring->nhi->hop_count); + spin_lock(&ring->lock); __ring_interrupt(ring); spin_unlock(&ring->lock); diff --git a/include/linux/thunderbolt.h b/include/linux/thunderbolt.h index e7c96c3..bbe7c7e 100644 --- a/include/linux/thunderbolt.h +++ b/include/linux/thunderbolt.h @@ -478,6 +478,7 @@ struct tb_nhi { struct tb_ring **rx_rings; struct ida msix_ida; bool going_away; + bool is_intr_autoclr; struct work_struct interrupt_work; u32 hop_count; }; From patchwork Mon Aug 2 12:58:19 2021 Content-Type: text/plain; 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Mon, 2 Aug 2021 12:58:51 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; linux.intel.com; dkim=none (message not signed) header.d=none;linux.intel.com; dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT052.mail.protection.outlook.com (10.13.174.225) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4373.18 via Frontend Transport; Mon, 2 Aug 2021 12:58:50 +0000 Received: from sanjuamdntb2.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2242.12; Mon, 2 Aug 2021 07:58:47 -0500 From: Sanjay R Mehta To: , , , , CC: , , , Sanjay R Mehta Subject: [PATCH 3/4] thunderbolt: Fix adapter init handling during switch add Date: Mon, 2 Aug 2021 07:58:19 -0500 Message-ID: <1627909100-83338-4-git-send-email-Sanju.Mehta@amd.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1627909100-83338-1-git-send-email-Sanju.Mehta@amd.com> References: <1627909100-83338-1-git-send-email-Sanju.Mehta@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: c6174010-dde4-452d-b799-08d955b54691 X-MS-TrafficTypeDiagnostic: CY4PR12MB1384: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5797; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Aug 2021 12:58:50.9463 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c6174010-dde4-452d-b799-08d955b54691 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT052.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR12MB1384 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Sanjay R Mehta Adapter0 (Port0) is the control adapter on the AMD USB4 host router. As per USB4 spec in "Section 1.8", Control Adapters do not have an Adapter Configuration Space". The read requests on Adapter0 time's out and driver initialization fails. Hence Disabling the Adapter in case of read-request timeout and continuing the driver init. Signed-off-by: Basavaraj Natikar Signed-off-by: Sanjay R Mehta --- drivers/thunderbolt/switch.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/thunderbolt/switch.c b/drivers/thunderbolt/switch.c index 83b1ef3..effbfe4 100644 --- a/drivers/thunderbolt/switch.c +++ b/drivers/thunderbolt/switch.c @@ -2747,8 +2747,9 @@ int tb_switch_add(struct tb_switch *sw) } ret = tb_init_port(&sw->ports[i]); if (ret) { + sw->ports[i].disabled = true; dev_err(&sw->dev, "failed to initialize port %d\n", i); - return ret; + continue; } } From patchwork Mon Aug 2 12:58:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Mehta, Sanju" X-Patchwork-Id: 12413911 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 89D82C4338F for ; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Aug 2021 12:58:56.2568 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fc6ff003-13ac-44cc-1abc-08d955b549bd X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT044.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR12MB3233 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Sanjay R Mehta In tb_switch_default_link_ports(), while linking of ports, only odd-numbered ports (1,3,5..) are considered and even-numbered ports are not considered. AMD host router has lane adapters at 2 & 3 and link ports at adapter-2 is not considered due to which lane bonding gets disabled. Hence added a fix such that all ports are considered during linking of ports. Fixes: 0d46c08d1ed4 ("thunderbolt: Add default linking between lane adapters if not provided by DROM") Signed-off-by: Basavaraj Natikar Signed-off-by: Sanjay R Mehta --- drivers/thunderbolt/switch.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/thunderbolt/switch.c b/drivers/thunderbolt/switch.c index effbfe4..8b2fe67 100644 --- a/drivers/thunderbolt/switch.c +++ b/drivers/thunderbolt/switch.c @@ -2456,7 +2456,7 @@ static void tb_switch_default_link_ports(struct tb_switch *sw) { int i; - for (i = 1; i <= sw->config.max_port_number; i += 2) { + for (i = 1; i <= sw->config.max_port_number; i++) { struct tb_port *port = &sw->ports[i]; struct tb_port *subordinate;