From patchwork Tue Aug 3 04:38:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 12415259 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3EAC5C4320A for ; Tue, 3 Aug 2021 04:39:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 268936103C for ; Tue, 3 Aug 2021 04:39:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233897AbhHCEjO (ORCPT ); Tue, 3 Aug 2021 00:39:14 -0400 Received: from mail.kernel.org ([198.145.29.99]:44794 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233830AbhHCEjO (ORCPT ); Tue, 3 Aug 2021 00:39:14 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id AE1166023B; Tue, 3 Aug 2021 04:39:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1627965543; bh=JQBY01HlySg61KGcooyIwhgyIlhQj6EZr5kggVNvmjA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=sMOQUsf2A68wiHayEJXRTsGdgkPIWOdCMfdB9ThgIojQq6rfA4hErsQ4R76vhrNWi iJ66XoXg3aTw1zmIqsjhvrCXVW9qEWpBCKfOSEoV3mLybt+oyMXg1/kBshQUAfKS/J 7vbbAc3+XoHktpDWyTxijqyHrbOaNkgD6Jz7vZ+EiHb0BX/s8wIT276aNsXIphpdB5 pqmuI8D54REdsziOnavcW9jTtPYK91RXC9uDCH1ZlJBVA9vS92/SICiG7wJMR30g54 zHi1Io0ywIkSUFwNUD3SCdvgbry9Tu9MD70ZJz1szmJkp/M5GJT9NjlgFVlRlXPDOO KNvwWZJyUnfWg== Received: by mail.kernel.org with local (Exim 4.94.2) (envelope-from ) id 1mAmCj-00D8KD-FZ; Tue, 03 Aug 2021 06:39:01 +0200 From: Mauro Carvalho Chehab To: Rob Herring Cc: linuxarm@huawei.com, mauro.chehab@huawei.com, Mauro Carvalho Chehab , Bjorn Helgaas , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Rob Herring Subject: [PATCH v3 1/4] dt-bindings: PCI: kirin: Fix compatible string Date: Tue, 3 Aug 2021 06:38:55 +0200 Message-Id: <3e3e29a88f8e71eb228edf33d70cbe70db431408.1627965261.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The pcie-kirin driver doesn't declare a hisilicon,kirin-pcie. Also, remove the useless comment after the description, as other compat will be supported by the same driver in the future. Acked-by: Rob Herring Signed-off-by: Mauro Carvalho Chehab --- Documentation/devicetree/bindings/pci/kirin-pcie.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/kirin-pcie.txt b/Documentation/devicetree/bindings/pci/kirin-pcie.txt index 7db30534498f..7adab8999a6a 100644 --- a/Documentation/devicetree/bindings/pci/kirin-pcie.txt +++ b/Documentation/devicetree/bindings/pci/kirin-pcie.txt @@ -9,7 +9,7 @@ Additional properties are described here: Required properties - compatible: - "hisilicon,kirin960-pcie" for PCIe of Kirin960 SoC + "hisilicon,kirin960-pcie" - reg: Should contain rc_dbi, apb, phy, config registers location and length. - reg-names: Must include the following entries: "dbi": controller configuration registers; @@ -23,7 +23,7 @@ Optional properties: Example based on kirin960: pcie@f4000000 { - compatible = "hisilicon,kirin-pcie"; + compatible = "hisilicon,kirin960-pcie"; reg = <0x0 0xf4000000 0x0 0x1000>, <0x0 0xff3fe000 0x0 0x1000>, <0x0 0xf3f20000 0x0 0x40000>, <0x0 0xF4000000 0 0x2000>; reg-names = "dbi","apb","phy", "config"; From patchwork Tue Aug 3 04:38:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 12415265 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 51A68C4320A for ; Tue, 3 Aug 2021 04:39:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 35250610CC for ; Tue, 3 Aug 2021 04:39:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233887AbhHCEjP (ORCPT ); Tue, 3 Aug 2021 00:39:15 -0400 Received: from mail.kernel.org ([198.145.29.99]:44802 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233878AbhHCEjO (ORCPT ); Tue, 3 Aug 2021 00:39:14 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id B2C0860F9C; Tue, 3 Aug 2021 04:39:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1627965543; bh=z0aya0UFmOacKi0Vl++gYqtojCgt6X7zC5DUdaHjVsE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZjEKd+3QNsqnXTe8oJpF+JKodXWdp8wkuC0pjj6iepntRC39Mm+oiAycdchcDkkn+ NP5L4VzRFDHwm5zgMb8lp268cWmpzGJ5uz4S5gvPnVJ1H/knZ1RebWDQ565I454Sif 6IHS9K2nQQiQrtqpZc6XLFzStET63fFto+HYXR35ZkcjTmcj//uVwoOrLiBTu1YNRs 0O1Hq0ja9OdSXHBC9jCtpBtOiTTdsSmuybwFF+2xpBmQCJx135HhFW6xICEWz54v3V nnJXOWRKdaP7l9PNlHfEbLTp77pD5rojeoSvdFZAi4FMJnZDTsce0QBZ8z6RQ6uk6m 8MF/TLt7/NnOA== Received: by mail.kernel.org with local (Exim 4.94.2) (envelope-from ) id 1mAmCj-00D8KH-HA; Tue, 03 Aug 2021 06:39:01 +0200 From: Mauro Carvalho Chehab To: Rob Herring Cc: linuxarm@huawei.com, mauro.chehab@huawei.com, Mauro Carvalho Chehab , Binghui Wang , Bjorn Helgaas , Gustavo Pimentel , Jingoo Han , Xiaowei Song , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v3 2/4] dt-bindings: PCI: kirin: Convert kirin-pcie.txt to yaml Date: Tue, 3 Aug 2021 06:38:56 +0200 Message-Id: <4d6e172cee9d477547d5ea26d0e5945fcbce15a1.1627965261.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Convert the file into a JSON description at the yaml format. Signed-off-by: Mauro Carvalho Chehab --- .../bindings/pci/hisilicon,kirin-pcie.yaml | 86 +++++++++++++++++++ .../devicetree/bindings/pci/kirin-pcie.txt | 50 ----------- .../devicetree/bindings/pci/snps,dw-pcie.yaml | 2 +- MAINTAINERS | 2 +- 4 files changed, 88 insertions(+), 52 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml delete mode 100644 Documentation/devicetree/bindings/pci/kirin-pcie.txt diff --git a/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml b/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml new file mode 100644 index 000000000000..90cab09e8d4b --- /dev/null +++ b/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/hisilicon,kirin-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: HiSilicon Kirin SoCs PCIe host DT description + +maintainers: + - Xiaowei Song + - Binghui Wang + +description: | + Kirin PCIe host controller is based on the Synopsys DesignWare PCI core. + It shares common functions with the PCIe DesignWare core driver and + inherits common properties defined in + Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml. + +allOf: + - $ref: /schemas/pci/snps,dw-pcie.yaml# + +properties: + compatible: + contains: + enum: + - hisilicon,kirin960-pcie + + reg: + description: | + Should contain dbi, apb, config registers location and length. + For HiKey960, it should also contain phy. + minItems: 3 + maxItems: 4 + + reg-names: + minItems: 3 + maxItems: 4 + +required: + - compatible + - reg + - reg-names + +unevaluatedProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie@f4000000 { + compatible = "hisilicon,kirin960-pcie"; + reg = <0x0 0xf4000000 0x0 0x1000>, + <0x0 0xff3fe000 0x0 0x1000>, + <0x0 0xf3f20000 0x0 0x40000>, + <0x0 0xf5000000 0x0 0x2000>; + reg-names = "dbi", "apb", "phy", "config"; + bus-range = <0x0 0x1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x02000000 0x0 0x00000000 + 0x0 0xf6000000 + 0x0 0x02000000>; + num-lanes = <1>; + #interrupt-cells = <1>; + interrupts = <0 283 4>; + interrupt-names = "msi"; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = <0x0 0 0 1 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 2 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 3 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, + <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, + <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, + <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, + <&crg_ctrl HI3660_ACLK_GATE_PCIE>; + clock-names = "pcie_phy_ref", "pcie_aux", "pcie_apb_phy", + "pcie_apb_sys", "pcie_aclk"; + }; + }; diff --git a/Documentation/devicetree/bindings/pci/kirin-pcie.txt b/Documentation/devicetree/bindings/pci/kirin-pcie.txt deleted file mode 100644 index 7adab8999a6a..000000000000 --- a/Documentation/devicetree/bindings/pci/kirin-pcie.txt +++ /dev/null @@ -1,50 +0,0 @@ -HiSilicon Kirin SoCs PCIe host DT description - -Kirin PCIe host controller is based on the Synopsys DesignWare PCI core. -It shares common functions with the PCIe DesignWare core driver and -inherits common properties defined in -Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml. - -Additional properties are described here: - -Required properties -- compatible: - "hisilicon,kirin960-pcie" -- reg: Should contain rc_dbi, apb, phy, config registers location and length. -- reg-names: Must include the following entries: - "dbi": controller configuration registers; - "apb": apb Ctrl register defined by Kirin; - "phy": apb PHY register defined by Kirin; - "config": PCIe configuration space registers. -- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal. - -Optional properties: - -Example based on kirin960: - - pcie@f4000000 { - compatible = "hisilicon,kirin960-pcie"; - reg = <0x0 0xf4000000 0x0 0x1000>, <0x0 0xff3fe000 0x0 0x1000>, - <0x0 0xf3f20000 0x0 0x40000>, <0x0 0xF4000000 0 0x2000>; - reg-names = "dbi","apb","phy", "config"; - bus-range = <0x0 0x1>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x02000000 0x0 0x00000000 0x0 0xf5000000 0x0 0x2000000>; - num-lanes = <1>; - #interrupt-cells = <1>; - interrupt-map-mask = <0xf800 0 0 7>; - interrupt-map = <0x0 0 0 1 &gic 0 0 0 282 4>, - <0x0 0 0 2 &gic 0 0 0 283 4>, - <0x0 0 0 3 &gic 0 0 0 284 4>, - <0x0 0 0 4 &gic 0 0 0 285 4>; - clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, - <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, - <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, - <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, - <&crg_ctrl HI3660_ACLK_GATE_PCIE>; - clock-names = "pcie_phy_ref", "pcie_aux", - "pcie_apb_phy", "pcie_apb_sys", "pcie_aclk"; - reset-gpios = <&gpio11 1 0 >; - }; diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml index a8c1db879fb9..6c7501b8df01 100644 --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml @@ -34,7 +34,7 @@ properties: minItems: 2 maxItems: 5 items: - enum: [dbi, dbi2, config, atu, app, elbi, mgmt, ctrl, parf, cfg, link] + enum: [dbi, dbi2, config, atu, apb, app, elbi, mgmt, ctrl, parf, cfg, link, phy] num-lanes: description: | diff --git a/MAINTAINERS b/MAINTAINERS index b54bd9dd07ec..d5f53b2d3f9c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14420,7 +14420,7 @@ M: Xiaowei Song M: Binghui Wang L: linux-pci@vger.kernel.org S: Maintained -F: Documentation/devicetree/bindings/pci/kirin-pcie.txt +F: Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml F: drivers/pci/controller/dwc/pcie-kirin.c PCIE DRIVER FOR HISILICON STB From patchwork Tue Aug 3 04:38:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 12415261 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B7C36C4338F for ; Tue, 3 Aug 2021 04:39:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9B8D961029 for ; Tue, 3 Aug 2021 04:39:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233830AbhHCEjQ (ORCPT ); Tue, 3 Aug 2021 00:39:16 -0400 Received: from mail.kernel.org ([198.145.29.99]:44812 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233888AbhHCEjO (ORCPT ); Tue, 3 Aug 2021 00:39:14 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id B81316104F; Tue, 3 Aug 2021 04:39:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1627965543; bh=LrrFZSakdUxKwsRUW/i3f6iMngeHtZ/JieQmAqMg4aI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ME1cin80LMWK3bk/ft2AS9dbDKCgdkF9Uz7YzLlejaJ9zBE5m/yZKSgXtwYBaFFbU jt/VCePPelSXrwc+HavXw59ttZRUySQWXvSIZQAY4qe0rVoy4J9/+qK3IsaiF1Aqxn dUfeQbVJMCsyHMvcLPLI/KUwBqEbXgaAELpGuieJLqRYSxCkH47NMTuW46SPWDRWy2 rEjEmDlsequvUsOdVYl+d5Ot8tZ9bSEOGmAfrihviHTPjHNBPjblDiKZBvKoE79D+c 2rRfY0Y4MIPivb8J8ktuE5FVSd6BZVRrFvSa0wmnbxRBj9uHrxqIEWgLkaRqhNCCh3 cV+ZlG6A1S5Hg== Received: by mail.kernel.org with local (Exim 4.94.2) (envelope-from ) id 1mAmCj-00D8KL-If; Tue, 03 Aug 2021 06:39:01 +0200 From: Mauro Carvalho Chehab To: Rob Herring Cc: linuxarm@huawei.com, mauro.chehab@huawei.com, Mauro Carvalho Chehab , Binghui Wang , Bjorn Helgaas , Xiaowei Song , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v3 3/4] dt-bindings: PCI: kirin: Add support for Kirin970 Date: Tue, 3 Aug 2021 06:38:57 +0200 Message-Id: X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add a new compatible, plus the new bindings needed by HiKey970 board. Signed-off-by: Mauro Carvalho Chehab --- .../bindings/pci/hisilicon,kirin-pcie.yaml | 76 ++++++++++++++++++- 1 file changed, 75 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml b/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml index 90cab09e8d4b..c0551d2e606d 100644 --- a/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml @@ -24,11 +24,12 @@ properties: contains: enum: - hisilicon,kirin960-pcie + - hisilicon,kirin970-pcie reg: description: | Should contain dbi, apb, config registers location and length. - For HiKey960, it should also contain phy. + For hisilicon,kirin960-pcie, it should also contain phy. minItems: 3 maxItems: 4 @@ -36,6 +37,11 @@ properties: minItems: 3 maxItems: 4 + hisilicon,clken-gpios: + description: | + Clock input enablement GPIOs from PCI devices like Ethernet, M.2 and + mini-PCIe slots. + required: - compatible - reg @@ -47,6 +53,7 @@ examples: - | #include #include + #include soc { #address-cells = <2>; @@ -83,4 +90,71 @@ examples: clock-names = "pcie_phy_ref", "pcie_aux", "pcie_apb_phy", "pcie_apb_sys", "pcie_aclk"; }; + + pcie@f5000000 { + compatible = "hisilicon,kirin970-pcie"; + reg = <0x0 0xf4000000 0x0 0x1000000>, + <0x0 0xfc180000 0x0 0x1000>, + <0x0 0xf5000000 0x0 0x2000>; + reg-names = "dbi", "apb", "config"; + bus-range = <0x0 0x1>; + msi-parent = <&its_pcie>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + phys = <&pcie_phy>; + ranges = <0x02000000 0x0 0x00000000 + 0x0 0xf6000000 + 0x0 0x02000000>; + num-lanes = <1>; + #interrupt-cells = <1>; + interrupts = ; + interrupt-names = "msi"; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0x0 0 0 1 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 2 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 3 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; + reset-gpios = <&gpio7 0 0>; + hisilicon,clken-gpios = <&gpio27 3 0>, <&gpio17 0 0>, <&gpio20 6 0>; + + pcie@0 { // Lane 0: PCIe switch: Bus 1, Device 0 + reg = <0 0 0 0 0>; + compatible = "pciclass,0604"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + ranges; + pcie@1,0 { // Lane 4: M.2 + reg = <0x800 0 0 0 0>; + compatible = "pciclass,0604"; + device_type = "pci"; + reset-gpios = <&gpio3 1 0>; + clkreq-gpios = <&gpio27 3 0 >; + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + pcie@5,0 { // Lane 5: Mini PCIe + reg = <0x2800 0 0 0 0>; + compatible = "pciclass,0604"; + device_type = "pci"; + reset-gpios = <&gpio27 4 0 >; + clkreq-gpios = <&gpio17 0 0 >; + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + pcie@7,0 { // Lane 6: Ethernet + reg = <0x3800 0 0 0 0>; + compatible = "pciclass,0604"; + device_type = "pci"; + reset-gpios = <&gpio25 2 0 >; + clkreq-gpios = <&gpio20 6 0 >; + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + }; + }; };