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Tue, 3 Aug 2021 12:35:16 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; linux.intel.com; dkim=none (message not signed) header.d=none;linux.intel.com; dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT012.mail.protection.outlook.com (10.13.177.55) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4373.18 via Frontend Transport; Tue, 3 Aug 2021 12:35:16 +0000 Received: from sanjuamdntb2.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2242.12; Tue, 3 Aug 2021 07:35:13 -0500 From: Sanjay R Mehta To: , , , CC: , , Sanjay R Mehta Subject: [PATCH v2 1/4] thunderbolt: Intel controller uses BIT(2) for intr auto Date: Tue, 3 Aug 2021 07:34:53 -0500 Message-ID: <1627994096-99972-2-git-send-email-Sanju.Mehta@amd.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1627994096-99972-1-git-send-email-Sanju.Mehta@amd.com> References: <1627994096-99972-1-git-send-email-Sanju.Mehta@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 4c67d835-b40c-4f94-4891-08d9567b259b X-MS-TrafficTypeDiagnostic: BN6PR12MB1490: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7219; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Aug 2021 12:35:16.1105 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4c67d835-b40c-4f94-4891-08d9567b259b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT012.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR12MB1490 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org From: Sanjay R Mehta REG_DMA_MISC_INT_AUTO_CLEAR which is bit 2 in that register is actually Intel specific. As per the USB4 spec bit 17 is used for interrupt auto clear and by default its enabled. Hence limit usage of REG_DMA_MISC_INT_AUTO_CLEAR for Intel controllers and moved this to quirk. Fixes: 046bee1f9ab8 ("thunderbolt: Add MSI-X support") Suggested-by: Mika Westerberg Signed-off-by: Basavaraj Natikar Signed-off-by: Sanjay R Mehta --- drivers/thunderbolt/nhi.c | 8 ++------ drivers/thunderbolt/quirks.c | 14 ++++++++++++++ drivers/thunderbolt/tb.h | 1 + 3 files changed, 17 insertions(+), 6 deletions(-) diff --git a/drivers/thunderbolt/nhi.c b/drivers/thunderbolt/nhi.c index fa44332..ef01aa6 100644 --- a/drivers/thunderbolt/nhi.c +++ b/drivers/thunderbolt/nhi.c @@ -57,8 +57,8 @@ static void ring_interrupt_active(struct tb_ring *ring, bool active) u32 old, new; if (ring->irq > 0) { - u32 step, shift, ivr, misc; void __iomem *ivr_base; + u32 step, shift, ivr; int index; if (ring->is_tx) @@ -70,11 +70,7 @@ static void ring_interrupt_active(struct tb_ring *ring, bool active) * Ask the hardware to clear interrupt status bits automatically * since we already know which interrupt was triggered. */ - misc = ioread32(ring->nhi->iobase + REG_DMA_MISC); - if (!(misc & REG_DMA_MISC_INT_AUTO_CLEAR)) { - misc |= REG_DMA_MISC_INT_AUTO_CLEAR; - iowrite32(misc, ring->nhi->iobase + REG_DMA_MISC); - } + quirk_enable_intr_auto_clr(ring); ivr_base = ring->nhi->iobase + REG_INT_VEC_ALLOC_BASE; step = index / REG_INT_VEC_ALLOC_REGS * REG_INT_VEC_ALLOC_BITS; diff --git a/drivers/thunderbolt/quirks.c b/drivers/thunderbolt/quirks.c index b5f2ec7..af6dab9 100644 --- a/drivers/thunderbolt/quirks.c +++ b/drivers/thunderbolt/quirks.c @@ -6,6 +6,7 @@ */ #include "tb.h" +#include "nhi_regs.h" static void quirk_force_power_link(struct tb_switch *sw) { @@ -64,3 +65,16 @@ void tb_check_quirks(struct tb_switch *sw) q->hook(sw); } } + +void quirk_enable_intr_auto_clr(struct tb_ring *ring) +{ + u32 misc; + + if (ring->nhi->pdev->vendor == PCI_VENDOR_ID_INTEL) { + misc = ioread32(ring->nhi->iobase + REG_DMA_MISC); + if (!(misc & REG_DMA_MISC_INT_AUTO_CLEAR)) { + misc |= REG_DMA_MISC_INT_AUTO_CLEAR; + iowrite32(misc, ring->nhi->iobase + REG_DMA_MISC); + } + } +} diff --git a/drivers/thunderbolt/tb.h b/drivers/thunderbolt/tb.h index 725104c..0b8f9d3 100644 --- a/drivers/thunderbolt/tb.h +++ b/drivers/thunderbolt/tb.h @@ -1122,6 +1122,7 @@ int usb4_port_device_resume(struct usb4_port *usb4); #define QUIRK_FORCE_POWER_LINK_CONTROLLER BIT(0) void tb_check_quirks(struct tb_switch *sw); +void quirk_enable_intr_auto_clr(struct tb_ring *ring); #ifdef CONFIG_ACPI void tb_acpi_add_links(struct tb_nhi *nhi); From patchwork Tue Aug 3 12:34:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Mehta, Sanju" X-Patchwork-Id: 12416169 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C7E9FC4338F for ; Tue, 3 Aug 2021 12:35:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B28EE60F93 for ; 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Tue, 3 Aug 2021 12:35:20 +0000 Received: from sanjuamdntb2.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2242.12; Tue, 3 Aug 2021 07:35:17 -0500 From: Sanjay R Mehta To: , , , CC: , , Sanjay R Mehta Subject: [PATCH v2 2/4] thunderbolt: Handle ring interrupt by reading intr status Date: Tue, 3 Aug 2021 07:34:54 -0500 Message-ID: <1627994096-99972-3-git-send-email-Sanju.Mehta@amd.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1627994096-99972-1-git-send-email-Sanju.Mehta@amd.com> References: <1627994096-99972-1-git-send-email-Sanju.Mehta@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a7915cea-10f2-41e5-165e-08d9567b2813 X-MS-TrafficTypeDiagnostic: DM6PR12MB2891: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5516; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Aug 2021 12:35:20.2501 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a7915cea-10f2-41e5-165e-08d9567b2813 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT008.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB2891 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org From: Sanjay R Mehta As per USB4 spec by default "Disable ISR Auto-Clear" bit is set to 0, and the Tx/Rx ring interrupt status is needs to be cleared. Hence handling it by reading the "Interrupt status" register in the ISR. Signed-off-by: Basavaraj Natikar Signed-off-by: Sanjay R Mehta --- drivers/thunderbolt/nhi.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/thunderbolt/nhi.c b/drivers/thunderbolt/nhi.c index ef01aa6..7ad2202 100644 --- a/drivers/thunderbolt/nhi.c +++ b/drivers/thunderbolt/nhi.c @@ -373,11 +373,25 @@ void tb_ring_poll_complete(struct tb_ring *ring) } EXPORT_SYMBOL_GPL(tb_ring_poll_complete); +static void check_and_clear_intr_status(struct tb_ring *ring) +{ + if (!(ring->nhi->pdev->vendor == PCI_VENDOR_ID_INTEL)) { + if (ring->is_tx) + ioread32(ring->nhi->iobase + + REG_RING_NOTIFY_BASE); + else + ioread32(ring->nhi->iobase + + REG_RING_NOTIFY_BASE + + 4 * (ring->nhi->hop_count / 32)); + } +} + static irqreturn_t ring_msix(int irq, void *data) { struct tb_ring *ring = data; spin_lock(&ring->nhi->lock); + check_and_clear_intr_status(ring); spin_lock(&ring->lock); __ring_interrupt(ring); spin_unlock(&ring->lock); From patchwork Tue Aug 3 12:34:55 2021 Content-Type: text/plain; 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Tue, 3 Aug 2021 12:35:24 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; linux.intel.com; dkim=none (message not signed) header.d=none;linux.intel.com; dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT043.mail.protection.outlook.com (10.13.177.218) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4373.18 via Frontend Transport; Tue, 3 Aug 2021 12:35:23 +0000 Received: from sanjuamdntb2.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2242.12; Tue, 3 Aug 2021 07:35:21 -0500 From: Sanjay R Mehta To: , , , CC: , , Sanjay R Mehta Subject: [PATCH v2 3/4] thunderbolt: Skip port init for control adapter(0) Date: Tue, 3 Aug 2021 07:34:55 -0500 Message-ID: <1627994096-99972-4-git-send-email-Sanju.Mehta@amd.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1627994096-99972-1-git-send-email-Sanju.Mehta@amd.com> References: <1627994096-99972-1-git-send-email-Sanju.Mehta@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 04ad7e8b-004f-47d8-f1a3-08d9567b2a4a X-MS-TrafficTypeDiagnostic: BN6PR12MB1442: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2887; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Aug 2021 12:35:23.9716 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 04ad7e8b-004f-47d8-f1a3-08d9567b2a4a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT043.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR12MB1442 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org From: Sanjay R Mehta Adapter (0) is control adapter and as per USB4 spec in "Section 1.8", Control Adapters do not have an Adapter Configuration Space". Hence skip port initialization for adapter (0). Fixes: e6b245ccd524 ("thunderbolt: Add support for host and device NVM firmware upgrade") Signed-off-by: Basavaraj Natikar Signed-off-by: Sanjay R Mehta --- drivers/thunderbolt/switch.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/thunderbolt/switch.c b/drivers/thunderbolt/switch.c index 83b1ef3..6447876 100644 --- a/drivers/thunderbolt/switch.c +++ b/drivers/thunderbolt/switch.c @@ -2740,7 +2740,7 @@ int tb_switch_add(struct tb_switch *sw) return ret; } - for (i = 0; i <= sw->config.max_port_number; i++) { + for (i = 1; i <= sw->config.max_port_number; i++) { if (sw->ports[i].disabled) { tb_port_dbg(&sw->ports[i], "disabled by eeprom\n"); continue; From patchwork Tue Aug 3 12:34:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Mehta, Sanju" X-Patchwork-Id: 12416173 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 51F65C4338F for ; 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client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT038.mail.protection.outlook.com (10.13.176.246) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4373.18 via Frontend Transport; Tue, 3 Aug 2021 12:35:28 +0000 Received: from sanjuamdntb2.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2242.12; Tue, 3 Aug 2021 07:35:25 -0500 From: Sanjay R Mehta To: , , , CC: , , Sanjay R Mehta Subject: [PATCH v2 4/4] thunderbolt: Fix port linking by checking all adapters Date: Tue, 3 Aug 2021 07:34:56 -0500 Message-ID: <1627994096-99972-5-git-send-email-Sanju.Mehta@amd.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1627994096-99972-1-git-send-email-Sanju.Mehta@amd.com> References: <1627994096-99972-1-git-send-email-Sanju.Mehta@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 01131942-bd34-4d42-caef-08d9567b2cfc X-MS-TrafficTypeDiagnostic: DM6PR12MB4545: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2958; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Aug 2021 12:35:28.4926 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 01131942-bd34-4d42-caef-08d9567b2cfc X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT038.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4545 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org From: Sanjay R Mehta In tb_switch_default_link_ports(), while linking of ports, only odd-numbered ports (1,3,5..) are considered and even-numbered ports are not considered. AMD host router has lane adapters at 2 & 3 and link ports at adapter-2 is not considered due to which lane bonding gets disabled. Hence added a fix such that all ports are considered during linking of ports. Fixes: 0d46c08d1ed4 ("thunderbolt: Add default linking between lane adapters if not provided by DROM") Signed-off-by: Basavaraj Natikar Signed-off-by: Sanjay R Mehta --- drivers/thunderbolt/switch.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/thunderbolt/switch.c b/drivers/thunderbolt/switch.c index 6447876..5c3d4bd 100644 --- a/drivers/thunderbolt/switch.c +++ b/drivers/thunderbolt/switch.c @@ -2456,7 +2456,7 @@ static void tb_switch_default_link_ports(struct tb_switch *sw) { int i; - for (i = 1; i <= sw->config.max_port_number; i += 2) { + for (i = 1; i <= sw->config.max_port_number; i++) { struct tb_port *port = &sw->ports[i]; struct tb_port *subordinate;