From patchwork Wed Aug 4 00:30:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "David E. Box" X-Patchwork-Id: 12417685 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 99C19C4338F for ; Wed, 4 Aug 2021 00:32:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 723EA60F58 for ; Wed, 4 Aug 2021 00:32:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234822AbhHDAc7 (ORCPT ); Tue, 3 Aug 2021 20:32:59 -0400 Received: from mga09.intel.com ([134.134.136.24]:55954 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234792AbhHDAc7 (ORCPT ); Tue, 3 Aug 2021 20:32:59 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10065"; a="213799588" X-IronPort-AV: E=Sophos;i="5.84,293,1620716400"; d="scan'208";a="213799588" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Aug 2021 17:32:47 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.84,293,1620716400"; d="scan'208";a="667604504" Received: from linux.intel.com ([10.54.29.200]) by fmsmga006.fm.intel.com with ESMTP; 03 Aug 2021 17:32:46 -0700 Received: from debox1-desk2.jf.intel.com (debox1-desk2.jf.intel.com [10.54.75.16]) by linux.intel.com (Postfix) with ESMTP id 93F7C58093B; Tue, 3 Aug 2021 17:32:46 -0700 (PDT) From: "David E. Box" To: irenic.rajneesh@gmail.com, novikov@ispras.ru, gayatri.kammela@intel.com, hdegoede@redhat.com, mgross@linux.intel.com, andy.shevchenko@gmail.com Cc: "David E. Box" , platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH] platform/x86: intel_pmc_core: Prevent possibile overflow Date: Tue, 3 Aug 2021 17:30:39 -0700 Message-Id: <20210804003039.359138-1-david.e.box@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: platform-driver-x86@vger.kernel.org Low Power Mode (LPM) priority is encoded in 4 bits. Yet, this value is used as an index to an array whose element size was less than 16, leading to the possibility of overflow should we read a larger than expected priority. Set the array size to 16 to prevent this. Reported-by: Evgeny Novikov Signed-off-by: David E. Box --- drivers/platform/x86/intel_pmc_core.c | 2 +- drivers/platform/x86/intel_pmc_core.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c index b0e486a6bdfb..2a761fe98277 100644 --- a/drivers/platform/x86/intel_pmc_core.c +++ b/drivers/platform/x86/intel_pmc_core.c @@ -1451,7 +1451,7 @@ DEFINE_SHOW_ATTRIBUTE(pmc_core_pkgc); static void pmc_core_get_low_power_modes(struct pmc_dev *pmcdev) { - u8 lpm_priority[LPM_MAX_NUM_MODES]; + u8 lpm_priority[LPM_MAX_PRI]; u32 lpm_en; int mode, i, p; diff --git a/drivers/platform/x86/intel_pmc_core.h b/drivers/platform/x86/intel_pmc_core.h index e8dae9c6c45f..b98c2b44c938 100644 --- a/drivers/platform/x86/intel_pmc_core.h +++ b/drivers/platform/x86/intel_pmc_core.h @@ -190,6 +190,7 @@ enum ppfear_regs { #define LPM_MAX_NUM_MODES 8 #define GET_X2_COUNTER(v) ((v) >> 1) #define LPM_STS_LATCH_MODE BIT(31) +#define LPM_MAX_PRI 16 /* size of 4 bits */ #define TGL_PMC_SLP_S0_RES_COUNTER_STEP 0x7A #define TGL_PMC_LTR_THC0 0x1C04