From patchwork Thu Aug 5 02:53:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LIU Zhiwei X-Patchwork-Id: 12420181 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F0E8EC432BE for ; Thu, 5 Aug 2021 02:56:45 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 920B061037 for ; Thu, 5 Aug 2021 02:56:45 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 920B061037 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=c-sky.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:60840 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mBTYq-0006bF-On for qemu-devel@archiver.kernel.org; Wed, 04 Aug 2021 22:56:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47376) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mBTXn-0004X6-Rq; Wed, 04 Aug 2021 22:55:39 -0400 Received: from out28-122.mail.aliyun.com ([115.124.28.122]:38930) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mBTXl-0005Uk-VV; Wed, 04 Aug 2021 22:55:39 -0400 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07566033|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.0121746-6.56494e-05-0.98776; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047208; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=7; RT=7; SR=0; TI=SMTPD_---.KvYquy-_1628132130; Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.KvYquy-_1628132130) by smtp.aliyun-inc.com(10.147.44.118); Thu, 05 Aug 2021 10:55:30 +0800 From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC PATCH 01/13] target/riscv: Add UXL to tb flags Date: Thu, 5 Aug 2021 10:53:00 +0800 Message-Id: <20210805025312.15720-2-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210805025312.15720-1-zhiwei_liu@c-sky.com> References: <20210805025312.15720-1-zhiwei_liu@c-sky.com> Received-SPF: none client-ip=115.124.28.122; envelope-from=zhiwei_liu@c-sky.com; helo=out28-122.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, richard.henderson@linaro.org, bin.meng@windriver.com, Alistair.Francis@wdc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" For 32-bit applications run on 64-bit cpu, it may share some code with other 64-bit applictions. Thus we should distinguish the translated cache of the share code with a tb flag. Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 15 +++++++++++++++ target/riscv/translate.c | 3 +++ 2 files changed, 18 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index bf1c899c00..2b3ba21a78 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -394,9 +394,20 @@ FIELD(TB_FLAGS, SEW, 5, 3) FIELD(TB_FLAGS, VILL, 8, 1) /* Is a Hypervisor instruction load/store allowed? */ FIELD(TB_FLAGS, HLSX, 9, 1) +FIELD(TB_FLAGS, UXL, 10, 2) bool riscv_cpu_is_32bit(CPURISCVState *env); +static inline bool riscv_cpu_is_uxl32(CPURISCVState *env) +{ +#ifndef CONFIG_USER_ONLY + return (get_field(env->mstatus, MSTATUS64_UXL) == 1) && + !riscv_cpu_is_32bit(env) && + (env->priv == PRV_U); +#endif + return false; +} + /* * A simplification for VLMAX * = (1 << LMUL) * VLEN / (8 * (1 << SEW)) @@ -451,6 +462,10 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1); } } + if (riscv_cpu_is_uxl32(env)) { + flags = FIELD_DP32(flags, TB_FLAGS, UXL, + get_field(env->mstatus, MSTATUS64_UXL)); + } #endif *pflags = flags; diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 076f28b9c1..ac4a545da8 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -67,6 +67,8 @@ typedef struct DisasContext { CPUState *cs; TCGv zero; TCGv sink; + /* UXLEN is 32 bit for 64-bit CPU */ + bool uxl32; } DisasContext; static inline bool has_ext(DisasContext *ctx, uint32_t ext) @@ -912,6 +914,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->mlen = 1 << (ctx->sew + 3 - ctx->lmul); ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); ctx->cs = cs; + ctx->uxl32 = FIELD_EX32(tb_flags, TB_FLAGS, UXL) == 1; } static void riscv_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu) From patchwork Thu Aug 5 02:53:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LIU Zhiwei X-Patchwork-Id: 12420183 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.9 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, UNWANTED_LANGUAGE_BODY,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EE320C432BE for ; Thu, 5 Aug 2021 02:57:20 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6EAE961037 for ; Thu, 5 Aug 2021 02:57:20 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 6EAE961037 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=c-sky.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:34716 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mBTZP-0007zY-KW for qemu-devel@archiver.kernel.org; Wed, 04 Aug 2021 22:57:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47478) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mBTYG-0005eb-B6; Wed, 04 Aug 2021 22:56:08 -0400 Received: from out28-100.mail.aliyun.com ([115.124.28.100]:57226) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mBTYE-0005x5-9v; Wed, 04 Aug 2021 22:56:08 -0400 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07436794|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_alarm|0.0297705-7.76435e-05-0.970152; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047190; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=7; RT=7; SR=0; TI=SMTPD_---.KvYnsuC_1628132160; Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.KvYnsuC_1628132160) by smtp.aliyun-inc.com(10.147.40.2); Thu, 05 Aug 2021 10:56:01 +0800 From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC PATCH 02/13] target/riscv: Support UXL32 for branch instructions Date: Thu, 5 Aug 2021 10:53:01 +0800 Message-Id: <20210805025312.15720-3-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210805025312.15720-1-zhiwei_liu@c-sky.com> References: <20210805025312.15720-1-zhiwei_liu@c-sky.com> Received-SPF: none client-ip=115.124.28.100; envelope-from=zhiwei_liu@c-sky.com; helo=out28-100.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, richard.henderson@linaro.org, bin.meng@windriver.com, Alistair.Francis@wdc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" When UXLEN is 32 on 64-bit CPU, only use the LSB 32 bits of source registers and sign-extend or zero-extend it according to different operations. Signed-off-by: LIU Zhiwei --- target/riscv/insn_trans/trans_rvi.c.inc | 38 ++++++++++++++++++++----- target/riscv/translate.c | 22 ++++++++++++++ 2 files changed, 53 insertions(+), 7 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc index 3705aad380..ea41d1de2d 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -84,11 +84,11 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a) return true; } -static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond) +static bool gen_branch_internal(DisasContext *ctx, arg_b *a, + TCGCond cond, + TCGv src1, TCGv src2) { TCGLabel *l = gen_new_label(); - TCGv src1 = gpr_src(ctx, a->rs1); - TCGv src2 = gpr_src(ctx, a->rs2); tcg_gen_brcond_tl(cond, src1, src2, l); gen_goto_tb(ctx, 1, ctx->pc_succ_insn); @@ -106,6 +106,30 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond) return true; } +static bool gen_branch_s(DisasContext *ctx, arg_b *a, TCGCond cond) +{ + TCGv src1 = gpr_src_s(ctx, a->rs1); + TCGv src2 = gpr_src_s(ctx, a->rs2); + + return gen_branch_internal(ctx, a, cond, src1, src2); +} + +static bool gen_branch_u(DisasContext *ctx, arg_b *a, TCGCond cond) +{ + TCGv src1 = gpr_src_u(ctx, a->rs1); + TCGv src2 = gpr_src_u(ctx, a->rs2); + + return gen_branch_internal(ctx, a, cond, src1, src2); +} + +static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond) +{ + TCGv src1 = gpr_src(ctx, a->rs1); + TCGv src2 = gpr_src(ctx, a->rs2); + + return gen_branch_internal(ctx, a, cond, src1, src2); +} + static bool trans_beq(DisasContext *ctx, arg_beq *a) { return gen_branch(ctx, a, TCG_COND_EQ); @@ -118,22 +142,22 @@ static bool trans_bne(DisasContext *ctx, arg_bne *a) static bool trans_blt(DisasContext *ctx, arg_blt *a) { - return gen_branch(ctx, a, TCG_COND_LT); + return gen_branch_s(ctx, a, TCG_COND_LT); } static bool trans_bge(DisasContext *ctx, arg_bge *a) { - return gen_branch(ctx, a, TCG_COND_GE); + return gen_branch_s(ctx, a, TCG_COND_GE); } static bool trans_bltu(DisasContext *ctx, arg_bltu *a) { - return gen_branch(ctx, a, TCG_COND_LTU); + return gen_branch_u(ctx, a, TCG_COND_LTU); } static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a) { - return gen_branch(ctx, a, TCG_COND_GEU); + return gen_branch_u(ctx, a, TCG_COND_GEU); } static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index ac4a545da8..d334a9db86 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -176,6 +176,28 @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) } } +static TCGv gpr_src_u(DisasContext *ctx, int reg_num) +{ + if (reg_num == 0) { + return ctx->zero; + } + if (ctx->uxl32) { + tcg_gen_ext32u_tl(cpu_gpr[reg_num], cpu_gpr[reg_num]); + } + return cpu_gpr[reg_num]; +} + +static TCGv gpr_src_s(DisasContext *ctx, int reg_num) +{ + if (reg_num == 0) { + return ctx->zero; + } + if (ctx->uxl32) { + tcg_gen_ext32s_tl(cpu_gpr[reg_num], cpu_gpr[reg_num]); + } + return cpu_gpr[reg_num]; +} + /* Wrapper for getting reg values - need to check of reg is zero since * cpu_gpr[0] is not actually allocated */ From patchwork Thu Aug 5 02:53:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LIU Zhiwei X-Patchwork-Id: 12420187 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CB04DC4338F for ; Thu, 5 Aug 2021 02:58:47 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8AAE661050 for ; Thu, 5 Aug 2021 02:58:47 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 8AAE661050 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=c-sky.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:39534 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mBTao-0002ok-Mh for qemu-devel@archiver.kernel.org; Wed, 04 Aug 2021 22:58:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47694) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mBTYj-000725-Ti; Wed, 04 Aug 2021 22:56:37 -0400 Received: from out28-101.mail.aliyun.com ([115.124.28.101]:46814) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mBTYi-0006N2-1r; Wed, 04 Aug 2021 22:56:37 -0400 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.1007043|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.00286054-4.40044e-05-0.997095; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047204; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=7; RT=7; SR=0; TI=SMTPD_---.KvYntEE_1628132191; Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.KvYntEE_1628132191) by smtp.aliyun-inc.com(10.147.40.2); Thu, 05 Aug 2021 10:56:31 +0800 From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC PATCH 03/13] target/riscv: Support UXL32 on 64-bit cpu for load/store Date: Thu, 5 Aug 2021 10:53:02 +0800 Message-Id: <20210805025312.15720-4-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210805025312.15720-1-zhiwei_liu@c-sky.com> References: <20210805025312.15720-1-zhiwei_liu@c-sky.com> Received-SPF: none client-ip=115.124.28.101; envelope-from=zhiwei_liu@c-sky.com; helo=out28-101.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, richard.henderson@linaro.org, bin.meng@windriver.com, Alistair.Francis@wdc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Get the LSB 32 bits and zero-extend as the base address. Signed-off-by: LIU Zhiwei --- target/riscv/insn_trans/trans_rvi.c.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc index ea41d1de2d..6823a6b3e0 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -163,7 +163,7 @@ static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a) static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop) { TCGv dest = gpr_dst(ctx, a->rd); - TCGv addr = gpr_src(ctx, a->rs1); + TCGv addr = gpr_src_u(ctx, a->rs1); TCGv temp = NULL; if (a->imm) { @@ -207,7 +207,7 @@ static bool trans_lhu(DisasContext *ctx, arg_lhu *a) static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop) { - TCGv addr = gpr_src(ctx, a->rs1); + TCGv addr = gpr_src_u(ctx, a->rs1); TCGv data = gpr_src(ctx, a->rs2); TCGv temp = NULL; From patchwork Thu Aug 5 02:53:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LIU Zhiwei X-Patchwork-Id: 12420185 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0FA09C4338F for ; Thu, 5 Aug 2021 02:58:25 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BA21060F42 for ; Thu, 5 Aug 2021 02:58:24 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org BA21060F42 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=c-sky.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:37744 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mBTaR-0001bi-Qo for qemu-devel@archiver.kernel.org; Wed, 04 Aug 2021 22:58:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47810) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mBTZF-0008Dc-AJ; Wed, 04 Aug 2021 22:57:09 -0400 Received: from out28-173.mail.aliyun.com ([115.124.28.173]:36272) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mBTZC-0006ma-Cy; Wed, 04 Aug 2021 22:57:09 -0400 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.0743679|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.0510524-0.00286427-0.946083; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047203; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=7; RT=7; SR=0; TI=SMTPD_---.KvYBBHl_1628132221; Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.KvYBBHl_1628132221) by smtp.aliyun-inc.com(10.147.42.22); Thu, 05 Aug 2021 10:57:02 +0800 From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC PATCH 04/13] target/riscv: Support UXL32 for slit/sltiu Date: Thu, 5 Aug 2021 10:53:03 +0800 Message-Id: <20210805025312.15720-5-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210805025312.15720-1-zhiwei_liu@c-sky.com> References: <20210805025312.15720-1-zhiwei_liu@c-sky.com> Received-SPF: none client-ip=115.124.28.173; envelope-from=zhiwei_liu@c-sky.com; helo=out28-173.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, richard.henderson@linaro.org, bin.meng@windriver.com, Alistair.Francis@wdc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" For slitu, the imm is sign-extend before unsigned compare. Thus we should only use the LSB 32 bits of the imm for UXL32. Signed-off-by: LIU Zhiwei --- target/riscv/insn_trans/trans_rvi.c.inc | 8 ++--- target/riscv/translate.c | 44 +++++++++++++++++++++++++ 2 files changed, 48 insertions(+), 4 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc index 6823a6b3e0..6201c07795 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -276,12 +276,12 @@ static void gen_sltu(TCGv ret, TCGv s1, TCGv s2) static bool trans_slti(DisasContext *ctx, arg_slti *a) { - return gen_arith_imm_tl(ctx, a, &gen_slt); + return gen_arith_simm_tl(ctx, a, &gen_slt); } static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a) { - return gen_arith_imm_tl(ctx, a, &gen_sltu); + return gen_arith_uimm_tl(ctx, a, &gen_sltu); } static bool trans_xori(DisasContext *ctx, arg_xori *a) @@ -328,12 +328,12 @@ static bool trans_sll(DisasContext *ctx, arg_sll *a) static bool trans_slt(DisasContext *ctx, arg_slt *a) { - return gen_arith(ctx, a, &gen_slt); + return gen_arith_s(ctx, a, &gen_slt); } static bool trans_sltu(DisasContext *ctx, arg_sltu *a) { - return gen_arith(ctx, a, &gen_sltu); + return gen_arith_u(ctx, a, &gen_sltu); } static bool trans_xor(DisasContext *ctx, arg_xor *a) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index d334a9db86..912e5f1061 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -494,6 +494,28 @@ static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, return true; } +static bool gen_arith_simm_tl(DisasContext *ctx, arg_i *a, + void (*func)(TCGv, TCGv, TCGv)) +{ + TCGv dest = gpr_dst(ctx, a->rd); + TCGv src1 = gpr_src_s(ctx, a->rs1); + TCGv src2 = tcg_constant_tl(a->imm); + + (*func)(dest, src1, src2); + return true; +} + +static bool gen_arith_uimm_tl(DisasContext *ctx, arg_i *a, + void (*func)(TCGv, TCGv, TCGv)) +{ + TCGv dest = gpr_dst(ctx, a->rd); + TCGv src1 = gpr_src_u(ctx, a->rs1); + TCGv src2 = tcg_constant_tl(ctx->uxl32 ? a->imm & UINT32_MAX : a->imm); + + (*func)(dest, src1, src2); + return true; +} + static void gen_addw(TCGv ret, TCGv arg1, TCGv arg2) { tcg_gen_add_tl(ret, arg1, arg2); @@ -779,6 +801,28 @@ static bool gen_arith(DisasContext *ctx, arg_r *a, return true; } +static bool gen_arith_u(DisasContext *ctx, arg_r *a, + void(*func)(TCGv, TCGv, TCGv)) +{ + TCGv dest = gpr_dst(ctx, a->rd); + TCGv src1 = gpr_src_u(ctx, a->rs1); + TCGv src2 = gpr_src_u(ctx, a->rs2); + + (*func)(dest, src1, src2); + return true; +} + +static bool gen_arith_s(DisasContext *ctx, arg_r *a, + void(*func)(TCGv, TCGv, TCGv)) +{ + TCGv dest = gpr_dst(ctx, a->rd); + TCGv src1 = gpr_src_s(ctx, a->rs1); + TCGv src2 = gpr_src_s(ctx, a->rs2); + + (*func)(dest, src1, src2); + return true; +} + static bool gen_shift(DisasContext *ctx, arg_r *a, void(*func)(TCGv, TCGv, TCGv)) { From patchwork Thu Aug 5 02:53:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LIU Zhiwei X-Patchwork-Id: 12420191 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A0FC1C4338F for ; Thu, 5 Aug 2021 02:59:39 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 680F761037 for ; Thu, 5 Aug 2021 02:59:39 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 680F761037 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=c-sky.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:44356 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mBTbe-0005zj-J6 for qemu-devel@archiver.kernel.org; Wed, 04 Aug 2021 22:59:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47902) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mBTZi-0000uX-Hg; Wed, 04 Aug 2021 22:57:38 -0400 Received: from out28-1.mail.aliyun.com ([115.124.28.1]:44010) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mBTZg-0007HX-MM; Wed, 04 Aug 2021 22:57:38 -0400 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.08995347|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.13775-0.000181703-0.862068; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047194; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=7; RT=7; SR=0; TI=SMTPD_---.KvYntve_1628132252; Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.KvYntve_1628132252) by smtp.aliyun-inc.com(10.147.40.2); Thu, 05 Aug 2021 10:57:32 +0800 From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC PATCH 05/13] target/riscv: Support UXL32 for shift instruction Date: Thu, 5 Aug 2021 10:53:04 +0800 Message-Id: <20210805025312.15720-6-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210805025312.15720-1-zhiwei_liu@c-sky.com> References: <20210805025312.15720-1-zhiwei_liu@c-sky.com> Received-SPF: none client-ip=115.124.28.1; envelope-from=zhiwei_liu@c-sky.com; helo=out28-1.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, richard.henderson@linaro.org, bin.meng@windriver.com, Alistair.Francis@wdc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Reuse 32-bit right shift instructions. Signed-off-by: LIU Zhiwei --- target/riscv/insn_trans/trans_rvi.c.inc | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc index 6201c07795..698a28731e 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -303,11 +303,17 @@ static bool trans_slli(DisasContext *ctx, arg_slli *a) static bool trans_srli(DisasContext *ctx, arg_srli *a) { + if (ctx->uxl32) { + return trans_srliw(ctx, a); + } return gen_shifti(ctx, a, tcg_gen_shr_tl); } static bool trans_srai(DisasContext *ctx, arg_srai *a) { + if (ctx->uxl32) { + return trans_sraiw(ctx, a); + } return gen_shifti(ctx, a, tcg_gen_sar_tl); } @@ -343,11 +349,17 @@ static bool trans_xor(DisasContext *ctx, arg_xor *a) static bool trans_srl(DisasContext *ctx, arg_srl *a) { + if (ctx->uxl32) { + return trans_srlw(ctx, a); + } return gen_shift(ctx, a, &tcg_gen_shr_tl); } static bool trans_sra(DisasContext *ctx, arg_sra *a) { + if (ctx->uxl32) { + return trans_sraw(ctx, a); + } return gen_shift(ctx, a, &tcg_gen_sar_tl); } From patchwork Thu Aug 5 02:53:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LIU Zhiwei X-Patchwork-Id: 12420189 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8F6FDC4338F for ; Thu, 5 Aug 2021 02:59:03 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 42EAF61037 for ; Thu, 5 Aug 2021 02:59:03 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 42EAF61037 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=c-sky.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:41050 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mBTb4-0003pk-Da for qemu-devel@archiver.kernel.org; Wed, 04 Aug 2021 22:59:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48004) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mBTaE-0001dV-H1; Wed, 04 Aug 2021 22:58:10 -0400 Received: from out28-172.mail.aliyun.com ([115.124.28.172]:33563) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mBTaB-0007iv-FM; Wed, 04 Aug 2021 22:58:10 -0400 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07436617|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.042309-0.000835167-0.956856; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047203; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=7; RT=7; SR=0; TI=SMTPD_---.KvYnuF._1628132282; Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.KvYnuF._1628132282) by smtp.aliyun-inc.com(10.147.40.2); Thu, 05 Aug 2021 10:58:02 +0800 From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC PATCH 06/13] target/riscv: Fix div instructions Date: Thu, 5 Aug 2021 10:53:05 +0800 Message-Id: <20210805025312.15720-7-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210805025312.15720-1-zhiwei_liu@c-sky.com> References: <20210805025312.15720-1-zhiwei_liu@c-sky.com> Received-SPF: none client-ip=115.124.28.172; envelope-from=zhiwei_liu@c-sky.com; helo=out28-172.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, richard.henderson@linaro.org, bin.meng@windriver.com, Alistair.Francis@wdc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Don't overwrite global source register after https://lists.gnu.org/archive/html/qemu-riscv/2021-07/msg00058.html. Signed-off-by: LIU Zhiwei --- target/riscv/translate.c | 46 +++++++++++++++++++++++----------------- 1 file changed, 26 insertions(+), 20 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 912e5f1061..2892eaa9a7 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -265,7 +265,7 @@ static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2) static void gen_div(TCGv ret, TCGv source1, TCGv source2) { - TCGv cond1, cond2, zeroreg, resultopt1; + TCGv cond1, cond2, zeroreg, resultopt1, t1, t2; /* * Handle by altering args to tcg_gen_div to produce req'd results: * For overflow: want source1 in source1 and 1 in source2 @@ -275,6 +275,8 @@ static void gen_div(TCGv ret, TCGv source1, TCGv source2) cond2 = tcg_temp_new(); zeroreg = tcg_constant_tl(0); resultopt1 = tcg_temp_new(); + t1 = tcg_temp_new(); + t2 = tcg_temp_new(); tcg_gen_movi_tl(resultopt1, (target_ulong)-1); tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)(~0L)); @@ -283,49 +285,52 @@ static void gen_div(TCGv ret, TCGv source1, TCGv source2) tcg_gen_and_tl(cond1, cond1, cond2); /* cond1 = overflow */ tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, 0); /* cond2 = div 0 */ /* if div by zero, set source1 to -1, otherwise don't change */ - tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond2, zeroreg, source1, - resultopt1); + tcg_gen_movcond_tl(TCG_COND_EQ, t1, cond2, zeroreg, source1, resultopt1); /* if overflow or div by zero, set source2 to 1, else don't change */ tcg_gen_or_tl(cond1, cond1, cond2); tcg_gen_movi_tl(resultopt1, (target_ulong)1); - tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2, - resultopt1); - tcg_gen_div_tl(ret, source1, source2); + tcg_gen_movcond_tl(TCG_COND_EQ, t2, cond1, zeroreg, source2, resultopt1); + tcg_gen_div_tl(ret, t1, t2); tcg_temp_free(cond1); tcg_temp_free(cond2); tcg_temp_free(resultopt1); + tcg_temp_free(t1); + tcg_temp_free(t2); } static void gen_divu(TCGv ret, TCGv source1, TCGv source2) { - TCGv cond1, zeroreg, resultopt1; + TCGv cond1, zeroreg, resultopt1, t1, t2; cond1 = tcg_temp_new(); zeroreg = tcg_constant_tl(0); resultopt1 = tcg_temp_new(); + t1 = tcg_temp_new(); + t2 = tcg_temp_new(); tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); tcg_gen_movi_tl(resultopt1, (target_ulong)-1); - tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond1, zeroreg, source1, - resultopt1); + tcg_gen_movcond_tl(TCG_COND_EQ, t1, cond1, zeroreg, source1, resultopt1); tcg_gen_movi_tl(resultopt1, (target_ulong)1); - tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2, - resultopt1); - tcg_gen_divu_tl(ret, source1, source2); + tcg_gen_movcond_tl(TCG_COND_EQ, t2, cond1, zeroreg, source2, resultopt1); + tcg_gen_divu_tl(ret, t1, t2); tcg_temp_free(cond1); tcg_temp_free(resultopt1); + tcg_temp_free(t1); + tcg_temp_free(t2); } static void gen_rem(TCGv ret, TCGv source1, TCGv source2) { - TCGv cond1, cond2, zeroreg, resultopt1; + TCGv cond1, cond2, zeroreg, resultopt1, t2; cond1 = tcg_temp_new(); cond2 = tcg_temp_new(); zeroreg = tcg_constant_tl(0); resultopt1 = tcg_temp_new(); + t2 = tcg_temp_new(); tcg_gen_movi_tl(resultopt1, 1L); tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)-1); @@ -335,9 +340,8 @@ static void gen_rem(TCGv ret, TCGv source1, TCGv source2) tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); /* cond2 = div 0 */ /* if overflow or div by zero, set source2 to 1, else don't change */ tcg_gen_or_tl(cond2, cond1, cond2); - tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond2, zeroreg, source2, - resultopt1); - tcg_gen_rem_tl(resultopt1, source1, source2); + tcg_gen_movcond_tl(TCG_COND_EQ, t2, cond2, zeroreg, source2, resultopt1); + tcg_gen_rem_tl(resultopt1, source1, t2); /* if div by zero, just return the original dividend */ tcg_gen_movcond_tl(TCG_COND_EQ, ret, cond1, zeroreg, resultopt1, source1); @@ -345,26 +349,28 @@ static void gen_rem(TCGv ret, TCGv source1, TCGv source2) tcg_temp_free(cond1); tcg_temp_free(cond2); tcg_temp_free(resultopt1); + tcg_temp_free(t2); } static void gen_remu(TCGv ret, TCGv source1, TCGv source2) { - TCGv cond1, zeroreg, resultopt1; + TCGv cond1, zeroreg, resultopt1, t2; cond1 = tcg_temp_new(); zeroreg = tcg_constant_tl(0); resultopt1 = tcg_temp_new(); + t2 = tcg_temp_new(); tcg_gen_movi_tl(resultopt1, (target_ulong)1); tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); - tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2, - resultopt1); - tcg_gen_remu_tl(resultopt1, source1, source2); + tcg_gen_movcond_tl(TCG_COND_EQ, t2, cond1, zeroreg, source2, resultopt1); + tcg_gen_remu_tl(resultopt1, source1, t2); /* if div by zero, just return the original dividend */ tcg_gen_movcond_tl(TCG_COND_EQ, ret, cond1, zeroreg, resultopt1, source1); tcg_temp_free(cond1); tcg_temp_free(resultopt1); + tcg_temp_free(t2); } static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) From patchwork Thu Aug 5 02:53:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LIU Zhiwei X-Patchwork-Id: 12420203 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C935CC4338F for ; Thu, 5 Aug 2021 03:00:47 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 590BF61037 for ; Thu, 5 Aug 2021 03:00:47 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 590BF61037 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=c-sky.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:48222 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mBTck-00009M-HM for qemu-devel@archiver.kernel.org; Wed, 04 Aug 2021 23:00:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48068) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mBTai-0003Et-M1; Wed, 04 Aug 2021 22:58:40 -0400 Received: from out28-221.mail.aliyun.com ([115.124.28.221]:51061) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mBTaf-000876-Hu; Wed, 04 Aug 2021 22:58:40 -0400 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07436282|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.0848442-0.00200604-0.91315; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047188; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=7; RT=7; SR=0; TI=SMTPD_---.KvYGVtQ_1628132313; Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.KvYGVtQ_1628132313) by smtp.aliyun-inc.com(10.147.42.135); Thu, 05 Aug 2021 10:58:33 +0800 From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC PATCH 07/13] target/riscv: Support UXL32 for RVM Date: Thu, 5 Aug 2021 10:53:06 +0800 Message-Id: <20210805025312.15720-8-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210805025312.15720-1-zhiwei_liu@c-sky.com> References: <20210805025312.15720-1-zhiwei_liu@c-sky.com> Received-SPF: none client-ip=115.124.28.221; envelope-from=zhiwei_liu@c-sky.com; helo=out28-221.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, richard.henderson@linaro.org, bin.meng@windriver.com, Alistair.Francis@wdc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: LIU Zhiwei --- target/riscv/insn_trans/trans_rvm.c.inc | 24 ++++++++--- target/riscv/translate.c | 56 +++++++++++++++++++------ 2 files changed, 62 insertions(+), 18 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_trans/trans_rvm.c.inc index 34220b824d..121d592351 100644 --- a/target/riscv/insn_trans/trans_rvm.c.inc +++ b/target/riscv/insn_trans/trans_rvm.c.inc @@ -28,43 +28,55 @@ static bool trans_mul(DisasContext *ctx, arg_mul *a) static bool trans_mulh(DisasContext *ctx, arg_mulh *a) { REQUIRE_EXT(ctx, RVM); - return gen_arith(ctx, a, gen_mulh); + return gen_arith_s(ctx, a, gen_mulh); } static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a) { REQUIRE_EXT(ctx, RVM); - return gen_arith(ctx, a, &gen_mulhsu); + return gen_arith_su(ctx, a, &gen_mulhsu); } static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a) { REQUIRE_EXT(ctx, RVM); - return gen_arith(ctx, a, gen_mulhu); + return gen_arith_u(ctx, a, gen_mulhu); } static bool trans_div(DisasContext *ctx, arg_div *a) { REQUIRE_EXT(ctx, RVM); - return gen_arith(ctx, a, &gen_div); + if (ctx->uxl32) { + return trans_divw(ctx, a); + } + return gen_arith_div(ctx, a, &gen_div); } static bool trans_divu(DisasContext *ctx, arg_divu *a) { REQUIRE_EXT(ctx, RVM); + if (ctx->uxl32) { + return trans_divuw(ctx, a); + } return gen_arith(ctx, a, &gen_divu); } static bool trans_rem(DisasContext *ctx, arg_rem *a) { REQUIRE_EXT(ctx, RVM); - return gen_arith(ctx, a, &gen_rem); + if (ctx->uxl32) { + return trans_remw(ctx, a); + } + return gen_arith_div(ctx, a, &gen_rem); } static bool trans_remu(DisasContext *ctx, arg_remu *a) { REQUIRE_EXT(ctx, RVM); - return gen_arith(ctx, a, &gen_remu); + if (ctx->uxl32) { + return trans_remuw(ctx, a); + } + return gen_arith_u(ctx, a, &gen_remu); } static bool trans_mulw(DisasContext *ctx, arg_mulw *a) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 2892eaa9a7..160a2df629 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -254,16 +254,14 @@ static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2) TCGv rh = tcg_temp_new(); tcg_gen_mulu2_tl(rl, rh, arg1, arg2); - /* fix up for one negative */ - tcg_gen_sari_tl(rl, arg1, TARGET_LONG_BITS - 1); - tcg_gen_and_tl(rl, rl, arg2); - tcg_gen_sub_tl(ret, rh, rl); + tcg_gen_sub_tl(rl, rh, arg2); + tcg_gen_movcond_tl(TCG_COND_LT, ret, arg1, tcg_constant_tl(0), rl, rh); tcg_temp_free(rl); tcg_temp_free(rh); } -static void gen_div(TCGv ret, TCGv source1, TCGv source2) +static void gen_div(DisasContext *ctx, TCGv ret, TCGv source1, TCGv source2) { TCGv cond1, cond2, zeroreg, resultopt1, t1, t2; /* @@ -280,8 +278,14 @@ static void gen_div(TCGv ret, TCGv source1, TCGv source2) tcg_gen_movi_tl(resultopt1, (target_ulong)-1); tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)(~0L)); - tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1, - ((target_ulong)1) << (TARGET_LONG_BITS - 1)); + + if (ctx->uxl32) { + tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1, INT32_MIN); + } else { + tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1, + ((target_ulong)1) << (TARGET_LONG_BITS - 1)); + } + tcg_gen_and_tl(cond1, cond1, cond2); /* cond1 = overflow */ tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, 0); /* cond2 = div 0 */ /* if div by zero, set source1 to -1, otherwise don't change */ @@ -322,7 +326,7 @@ static void gen_divu(TCGv ret, TCGv source1, TCGv source2) tcg_temp_free(t2); } -static void gen_rem(TCGv ret, TCGv source1, TCGv source2) +static void gen_rem(DisasContext *ctx, TCGv ret, TCGv source1, TCGv source2) { TCGv cond1, cond2, zeroreg, resultopt1, t2; @@ -334,8 +338,14 @@ static void gen_rem(TCGv ret, TCGv source1, TCGv source2) tcg_gen_movi_tl(resultopt1, 1L); tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)-1); - tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1, - (target_ulong)1 << (TARGET_LONG_BITS - 1)); + + if (ctx->uxl32) { + tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1, INT32_MIN); + } else { + tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1, + ((target_long)1) << (TARGET_LONG_BITS - 1)); + } + tcg_gen_and_tl(cond2, cond1, cond2); /* cond1 = overflow */ tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); /* cond2 = div 0 */ /* if overflow or div by zero, set source2 to 1, else don't change */ @@ -541,7 +551,7 @@ static void gen_mulw(TCGv ret, TCGv arg1, TCGv arg2) } static bool gen_arith_div_w(DisasContext *ctx, arg_r *a, - void(*func)(TCGv, TCGv, TCGv)) + void(*func)(DisasContext *, TCGv, TCGv, TCGv)) { TCGv dest = gpr_dst(ctx, a->rd); TCGv src1 = gpr_src(ctx, a->rs1); @@ -552,7 +562,7 @@ static bool gen_arith_div_w(DisasContext *ctx, arg_r *a, tcg_gen_ext32s_tl(ext1, src1); tcg_gen_ext32s_tl(ext2, src2); - (*func)(dest, ext1, ext2); + (*func)(ctx, dest, ext1, ext2); tcg_temp_free(ext1); tcg_temp_free(ext2); @@ -829,6 +839,28 @@ static bool gen_arith_s(DisasContext *ctx, arg_r *a, return true; } +static bool gen_arith_su(DisasContext *ctx, arg_r *a, + void(*func)(TCGv, TCGv, TCGv)) +{ + TCGv dest = gpr_dst(ctx, a->rd); + TCGv src1 = gpr_src_u(ctx, a->rs1); + TCGv src2 = gpr_src_u(ctx, a->rs2); + + (*func)(dest, src1, src2); + return true; +} + +static bool gen_arith_div(DisasContext *ctx, arg_r *a, + void(*func)(DisasContext *, TCGv, TCGv, TCGv)) +{ + TCGv dest = gpr_dst(ctx, a->rd); + TCGv src1 = gpr_src_s(ctx, a->rs1); + TCGv src2 = gpr_src_s(ctx, a->rs2); + + (*func)(ctx, dest, src1, src2); + return true; +} + static bool gen_shift(DisasContext *ctx, arg_r *a, void(*func)(TCGv, TCGv, TCGv)) { From patchwork Thu Aug 5 02:53:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LIU Zhiwei X-Patchwork-Id: 12420205 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B0539C4320A for ; Thu, 5 Aug 2021 03:01:01 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 49B1060184 for ; Thu, 5 Aug 2021 03:01:01 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 49B1060184 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=c-sky.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:48484 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mBTcu-0000Pi-Ej for qemu-devel@archiver.kernel.org; Wed, 04 Aug 2021 23:01:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48114) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mBTbB-0004yU-R9; Wed, 04 Aug 2021 22:59:09 -0400 Received: from out28-173.mail.aliyun.com ([115.124.28.173]:33180) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mBTb9-0008Ve-5N; Wed, 04 Aug 2021 22:59:09 -0400 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07608247|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_alarm|0.00299586-4.10079e-05-0.996963; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047213; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=7; RT=7; SR=0; TI=SMTPD_---.KvY-JEZ_1628132343; Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.KvY-JEZ_1628132343) by smtp.aliyun-inc.com(10.147.41.199); Thu, 05 Aug 2021 10:59:03 +0800 From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC PATCH 08/13] target/riscv: Support UXL32 for vector instructions Date: Thu, 5 Aug 2021 10:53:07 +0800 Message-Id: <20210805025312.15720-9-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210805025312.15720-1-zhiwei_liu@c-sky.com> References: <20210805025312.15720-1-zhiwei_liu@c-sky.com> Received-SPF: none client-ip=115.124.28.173; envelope-from=zhiwei_liu@c-sky.com; helo=out28-173.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, richard.henderson@linaro.org, bin.meng@windriver.com, Alistair.Francis@wdc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" For integer operations, the scalar can be taken from the scalar x register specified by rs1. If XLEN --- target/riscv/cpu.h | 3 ++ target/riscv/insn_trans/trans_rvv.c.inc | 44 ++++++++++++-------- target/riscv/vector_helper.c | 54 +++++++++++++++++-------- 3 files changed, 68 insertions(+), 33 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 2b3ba21a78..9c96a1e818 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -111,6 +111,9 @@ FIELD(VTYPE, VEDIV, 5, 2) FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 9) FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1) +FIELD(VTYPE, RESERVED_UXL32, 7, 23) +FIELD(VTYPE, VILL_UXL32, 31, 1) + struct CPURISCVState { target_ulong gpr[32]; uint64_t fpr[32]; /* assume both F and D extensions */ diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 84a45fac38..732b8ab460 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -35,7 +35,7 @@ static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a) /* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */ s1 = tcg_constant_tl(RV_VLEN_MAX); } else { - s1 = gpr_src(ctx, a->rs1); + s1 = gpr_src_u(ctx, a->rs1); } gen_helper_vsetvl(dst, cpu_env, s1, s2); @@ -61,7 +61,7 @@ static bool trans_vsetvli(DisasContext *ctx, arg_vsetvli *a) /* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */ s1 = tcg_constant_tl(RV_VLEN_MAX); } else { - s1 = gpr_src(ctx, a->rs1); + s1 = gpr_src_u(ctx, a->rs1); } gen_helper_vsetvl(dst, cpu_env, s1, s2); @@ -163,7 +163,7 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data, dest = tcg_temp_new_ptr(); mask = tcg_temp_new_ptr(); - base = gpr_src(s, rs1); + base = gpr_src_u(s, rs1); /* * As simd_desc supports at most 256 bytes, and in this implementation, @@ -318,8 +318,8 @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2, dest = tcg_temp_new_ptr(); mask = tcg_temp_new_ptr(); - base = gpr_src(s, rs1); - stride = gpr_src(s, rs2); + base = gpr_src_u(s, rs1); + stride = gpr_src_s(s, rs2); desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); @@ -442,7 +442,7 @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, dest = tcg_temp_new_ptr(); mask = tcg_temp_new_ptr(); index = tcg_temp_new_ptr(); - base = gpr_src(s, rs1); + base = gpr_src_u(s, rs1); desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); @@ -571,7 +571,7 @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data, dest = tcg_temp_new_ptr(); mask = tcg_temp_new_ptr(); - base = gpr_src(s, rs1); + base = gpr_src_u(s, rs1); desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); @@ -645,7 +645,7 @@ static bool amo_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, dest = tcg_temp_new_ptr(); mask = tcg_temp_new_ptr(); index = tcg_temp_new_ptr(); - base = gpr_src(s, rs1); + base = gpr_src_u(s, rs1); desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); @@ -731,12 +731,13 @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t seq) */ static bool amo_check(DisasContext *s, arg_rwdvm* a) { - return (!s->vill && has_ext(s, RVA) && - (!a->wd || vext_check_overlap_mask(s, a->rd, a->vm, false)) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs2, false) && - ((1 << s->sew) <= sizeof(target_ulong)) && - ((1 << s->sew) >= 4)); + return !s->vill && has_ext(s, RVA) && + (!a->wd || vext_check_overlap_mask(s, a->rd, a->vm, false)) && + vext_check_reg(s, a->rd, false) && + vext_check_reg(s, a->rs2, false) && + (s->uxl32 ? ((1 << s->sew) == 4) : + (((1 << s->sew) <= sizeof(target_ulong)) && + ((1 << s->sew) >= 4))); } static bool amo_check64(DisasContext *s, arg_rwdvm* a) @@ -840,7 +841,7 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm, dest = tcg_temp_new_ptr(); mask = tcg_temp_new_ptr(); src2 = tcg_temp_new_ptr(); - src1 = gpr_src(s, rs1); + src1 = gpr_src_s(s, rs1); data = FIELD_DP32(data, VDATA, MLEN, s->mlen); data = FIELD_DP32(data, VDATA, VM, vm); @@ -882,7 +883,7 @@ do_opivx_gvec(DisasContext *s, arg_rmrr *a, GVecGen2sFn *gvec_fn, if (a->vm && s->vl_eq_vlmax) { TCGv_i64 src1 = tcg_temp_new_i64(); - tcg_gen_ext_tl_i64(src1, gpr_src(s, a->rs1)); + tcg_gen_ext_tl_i64(src1, gpr_src_s(s, a->rs1)); gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), src1, MAXSZ(s), MAXSZ(s)); @@ -1635,7 +1636,7 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a) TCGLabel *over = gen_new_label(); tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); - s1 = gpr_src(s, a->rs1); + s1 = gpr_src_s(s, a->rs1); if (s->vl_eq_vlmax) { tcg_gen_gvec_dup_tl(s->sew, vreg_ofs(s, a->rd), @@ -2609,6 +2610,9 @@ static bool trans_vext_x_v(DisasContext *s, arg_r *a) } else { /* This instruction ignores LMUL and vector register groups */ int vlmax = s->vlen >> (3 + s->sew); + if (s->uxl32) { + tcg_gen_ext32u_tl(cpu_gpr[a->rs1], cpu_gpr[a->rs1]); + } vec_element_loadx(s, tmp, a->rs2, cpu_gpr[a->rs1], vlmax); } @@ -2667,6 +2671,9 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a) } t1 = tcg_temp_new_i64(); + if (s->uxl32) { + tcg_gen_ext32u_tl(cpu_gpr[a->rs1], cpu_gpr[a->rs1]); + } tcg_gen_extu_tl_i64(t1, cpu_gpr[a->rs1]); vec_element_storei(s, a->rd, 0, t1); tcg_temp_free_i64(t1); @@ -2780,6 +2787,9 @@ static bool trans_vrgather_vx(DisasContext *s, arg_rmrr *a) if (a->rs1 == 0) { vec_element_loadi(s, dest, a->rs2, 0); } else { + if (unlikely(s->uxl32)) { + tcg_gen_ext32u_tl(cpu_gpr[a->rs1], cpu_gpr[a->rs1]); + } vec_element_loadx(s, dest, a->rs2, cpu_gpr[a->rs1], vlmax); } diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 12c31aa4b4..4babd1b6aa 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -35,10 +35,19 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1, uint8_t ediv = FIELD_EX64(s2, VTYPE, VEDIV); bool vill = FIELD_EX64(s2, VTYPE, VILL); target_ulong reserved = FIELD_EX64(s2, VTYPE, RESERVED); + bool uxl32 = riscv_cpu_is_uxl32(env); + if (uxl32) { + vill = FIELD_EX64(s2, VTYPE, VILL_UXL32); + reserved = FIELD_EX64(s2, VTYPE, RESERVED_UXL32); + } if ((sew > cpu->cfg.elen) || vill || (ediv != 0) || (reserved != 0)) { /* only set vill bit. */ - env->vtype = FIELD_DP64(0, VTYPE, VILL, 1); + if (uxl32) { + env->vtype = FIELD_DP64(0, VTYPE, VILL_UXL32, 1); + } else { + env->vtype = FIELD_DP64(0, VTYPE, VILL, 1); + } env->vl = 0; env->vstart = 0; return 0; @@ -479,14 +488,18 @@ GEN_VEXT_ST_US(vse_v_d, int64_t, int64_t, ste_d) /* *** index: access vector element from indexed memory */ -typedef target_ulong vext_get_index_addr(target_ulong base, - uint32_t idx, void *vs2); +typedef target_ulong vext_get_index_addr(bool uxl32, target_ulong base, + uint32_t idx, void *vs2); -#define GEN_VEXT_GET_INDEX_ADDR(NAME, ETYPE, H) \ -static target_ulong NAME(target_ulong base, \ - uint32_t idx, void *vs2) \ -{ \ - return (base + *((ETYPE *)vs2 + H(idx))); \ +#define GEN_VEXT_GET_INDEX_ADDR(NAME, ETYPE, H) \ +static target_ulong NAME(bool uxl32, target_ulong base, \ + uint32_t idx, void *vs2) \ +{ \ + if (uxl32) { \ + return base + (int32_t)(*((ETYPE *)vs2 + H(idx))); \ + } else { \ + return base + *((ETYPE *)vs2 + H(idx)); \ + } \ } GEN_VEXT_GET_INDEX_ADDR(idx_b, int8_t, H1) @@ -508,13 +521,14 @@ vext_ldst_index(void *vd, void *v0, target_ulong base, uint32_t vm = vext_vm(desc); uint32_t mlen = vext_mlen(desc); uint32_t vlmax = vext_maxsz(desc) / esz; + bool uxl32 = riscv_cpu_is_uxl32(env); /* probe every access*/ for (i = 0; i < env->vl; i++) { if (!vm && !vext_elem_mask(v0, mlen, i)) { continue; } - probe_pages(env, get_index_addr(base, i, vs2), nf * msz, ra, + probe_pages(env, get_index_addr(uxl32, base, i, vs2), nf * msz, ra, access_type); } /* load bytes from guest memory */ @@ -524,7 +538,7 @@ vext_ldst_index(void *vd, void *v0, target_ulong base, continue; } while (k < nf) { - abi_ptr addr = get_index_addr(base, i, vs2) + k * msz; + abi_ptr addr = get_index_addr(uxl32, base, i, vs2) + k * msz; ldst_elem(env, addr, i + k * vlmax, vd, ra); k++; } @@ -784,19 +798,22 @@ vext_amo_noatomic(void *vs3, void *v0, target_ulong base, uint32_t vm = vext_vm(desc); uint32_t mlen = vext_mlen(desc); uint32_t vlmax = vext_maxsz(desc) / esz; + bool uxl32 = riscv_cpu_is_uxl32(env); for (i = 0; i < env->vl; i++) { if (!vm && !vext_elem_mask(v0, mlen, i)) { continue; } - probe_pages(env, get_index_addr(base, i, vs2), msz, ra, MMU_DATA_LOAD); - probe_pages(env, get_index_addr(base, i, vs2), msz, ra, MMU_DATA_STORE); + probe_pages(env, get_index_addr(uxl32, base, i, vs2), msz, ra, + MMU_DATA_LOAD); + probe_pages(env, get_index_addr(uxl32, base, i, vs2), msz, ra, + MMU_DATA_STORE); } for (i = 0; i < env->vl; i++) { if (!vm && !vext_elem_mask(v0, mlen, i)) { continue; } - addr = get_index_addr(base, i, vs2); + addr = get_index_addr(uxl32, base, i, vs2); noatomic_op(vs3, addr, wd, i, env, ra); } clear_elem(vs3, env->vl, env->vl * esz, vlmax * esz); @@ -4682,7 +4699,8 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ - target_ulong offset = s1, i; \ + target_ulong offset, i; \ + offset = riscv_cpu_is_uxl32(env) ? s1 & UINT32_MAX : s1; \ \ for (i = offset; i < vl; i++) { \ if (!vm && !vext_elem_mask(v0, mlen, i)) { \ @@ -4707,7 +4725,8 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ - target_ulong offset = s1, i; \ + target_ulong offset, i; \ + offset = riscv_cpu_is_uxl32(env) ? s1 & UINT32_MAX : s1; \ \ for (i = 0; i < vl; ++i) { \ target_ulong j = i + offset; \ @@ -4734,6 +4753,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ uint32_t i; \ + s1 = riscv_cpu_is_uxl32(env) ? s1 & UINT32_MAX : s1; \ \ for (i = 0; i < vl; i++) { \ if (!vm && !vext_elem_mask(v0, mlen, i)) { \ @@ -4763,6 +4783,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ uint32_t i; \ + s1 = riscv_cpu_is_uxl32(env) ? s1 & UINT32_MAX : s1; \ \ for (i = 0; i < vl; i++) { \ if (!vm && !vext_elem_mask(v0, mlen, i)) { \ @@ -4823,8 +4844,9 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ - uint64_t index = s1; \ + uint64_t index; \ uint32_t i; \ + index = riscv_cpu_is_uxl32(env) ? s1 & UINT32_MAX : s1; \ \ for (i = 0; i < vl; i++) { \ if (!vm && !vext_elem_mask(v0, mlen, i)) { \ From patchwork Thu Aug 5 02:53:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LIU Zhiwei X-Patchwork-Id: 12420207 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9C27FC4320A for ; Thu, 5 Aug 2021 03:01:22 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 69FC660184 for ; Thu, 5 Aug 2021 03:01:22 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 69FC660184 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=c-sky.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:49530 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mBTdJ-00018f-I2 for qemu-devel@archiver.kernel.org; Wed, 04 Aug 2021 23:01:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48180) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mBTbg-0006sB-OI; Wed, 04 Aug 2021 22:59:40 -0400 Received: from out28-197.mail.aliyun.com ([115.124.28.197]:42927) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mBTbe-0000SN-Rq; Wed, 04 Aug 2021 22:59:40 -0400 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07594667|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_alarm|0.0254385-0.000642626-0.973919; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047211; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=7; RT=7; SR=0; TI=SMTPD_---.KvYYLWy_1628132374; Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.KvYYLWy_1628132374) by smtp.aliyun-inc.com(10.147.43.230); Thu, 05 Aug 2021 10:59:34 +0800 From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC PATCH 09/13] target/riscv: Support UXL32 for atomic instructions Date: Thu, 5 Aug 2021 10:53:08 +0800 Message-Id: <20210805025312.15720-10-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210805025312.15720-1-zhiwei_liu@c-sky.com> References: <20210805025312.15720-1-zhiwei_liu@c-sky.com> Received-SPF: none client-ip=115.124.28.197; envelope-from=zhiwei_liu@c-sky.com; helo=out28-197.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, richard.henderson@linaro.org, bin.meng@windriver.com, Alistair.Francis@wdc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Only load or store 32 bits data for atomic instructions when UXL32. Signed-off-by: LIU Zhiwei --- target/riscv/insn_trans/trans_rva.c.inc | 36 ++++++++++++++++++++----- 1 file changed, 30 insertions(+), 6 deletions(-) diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_trans/trans_rva.c.inc index 5bb5bbd09c..07c94416e5 100644 --- a/target/riscv/insn_trans/trans_rva.c.inc +++ b/target/riscv/insn_trans/trans_rva.c.inc @@ -20,12 +20,19 @@ static bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop) { - TCGv src1 = gpr_src(ctx, a->rs1); + TCGv src1 = gpr_src_u(ctx, a->rs1); /* Put addr in load_res, data in load_val. */ if (a->rl) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); } + if (ctx->uxl32) { + TCGv_i32 val = tcg_temp_new_i32(); + tcg_gen_qemu_ld_i32(val, src1, ctx->mem_idx, mop); + tcg_gen_extu_i32_tl(load_val, val); + } else { + tcg_gen_qemu_ld_tl(load_val, src1, ctx->mem_idx, mop); + } tcg_gen_qemu_ld_tl(load_val, src1, ctx->mem_idx, mop); if (a->aq) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); @@ -39,8 +46,8 @@ static bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop) static bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop) { TCGv dest = gpr_dst(ctx, a->rd); - TCGv src1 = gpr_src(ctx, a->rs1); - TCGv src2 = gpr_src(ctx, a->rs2); + TCGv src1 = gpr_src_u(ctx, a->rs1); + TCGv src2 = gpr_src_u(ctx, a->rs2); TCGLabel *l1 = gen_new_label(); TCGLabel *l2 = gen_new_label(); @@ -50,8 +57,25 @@ static bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop) * Note that the TCG atomic primitives are SC, * so we can ignore AQ/RL along this path. */ - tcg_gen_atomic_cmpxchg_tl(dest, load_res, load_val, src2, - ctx->mem_idx, mop); + if (ctx->uxl32) { + TCGv_i32 retv, cmpv, newv; + retv = tcg_temp_new_i32(); + cmpv = tcg_temp_new_i32(); + newv = tcg_temp_new_i32(); + tcg_gen_trunc_tl_i32(cmpv, load_val); + tcg_gen_trunc_tl_i32(newv, src2); + + tcg_gen_atomic_cmpxchg_i32(retv, load_res, cmpv, newv, + ctx->mem_idx, mop); + + tcg_gen_extu_i32_tl(dest, retv); + tcg_temp_free_i32(retv); + tcg_temp_free_i32(cmpv); + tcg_temp_free_i32(newv); + } else { + tcg_gen_atomic_cmpxchg_tl(dest, load_res, load_val, src2, + ctx->mem_idx, mop); + } tcg_gen_setcond_tl(TCG_COND_NE, dest, dest, load_val); tcg_gen_br(l2); @@ -78,7 +102,7 @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a, MemOp mop) { TCGv dest = gpr_dst(ctx, a->rd); - TCGv src1 = gpr_src(ctx, a->rs1); + TCGv src1 = gpr_src_u(ctx, a->rs1); TCGv src2 = gpr_src(ctx, a->rs2); (*func)(dest, src1, src2, ctx->mem_idx, mop); From patchwork Thu Aug 5 02:53:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LIU Zhiwei X-Patchwork-Id: 12420211 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 64B61C4338F for ; Thu, 5 Aug 2021 03:03:16 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0FD1461004 for ; Thu, 5 Aug 2021 03:03:16 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 0FD1461004 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=c-sky.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:55854 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mBTf9-0005Wj-6L for qemu-devel@archiver.kernel.org; Wed, 04 Aug 2021 23:03:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48286) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mBTcC-00086z-FG; Wed, 04 Aug 2021 23:00:12 -0400 Received: from out28-76.mail.aliyun.com ([115.124.28.76]:44833) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mBTcA-0000sL-KS; Wed, 04 Aug 2021 23:00:12 -0400 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07822467|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.00526741-8.74947e-05-0.994645; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047212; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=7; RT=7; SR=0; TI=SMTPD_---.KvYMzRs_1628132404; Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.KvYMzRs_1628132404) by smtp.aliyun-inc.com(10.147.44.145); Thu, 05 Aug 2021 11:00:04 +0800 From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC PATCH 10/13] target/riscv: Support UXL32 for float instructions Date: Thu, 5 Aug 2021 10:53:09 +0800 Message-Id: <20210805025312.15720-11-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210805025312.15720-1-zhiwei_liu@c-sky.com> References: <20210805025312.15720-1-zhiwei_liu@c-sky.com> Received-SPF: none client-ip=115.124.28.76; envelope-from=zhiwei_liu@c-sky.com; helo=out28-76.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, richard.henderson@linaro.org, bin.meng@windriver.com, Alistair.Francis@wdc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: LIU Zhiwei --- target/riscv/insn_trans/trans_rvd.c.inc | 4 ++-- target/riscv/insn_trans/trans_rvf.c.inc | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_trans/trans_rvd.c.inc index 9bb15fdc12..fb033ccd97 100644 --- a/target/riscv/insn_trans/trans_rvd.c.inc +++ b/target/riscv/insn_trans/trans_rvd.c.inc @@ -23,7 +23,7 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); - TCGv addr = gpr_src(ctx, a->rs1); + TCGv addr = gpr_src_u(ctx, a->rs1); TCGv temp = NULL; if (a->imm) { @@ -46,7 +46,7 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); - TCGv addr = gpr_src(ctx, a->rs1); + TCGv addr = gpr_src_u(ctx, a->rs1); TCGv temp = NULL; if (a->imm) { diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc index ff8e942199..4576072124 100644 --- a/target/riscv/insn_trans/trans_rvf.c.inc +++ b/target/riscv/insn_trans/trans_rvf.c.inc @@ -28,7 +28,7 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); - TCGv addr = gpr_src(ctx, a->rs1); + TCGv addr = gpr_src_u(ctx, a->rs1); TCGv temp = NULL; if (a->imm) { @@ -53,7 +53,7 @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); - TCGv addr = gpr_src(ctx, a->rs1); + TCGv addr = gpr_src_u(ctx, a->rs1); TCGv temp = NULL; if (a->imm) { From patchwork Thu Aug 5 02:53:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LIU Zhiwei X-Patchwork-Id: 12420213 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 40948C4338F for ; Thu, 5 Aug 2021 03:03:24 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0A0D361050 for ; Thu, 5 Aug 2021 03:03:24 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 0A0D361050 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=c-sky.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:56298 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mBTfH-0005pg-3H for qemu-devel@archiver.kernel.org; Wed, 04 Aug 2021 23:03:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48378) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mBTcf-0000te-PY; Wed, 04 Aug 2021 23:00:41 -0400 Received: from out28-170.mail.aliyun.com ([115.124.28.170]:48057) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mBTcd-0001Oa-VA; Wed, 04 Aug 2021 23:00:41 -0400 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.08804092|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.0587047-0.000653314-0.940642; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047213; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=7; RT=7; SR=0; TI=SMTPD_---.KvYsTR0_1628132434; Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.KvYsTR0_1628132434) by smtp.aliyun-inc.com(10.147.41.187); Thu, 05 Aug 2021 11:00:35 +0800 From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC PATCH 11/13] target/riscv: Fix srow Date: Thu, 5 Aug 2021 10:53:10 +0800 Message-Id: <20210805025312.15720-12-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210805025312.15720-1-zhiwei_liu@c-sky.com> References: <20210805025312.15720-1-zhiwei_liu@c-sky.com> Received-SPF: none client-ip=115.124.28.170; envelope-from=zhiwei_liu@c-sky.com; helo=out28-170.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, richard.henderson@linaro.org, bin.meng@windriver.com, Alistair.Francis@wdc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Always fill MSB 32 bits with 1s in source register before calling gen_sro. Otherwise it may not only shift in 1s. Signed-off-by: LIU Zhiwei --- target/riscv/insn_trans/trans_rvb.c.inc | 4 ++-- target/riscv/translate.c | 7 +++++++ 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index 58921f3224..0bae0a2bbf 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -339,14 +339,14 @@ static bool trans_srow(DisasContext *ctx, arg_srow *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVB); - return gen_shiftw(ctx, a, gen_sro); + return gen_shiftw(ctx, a, gen_srow); } static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVB); - return gen_shiftiw(ctx, a, gen_sro); + return gen_shiftiw(ctx, a, gen_srow); } static bool trans_rorw(DisasContext *ctx, arg_rorw *a) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 160a2df629..5ee0feac4b 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -669,6 +669,13 @@ static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2) tcg_gen_not_tl(ret, ret); } +static void gen_srow(TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGv ones = tcg_constant_tl(UINT32_MAX); + tcg_gen_deposit_tl(arg1, arg1, ones, 32, 32); + gen_sro(ret, arg1, arg2); +} + static bool gen_grevi(DisasContext *ctx, arg_grevi *a) { TCGv dest = gpr_dst(ctx, a->rd); From patchwork Thu Aug 5 02:53:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LIU Zhiwei X-Patchwork-Id: 12420215 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AF05CC4338F for ; Thu, 5 Aug 2021 03:04:32 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 68F8B61078 for ; Thu, 5 Aug 2021 03:04:32 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 68F8B61078 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=c-sky.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:60334 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mBTgN-0008Vi-Ie for qemu-devel@archiver.kernel.org; Wed, 04 Aug 2021 23:04:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48462) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mBTdA-0001ed-Pp; Wed, 04 Aug 2021 23:01:12 -0400 Received: from out28-2.mail.aliyun.com ([115.124.28.2]:50583) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mBTd8-0001nk-K9; Wed, 04 Aug 2021 23:01:12 -0400 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07436282|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.0184785-0.00121228-0.980309; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047212; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=7; RT=7; SR=0; TI=SMTPD_---.KvYwGgT_1628132465; Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.KvYwGgT_1628132465) by smtp.aliyun-inc.com(10.147.42.241); Thu, 05 Aug 2021 11:01:05 +0800 From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC PATCH 12/13] target/riscv: Support UXL32 for RVB Date: Thu, 5 Aug 2021 10:53:11 +0800 Message-Id: <20210805025312.15720-13-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210805025312.15720-1-zhiwei_liu@c-sky.com> References: <20210805025312.15720-1-zhiwei_liu@c-sky.com> Received-SPF: none client-ip=115.124.28.2; envelope-from=zhiwei_liu@c-sky.com; helo=out28-2.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, richard.henderson@linaro.org, bin.meng@windriver.com, Alistair.Francis@wdc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: LIU Zhiwei --- target/riscv/insn_trans/trans_rvb.c.inc | 47 +++++++++++++++++++------ target/riscv/translate.c | 8 +++++ 2 files changed, 45 insertions(+), 10 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index 0bae0a2bbf..5de24c3a24 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -20,19 +20,19 @@ static bool trans_clz(DisasContext *ctx, arg_clz *a) { REQUIRE_EXT(ctx, RVB); - return gen_unary(ctx, a, gen_clz); + return gen_unary(ctx, a, ctx->uxl32 ? gen_clzw : gen_clz); } static bool trans_ctz(DisasContext *ctx, arg_ctz *a) { REQUIRE_EXT(ctx, RVB); - return gen_unary(ctx, a, gen_ctz); + return gen_unary(ctx, a, ctx->uxl32 ? gen_ctzw : gen_ctz); } static bool trans_cpop(DisasContext *ctx, arg_cpop *a) { REQUIRE_EXT(ctx, RVB); - return gen_unary(ctx, a, tcg_gen_ctpop_tl); + return gen_unary(ctx, a, ctx->uxl32 ? gen_cpopw : tcg_gen_ctpop_tl); } static bool trans_andn(DisasContext *ctx, arg_andn *a) @@ -56,43 +56,43 @@ static bool trans_xnor(DisasContext *ctx, arg_xnor *a) static bool trans_pack(DisasContext *ctx, arg_pack *a) { REQUIRE_EXT(ctx, RVB); - return gen_arith(ctx, a, gen_pack); + return gen_arith(ctx, a, ctx->uxl32 ? gen_packw : gen_pack); } static bool trans_packu(DisasContext *ctx, arg_packu *a) { REQUIRE_EXT(ctx, RVB); - return gen_arith(ctx, a, gen_packu); + return gen_arith(ctx, a, ctx->uxl32 ? gen_packuw : gen_packu); } static bool trans_packh(DisasContext *ctx, arg_packh *a) { REQUIRE_EXT(ctx, RVB); - return gen_arith(ctx, a, gen_packh); + return gen_arith(ctx, a, ctx->uxl32 ? gen_packhw : gen_packh); } static bool trans_min(DisasContext *ctx, arg_min *a) { REQUIRE_EXT(ctx, RVB); - return gen_arith(ctx, a, tcg_gen_smin_tl); + return gen_arith_s(ctx, a, tcg_gen_smin_tl); } static bool trans_max(DisasContext *ctx, arg_max *a) { REQUIRE_EXT(ctx, RVB); - return gen_arith(ctx, a, tcg_gen_smax_tl); + return gen_arith_s(ctx, a, tcg_gen_smax_tl); } static bool trans_minu(DisasContext *ctx, arg_minu *a) { REQUIRE_EXT(ctx, RVB); - return gen_arith(ctx, a, tcg_gen_umin_tl); + return gen_arith_u(ctx, a, tcg_gen_umin_tl); } static bool trans_maxu(DisasContext *ctx, arg_maxu *a) { REQUIRE_EXT(ctx, RVB); - return gen_arith(ctx, a, tcg_gen_umax_tl); + return gen_arith_u(ctx, a, tcg_gen_umax_tl); } static bool trans_sext_b(DisasContext *ctx, arg_sext_b *a) @@ -170,36 +170,54 @@ static bool trans_sloi(DisasContext *ctx, arg_sloi *a) static bool trans_sro(DisasContext *ctx, arg_sro *a) { REQUIRE_EXT(ctx, RVB); + if (ctx->uxl32) { + return trans_srow(ctx, a); + } return gen_shift(ctx, a, gen_sro); } static bool trans_sroi(DisasContext *ctx, arg_sroi *a) { REQUIRE_EXT(ctx, RVB); + if (ctx->uxl32) { + return trans_sroiw(ctx, a); + } return gen_shifti(ctx, a, gen_sro); } static bool trans_ror(DisasContext *ctx, arg_ror *a) { REQUIRE_EXT(ctx, RVB); + if (ctx->uxl32) { + return trans_rorw(ctx, a); + } return gen_shift(ctx, a, tcg_gen_rotr_tl); } static bool trans_rori(DisasContext *ctx, arg_rori *a) { REQUIRE_EXT(ctx, RVB); + if (ctx->uxl32) { + return trans_roriw(ctx, a); + } return gen_shifti(ctx, a, tcg_gen_rotr_tl); } static bool trans_rol(DisasContext *ctx, arg_rol *a) { REQUIRE_EXT(ctx, RVB); + if (ctx->uxl32) { + return trans_rolw(ctx, a); + } return gen_shift(ctx, a, tcg_gen_rotl_tl); } static bool trans_grev(DisasContext *ctx, arg_grev *a) { REQUIRE_EXT(ctx, RVB); + if (ctx->uxl32) { + return trans_grevw(ctx, a); + } return gen_shift(ctx, a, gen_helper_grev); } @@ -207,6 +225,9 @@ static bool trans_grevi(DisasContext *ctx, arg_grevi *a) { REQUIRE_EXT(ctx, RVB); + if (ctx->uxl32) { + return trans_grevi(ctx, a); + } if (a->shamt >= TARGET_LONG_BITS) { return false; } @@ -217,12 +238,18 @@ static bool trans_grevi(DisasContext *ctx, arg_grevi *a) static bool trans_gorc(DisasContext *ctx, arg_gorc *a) { REQUIRE_EXT(ctx, RVB); + if (ctx->uxl32) { + return trans_gorcw(ctx, a); + } return gen_shift(ctx, a, gen_helper_gorc); } static bool trans_gorci(DisasContext *ctx, arg_gorci *a) { REQUIRE_EXT(ctx, RVB); + if (ctx->uxl32) { + return trans_gorciw(ctx, a); + } return gen_shifti(ctx, a, gen_helper_gorc); } diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 5ee0feac4b..f4b2f75812 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -742,6 +742,14 @@ static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2) tcg_temp_free(t); } +static void gen_packhw(TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGv t = tcg_temp_new(); + tcg_gen_ext8u_tl(t, arg2); + tcg_gen_deposit_tl(ret, arg1, t, 8, 24); + tcg_temp_free(t); +} + static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2) { TCGv_i32 t1 = tcg_temp_new_i32(); From patchwork Thu Aug 5 02:53:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LIU Zhiwei X-Patchwork-Id: 12420209 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D3919C4338F for ; Thu, 5 Aug 2021 03:02:44 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8619E61078 for ; Thu, 5 Aug 2021 03:02:44 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 8619E61078 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=c-sky.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:54764 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mBTed-0004od-JJ for qemu-devel@archiver.kernel.org; Wed, 04 Aug 2021 23:02:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48552) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mBTdi-0002TV-4q; Wed, 04 Aug 2021 23:01:46 -0400 Received: from out28-53.mail.aliyun.com ([115.124.28.53]:37186) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mBTde-00028n-DG; Wed, 04 Aug 2021 23:01:45 -0400 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07748418|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_alarm|0.0530431-0.000661099-0.946296; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047202; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=7; RT=7; SR=0; TI=SMTPD_---.KvYBEPC_1628132495; Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.KvYBEPC_1628132495) by smtp.aliyun-inc.com(10.147.42.22); Thu, 05 Aug 2021 11:01:36 +0800 From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC PATCH 13/13] target/riscv: Changing the width of U-mode CSR Date: Thu, 5 Aug 2021 10:53:12 +0800 Message-Id: <20210805025312.15720-14-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210805025312.15720-1-zhiwei_liu@c-sky.com> References: <20210805025312.15720-1-zhiwei_liu@c-sky.com> Received-SPF: none client-ip=115.124.28.53; envelope-from=zhiwei_liu@c-sky.com; helo=out28-53.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, richard.henderson@linaro.org, bin.meng@windriver.com, Alistair.Francis@wdc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: LIU Zhiwei --- target/riscv/csr.c | 42 +++++++++++++++++++++++++++++++++++++----- 1 file changed, 37 insertions(+), 5 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 9a4ed18ac5..dc9807c0ff 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -297,7 +297,7 @@ static RISCVException read_vxrm(CPURISCVState *env, int csrno, static RISCVException write_vxrm(CPURISCVState *env, int csrno, target_ulong val) { - env->vxrm = val; + env->vxrm = riscv_cpu_is_uxl32(env) ? val & UINT32_MAX : val; return RISCV_EXCP_NONE; } @@ -311,7 +311,7 @@ static RISCVException read_vxsat(CPURISCVState *env, int csrno, static RISCVException write_vxsat(CPURISCVState *env, int csrno, target_ulong val) { - env->vxsat = val; + env->vxsat = riscv_cpu_is_uxl32(env) ? val & UINT32_MAX : val; return RISCV_EXCP_NONE; } @@ -325,7 +325,7 @@ static RISCVException read_vstart(CPURISCVState *env, int csrno, static RISCVException write_vstart(CPURISCVState *env, int csrno, target_ulong val) { - env->vstart = val; + env->vstart = riscv_cpu_is_uxl32(env) ? val & UINT32_MAX : val; return RISCV_EXCP_NONE; } @@ -493,6 +493,36 @@ static int validate_vm(CPURISCVState *env, target_ulong vm) } } +static void uxl32_switch(CPURISCVState *env, target_ulong val) +{ + uint32_t old = get_field(env->mstatus, MSTATUS64_UXL); + uint32_t new = get_field(val, MSTATUS64_UXL); + + if (old == new) { + return; + } + + /* + * For the read-only bits of the previous-width CSR, the bits at the + * same positions in the temporary register are set to zeros. + */ + if (env->misa & RVV) { + env->vl = 0; + env->vtype = 0; + } + + /* + * If the new width W is narrower than the previous width, the + * least-significant W bits of the temporary register are retained and + * the more-significant bits are discarded. + */ + if ((old == 2) && (new == 1)) { + if (env->misa & RVV) { + env->vtype &= UINT32_MAX; + } + } +} + static RISCVException write_mstatus(CPURISCVState *env, int csrno, target_ulong val) { @@ -502,13 +532,13 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno, /* flush tlb on mstatus fields that affect VM */ if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV | - MSTATUS_MPRV | MSTATUS_SUM)) { + MSTATUS_MPRV | MSTATUS_SUM | MSTATUS64_UXL)) { tlb_flush(env_cpu(env)); } mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR | - MSTATUS_TW; + MSTATUS_TW | MSTATUS64_UXL; if (!riscv_cpu_is_32bit(env)) { /* @@ -518,6 +548,8 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno, mask |= MSTATUS_MPV | MSTATUS_GVA; } + uxl32_switch(env, val); + mstatus = (mstatus & ~mask) | (val & mask); dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) |