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Thu, 5 Aug 2021 20:55:22 +0000 From: Wei Huang To: kvm@vger.kernel.org Cc: linux-kernel@vger.kernel.org, pbonzini@redhat.com, vkuznets@redhat.com, seanjc@google.com, wanpengli@tencent.com, jmattson@google.com, joro@8bytes.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, x86@kernel.org, hpa@zytor.com, wei.huang2@amd.com Subject: [PATCH v1 1/3] KVM: x86: Convert TDP level calculation to vendor's specific code Date: Thu, 5 Aug 2021 15:55:02 -0500 Message-Id: <20210805205504.2647362-2-wei.huang2@amd.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210805205504.2647362-1-wei.huang2@amd.com> References: <20210805205504.2647362-1-wei.huang2@amd.com> X-ClientProxiedBy: SN4PR0401CA0003.namprd04.prod.outlook.com (2603:10b6:803:21::13) To DM5PR1201MB0201.namprd12.prod.outlook.com (2603:10b6:4:5b::21) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from weiserver.amd.com (165.204.77.1) by SN4PR0401CA0003.namprd04.prod.outlook.com (2603:10b6:803:21::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4394.15 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: hFHbP0GM0anhBI9Bc8JSRxwpk1WTB2RQ0H7wMmIdJPSYP5lt0BPBAyEfUCQHKtZOgw/C/r66lY1q/2tMm6DWmQ974e4ZbGGklFMCg1xC1kpqTt1z+xRfZbxcmOEgw8l6mRu8SYMGsLwvdBQ4qE97ybp+smPSDSLLWVf9JrehKnwxoTWZvmbib4fkMV9Vetju8yHCf3UFYQcrJ1wWT6tdJtKEj1e2KQIQaFIixyYFSDSmghWTsNPepKeE9KJYG5KOH87qVNMqh92+25Ws2/2oLK1zcngNoZtbIUBWNhQF1JJc76xJQgqQxnO1Q/KPxsjU0iD5uTeLOYqLr+g1XIqYXLPx1esuHUQs11AHQh8YzVEeIwjLUtOE+y5pfGLJTlGtze+umbqonpc+sMTaC9Qj0fCTFjo3Yu8imWn/RfSye1hV8Z4yQb2xuficzRr/rH4A1I1Q9Be0KYSqmz+NRW+07T01LJgG6F7pLtmF+E/nd0E1gm9So/1VbnED48NdNH4t5lOwN36YxO9fJMYQpXeHFRGa9tdAiN3l8c863kgT/qf8vWDbmj1nRBYBBn5sBWcX39HADJMCUCnVG5eB0QRbo/7qJpMPGJa/LyDBWIsH+X3TwnWU6xPEqrbY6FxoiLwJSA33p7MdorP/R36bnlfEazf5Ef3iHmgBiEX1M0M0CyK2r/2lvWGTYBdPiJWvs4oDgk6zIopbZH8EtJ3Sf3X0KH4b1VdNnbKKeuDBDzsxGxUItUnV8eCWI6JTBPCiUiyzSh+txXekkSBjW7NTZOJUmEU4ybgOSVmDcXg3mFdqNpTidMr359Hg3ZCyeJ0S4R3/870GgIsgP5qWA225XlWVIuhbJ4lKmlw2IdOhKn67Ou08NYlXvXm77DN0UEocLTycs5NBDcCLL3riqSLFPqtT8k9isO7wPLPIAoF1AUBivqgA5jdaQqN57/qX5ydu7ilLrddrqOfMupOsitloSerlCm7fO3mJjR7KuLmFnL22fjaN1nwx88/88KjHOUhTP0bCAKxUT3Fthwmd0yjqGzgpNimX++IsqXOCCbb/3L1hUc6S4fddWbeu8IHWpYYt4D8Fh1BBqUl9qniEe8yuntkRiRY636YUfWUXwqtzF69WrbuichNJbD7sX6u3VEJrYY+IA/89cnXJ2JTctCai5xx7nB6JbY9RimfK4zvMfJFShgNWb8/9AHev3hNOmfe7GuKNFkke19HzK4DevimRMRspDIHcQQT46sBqXI45OMPt589nvaLXwXr7j12E8qiD6CBmvZvHr3HlSh4bNw5IavP7Qu8PqucjUX1BzM9WYxQGPa03UNFpQ2oR9YRhG592LPab X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 0a793df1-b75e-480b-f59e-08d9585357b7 X-MS-Exchange-CrossTenant-AuthSource: DM5PR1201MB0201.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Aug 2021 20:55:22.8478 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: C8khWwR76kB0tu0ZiFgnPQa0+CDh/22p9xSWFyKupAlWgpjk+YmxiKF5cwY/ObQf X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1241 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Currently the TDP level for x86 vCPU is calculated by checking both MAXPHYADDR and max_tdp_level. This design assumes that all x86 CPUs have the flexibility of changing the nested page table level different from host CPU. This assumption might not be true. To solve this problem, let us create a kvm_x86_ops specific function for TDP level calculation. Signed-off-by: Wei Huang --- arch/x86/include/asm/kvm-x86-ops.h | 1 + arch/x86/include/asm/kvm_host.h | 5 ++--- arch/x86/kvm/mmu/mmu.c | 22 +++++----------------- arch/x86/kvm/svm/svm.c | 5 +++-- arch/x86/kvm/vmx/vmx.c | 7 ++++--- 5 files changed, 15 insertions(+), 25 deletions(-) diff --git a/arch/x86/include/asm/kvm-x86-ops.h b/arch/x86/include/asm/kvm-x86-ops.h index a12a4987154e..9853a7c9e4b7 100644 --- a/arch/x86/include/asm/kvm-x86-ops.h +++ b/arch/x86/include/asm/kvm-x86-ops.h @@ -85,6 +85,7 @@ KVM_X86_OP_NULL(sync_pir_to_irr) KVM_X86_OP(set_tss_addr) KVM_X86_OP(set_identity_map_addr) KVM_X86_OP(get_mt_mask) +KVM_X86_OP(get_tdp_level) KVM_X86_OP(load_mmu_pgd) KVM_X86_OP_NULL(has_wbinvd_exit) KVM_X86_OP(get_l2_tsc_offset) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h index 974cbfb1eefe..20ddfbac966e 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -723,7 +723,6 @@ struct kvm_vcpu_arch { u64 reserved_gpa_bits; int maxphyaddr; - int max_tdp_level; /* emulate context */ @@ -1365,6 +1364,7 @@ struct kvm_x86_ops { int (*set_tss_addr)(struct kvm *kvm, unsigned int addr); int (*set_identity_map_addr)(struct kvm *kvm, u64 ident_addr); u64 (*get_mt_mask)(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio); + int (*get_tdp_level)(struct kvm_vcpu *vcpu); void (*load_mmu_pgd)(struct kvm_vcpu *vcpu, hpa_t root_hpa, int root_level); @@ -1747,8 +1747,7 @@ void kvm_mmu_invalidate_gva(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, void kvm_mmu_invpcid_gva(struct kvm_vcpu *vcpu, gva_t gva, unsigned long pcid); void kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t new_pgd); -void kvm_configure_mmu(bool enable_tdp, int tdp_max_root_level, - int tdp_huge_page_level); +void kvm_configure_mmu(bool enable_tdp, int tdp_huge_page_level); static inline u16 kvm_read_ldt(void) { diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c index 66f7f5bc3482..44e4561e41f5 100644 --- a/arch/x86/kvm/mmu/mmu.c +++ b/arch/x86/kvm/mmu/mmu.c @@ -97,7 +97,6 @@ module_param_named(flush_on_reuse, force_flush_and_sync_on_reuse, bool, 0644); bool tdp_enabled = false; static int max_huge_page_level __read_mostly; -static int max_tdp_level __read_mostly; enum { AUDIT_PRE_PAGE_FAULT, @@ -4560,15 +4559,6 @@ static union kvm_mmu_role kvm_calc_mmu_role_common(struct kvm_vcpu *vcpu, return role; } -static inline int kvm_mmu_get_tdp_level(struct kvm_vcpu *vcpu) -{ - /* Use 5-level TDP if and only if it's useful/necessary. */ - if (max_tdp_level == 5 && cpuid_maxphyaddr(vcpu) <= 48) - return 4; - - return max_tdp_level; -} - static union kvm_mmu_role kvm_calc_tdp_mmu_root_page_role(struct kvm_vcpu *vcpu, struct kvm_mmu_role_regs *regs, bool base_only) @@ -4576,7 +4566,7 @@ kvm_calc_tdp_mmu_root_page_role(struct kvm_vcpu *vcpu, union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, regs, base_only); role.base.ad_disabled = (shadow_accessed_mask == 0); - role.base.level = kvm_mmu_get_tdp_level(vcpu); + role.base.level = static_call(kvm_x86_get_tdp_level)(vcpu); role.base.direct = true; role.base.gpte_is_8_bytes = true; @@ -4597,7 +4587,7 @@ static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu) context->page_fault = kvm_tdp_page_fault; context->sync_page = nonpaging_sync_page; context->invlpg = NULL; - context->shadow_root_level = kvm_mmu_get_tdp_level(vcpu); + context->shadow_root_level = static_call(kvm_x86_get_tdp_level)(vcpu); context->direct_map = true; context->get_guest_pgd = get_cr3; context->get_pdptr = kvm_pdptr_read; @@ -4688,7 +4678,7 @@ kvm_calc_shadow_npt_root_page_role(struct kvm_vcpu *vcpu, kvm_calc_shadow_root_page_role_common(vcpu, regs, false); role.base.direct = false; - role.base.level = kvm_mmu_get_tdp_level(vcpu); + role.base.level = static_call(kvm_x86_get_tdp_level)(vcpu); return role; } @@ -5253,11 +5243,9 @@ void kvm_mmu_invpcid_gva(struct kvm_vcpu *vcpu, gva_t gva, unsigned long pcid) */ } -void kvm_configure_mmu(bool enable_tdp, int tdp_max_root_level, - int tdp_huge_page_level) +void kvm_configure_mmu(bool enable_tdp, int tdp_huge_page_level) { tdp_enabled = enable_tdp; - max_tdp_level = tdp_max_root_level; /* * max_huge_page_level reflects KVM's MMU capabilities irrespective @@ -5356,7 +5344,7 @@ static int __kvm_mmu_create(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu) * other exception is for shadowing L1's 32-bit or PAE NPT on 64-bit * KVM; that horror is handled on-demand by mmu_alloc_shadow_roots(). */ - if (tdp_enabled && kvm_mmu_get_tdp_level(vcpu) > PT32E_ROOT_LEVEL) + if (tdp_enabled && static_call(kvm_x86_get_tdp_level)(vcpu) > PT32E_ROOT_LEVEL) return 0; page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_DMA32); diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index e8ccab50ebf6..04710e10d04a 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -258,7 +258,7 @@ u32 svm_msrpm_offset(u32 msr) #define MAX_INST_SIZE 15 -static int get_max_npt_level(void) +static int svm_get_npt_level(struct kvm_vcpu *vcpu) { #ifdef CONFIG_X86_64 return PT64_ROOT_4LEVEL; @@ -1015,7 +1015,7 @@ static __init int svm_hardware_setup(void) if (!boot_cpu_has(X86_FEATURE_NPT)) npt_enabled = false; - kvm_configure_mmu(npt_enabled, get_max_npt_level(), PG_LEVEL_1G); + kvm_configure_mmu(npt_enabled, PG_LEVEL_1G); pr_info("kvm: Nested Paging %sabled\n", npt_enabled ? "en" : "dis"); /* Note, SEV setup consumes npt_enabled. */ @@ -4619,6 +4619,7 @@ static struct kvm_x86_ops svm_x86_ops __initdata = { .set_tss_addr = svm_set_tss_addr, .set_identity_map_addr = svm_set_identity_map_addr, .get_mt_mask = svm_get_mt_mask, + .get_tdp_level = svm_get_npt_level, .get_exit_info = svm_get_exit_info, diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 927a552393b9..419cea586646 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -3062,9 +3062,9 @@ void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) vmx->emulation_required = emulation_required(vcpu); } -static int vmx_get_max_tdp_level(void) +static int vmx_get_tdp_level(struct kvm_vcpu *vcpu) { - if (cpu_has_vmx_ept_5levels()) + if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48)) return 5; return 4; } @@ -7613,6 +7613,7 @@ static struct kvm_x86_ops vmx_x86_ops __initdata = { .set_tss_addr = vmx_set_tss_addr, .set_identity_map_addr = vmx_set_identity_map_addr, .get_mt_mask = vmx_get_mt_mask, + .get_tdp_level = vmx_get_tdp_level, .get_exit_info = vmx_get_exit_info, @@ -7803,7 +7804,7 @@ static __init int hardware_setup(void) ept_lpage_level = PG_LEVEL_2M; else ept_lpage_level = PG_LEVEL_4K; - kvm_configure_mmu(enable_ept, vmx_get_max_tdp_level(), ept_lpage_level); + kvm_configure_mmu(enable_ept, ept_lpage_level); /* * Only enable PML when hardware supports PML feature, and both EPT From patchwork Thu Aug 5 20:55:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wei Huang X-Patchwork-Id: 12422117 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D50BEC4338F for ; Thu, 5 Aug 2021 20:55:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B76AC61104 for ; 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dmarc=none action=none header.from=amd.com; Received: from DM5PR1201MB0201.namprd12.prod.outlook.com (2603:10b6:4:5b::21) by DM5PR1201MB0107.namprd12.prod.outlook.com (2603:10b6:4:55::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4373.26; Thu, 5 Aug 2021 20:55:35 +0000 Received: from DM5PR1201MB0201.namprd12.prod.outlook.com ([fe80::7410:8a22:1bdb:d24d]) by DM5PR1201MB0201.namprd12.prod.outlook.com ([fe80::7410:8a22:1bdb:d24d%6]) with mapi id 15.20.4394.017; Thu, 5 Aug 2021 20:55:35 +0000 From: Wei Huang To: kvm@vger.kernel.org Cc: linux-kernel@vger.kernel.org, pbonzini@redhat.com, vkuznets@redhat.com, seanjc@google.com, wanpengli@tencent.com, jmattson@google.com, joro@8bytes.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, x86@kernel.org, hpa@zytor.com, wei.huang2@amd.com Subject: [PATCH v1 2/3] KVM: x86: Handle the case of 5-level shadow page table Date: Thu, 5 Aug 2021 15:55:03 -0500 Message-Id: <20210805205504.2647362-3-wei.huang2@amd.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210805205504.2647362-1-wei.huang2@amd.com> References: <20210805205504.2647362-1-wei.huang2@amd.com> X-ClientProxiedBy: SN2PR01CA0082.prod.exchangelabs.com (2603:10b6:800::50) To DM5PR1201MB0201.namprd12.prod.outlook.com (2603:10b6:4:5b::21) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from weiserver.amd.com (165.204.77.1) by SN2PR01CA0082.prod.exchangelabs.com (2603:10b6:800::50) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4394.15 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: WxvQ66RACsyrTZ+PsgwVC1l2TdxcFfs9oDWTddAg3F9tJaHgP2i71I7NeKmIl880/ZyYR0WmKNif6WpdgbbMAu/o1gcO/emiaX2SrIsmDJKuDNKiWwopGYQ9QDSL3zjdCJX+lUvLi+VWSMRfKg+iVqFlssh6v8wS+7q5rYe8prXyHeLUKV3jmJmMaAtLqz4z+tomBim73Gxh4sIr8AXQp9yDrRqgvKDeoHTbtTofRqXv+uyFklD2gUjJAwYfsW5B5U4Je3IJ7xD8SH2J7at5ndlSaywAea/Bk5N8fGj6ruLjuJ3G2V0Rr96wvkA/HutOGk10Tjgjxg+fjU3j292JWoqwGxOGQNLN8BOa4XrdjfpsnLYyf8vX6CfpDoQZVyThAAXdQ3fhh7sgRgX4KYLY4+x9220KU7WSw4ObSbOmpOlf5JWLzdkYCJQ93Ap4Z4i6s2kuoPDUmhrAU7/dxQK5dytw6tNRHepXRzpsDkrjlkitVHkE3yeufWmmUfVdeo9mVVgB/ksWimgnztPcOH02TjPRvMput5RjGYlwJSpsBvynBxL+tMWpWuLI1wKsq8yD2Rb4HOXokWVxYDtzRkkvYekpmh+wMrQ111qxqk7EW9IjRQdg0rVXodNgAVnlv2Umc8pOL+sN7YIYm3X9fE6L1EZ79C36GHISFyjGtc/V+bhuvMiM7MGUAuWO3LJRB418DiY8bH0BCQ3tzkfs0EiBKyfCs1JytAQYJBj7BX2SnMF1/aeqEDHJ5A+HrZfzAImeI8gcRADf9jY8+D5cMiBs7XnYTxZBhvNTZPclQnWPF6/K/hTtNxRdPQ5aINHrPxzqLlCZevlAIjSrkS46cRv+1jCzqjV4l30TGJ4ff1c9jPEgN8hEgy3waPjsUDr7xE+Wi7Rw7DexD7CGuSKXpmmbotNKUAcYZKNpiCvQoOSfp89k0XANG1m45COfXzpQ0mlXh8vbN/sogn+DbTUPWZB3uAx6rpimP2ibAauLCFwDKbKwLdPcd6tKKGtSpF8nwvEURwvcDA9/VEAmKg/s1699U/E/KZ9hcfumG6rytpLz2wAKfj43NA1lGL+6qOaAxxvjJUnI5a+Ro1MDQN8+aNLqZ6sajBYSeHHzAxIKM9T6Y2aWLLaP8xR+ORfVvzNxRGAZD29mP2/vk3WHM412H1jp38QUIo2TfI5O3oZhAUBc/FF2y9scFDjgXKeauAN4ig908Z3BVDzntrxttatHwtpxzWpkZbifQFO9RKdjW8Vtjpb/GIC2hsUlAnt8UNCqsYKySl6acG4g7D3hm71+gPdWAGVo2Vn1Y7b0u5cjmvdXikMvUdUyZMSI66Me6gN4fvsI X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5179ff0f-36ca-4854-74fb-08d958535f06 X-MS-Exchange-CrossTenant-AuthSource: DM5PR1201MB0201.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Aug 2021 20:55:35.1533 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: cTimOkO3I6xw20zKXpoHGXkk9oVc6xYf8oCuDHMChVTOFI6Nf17+oqHJL6hdJoaR X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR1201MB0107 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org When the 5-level page table CPU flag is exposed, KVM code needs to handle this case by pointing mmu->root_hpa to a properly-constructed 5-level page table. Suggested-by: Paolo Bonzini Signed-off-by: Wei Huang --- arch/x86/include/asm/kvm_host.h | 1 + arch/x86/kvm/mmu/mmu.c | 46 +++++++++++++++++++++++---------- 2 files changed, 34 insertions(+), 13 deletions(-) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h index 20ddfbac966e..8586ffdf4de8 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -447,6 +447,7 @@ struct kvm_mmu { u64 *pae_root; u64 *pml4_root; + u64 *pml5_root; /* * check zero bits on shadow page table entries, these diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c index 44e4561e41f5..b162c3e530aa 100644 --- a/arch/x86/kvm/mmu/mmu.c +++ b/arch/x86/kvm/mmu/mmu.c @@ -3428,7 +3428,7 @@ static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu) * the shadow page table may be a PAE or a long mode page table. */ pm_mask = PT_PRESENT_MASK | shadow_me_mask; - if (mmu->shadow_root_level == PT64_ROOT_4LEVEL) { + if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL) { pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK; if (WARN_ON_ONCE(!mmu->pml4_root)) { @@ -3454,11 +3454,17 @@ static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu) PT32_ROOT_LEVEL, false); mmu->pae_root[i] = root | pm_mask; } + mmu->root_hpa = __pa(mmu->pae_root); - if (mmu->shadow_root_level == PT64_ROOT_4LEVEL) + if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL) { + mmu->pml4_root[0] = mmu->root_hpa | pm_mask; mmu->root_hpa = __pa(mmu->pml4_root); - else - mmu->root_hpa = __pa(mmu->pae_root); + } + + if (mmu->shadow_root_level == PT64_ROOT_5LEVEL) { + mmu->pml5_root[0] = mmu->root_hpa | pm_mask; + mmu->root_hpa = __pa(mmu->pml5_root); + } set_root_pgd: mmu->root_pgd = root_pgd; @@ -3471,7 +3477,7 @@ static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu) static int mmu_alloc_special_roots(struct kvm_vcpu *vcpu) { struct kvm_mmu *mmu = vcpu->arch.mmu; - u64 *pml4_root, *pae_root; + u64 *pml5_root, *pml4_root, *pae_root; /* * When shadowing 32-bit or PAE NPT with 64-bit NPT, the PML4 and PDP @@ -3487,17 +3493,18 @@ static int mmu_alloc_special_roots(struct kvm_vcpu *vcpu) * This mess only works with 4-level paging and needs to be updated to * work with 5-level paging. */ - if (WARN_ON_ONCE(mmu->shadow_root_level != PT64_ROOT_4LEVEL)) + if (WARN_ON_ONCE(mmu->shadow_root_level < PT64_ROOT_4LEVEL)) { return -EIO; + } - if (mmu->pae_root && mmu->pml4_root) + if (mmu->pae_root && mmu->pml4_root && mmu->pml5_root) return 0; /* * The special roots should always be allocated in concert. Yell and * bail if KVM ends up in a state where only one of the roots is valid. */ - if (WARN_ON_ONCE(!tdp_enabled || mmu->pae_root || mmu->pml4_root)) + if (WARN_ON_ONCE(!tdp_enabled || mmu->pae_root || mmu->pml4_root || mmu->pml5_root)) return -EIO; /* @@ -3506,18 +3513,30 @@ static int mmu_alloc_special_roots(struct kvm_vcpu *vcpu) */ pae_root = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT); if (!pae_root) - return -ENOMEM; + goto err_out; pml4_root = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT); - if (!pml4_root) { - free_page((unsigned long)pae_root); - return -ENOMEM; - } + if (!pml4_root) + goto err_out; + + pml5_root = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT); + if (!pml5_root) + goto err_out; mmu->pae_root = pae_root; mmu->pml4_root = pml4_root; + mmu->pml5_root = pml5_root; return 0; +err_out: + if (pae_root) + free_page((unsigned long)pae_root); + if (pml4_root) + free_page((unsigned long)pml4_root); + if (pml5_root) + free_page((unsigned long)pml5_root); + + return -ENOMEM; } void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu) @@ -5320,6 +5339,7 @@ static void free_mmu_pages(struct kvm_mmu *mmu) set_memory_encrypted((unsigned long)mmu->pae_root, 1); free_page((unsigned long)mmu->pae_root); free_page((unsigned long)mmu->pml4_root); + free_page((unsigned long)mmu->pml5_root); } static int __kvm_mmu_create(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu) From patchwork Thu Aug 5 20:55:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wei Huang X-Patchwork-Id: 12422119 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CA781C4338F for ; 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dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=none action=none header.from=amd.com; Received: from DM5PR1201MB0201.namprd12.prod.outlook.com (2603:10b6:4:5b::21) by DM5PR1201MB0107.namprd12.prod.outlook.com (2603:10b6:4:55::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4373.26; Thu, 5 Aug 2021 20:55:47 +0000 Received: from DM5PR1201MB0201.namprd12.prod.outlook.com ([fe80::7410:8a22:1bdb:d24d]) by DM5PR1201MB0201.namprd12.prod.outlook.com ([fe80::7410:8a22:1bdb:d24d%6]) with mapi id 15.20.4394.017; Thu, 5 Aug 2021 20:55:47 +0000 From: Wei Huang To: kvm@vger.kernel.org Cc: linux-kernel@vger.kernel.org, pbonzini@redhat.com, vkuznets@redhat.com, seanjc@google.com, wanpengli@tencent.com, jmattson@google.com, joro@8bytes.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, x86@kernel.org, hpa@zytor.com, wei.huang2@amd.com Subject: [PATCH v1 3/3] KVM: SVM: Add 5-level page table support for SVM Date: Thu, 5 Aug 2021 15:55:04 -0500 Message-Id: <20210805205504.2647362-4-wei.huang2@amd.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210805205504.2647362-1-wei.huang2@amd.com> References: <20210805205504.2647362-1-wei.huang2@amd.com> X-ClientProxiedBy: SA0PR11CA0168.namprd11.prod.outlook.com (2603:10b6:806:1bb::23) To DM5PR1201MB0201.namprd12.prod.outlook.com (2603:10b6:4:5b::21) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from weiserver.amd.com (165.204.77.1) by SA0PR11CA0168.namprd11.prod.outlook.com (2603:10b6:806:1bb::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4394.15 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: YL85H4qHY4W0rNMgyuNdm2bWQ6ONXb3rU9LrfPJU5ay5LcxZlpJ+V/T4AkQA8ikxoW3+ylNJHqaxksfz9K1dd/Zwvqx0Zc5izw5fZMvAyxyoHNqfXxAemJTEazwF2tySwu8OQWcrdlnrk58wbvTOMR7d+JpqSiXs21IrD8kWrPF+VN3URLQPYXPnpFpAsMdYGXJw3AcjJxbhf/ciz3ch3uAUYLtX73pGkQTp9xRU5ZuIPh5WhjxRXoNABU0A9VSVbFTWNTI/69wT7s2YtdVVFcQWSgPdNWIV6gsUYKjgjFgm/KD00T15NCR7iYXu2HOAn6fheFpgHdQRV+oChx3LEGTDqtNbVWtrZXmsJa8pW9u8sN6S3ljv+ShmjlWZ5t0JbsDUIlUZmeLCyL0NVykQbJcMS/aOiZzNiHAqD/shCK4g5cShRAc1SiA4nzfzC+kHxmoKKLSQ7bUDsDW8EA91b1+OLBbHQjuq/ejWObzAlMAz5XsD735XJc/7LhJViS0PeUyh+f+QAA4xEeSNO2bM2ACOj7wqNe3xBxVUHpcII/fniIA+K5Bu6eWXrBBnOEEE0pVLVq1b70wiBjkvv6rQ4+QA9DXK0CQZGW8cBUkr+ra5iLElsq9FEw6gcDjW5AXlENz8KvEHYq5YLRVmWDpLLf4/zU0WNBt799v8WJaLG5K0Yuc0r5qOSnHO8S6qnY/gyYApsFdEF/vACs4OdEx5T9wrQUYlH8inpghmYc1a8J1MKcSuM3/tB56orQHxAFQ0mae7D+/Qow4iHr325KgLwmg/4oYA004+uDMnAEa8KKZvqnfTzW3zM8A6RyzFnkQ5/tyFfZ2J2pzcaeGa674VQbg/4/nSgIuATDFWFiQjyE2mwmEkdA1fXMZvBOzHAsx4XVdzTHXIFs0ZK9zT99tI+flCAnxBp+CVkE7AEGOrViYfWi5eD1Vpp8dMsgRygPu0HAv4EC/a5SggKRB3ZH/emIvFmfJfdl8q5215jO2Ey4uf8piI99ppFN5Hq/yvtGy4I0yaX5BPlVrmTbayPLhdWzzk3ogwIITy0gDl9RM5U49ukp6auJeCVsLBxhUNMjE3dPFI4zyRsCrWSCufOUXXhGG5qX4t4rNIv/sGNxsZMjre+eIjTtK6QWaJJ+mVgn5H2+eqGhowXgb8EobZzWnG/Gu0fD2a2k4bwCNQ18v7KYTP9cSMCYbvjU2Qk19JvTS7H8DoLic7X0E6luQz4vAC2CCsfK/oEsNmUFEAdFT6Fbkjw6aUFKwehgREkIkvKainUsCw8CxkVKOCBr2tTot/hTPNrE6zPBXn7XCeOfILACzn7jgLNauMqhoH+if/fv1U X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4147ef05-f658-455d-0e80-08d958536652 X-MS-Exchange-CrossTenant-AuthSource: DM5PR1201MB0201.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Aug 2021 20:55:47.3738 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 6371eLeC8F6hjngoRfm+FfyHtzKhBcO0/VsRfbDroDWdIkNudWqc9815uwu2GhI6 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR1201MB0107 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Future AMD CPUs will support 5-level page table which is indicated by X86_CR4_LA57 flag. When the 5-level page table is enabled on host OS, the nested page table for guest VMs must use 5-level as well. Update get_npt_level() function to reflect this requirement. In the meanwhile, remove the code that prevents kvm-amd driver from being loaded when 5-level page table is detected. Signed-off-by: Wei Huang Signed-off-by: Paolo Bonzini --- arch/x86/kvm/svm/svm.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 04710e10d04a..f91ff7d2d9f9 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -261,7 +261,9 @@ u32 svm_msrpm_offset(u32 msr) static int svm_get_npt_level(struct kvm_vcpu *vcpu) { #ifdef CONFIG_X86_64 - return PT64_ROOT_4LEVEL; + bool la57 = (cr4_read_shadow() & X86_CR4_LA57) != 0; + + return la57 ? PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL; #else return PT32E_ROOT_LEVEL; #endif @@ -462,11 +464,6 @@ static int has_svm(void) return 0; } - if (pgtable_l5_enabled()) { - pr_info("KVM doesn't yet support 5-level paging on AMD SVM\n"); - return 0; - } - return 1; }