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Sun, 8 Aug 2021 19:27:17 +0000 From: Wei Huang To: kvm@vger.kernel.org Cc: linux-kernel@vger.kernel.org, pbonzini@redhat.com, seanjc@google.com, vkuznets@redhat.com, wanpengli@tencent.com, jmattson@google.com, joro@8bytes.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, x86@kernel.org, hpa@zytor.com Subject: [PATCH v2 1/3] KVM: x86: Allow CPU to force vendor-specific TDP level Date: Sun, 8 Aug 2021 14:26:56 -0500 Message-Id: <20210808192658.2923641-2-wei.huang2@amd.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210808192658.2923641-1-wei.huang2@amd.com> References: <20210808192658.2923641-1-wei.huang2@amd.com> X-ClientProxiedBy: SN1PR12CA0057.namprd12.prod.outlook.com (2603:10b6:802:20::28) To DM5PR1201MB0201.namprd12.prod.outlook.com (2603:10b6:4:5b::21) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from weiserver.amd.com (165.204.77.1) by SN1PR12CA0057.namprd12.prod.outlook.com (2603:10b6:802:20::28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4394.15 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Ye+Zwbkz3mGrP6fter3q46kbRizCrfkl0++ARO4Vu5Mny7Kf0nRZiRZzDTaODwBNQ2GgsaLrZhU4mEMVz5b6qcMYl6nMQkclTY4nv/TqrULSET/jqFi7JoaFDdYaLyqvZX9r/+5aLf/ghbZTXxEnw65HpjGPYhT1oh+piqs1+HPlLHe6eDw76kffIwTtsj2ey8vbJncTryw3kar8MRFwKuLWhvBsjx1nJhTcynRvgVzpBhU5yER+vxiZet7XCnG7pN2RsjI9cJRJSv9ynLo6Fcu64SPZySwvlLC3MGYS/7mE0GOSoKLqqI1kvDB8PNs9GHsS4/nIdmm5Yu41AueS8NcH5EwVj6CW/JQeb1QswWjGLtinZgnN5gx84/LBPE1IgKsWksPNkC15kSq57DFSJDL7c361RDzZmqH4BuhZju5ykdPq2WOJaUOtb644kpY5JrbUlP4tSTnHtoslVGkv6q0PJywL2K2vm7R7aiZzDAsmpqvku4ZxQUtt6c7i5+J6O/W5ET6stlEJgeOxivXkC/2F5LY6eRryoMjKdOHzYkZhALoAVq8kcLz0tujXH4gbfdxdfNX87W7y59SdrZxZJ6QU3Ox+Xmt3YF82ZeJlermU65i0s8YAWuv3pIJqP4KDbSR9CXImX487k0E13jAXhMIVLSDPPuIh/LMKip/OpMids/WY4heZMl1HKoj5LQORbE6hJyv6k0JmRgWFQ79EvaXhl3daRbdPu2h/IG46lMaNJfETgm0d/94RRrEoLzubn8RiPNhcBCyswpzOI/yghp3zDCt4drMhjwN916LIATI64GONdh38D8g5RTQelOpeUysJyK5IYOC/b4sB7aXtqFY1spbzFjoqxS2tCvN+4RnGq0gAX2Ct8lAeY/8N2IxrRTeLs6r3S6LLOEwFEBrqk5qHOirDdbFOx+DwQUVirtKE6hBD9H3pWHAuDiA28qfKDW9trZXs5sGUE/g+HdqSiRJkCj0uwgCOGetMeO8uG+gmVzxL62cNztualZ+zwue/E1FswFPZJwBb12eCV/a4nwQcrX9dVe2L3tb8bcOS7zM8TRPlHHSOg3uRoIXsyWXvNO7MR/hw/GrB9B7x/+4O9xl/Br5ruC5su+LlRivL1p8HTJ46o8FPvm06MIIVFhlyklGaZHxoZWIgpLbM++mDC3DbzZTuCZOyEraYFPzlj1oZ41HBF6zZHvB7OuIjx610I+h7JR2j2ZWNr8ZhFCgcMtEKwz4uNPv34GVr8D/0YW+GNSVypNQJ/nkzuZ96gW7hpGvxp7X24S9dqxEdOCDPUQxAo01U3NSb7CzgfqUf0X8lMu5RQ62P0B+l6UxTM9OB X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: c60caf61-6a3e-4fb7-22cd-08d95aa288a5 X-MS-Exchange-CrossTenant-AuthSource: DM5PR1201MB0201.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Aug 2021 19:27:17.4720 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: ujFbqg8906HZQ7s8QMjPPwm74n505EZ8CfTo6jcRUHJgkX0aO8wTAf0bEiPeiE6A X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1434 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org AMD future CPUs will require a 5-level NPT if host CR4.LA57 is set. To prevent kvm_mmu_get_tdp_level() from incorrectly changing NPT level on behalf of CPUs, add a new parameter in kvm_configure_mmu() to force a fixed TDP level. Signed-off-by: Wei Huang --- arch/x86/include/asm/kvm_host.h | 5 ++--- arch/x86/kvm/mmu/mmu.c | 10 ++++++++-- arch/x86/kvm/svm/svm.c | 4 +++- arch/x86/kvm/vmx/vmx.c | 3 ++- 4 files changed, 15 insertions(+), 7 deletions(-) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h index 974cbfb1eefe..6d16f75cc8da 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -723,7 +723,6 @@ struct kvm_vcpu_arch { u64 reserved_gpa_bits; int maxphyaddr; - int max_tdp_level; /* emulate context */ @@ -1747,8 +1746,8 @@ void kvm_mmu_invalidate_gva(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, void kvm_mmu_invpcid_gva(struct kvm_vcpu *vcpu, gva_t gva, unsigned long pcid); void kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t new_pgd); -void kvm_configure_mmu(bool enable_tdp, int tdp_max_root_level, - int tdp_huge_page_level); +void kvm_configure_mmu(bool enable_tdp, int tdp_forced_root_level, + int tdp_max_root_level, int tdp_huge_page_level); static inline u16 kvm_read_ldt(void) { diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c index 66f7f5bc3482..c11ee4531f6d 100644 --- a/arch/x86/kvm/mmu/mmu.c +++ b/arch/x86/kvm/mmu/mmu.c @@ -97,6 +97,7 @@ module_param_named(flush_on_reuse, force_flush_and_sync_on_reuse, bool, 0644); bool tdp_enabled = false; static int max_huge_page_level __read_mostly; +static int tdp_root_level __read_mostly; static int max_tdp_level __read_mostly; enum { @@ -4562,6 +4563,10 @@ static union kvm_mmu_role kvm_calc_mmu_role_common(struct kvm_vcpu *vcpu, static inline int kvm_mmu_get_tdp_level(struct kvm_vcpu *vcpu) { + /* tdp_root_level is architecture forced level, use it if nonzero */ + if (tdp_root_level) + return tdp_root_level; + /* Use 5-level TDP if and only if it's useful/necessary. */ if (max_tdp_level == 5 && cpuid_maxphyaddr(vcpu) <= 48) return 4; @@ -5253,10 +5258,11 @@ void kvm_mmu_invpcid_gva(struct kvm_vcpu *vcpu, gva_t gva, unsigned long pcid) */ } -void kvm_configure_mmu(bool enable_tdp, int tdp_max_root_level, - int tdp_huge_page_level) +void kvm_configure_mmu(bool enable_tdp, int tdp_forced_root_level, + int tdp_max_root_level, int tdp_huge_page_level) { tdp_enabled = enable_tdp; + tdp_root_level = tdp_forced_root_level; max_tdp_level = tdp_max_root_level; /* diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index e8ccab50ebf6..f361d466e18e 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -1015,7 +1015,9 @@ static __init int svm_hardware_setup(void) if (!boot_cpu_has(X86_FEATURE_NPT)) npt_enabled = false; - kvm_configure_mmu(npt_enabled, get_max_npt_level(), PG_LEVEL_1G); + /* Force VM NPT level equal to the host's max NPT level */ + kvm_configure_mmu(npt_enabled, get_max_npt_level(), + get_max_npt_level(), PG_LEVEL_1G); pr_info("kvm: Nested Paging %sabled\n", npt_enabled ? "en" : "dis"); /* Note, SEV setup consumes npt_enabled. */ diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 927a552393b9..034e1397c7d5 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -7803,7 +7803,8 @@ static __init int hardware_setup(void) ept_lpage_level = PG_LEVEL_2M; else ept_lpage_level = PG_LEVEL_4K; - kvm_configure_mmu(enable_ept, vmx_get_max_tdp_level(), ept_lpage_level); + kvm_configure_mmu(enable_ept, 0, vmx_get_max_tdp_level(), + ept_lpage_level); /* * Only enable PML when hardware supports PML feature, and both EPT From patchwork Sun Aug 8 19:26:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wei Huang X-Patchwork-Id: 12425091 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7947DC4338F for ; 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dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=none action=none header.from=amd.com; Received: from DM5PR1201MB0201.namprd12.prod.outlook.com (2603:10b6:4:5b::21) by DM5PR12MB1434.namprd12.prod.outlook.com (2603:10b6:3:77::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4394.17; Sun, 8 Aug 2021 19:27:29 +0000 Received: from DM5PR1201MB0201.namprd12.prod.outlook.com ([fe80::7410:8a22:1bdb:d24d]) by DM5PR1201MB0201.namprd12.prod.outlook.com ([fe80::7410:8a22:1bdb:d24d%6]) with mapi id 15.20.4394.022; Sun, 8 Aug 2021 19:27:29 +0000 From: Wei Huang To: kvm@vger.kernel.org Cc: linux-kernel@vger.kernel.org, pbonzini@redhat.com, seanjc@google.com, vkuznets@redhat.com, wanpengli@tencent.com, jmattson@google.com, joro@8bytes.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, x86@kernel.org, hpa@zytor.com Subject: [PATCH v2 2/3] KVM: x86: Handle the case of 5-level shadow page table Date: Sun, 8 Aug 2021 14:26:57 -0500 Message-Id: <20210808192658.2923641-3-wei.huang2@amd.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210808192658.2923641-1-wei.huang2@amd.com> References: <20210808192658.2923641-1-wei.huang2@amd.com> X-ClientProxiedBy: SN7PR04CA0093.namprd04.prod.outlook.com (2603:10b6:806:122::8) To DM5PR1201MB0201.namprd12.prod.outlook.com (2603:10b6:4:5b::21) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from weiserver.amd.com (165.204.77.1) by SN7PR04CA0093.namprd04.prod.outlook.com (2603:10b6:806:122::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4394.15 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 8ZbW+jVhIH+0lL3UgzdbCFVG0r46BTLsmZrxyPhyxiFhLYJJbVHbUIJ7p3lJSUqsnb+ieHmfJK6Utwb4vevpGEpUQcDJPzxcFOzYSdK8/RCOdWXWoTHZk3ME/u/L5h/y4Xsh/MyVofdLd4x7rMBMGUXver21oFl5PiB4bQNTQUaowlA8MQ4v/FuR3WtDgVsDXazAROnek17/t/gjlE6gPOKoUXs4WrpnX6QyJxmCmQEWNonzh3G5Q2CmGC1l1SOpiaj1Z6tJ2ZaDc1DmJTZH91q2us4eqvnesfUP1jjiyKI5cHtWXOaQJ4UC/F5d2TL0r3s9L56OVRewiSG7JJdA+ooa3zVRV4hZ2pHdC58ksCtFefASm5DTAW3lBsluMv9ScGRTYQfCxXXzWzJFEqbhqBF3ieR0hEGvXrOaUb3oEEhGhFT93j8uojMhn1jGUrkyN1YQdklBPzjBq3PYTyuMpt5P2r2M/l5yBpz1ZPqMnOIrfT1exoenRIdRLpJgNnZJTkPdv5qOIgj4RKlDZ/k9eZ63vaHCq9LcwYCiIbFPTtIvvHbeNyg+ig6vlsb4nGGxZhxSINgT9OYcHZO0ZG/XDZr8yWC/G62NI8kKLC7YAlGUwJoHmmZXF0JkwXQAOQ4cKjMIggTaPUcZh1tg/d0r9H53/G6H7rIYT4hX0iBvCPFGeHaEziIJ74TBGpN+TL2eLVVv675HqjZJkc391+tmsM0b4/MOGBiVTEhqeVuGr2nR23fFHNiEcA0e1wGK0enTkaqpFO7PyigYbOU9oCQeT8AsSsIiUkHiLHnbUMgpihhhqap3QtSKTSX2mg1KlrgVM7KfIkMg+AZOxs1LJknXqUvnzWGke5zLqql6072VzOxrJCT4I1h4ra7eCVIgm75OgVaOHPyOhOULkoUorvn5gn1tMalGNTAx8OBat7SYZ6v8KE+G+9UhRxE51Kh1sInWfkJRHMZt9yxkdEcGDnGsFFXkMu2+vjeohPxRuy/keG/gHZqf7n0K9cuA+JWy0gI6/w2LqQwv8zHiyEGjlTYGF0o/5p93bmKL1/2VDYP0pxJCkRdnuiOcsymPxhD1HLGzcIPg5iq7dD2/6Zbd17A/XzBjIXmmjzKG2KxyBmjnYTGwz5F7Sdm/s4CZK1JjJcW3SLBO9WneLDSfMZUAEeukk+jfW+8uFhHiv2lE1Xccn8Zn2cA/4DwUH2hlTafJ2W43yW1pMoUVhzHfwendvwu6s9Ge0VM0adNsJaINWiMUr+cVg/L+NS3NkxaHr2yfZrUpYw8ztKL9op9aTHjNC1QZdnjGeEqDsy61Yu8fVmxyyuarEj/6xaO95dJpS+B6CK7r X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: bc09662f-8f72-4cfa-73cd-08d95aa28fc1 X-MS-Exchange-CrossTenant-AuthSource: DM5PR1201MB0201.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Aug 2021 19:27:29.4486 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: r2Fhjr4+allgNt1ChR8hEjIP10umz8dpsHxPvnquXVEQ6P2WZs0mBi9f3Jux/FbK X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1434 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org When the 5-level page table CPU flag is exposed, KVM code needs to handle this case by pointing mmu->root_hpa to a properly-constructed 5-level page table. Suggested-by: Paolo Bonzini Signed-off-by: Wei Huang --- arch/x86/include/asm/kvm_host.h | 1 + arch/x86/kvm/mmu/mmu.c | 48 +++++++++++++++++++++------------ 2 files changed, 32 insertions(+), 17 deletions(-) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h index 6d16f75cc8da..5d66a94ca428 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -447,6 +447,7 @@ struct kvm_mmu { u64 *pae_root; u64 *pml4_root; + u64 *pml5_root; /* * check zero bits on shadow page table entries, these diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c index c11ee4531f6d..9985488c9524 100644 --- a/arch/x86/kvm/mmu/mmu.c +++ b/arch/x86/kvm/mmu/mmu.c @@ -3430,7 +3430,7 @@ static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu) * the shadow page table may be a PAE or a long mode page table. */ pm_mask = PT_PRESENT_MASK | shadow_me_mask; - if (mmu->shadow_root_level == PT64_ROOT_4LEVEL) { + if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL) { pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK; if (WARN_ON_ONCE(!mmu->pml4_root)) { @@ -3457,10 +3457,19 @@ static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu) mmu->pae_root[i] = root | pm_mask; } - if (mmu->shadow_root_level == PT64_ROOT_4LEVEL) + /* + * Depending on the shadow_root_level, build the root_hpa table by + * chaining either pml5->pml4->pae or pml4->pae. + */ + mmu->root_hpa = __pa(mmu->pae_root); + if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL) { + mmu->pml4_root[0] = mmu->root_hpa | pm_mask; mmu->root_hpa = __pa(mmu->pml4_root); - else - mmu->root_hpa = __pa(mmu->pae_root); + } + if (mmu->shadow_root_level == PT64_ROOT_5LEVEL) { + mmu->pml5_root[0] = mmu->root_hpa | pm_mask; + mmu->root_hpa = __pa(mmu->pml5_root); + } set_root_pgd: mmu->root_pgd = root_pgd; @@ -3473,7 +3482,7 @@ static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu) static int mmu_alloc_special_roots(struct kvm_vcpu *vcpu) { struct kvm_mmu *mmu = vcpu->arch.mmu; - u64 *pml4_root, *pae_root; + u64 *pml5_root, *pml4_root, *pae_root; /* * When shadowing 32-bit or PAE NPT with 64-bit NPT, the PML4 and PDP @@ -3485,21 +3494,15 @@ static int mmu_alloc_special_roots(struct kvm_vcpu *vcpu) mmu->shadow_root_level < PT64_ROOT_4LEVEL) return 0; - /* - * This mess only works with 4-level paging and needs to be updated to - * work with 5-level paging. - */ - if (WARN_ON_ONCE(mmu->shadow_root_level != PT64_ROOT_4LEVEL)) - return -EIO; - - if (mmu->pae_root && mmu->pml4_root) + if (mmu->pae_root && mmu->pml4_root && mmu->pml5_root) return 0; /* * The special roots should always be allocated in concert. Yell and * bail if KVM ends up in a state where only one of the roots is valid. */ - if (WARN_ON_ONCE(!tdp_enabled || mmu->pae_root || mmu->pml4_root)) + if (WARN_ON_ONCE(!tdp_enabled || mmu->pae_root || mmu->pml4_root || + mmu->pml5_root)) return -EIO; /* @@ -3511,15 +3514,25 @@ static int mmu_alloc_special_roots(struct kvm_vcpu *vcpu) return -ENOMEM; pml4_root = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT); - if (!pml4_root) { - free_page((unsigned long)pae_root); - return -ENOMEM; + if (!pml4_root) + goto err_pml4; + + if (mmu->shadow_root_level > PT64_ROOT_4LEVEL) { + pml5_root = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT); + if (!pml5_root) + goto err_pml5; } mmu->pae_root = pae_root; mmu->pml4_root = pml4_root; + mmu->pml5_root = pml5_root; return 0; +err_pml5: + free_page((unsigned long)pml4_root); +err_pml4: + free_page((unsigned long)pae_root); + return -ENOMEM; } void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu) @@ -5338,6 +5351,7 @@ static void free_mmu_pages(struct kvm_mmu *mmu) set_memory_encrypted((unsigned long)mmu->pae_root, 1); free_page((unsigned long)mmu->pae_root); free_page((unsigned long)mmu->pml4_root); + free_page((unsigned long)mmu->pml5_root); } static int __kvm_mmu_create(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu) From patchwork Sun Aug 8 19:26:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wei Huang X-Patchwork-Id: 12425093 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6A9C0C4338F for ; Sun, 8 Aug 2021 19:27:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4E38260EB5 for ; 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dmarc=none action=none header.from=amd.com; Received: from DM5PR1201MB0201.namprd12.prod.outlook.com (2603:10b6:4:5b::21) by DM5PR12MB1434.namprd12.prod.outlook.com (2603:10b6:3:77::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4394.17; Sun, 8 Aug 2021 19:27:41 +0000 Received: from DM5PR1201MB0201.namprd12.prod.outlook.com ([fe80::7410:8a22:1bdb:d24d]) by DM5PR1201MB0201.namprd12.prod.outlook.com ([fe80::7410:8a22:1bdb:d24d%6]) with mapi id 15.20.4394.022; Sun, 8 Aug 2021 19:27:41 +0000 From: Wei Huang To: kvm@vger.kernel.org Cc: linux-kernel@vger.kernel.org, pbonzini@redhat.com, seanjc@google.com, vkuznets@redhat.com, wanpengli@tencent.com, jmattson@google.com, joro@8bytes.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, x86@kernel.org, hpa@zytor.com Subject: [PATCH v2 3/3] KVM: SVM: Add 5-level page table support for SVM Date: Sun, 8 Aug 2021 14:26:58 -0500 Message-Id: <20210808192658.2923641-4-wei.huang2@amd.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210808192658.2923641-1-wei.huang2@amd.com> References: <20210808192658.2923641-1-wei.huang2@amd.com> X-ClientProxiedBy: SN6PR05CA0007.namprd05.prod.outlook.com (2603:10b6:805:de::20) To DM5PR1201MB0201.namprd12.prod.outlook.com (2603:10b6:4:5b::21) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from weiserver.amd.com (165.204.77.1) by SN6PR05CA0007.namprd05.prod.outlook.com (2603:10b6:805:de::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4415.4 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: fUvwuOUJIP2Px2itG6usAecDsyGGIgvGWxEhg3f1M2gau8KE7FQtPQVTZPfGLndKQjET55uR6kV/4+mf8QEQ84juLFdJVUfP8sGn7aSXn3Wa6ylecHLKq79vAcUsdJ+oPb/mkujgbUVaSlQDeqTzB3Z1UoPI3dNw3eC8UeUAR/3xBiPw0rYOs1WdomFL+M5wgVyqpYtZ3Nss/TQ7TRKfF1oGsN3gD2yHSyikzUoPAK9onMFGzeybZuo0nqxMExzZHPGk6q2eY9KLfAshAOem2EIBz01ogKBtD1teZ1+75wlV23sjUKYU8Q9vUXACaanJ0KAaR9QpTrqB1IdfHfNWvSZiHJF8Y9L1K7a13f5a+unoaqF1lkzRtC7a/q5bprcfWKztJmZIsRqz5DU9JzeIwcwvkUb4DI6V8q8WKd+/JmkGxI5J6xbOzdyHWeNv1az64DbP6ryFvE86nX19phibYiBNTH/8Bzc3oxbYgC3j1qXyrWvL9Ab3AtbFXVJU0jTZpO40wyHQO7er0ixxvsAmOyLFb+RIODhoXdI+urja/VF7g9MpVa4KcXPll9Qd2D2hAmbMqXwoUzqvr015SFnXEN4dtpGKEmIL+KbUj7+hBStrg0i/iL3DNpS02yNBqsuxntjU310LmKbXun59b2zUrfghhIXX88oqwVFu9yegLoSIC5flU53FmmeRP6Bxq4IbDcJ2ezHPmeemSsgrnwHjVxEzA4qMWSfsWe3qnPAoWn/zKD94V8FjY3GFHnEra6wZn/eEx5DIX94VujokevialYh04TIMFjGUnazNDkOecjguVaL9VqogHiGQmcjtWm/WeFXO0irhv8NgHtdseqqf06umjvdcprS2Ue7F50MIkVHzmOVjYIcDaFpLEBOpNn79lBdPG2XiThVBGvV1dYINMKiH3Ic5FWp0HzBoBvIFdWpawQY879PVPGvagBAjPy3v+XeTMDvbjHbUK37JaAwSovPyNRQWBagvs3VGPtjEkMFBmCjGbIPfnBvIGLEjX5Wa3sI4WIVb+8fe7KHVa7xZXKJd5jPC6ISvvFPyRrIGBU87gYKK+y4vsrmE0pgmhfNRpS4oXfNsV6VwNTv2l/Gj9qwMzTeynzKLLoTAKNeawksm29o+GZwPc4T0VvcOGAqjZMea211lHryvz+UwJIhic4AqDnVPqwkeJIqQhhR89iP0cHH6SoMufz69rES7M7SOfg+Hh7M7JoRqhW488yegt8+eGtw/f2f+XW54Wd4GueO8vlLKUOrW0OWcYTW90J33rwEBfaJQZHYuBf6+ut/GQVnzZAkkdUnuGbkbPChnpR9+QHWMmH+91JVC2QQPL44R X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 6ba058ba-d4fe-48cb-6969-08d95aa296e3 X-MS-Exchange-CrossTenant-AuthSource: DM5PR1201MB0201.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Aug 2021 19:27:41.3922 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: wkaTCujOfzZq454JrFI8U+YNsBTz9JKF8yzQyAk1IxBCHnkRGoToHJ1cjLcAAA9P X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1434 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org When the 5-level page table is enabled on host OS, the nested page table for guest VMs must use 5-level as well. Update get_npt_level() function to reflect this requirement. In the meanwhile, remove the code that prevents kvm-amd driver from being loaded when 5-level page table is detected. Signed-off-by: Wei Huang Signed-off-by: Paolo Bonzini --- arch/x86/kvm/svm/svm.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index f361d466e18e..dfb864f2674b 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -261,7 +261,9 @@ u32 svm_msrpm_offset(u32 msr) static int get_max_npt_level(void) { #ifdef CONFIG_X86_64 - return PT64_ROOT_4LEVEL; + bool la57 = (cr4_read_shadow() & X86_CR4_LA57) != 0; + + return la57 ? PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL; #else return PT32E_ROOT_LEVEL; #endif @@ -462,11 +464,6 @@ static int has_svm(void) return 0; } - if (pgtable_l5_enabled()) { - pr_info("KVM doesn't yet support 5-level paging on AMD SVM\n"); - return 0; - } - return 1; }