From patchwork Thu Dec 6 18:20:53 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krish Sadhukhan X-Patchwork-Id: 10716643 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 73F10109C for ; Thu, 6 Dec 2018 18:46:16 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 65CA62ECBF for ; Thu, 6 Dec 2018 18:46:16 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 59FE62ECD8; Thu, 6 Dec 2018 18:46:16 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D4EF32EE79 for ; Thu, 6 Dec 2018 18:46:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726137AbeLFSqO (ORCPT ); Thu, 6 Dec 2018 13:46:14 -0500 Received: from userp2130.oracle.com ([156.151.31.86]:53848 "EHLO userp2130.oracle.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726099AbeLFSqO (ORCPT ); Thu, 6 Dec 2018 13:46:14 -0500 Received: from pps.filterd (userp2130.oracle.com [127.0.0.1]) by userp2130.oracle.com (8.16.0.22/8.16.0.22) with SMTP id wB6IcwJe056220; Thu, 6 Dec 2018 18:46:08 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oracle.com; h=from : to : cc : subject : date : message-id : in-reply-to : references; s=corp-2018-07-02; bh=scC76Ol5xIpTdxOB2VpuzqDFpZQYIhBN0WXv4B4qpSg=; b=PYyYyA+yqq9VNAG4GQwGAoSI++IC7LHQQ/bgy5GoJKjxf99lWw8nGt150IeMFAwbi3Y2 /ZHK2sV5HGivADyW1w5CtVAlTcrSbf+0w0dBM6Z5GiPWxBoSAWZdbKnRVgGIOODJYHwR BSObx9lMdu/TGOXjv+AfjnwrIxL4LP+Kk/84hKcDWjT5Aourb4xJ5ODvpU6xEoPq5xsH Su8CYizugC5b2Z7X0o8AuV13fmmcOJd0pRDZBDXBLJOgqIailjCuz22ELjrAvK0tlL1k gsDkbGFmeeh3TwXOtT3T2PXVAa8dBPRAlQwfHupd+feiAiBlPCsOx+8FDeZHtslPaCaM 4A== Received: from userv0022.oracle.com (userv0022.oracle.com [156.151.31.74]) by userp2130.oracle.com with ESMTP id 2p3hqua0yf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 06 Dec 2018 18:46:07 +0000 Received: from aserv0122.oracle.com (aserv0122.oracle.com [141.146.126.236]) by userv0022.oracle.com (8.14.4/8.14.4) with ESMTP id wB6Ik7YY024991 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 6 Dec 2018 18:46:07 GMT Received: from abhmp0015.oracle.com (abhmp0015.oracle.com [141.146.116.21]) by aserv0122.oracle.com (8.14.4/8.14.4) with ESMTP id wB6Ik66s015079; Thu, 6 Dec 2018 18:46:07 GMT Received: from ban25x6uut29.us.oracle.com (/10.153.73.29) by default (Oracle Beehive Gateway v4.0) with ESMTP ; Thu, 06 Dec 2018 10:46:06 -0800 From: Krish Sadhukhan To: kvm@vger.kernel.org Cc: pbonzini@redhat.com, rkrcmar@redhat.com, jmattson@google.com Subject: [kvm-unit-test 1/3] KVM nVMX: test_vmcs_page_* functions need to accept alignment size as a parameter Date: Thu, 6 Dec 2018 13:20:53 -0500 Message-Id: <20181206182055.16927-2-krish.sadhukhan@oracle.com> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20181206182055.16927-1-krish.sadhukhan@oracle.com> References: <20181206182055.16927-1-krish.sadhukhan@oracle.com> X-Proofpoint-Virus-Version: vendor=nai engine=5900 definitions=9099 signatures=668679 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 suspectscore=1 malwarescore=0 phishscore=0 bulkscore=0 spamscore=0 mlxscore=0 mlxlogscore=646 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1812060156 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP .. because not all alignments fall on page size boundary. Signed-off-by: Krish Sadhukhan Reviewed-by: Mihai Carabas --- x86/vmx_tests.c | 44 ++++++++++++++++++++++++++------------------ 1 file changed, 26 insertions(+), 18 deletions(-) diff --git a/x86/vmx_tests.c b/x86/vmx_tests.c index b105b23..76bf1f4 100644 --- a/x86/vmx_tests.c +++ b/x86/vmx_tests.c @@ -3464,16 +3464,17 @@ static void test_vmcs_page_addr(const char *name, enum Encoding encoding, bool ignored, bool xfail_beyond_mapped_ram, - u64 addr) + u64 addr, + u64 align) { bool xfail = (xfail_beyond_mapped_ram && - addr > fwcfg_get_u64(FW_CFG_RAM_SIZE) - PAGE_SIZE && + addr > fwcfg_get_u64(FW_CFG_RAM_SIZE) - align && addr < (1ul << cpuid_maxphyaddr())); report_prefix_pushf("%s = %lx", name, addr); vmcs_write(encoding, addr); - test_vmx_controls(ignored || (IS_ALIGNED(addr, PAGE_SIZE) && + test_vmx_controls(ignored || (IS_ALIGNED(addr, align) && addr < (1ul << cpuid_maxphyaddr())), xfail); report_prefix_pop(); @@ -3486,25 +3487,30 @@ static void test_vmcs_page_addr(const char *name, static void test_vmcs_page_values(const char *name, enum Encoding encoding, bool ignored, - bool xfail_beyond_mapped_ram) + bool xfail_beyond_mapped_ram, + u64 align) { unsigned i; u64 orig_val = vmcs_read(encoding); for (i = 0; i < 64; i++) test_vmcs_page_addr(name, encoding, ignored, - xfail_beyond_mapped_ram, 1ul << i); + xfail_beyond_mapped_ram, 1ul << i, + align); test_vmcs_page_addr(name, encoding, ignored, - xfail_beyond_mapped_ram, PAGE_SIZE - 1); + xfail_beyond_mapped_ram, PAGE_SIZE - 1, + align); test_vmcs_page_addr(name, encoding, ignored, - xfail_beyond_mapped_ram, PAGE_SIZE); + xfail_beyond_mapped_ram, PAGE_SIZE, + align); test_vmcs_page_addr(name, encoding, ignored, xfail_beyond_mapped_ram, - (1ul << cpuid_maxphyaddr()) - PAGE_SIZE); + (1ul << cpuid_maxphyaddr()) - PAGE_SIZE, + align); test_vmcs_page_addr(name, encoding, ignored, xfail_beyond_mapped_ram, - -1ul); + -1ul, align); vmcs_write(encoding, orig_val); } @@ -3517,7 +3523,7 @@ static void test_vmcs_page_reference(u32 control_bit, enum Encoding field, const char *field_name, const char *control_name, bool xfail_beyond_mapped_ram, - bool control_primary) + bool control_primary, u64 align) { u32 primary = vmcs_read(CPU_EXEC_CTRL0); u32 secondary = vmcs_read(CPU_EXEC_CTRL1); @@ -3540,7 +3546,8 @@ static void test_vmcs_page_reference(u32 control_bit, enum Encoding field, vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); vmcs_write(CPU_EXEC_CTRL1, secondary | control_bit); } - test_vmcs_page_values(field_name, field, false, xfail_beyond_mapped_ram); + test_vmcs_page_values(field_name, field, false, + xfail_beyond_mapped_ram, align); report_prefix_pop(); report_prefix_pushf("%s disabled", control_name); @@ -3550,7 +3557,7 @@ static void test_vmcs_page_reference(u32 control_bit, enum Encoding field, vmcs_write(CPU_EXEC_CTRL0, primary & ~CPU_SECONDARY); vmcs_write(CPU_EXEC_CTRL1, secondary & ~control_bit); } - test_vmcs_page_values(field_name, field, true, false); + test_vmcs_page_values(field_name, field, true, false, align); report_prefix_pop(); vmcs_write(field, page_addr); @@ -3567,10 +3574,10 @@ static void test_io_bitmaps(void) { test_vmcs_page_reference(CPU_IO_BITMAP, IO_BITMAP_A, "I/O bitmap A", "Use I/O bitmaps", false, - true); + true, PAGE_SIZE); test_vmcs_page_reference(CPU_IO_BITMAP, IO_BITMAP_B, "I/O bitmap B", "Use I/O bitmaps", false, - true); + true, PAGE_SIZE); } /* @@ -3583,7 +3590,7 @@ static void test_msr_bitmap(void) { test_vmcs_page_reference(CPU_MSR_BITMAP, MSR_BITMAP, "MSR bitmap", "Use MSR bitmaps", false, - true); + true, PAGE_SIZE); } /* @@ -3598,7 +3605,7 @@ static void test_apic_virt_addr(void) { test_vmcs_page_reference(CPU_TPR_SHADOW, APIC_VIRT_ADDR, "virtual-APIC address", "Use TPR shadow", - true, true); + true, true, PAGE_SIZE); } /* @@ -3617,7 +3624,8 @@ static void test_apic_access_addr(void) test_vmcs_page_reference(CPU_VIRT_APIC_ACCESSES, APIC_ACCS_ADDR, "APIC-access address", - "virtualize APIC-accesses", false, false); + "virtualize APIC-accesses", false, false, + PAGE_SIZE); } static bool set_bit_pattern(u8 mask, u32 *secondary) @@ -4715,7 +4723,7 @@ static void test_pml(void) report_prefix_pop(); test_vmcs_page_reference(CPU_PML, PMLADDR, "PML address", - "PML", false, false); + "PML", false, false, PAGE_SIZE); vmcs_write(CPU_EXEC_CTRL0, primary_saved); vmcs_write(CPU_EXEC_CTRL1, secondary_saved); From patchwork Thu Dec 6 18:20:54 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krish Sadhukhan X-Patchwork-Id: 10716645 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E62711923 for ; Thu, 6 Dec 2018 18:46:16 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D7D3F2ECBF for ; Thu, 6 Dec 2018 18:46:16 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id CC2D42EE64; Thu, 6 Dec 2018 18:46:16 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 79C312ECBF for ; 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Thu, 06 Dec 2018 18:46:08 +0000 Received: from aserv0122.oracle.com (aserv0122.oracle.com [141.146.126.236]) by aserv0022.oracle.com (8.14.4/8.14.4) with ESMTP id wB6Ik7CR012524 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 6 Dec 2018 18:46:07 GMT Received: from abhmp0015.oracle.com (abhmp0015.oracle.com [141.146.116.21]) by aserv0122.oracle.com (8.14.4/8.14.4) with ESMTP id wB6Ik7NT015086; Thu, 6 Dec 2018 18:46:07 GMT Received: from ban25x6uut29.us.oracle.com (/10.153.73.29) by default (Oracle Beehive Gateway v4.0) with ESMTP ; Thu, 06 Dec 2018 10:46:07 -0800 From: Krish Sadhukhan To: kvm@vger.kernel.org Cc: pbonzini@redhat.com, rkrcmar@redhat.com, jmattson@google.com Subject: [kvm-unit-test 2/3] KVM nVMX: test_vmcs_page_values() needs to accept a bit range Date: Thu, 6 Dec 2018 13:20:54 -0500 Message-Id: <20181206182055.16927-3-krish.sadhukhan@oracle.com> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20181206182055.16927-1-krish.sadhukhan@oracle.com> References: <20181206182055.16927-1-krish.sadhukhan@oracle.com> X-Proofpoint-Virus-Version: vendor=nai engine=5900 definitions=9099 signatures=668679 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 suspectscore=1 malwarescore=0 phishscore=0 bulkscore=0 spamscore=0 mlxscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1812060156 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP ... because various addresses need to be tested for various bit ranges. Signed-off-by: Krish Sadhukhan Reviewed-by: Mihai Carabas --- x86/vmx_tests.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/x86/vmx_tests.c b/x86/vmx_tests.c index 76bf1f4..900dcf4 100644 --- a/x86/vmx_tests.c +++ b/x86/vmx_tests.c @@ -3488,12 +3488,12 @@ static void test_vmcs_page_values(const char *name, enum Encoding encoding, bool ignored, bool xfail_beyond_mapped_ram, - u64 align) + u64 align, u32 addr_start, u32 addr_end) { unsigned i; u64 orig_val = vmcs_read(encoding); - for (i = 0; i < 64; i++) + for (i = addr_start; i < addr_end; i++) test_vmcs_page_addr(name, encoding, ignored, xfail_beyond_mapped_ram, 1ul << i, align); @@ -3547,7 +3547,7 @@ static void test_vmcs_page_reference(u32 control_bit, enum Encoding field, vmcs_write(CPU_EXEC_CTRL1, secondary | control_bit); } test_vmcs_page_values(field_name, field, false, - xfail_beyond_mapped_ram, align); + xfail_beyond_mapped_ram, align, 0, 64); report_prefix_pop(); report_prefix_pushf("%s disabled", control_name); @@ -3557,7 +3557,8 @@ static void test_vmcs_page_reference(u32 control_bit, enum Encoding field, vmcs_write(CPU_EXEC_CTRL0, primary & ~CPU_SECONDARY); vmcs_write(CPU_EXEC_CTRL1, secondary & ~control_bit); } - test_vmcs_page_values(field_name, field, true, false, align); + test_vmcs_page_values(field_name, field, true, false, align, + 0, 64); report_prefix_pop(); vmcs_write(field, page_addr); @@ -3912,7 +3913,7 @@ static void test_posted_intr(void) test_pi_desc_addr(0xc000, true); test_vmcs_page_values("process-posted interrupts", - POSTED_INTR_DESC_ADDR, false, false); + POSTED_INTR_DESC_ADDR, false, false, PAGE_SIZE, 0, 64); vmcs_write(CPU_EXEC_CTRL0, saved_primary); vmcs_write(CPU_EXEC_CTRL1, saved_secondary); From patchwork Thu Dec 6 18:20:55 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Krish Sadhukhan X-Patchwork-Id: 10716647 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3E04613BB for ; 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Thu, 06 Dec 2018 18:46:13 +0000 Received: from aserv0121.oracle.com (aserv0121.oracle.com [141.146.126.235]) by aserv0022.oracle.com (8.14.4/8.14.4) with ESMTP id wB6Ik8Km012547 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 6 Dec 2018 18:46:08 GMT Received: from abhmp0015.oracle.com (abhmp0015.oracle.com [141.146.116.21]) by aserv0121.oracle.com (8.14.4/8.13.8) with ESMTP id wB6Ik8T9014385; Thu, 6 Dec 2018 18:46:08 GMT Received: from ban25x6uut29.us.oracle.com (/10.153.73.29) by default (Oracle Beehive Gateway v4.0) with ESMTP ; Thu, 06 Dec 2018 10:46:07 -0800 From: Krish Sadhukhan To: kvm@vger.kernel.org Cc: pbonzini@redhat.com, rkrcmar@redhat.com, jmattson@google.com Subject: [kvm-unit-test 3/3] KVM nVMX: Check VM-exit MSR-store address on vmentry of L2 guests Date: Thu, 6 Dec 2018 13:20:55 -0500 Message-Id: <20181206182055.16927-4-krish.sadhukhan@oracle.com> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20181206182055.16927-1-krish.sadhukhan@oracle.com> References: <20181206182055.16927-1-krish.sadhukhan@oracle.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=nai engine=5900 definitions=9099 signatures=668679 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 suspectscore=1 malwarescore=0 phishscore=0 bulkscore=0 spamscore=0 mlxscore=0 mlxlogscore=790 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1812060156 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP According to section "Checks on VMX Controls" in Intel SDM vol 3C, the following checks performed for the VM-exit MSR-store address if the the VM-exit MSR-store count field is non-zero: - The lower 4 bits of the VM-exit MSR-store address must be 0. The address should not set any bits beyond the processor’s physical-address width. - The address of the last byte in the VM-exit MSR-store area should not set any bits beyond the processor’s physical-address width. The address of this last byte is VM-exit MSR-store address + (MSR count * 16) - 1. (The arithmetic used for the computation uses more bits than the processor’s physical-address width.) If IA32_VMX_BASIC[48] is read as 1, neither address should set any bits in the range 63:32. Signed-off-by: Krish Sadhukhan Reviewed-by: Mihai Carabas --- x86/vmx_tests.c | 70 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/x86/vmx_tests.c b/x86/vmx_tests.c index 900dcf4..af856cf 100644 --- a/x86/vmx_tests.c +++ b/x86/vmx_tests.c @@ -4731,6 +4731,75 @@ static void test_pml(void) } /* + * The following checks are performed for the VM-exit MSR-store address if + * the VM-exit MSR-store count field is non-zero: + * + * - The lower 4 bits of the VM-exit MSR-store address must be 0. + * The address should not set any bits beyond the processor’s + * physical-address width. + * + * - The address of the last byte in the VM-exit MSR-store area + * should not set any bits beyond the processor’s physical-address + * width. The address of this last byte is VM-exit MSR-store address + * + (MSR count * 16) - 1. (The arithmetic used for the computation + * uses more bits than the processor’s physical-address width.) + * + * If IA32_VMX_BASIC[48] is read as 1, neither address should set any bits + * in the range 63:32. + * + * [Intel SDM] + */ +static void test_exit_msr_store(void) +{ + exit_msr_store = alloc_page(); + u64 tmp; + u32 exit_msr_st_cnt = 1; + int i; + bool ctrl = true; + u32 addr_len = 64; + + vmcs_write(EXI_MSR_ST_CNT, exit_msr_st_cnt); + + /* Check first 4 bits of VM-exit MSR-store address */ + for (i = 0; i < 4; i++) { + tmp = (u64)exit_msr_store | 1ull << i; + vmcs_write(EXIT_MSR_ST_ADDR, tmp); + report_prefix_pushf("VM-exit MSR-store addr [4:0] %lx", + tmp & 0xf); + if (i && ctrl == true) { + ctrl = false; + } + test_vmx_controls(false, false); + report_prefix_pop(); + } + + if (basic.val & (1ul << 48)) + addr_len = 32; + + test_vmcs_page_values("VM-exit-MSR-store address", + EXIT_MSR_ST_ADDR, false, false, 16, + 4, addr_len - 1); + + /* Check last byte of VM-exit MSR-store address */ + for (i = (addr_len == 64 ? cpuid_maxphyaddr() : addr_len); i < 64; i++) { + exit_msr_store = (struct vmx_msr_entry *) + (((u64)exit_msr_store + (exit_msr_st_cnt * 16) - 1) | + 1ul << i); + + vmcs_write(EXIT_MSR_ST_ADDR, (u64)exit_msr_store); + test_vmx_controls(false, false); + } +} + +/* + * Tests for VMX exit controls + */ +static void test_exit_ctls(void) +{ + test_exit_msr_store(); +} + +/* * Check that the virtual CPU checks all of the VMX controls as * documented in the Intel SDM. */ @@ -4756,6 +4825,7 @@ static void vmx_controls_test(void) test_invalid_event_injection(); test_vpid(); test_eptp(); + test_exit_ctls(); } static bool valid_vmcs_for_vmentry(void)