From patchwork Thu Aug 12 08:58:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dawei Chien X-Patchwork-Id: 12432999 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 08E99C19F3C for ; Thu, 12 Aug 2021 09:00:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DB8BD6108C for ; Thu, 12 Aug 2021 09:00:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235750AbhHLJBA (ORCPT ); Thu, 12 Aug 2021 05:01:00 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:59856 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S235577AbhHLJA5 (ORCPT ); Thu, 12 Aug 2021 05:00:57 -0400 X-UUID: c8b14e9f0d6c457ba17493273c6f2265-20210812 X-UUID: c8b14e9f0d6c457ba17493273c6f2265-20210812 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 489903549; Thu, 12 Aug 2021 17:00:22 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs02n1.mediatek.inc (172.21.101.77) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 12 Aug 2021 17:00:20 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 12 Aug 2021 17:00:21 +0800 From: Dawei Chien To: Georgi Djakov , Rob Herring , Matthias Brugger , Stephen Boyd , Ryan Case CC: Mark Rutland , Nicolas Boichat , , , , , , Fan Chen , Arvin Wang , James Liao , Dawei Chien , Henry Chen Subject: [V11,PATCH 01/19] dt-bindings: soc: Add dvfsrc driver bindings Date: Thu, 12 Aug 2021 16:58:28 +0800 Message-ID: <20210812085846.2628-2-dawei.chien@mediatek.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20210812085846.2628-1-dawei.chien@mediatek.com> References: <20210812085846.2628-1-dawei.chien@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Henry Chen Document the binding for enabling dvfsrc on MediaTek SoC. Signed-off-by: Henry Chen Reviewed-by: Rob Herring --- .../devicetree/bindings/soc/mediatek/dvfsrc.yaml | 67 ++++++++++++++++++++++ include/dt-bindings/interconnect/mtk,mt8183-emi.h | 21 +++++++ 2 files changed, 88 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/mediatek/dvfsrc.yaml create mode 100644 include/dt-bindings/interconnect/mtk,mt8183-emi.h diff --git a/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.yaml b/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.yaml new file mode 100644 index 000000000000..f2b67b99921b --- /dev/null +++ b/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/soc/mediatek/dvfsrc.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: MediaTek dynamic voltage and frequency scaling resource collector (DVFSRC) + +description: | + The Dynamic Voltage and Frequency Scaling Resource Collector (DVFSRC) is a + HW module which is used to collect all the requests from both software and + hardware and turn into the decision of minimum operating voltage and minimum + DRAM frequency to fulfill those requests. + +maintainers: + - henryc.chen + +properties: + reg: + maxItems: 1 + description: DVFSRC common register address and length. + + compatible: + enum: + - mediatek,mt6873-dvfsrc + - mediatek,mt8183-dvfsrc + - mediatek,mt8192-dvfsrc + + '#interconnect-cells': + const: 1 + + dvfsrc-vcore: + type: object + description: + The DVFSRC regulator is modelled as a subdevice of the DVFSRC. + Because DVFSRC can request power directly via register read/write, likes + vcore which is a core power of mt8183. As such, the DVFSRC regulator + requires that DVFSRC nodes be present. + $ref: /schemas/regulator/regulator.yaml# + +required: + - compatible + - reg + - "#interconnect-cells" + +additionalProperties: false + +examples: + - | + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + dvfsrc@10012000 { + compatible = "mediatek,mt8183-dvfsrc"; + reg = <0 0x10012000 0 0x1000>; + #interconnect-cells = <1>; + dvfsrc_vcore: dvfsrc-vcore { + regulator-name = "dvfsrc-vcore"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <800000>; + regulator-always-on; + }; + }; + }; diff --git a/include/dt-bindings/interconnect/mtk,mt8183-emi.h b/include/dt-bindings/interconnect/mtk,mt8183-emi.h new file mode 100644 index 000000000000..dfd143f87885 --- /dev/null +++ b/include/dt-bindings/interconnect/mtk,mt8183-emi.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (c) 2021 MediaTek Inc. + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_MTK_MT8183_EMI_H +#define __DT_BINDINGS_INTERCONNECT_MTK_MT8183_EMI_H + +#define MT8183_SLAVE_DDR_EMI 0 +#define MT8183_MASTER_MCUSYS 1 +#define MT8183_MASTER_GPU 2 +#define MT8183_MASTER_MMSYS 3 +#define MT8183_MASTER_MM_VPU 4 +#define MT8183_MASTER_MM_DISP 5 +#define MT8183_MASTER_MM_VDEC 6 +#define MT8183_MASTER_MM_VENC 7 +#define MT8183_MASTER_MM_CAM 8 +#define MT8183_MASTER_MM_IMG 9 +#define MT8183_MASTER_MM_MDP 10 + +#endif From patchwork Thu Aug 12 08:58:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dawei Chien X-Patchwork-Id: 12432963 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3CD39C4320A for ; Thu, 12 Aug 2021 09:00:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1CF666103A for ; Thu, 12 Aug 2021 09:00:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235603AbhHLJAt (ORCPT ); Thu, 12 Aug 2021 05:00:49 -0400 Received: from mailgw01.mediatek.com ([60.244.123.138]:37280 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S235447AbhHLJAt (ORCPT ); Thu, 12 Aug 2021 05:00:49 -0400 X-UUID: 2328df363348403a9c2e7321a40d8671-20210812 X-UUID: 2328df363348403a9c2e7321a40d8671-20210812 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 79671751; Thu, 12 Aug 2021 17:00:22 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 12 Aug 2021 17:00:21 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 12 Aug 2021 17:00:21 +0800 From: Dawei Chien To: Georgi Djakov , Rob Herring , Matthias Brugger , Stephen Boyd , Ryan Case CC: Mark Rutland , Nicolas Boichat , , , , , , Fan Chen , Arvin Wang , James Liao , Dawei Chien Subject: [V11,PATCH 02/19] dt-bindings: mediatek: add compatible for MT8195 dvfsrc Date: Thu, 12 Aug 2021 16:58:29 +0800 Message-ID: <20210812085846.2628-3-dawei.chien@mediatek.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20210812085846.2628-1-dawei.chien@mediatek.com> References: <20210812085846.2628-1-dawei.chien@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org This adds dt-binding documentation of dvfsrc for Mediatek MT8195 SoCs Platform. Signed-off-by: Dawei Chien Acked-by: Rob Herring --- Documentation/devicetree/bindings/soc/mediatek/dvfsrc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.yaml b/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.yaml index f2b67b99921b..ec3feaf1ef73 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.yaml +++ b/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.yaml @@ -25,6 +25,7 @@ properties: - mediatek,mt6873-dvfsrc - mediatek,mt8183-dvfsrc - mediatek,mt8192-dvfsrc + - mediatek,mt8195-dvfsrc '#interconnect-cells': const: 1 From patchwork Thu Aug 12 08:58:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dawei Chien X-Patchwork-Id: 12432987 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 472E4C19F3F for ; Thu, 12 Aug 2021 09:00:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 26F24610FF for ; Thu, 12 Aug 2021 09:00:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235649AbhHLJAw (ORCPT ); Thu, 12 Aug 2021 05:00:52 -0400 Received: from mailgw01.mediatek.com ([60.244.123.138]:37316 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S235596AbhHLJAu (ORCPT ); Thu, 12 Aug 2021 05:00:50 -0400 X-UUID: 9e7560f14d404aac8b36472e444251c9-20210812 X-UUID: 9e7560f14d404aac8b36472e444251c9-20210812 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 19632994; Thu, 12 Aug 2021 17:00:22 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 12 Aug 2021 17:00:21 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 12 Aug 2021 17:00:21 +0800 From: Dawei Chien To: Georgi Djakov , Rob Herring , Matthias Brugger , Stephen Boyd , Ryan Case CC: Mark Rutland , Nicolas Boichat , , , , , , Fan Chen , Arvin Wang , James Liao , Dawei Chien , Henry Chen Subject: [V11,PATCH 03/19] soc: mediatek: add header for mediatek SIP interface Date: Thu, 12 Aug 2021 16:58:30 +0800 Message-ID: <20210812085846.2628-4-dawei.chien@mediatek.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20210812085846.2628-1-dawei.chien@mediatek.com> References: <20210812085846.2628-1-dawei.chien@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Henry Chen Add a header to collect SIPs and add one SIP call to initialize power management hardware for the SIP interface defined to access the SPM handling vcore voltage and ddr rate changes on mt8183 (and most likely later socs). Signed-off-by: Henry Chen Signed-off-by: Arvin Wang --- include/linux/soc/mediatek/mtk_sip_svc.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/linux/soc/mediatek/mtk_sip_svc.h b/include/linux/soc/mediatek/mtk_sip_svc.h index 082398e0cfb1..079bbcb361ba 100644 --- a/include/linux/soc/mediatek/mtk_sip_svc.h +++ b/include/linux/soc/mediatek/mtk_sip_svc.h @@ -22,4 +22,8 @@ ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, MTK_SIP_SMC_CONVENTION, \ ARM_SMCCC_OWNER_SIP, fn_id) +/* VCOREFS */ +#define MTK_SIP_VCOREFS_CONTROL \ + MTK_SIP_SMC_CMD(0x506) + #endif From patchwork Thu Aug 12 08:58:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dawei Chien X-Patchwork-Id: 12432965 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4A5FEC43214 for ; Thu, 12 Aug 2021 09:00:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2C4B56109F for ; Thu, 12 Aug 2021 09:00:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235630AbhHLJAv (ORCPT ); Thu, 12 Aug 2021 05:00:51 -0400 Received: from mailgw01.mediatek.com ([60.244.123.138]:37280 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S235600AbhHLJAu (ORCPT ); Thu, 12 Aug 2021 05:00:50 -0400 X-UUID: b8d7d5f616fb49448049c3747ff95b3c-20210812 X-UUID: b8d7d5f616fb49448049c3747ff95b3c-20210812 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 916630125; Thu, 12 Aug 2021 17:00:22 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 12 Aug 2021 17:00:21 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 12 Aug 2021 17:00:21 +0800 From: Dawei Chien To: Georgi Djakov , Rob Herring , Matthias Brugger , Stephen Boyd , Ryan Case CC: Mark Rutland , Nicolas Boichat , , , , , , Fan Chen , Arvin Wang , James Liao , Dawei Chien , Henry Chen Subject: [V11,PATCH 04/19] soc: mediatek: add driver for dvfsrc support Date: Thu, 12 Aug 2021 16:58:31 +0800 Message-ID: <20210812085846.2628-5-dawei.chien@mediatek.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20210812085846.2628-1-dawei.chien@mediatek.com> References: <20210812085846.2628-1-dawei.chien@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Henry Chen Add dvfsrc driver for MT6873/MT8183/MT8192 Signed-off-by: Henry Chen Signed-off-by: Dawei Chien --- drivers/soc/mediatek/Kconfig | 11 + drivers/soc/mediatek/Makefile | 1 + drivers/soc/mediatek/mtk-dvfsrc.c | 421 ++++++++++++++++++++++++++++++++ include/linux/soc/mediatek/mtk_dvfsrc.h | 35 +++ 4 files changed, 468 insertions(+) create mode 100644 drivers/soc/mediatek/mtk-dvfsrc.c create mode 100644 include/linux/soc/mediatek/mtk_dvfsrc.h diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig index fdd8bc08569e..2dcf02384639 100644 --- a/drivers/soc/mediatek/Kconfig +++ b/drivers/soc/mediatek/Kconfig @@ -26,6 +26,17 @@ config MTK_DEVAPC The violation information is logged for further analysis or countermeasures. +config MTK_DVFSRC + tristate "MediaTek DVFSRC Support" + depends on ARCH_MEDIATEK + help + Say yes here to add support for the MediaTek DVFSRC (dynamic voltage + and frequency scaling resource collector) found + on different MediaTek SoCs. The DVFSRC is a proprietary + hardware which is used to collect all the requests from + system and turn into the decision of minimum Vcore voltage + and minimum DRAM frequency to fulfill those requests. + config MTK_INFRACFG bool "MediaTek INFRACFG Support" select REGMAP diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile index 90270f8114ed..365d14fd7d49 100644 --- a/drivers/soc/mediatek/Makefile +++ b/drivers/soc/mediatek/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o obj-$(CONFIG_MTK_DEVAPC) += mtk-devapc.o +obj-$(CONFIG_MTK_DVFSRC) += mtk-dvfsrc.o obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o diff --git a/drivers/soc/mediatek/mtk-dvfsrc.c b/drivers/soc/mediatek/mtk-dvfsrc.c new file mode 100644 index 000000000000..6ef167cf55bd --- /dev/null +++ b/drivers/soc/mediatek/mtk-dvfsrc.c @@ -0,0 +1,421 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 MediaTek Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DVFSRC_IDLE 0x00 +#define DVFSRC_GET_TARGET_LEVEL(x) (((x) >> 0) & 0x0000ffff) +#define DVFSRC_GET_CURRENT_LEVEL(x) (((x) >> 16) & 0x0000ffff) +#define kbps_to_mbps(x) ((x) / 1000) + +#define POLL_TIMEOUT 1000 +#define STARTUP_TIME 1 + +#define MTK_SIP_DVFSRC_INIT 0x00 + +#define DVFSRC_OPP_DESC(_opp_table) \ +{ \ + .opps = _opp_table, \ + .num_opp = ARRAY_SIZE(_opp_table), \ +} + +struct dvfsrc_opp { + u32 vcore_opp; + u32 dram_opp; +}; + +struct dvfsrc_opp_desc { + const struct dvfsrc_opp *opps; + u32 num_opp; +}; + +struct mtk_dvfsrc; +struct dvfsrc_soc_data { + const int *regs; + const struct dvfsrc_opp_desc *opps_desc; + int (*get_target_level)(struct mtk_dvfsrc *dvfsrc); + int (*get_current_level)(struct mtk_dvfsrc *dvfsrc); + u32 (*get_vcore_level)(struct mtk_dvfsrc *dvfsrc); + u32 (*get_vcp_level)(struct mtk_dvfsrc *dvfsrc); + void (*set_dram_bw)(struct mtk_dvfsrc *dvfsrc, u64 bw); + void (*set_dram_peak_bw)(struct mtk_dvfsrc *dvfsrc, u64 bw); + void (*set_dram_hrtbw)(struct mtk_dvfsrc *dvfsrc, u64 bw); + void (*set_opp_level)(struct mtk_dvfsrc *dvfsrc, u32 level); + void (*set_vcore_level)(struct mtk_dvfsrc *dvfsrc, u32 level); + void (*set_vscp_level)(struct mtk_dvfsrc *dvfsrc, u32 level); + int (*wait_for_opp_level)(struct mtk_dvfsrc *dvfsrc, u32 level); + int (*wait_for_vcore_level)(struct mtk_dvfsrc *dvfsrc, u32 level); +}; + +struct mtk_dvfsrc { + struct device *dev; + struct platform_device *icc; + struct platform_device *regulator; + const struct dvfsrc_soc_data *dvd; + int dram_type; + const struct dvfsrc_opp_desc *curr_opps; + void __iomem *regs; + spinlock_t req_lock; + struct mutex pstate_lock; + struct notifier_block scpsys_notifier; +}; + +static u32 dvfsrc_read(struct mtk_dvfsrc *dvfs, u32 offset) +{ + return readl(dvfs->regs + dvfs->dvd->regs[offset]); +} + +static void dvfsrc_write(struct mtk_dvfsrc *dvfs, u32 offset, u32 val) +{ + writel(val, dvfs->regs + dvfs->dvd->regs[offset]); +} + +#define dvfsrc_rmw(dvfs, offset, val, mask, shift) \ + dvfsrc_write(dvfs, offset, \ + (dvfsrc_read(dvfs, offset) & ~(mask << shift)) | (val << shift)) + +enum dvfsrc_regs { + DVFSRC_SW_REQ, + DVFSRC_SW_REQ2, + DVFSRC_LEVEL, + DVFSRC_TARGET_LEVEL, + DVFSRC_SW_BW, + DVFSRC_SW_PEAK_BW, + DVFSRC_SW_HRT_BW, + DVFSRC_VCORE_REQUEST, +}; + +static const int mt8183_regs[] = { + [DVFSRC_SW_REQ] = 0x4, + [DVFSRC_SW_REQ2] = 0x8, + [DVFSRC_LEVEL] = 0xDC, + [DVFSRC_SW_BW] = 0x160, +}; + +static const struct dvfsrc_opp *get_current_opp(struct mtk_dvfsrc *dvfsrc) +{ + int level; + + level = dvfsrc->dvd->get_current_level(dvfsrc); + return &dvfsrc->curr_opps->opps[level]; +} + +static int dvfsrc_is_idle(struct mtk_dvfsrc *dvfsrc) +{ + if (!dvfsrc->dvd->get_target_level) + return true; + + return dvfsrc->dvd->get_target_level(dvfsrc); +} + +static int dvfsrc_wait_for_vcore_level(struct mtk_dvfsrc *dvfsrc, u32 level) +{ + const struct dvfsrc_opp *curr; + + return readx_poll_timeout_atomic(get_current_opp, dvfsrc, curr, + curr->vcore_opp >= level, STARTUP_TIME, + POLL_TIMEOUT); +} + +static int mt8183_wait_for_opp_level(struct mtk_dvfsrc *dvfsrc, u32 level) +{ + const struct dvfsrc_opp *target, *curr; + int ret; + + target = &dvfsrc->curr_opps->opps[level]; + ret = readx_poll_timeout(get_current_opp, dvfsrc, curr, + curr->dram_opp >= target->dram_opp && + curr->vcore_opp >= target->vcore_opp, + STARTUP_TIME, POLL_TIMEOUT); + if (ret < 0) { + dev_warn(dvfsrc->dev, + "timeout, target: %u, dram: %d, vcore: %d\n", level, + curr->dram_opp, curr->vcore_opp); + return ret; + } + + return 0; +} + +static int mt8183_get_target_level(struct mtk_dvfsrc *dvfsrc) +{ + return DVFSRC_GET_TARGET_LEVEL(dvfsrc_read(dvfsrc, DVFSRC_LEVEL)); +} + +static int mt8183_get_current_level(struct mtk_dvfsrc *dvfsrc) +{ + int level; + + /* HW level 0 is begin from 0x10000 */ + level = DVFSRC_GET_CURRENT_LEVEL(dvfsrc_read(dvfsrc, DVFSRC_LEVEL)); + /* Array index start from 0 */ + return ffs(level) - 1; +} + +static u32 mt8183_get_vcore_level(struct mtk_dvfsrc *dvfsrc) +{ + return (dvfsrc_read(dvfsrc, DVFSRC_SW_REQ2) >> 2) & 0x3; +} + +static void mt8183_set_dram_bw(struct mtk_dvfsrc *dvfsrc, u64 bw) +{ + dvfsrc_write(dvfsrc, DVFSRC_SW_BW, div_u64(kbps_to_mbps(bw), 100)); +} + +static void mt8183_set_opp_level(struct mtk_dvfsrc *dvfsrc, u32 level) +{ + int vcore_opp, dram_opp; + const struct dvfsrc_opp *opp; + + /* translate pstate to dvfsrc level, and set it to DVFSRC HW */ + opp = &dvfsrc->curr_opps->opps[level]; + vcore_opp = opp->vcore_opp; + dram_opp = opp->dram_opp; + + dev_dbg(dvfsrc->dev, "vcore_opp: %d, dram_opp: %d\n", + vcore_opp, dram_opp); + dvfsrc_write(dvfsrc, DVFSRC_SW_REQ, dram_opp | vcore_opp << 2); +} + +static void mt8183_set_vcore_level(struct mtk_dvfsrc *dvfsrc, u32 level) +{ + dvfsrc_write(dvfsrc, DVFSRC_SW_REQ2, level << 2); +} + +void mtk_dvfsrc_send_request(const struct device *dev, u32 cmd, u64 data) +{ + int ret, state; + struct mtk_dvfsrc *dvfsrc = dev_get_drvdata(dev); + + dev_dbg(dvfsrc->dev, "cmd: %d, data: %llu\n", cmd, data); + + switch (cmd) { + case MTK_DVFSRC_CMD_BW_REQUEST: + dvfsrc->dvd->set_dram_bw(dvfsrc, data); + return; + case MTK_DVFSRC_CMD_PEAK_BW_REQUEST: + if (dvfsrc->dvd->set_dram_peak_bw) + dvfsrc->dvd->set_dram_peak_bw(dvfsrc, data); + return; + case MTK_DVFSRC_CMD_OPP_REQUEST: + if (dvfsrc->dvd->set_opp_level) + dvfsrc->dvd->set_opp_level(dvfsrc, data); + break; + case MTK_DVFSRC_CMD_VCORE_REQUEST: + dvfsrc->dvd->set_vcore_level(dvfsrc, data); + break; + case MTK_DVFSRC_CMD_HRTBW_REQUEST: + if (dvfsrc->dvd->set_dram_hrtbw) + dvfsrc->dvd->set_dram_hrtbw(dvfsrc, data); + else + return; + break; + case MTK_DVFSRC_CMD_VSCP_REQUEST: + dvfsrc->dvd->set_vscp_level(dvfsrc, data); + break; + default: + dev_err(dvfsrc->dev, "unknown command: %d\n", cmd); + return; + } + + /* DVFSRC needs to wait at least 2T(~196ns) to handle request + * after receiving command + */ + udelay(STARTUP_TIME); + + ret = readx_poll_timeout(dvfsrc_is_idle, dvfsrc, + state, state == DVFSRC_IDLE, + STARTUP_TIME, POLL_TIMEOUT); + + if (ret < 0) { + dev_warn(dvfsrc->dev, + "%d: idle timeout, data: %llu, last: %d -> %d\n", + cmd, data, + dvfsrc->dvd->get_current_level(dvfsrc), + dvfsrc->dvd->get_target_level(dvfsrc)); + return; + } + + /* The previous change may be requested by previous request. + * So we delay 1us, then start checking opp is reached enough. + */ + udelay(STARTUP_TIME); + + if (cmd == MTK_DVFSRC_CMD_OPP_REQUEST) + ret = dvfsrc->dvd->wait_for_opp_level(dvfsrc, data); + else + ret = dvfsrc->dvd->wait_for_vcore_level(dvfsrc, data); + + if (ret < 0) { + dev_warn(dvfsrc->dev, + "%d: wait timeout, data: %llu, last: %d -> %d\n", + cmd, data, + dvfsrc->dvd->get_current_level(dvfsrc), + dvfsrc->dvd->get_target_level(dvfsrc)); + } + +} +EXPORT_SYMBOL(mtk_dvfsrc_send_request); + +int mtk_dvfsrc_query_info(const struct device *dev, u32 cmd, int *data) +{ + struct mtk_dvfsrc *dvfsrc = dev_get_drvdata(dev); + + switch (cmd) { + case MTK_DVFSRC_CMD_VCORE_LEVEL_QUERY: + *data = dvfsrc->dvd->get_vcore_level(dvfsrc); + break; + case MTK_DVFSRC_CMD_VSCP_LEVEL_QUERY: + *data = dvfsrc->dvd->get_vcp_level(dvfsrc); + break; + default: + return -EINVAL; + } + + return 0; +} +EXPORT_SYMBOL(mtk_dvfsrc_query_info); + +static int mtk_dvfsrc_probe(struct platform_device *pdev) +{ + struct arm_smccc_res ares; + struct resource *res; + struct mtk_dvfsrc *dvfsrc; + int ret; + + dvfsrc = devm_kzalloc(&pdev->dev, sizeof(*dvfsrc), GFP_KERNEL); + if (!dvfsrc) + return -ENOMEM; + + dvfsrc->dvd = of_device_get_match_data(&pdev->dev); + dvfsrc->dev = &pdev->dev; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + dvfsrc->regs = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(dvfsrc->regs)) + return PTR_ERR(dvfsrc->regs); + + spin_lock_init(&dvfsrc->req_lock); + mutex_init(&dvfsrc->pstate_lock); + + arm_smccc_smc(MTK_SIP_VCOREFS_CONTROL, MTK_SIP_DVFSRC_INIT, 0, 0, 0, + 0, 0, 0, &ares); + + if (!ares.a0) { + dvfsrc->dram_type = ares.a1; + dev_info(dvfsrc->dev, "dram_type: %d\n", dvfsrc->dram_type); + } else { + dev_err(dvfsrc->dev, "init fails: %lu\n", ares.a0); + return ares.a0; + } + + dvfsrc->curr_opps = &dvfsrc->dvd->opps_desc[dvfsrc->dram_type]; + platform_set_drvdata(pdev, dvfsrc); + + dvfsrc->regulator = platform_device_register_data(dvfsrc->dev, + "mtk-dvfsrc-regulator", -1, NULL, 0); + if (IS_ERR(dvfsrc->regulator)) { + dev_err(dvfsrc->dev, "Failed create regulator device\n"); + ret = PTR_ERR(dvfsrc->regulator); + goto err; + } + + dvfsrc->icc = platform_device_register_data(dvfsrc->dev, + "mediatek-emi-icc", -1, NULL, 0); + if (IS_ERR(dvfsrc->icc)) { + dev_err(dvfsrc->dev, "Failed create icc device\n"); + ret = PTR_ERR(dvfsrc->icc); + goto unregister_regulator; + } + + ret = devm_of_platform_populate(&pdev->dev); + if (ret) + platform_device_unregister(dvfsrc->icc); + + return 0; + +unregister_regulator: + platform_device_unregister(dvfsrc->regulator); +err: + return ret; +} + +static const struct dvfsrc_opp dvfsrc_opp_mt8183_lp4[] = { + {0, 0}, {0, 1}, {0, 2}, {1, 2}, +}; + +static const struct dvfsrc_opp dvfsrc_opp_mt8183_lp3[] = { + {0, 0}, {0, 1}, {1, 1}, {1, 2}, +}; + +static const struct dvfsrc_opp_desc dvfsrc_opp_mt8183_desc[] = { + DVFSRC_OPP_DESC(dvfsrc_opp_mt8183_lp4), + DVFSRC_OPP_DESC(dvfsrc_opp_mt8183_lp3), + DVFSRC_OPP_DESC(dvfsrc_opp_mt8183_lp3), +}; + +static const struct dvfsrc_soc_data mt8183_data = { + .opps_desc = dvfsrc_opp_mt8183_desc, + .regs = mt8183_regs, + .get_target_level = mt8183_get_target_level, + .get_current_level = mt8183_get_current_level, + .get_vcore_level = mt8183_get_vcore_level, + .set_dram_bw = mt8183_set_dram_bw, + .set_opp_level = mt8183_set_opp_level, + .set_vcore_level = mt8183_set_vcore_level, + .wait_for_opp_level = mt8183_wait_for_opp_level, + .wait_for_vcore_level = dvfsrc_wait_for_vcore_level, +}; + +static int mtk_dvfsrc_remove(struct platform_device *pdev) +{ + struct mtk_dvfsrc *dvfsrc = platform_get_drvdata(pdev); + + platform_device_unregister(dvfsrc->regulator); + platform_device_unregister(dvfsrc->icc); + + return 0; +} + +static const struct of_device_id mtk_dvfsrc_of_match[] = { + { + .compatible = "mediatek,mt8183-dvfsrc", + .data = &mt8183_data, + }, { + /* sentinel */ + }, +}; + +static struct platform_driver mtk_dvfsrc_driver = { + .probe = mtk_dvfsrc_probe, + .remove = mtk_dvfsrc_remove, + .driver = { + .name = "mtk-dvfsrc", + .of_match_table = of_match_ptr(mtk_dvfsrc_of_match), + }, +}; + +static int __init mtk_dvfsrc_init(void) +{ + return platform_driver_register(&mtk_dvfsrc_driver); +} +subsys_initcall(mtk_dvfsrc_init); + +static void __exit mtk_dvfsrc_exit(void) +{ + platform_driver_unregister(&mtk_dvfsrc_driver); +} +module_exit(mtk_dvfsrc_exit); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("MTK DVFSRC driver"); diff --git a/include/linux/soc/mediatek/mtk_dvfsrc.h b/include/linux/soc/mediatek/mtk_dvfsrc.h new file mode 100644 index 000000000000..823eff9bb19f --- /dev/null +++ b/include/linux/soc/mediatek/mtk_dvfsrc.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (c) 2021 MediaTek Inc. + */ + +#ifndef __SOC_MTK_DVFSRC_H +#define __SOC_MTK_DVFSRC_H + +#define MTK_DVFSRC_CMD_BW_REQUEST 0 +#define MTK_DVFSRC_CMD_OPP_REQUEST 1 +#define MTK_DVFSRC_CMD_VCORE_REQUEST 2 +#define MTK_DVFSRC_CMD_HRTBW_REQUEST 3 +#define MTK_DVFSRC_CMD_VSCP_REQUEST 4 +#define MTK_DVFSRC_CMD_PEAK_BW_REQUEST 5 + +#define MTK_DVFSRC_CMD_VCORE_LEVEL_QUERY 0 +#define MTK_DVFSRC_CMD_VSCP_LEVEL_QUERY 1 + +#if IS_ENABLED(CONFIG_MTK_DVFSRC) +void mtk_dvfsrc_send_request(const struct device *dev, u32 cmd, u64 data); +int mtk_dvfsrc_query_info(const struct device *dev, u32 cmd, int *data); + +#else + +static inline void mtk_dvfsrc_send_request(const struct device *dev, u32 cmd, + u64 data) +{ return -ENODEV; } + +static inline int mtk_dvfsrc_query_info(const struct device *dev, u32 cmd, + int *data); +{ return -ENODEV; } + +#endif /* CONFIG_MTK_DVFSRC */ + +#endif From patchwork Thu Aug 12 08:58:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dawei Chien X-Patchwork-Id: 12432979 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8732DC43216 for ; Thu, 12 Aug 2021 09:00:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 67E29610A5 for ; Thu, 12 Aug 2021 09:00:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235734AbhHLJA6 (ORCPT ); Thu, 12 Aug 2021 05:00:58 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:59956 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S235707AbhHLJAz (ORCPT ); Thu, 12 Aug 2021 05:00:55 -0400 X-UUID: 71d9628a1355410e85c6fa583e12266c-20210812 X-UUID: 71d9628a1355410e85c6fa583e12266c-20210812 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1087340379; Thu, 12 Aug 2021 17:00:23 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 12 Aug 2021 17:00:21 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 12 Aug 2021 17:00:21 +0800 From: Dawei Chien To: Georgi Djakov , Rob Herring , Matthias Brugger , Stephen Boyd , Ryan Case CC: Mark Rutland , Nicolas Boichat , , , , , , Fan Chen , Arvin Wang , James Liao , Dawei Chien , Henry Chen Subject: [V11,PATCH 05/19] soc: mediatek: add support for mt6873 Date: Thu, 12 Aug 2021 16:58:32 +0800 Message-ID: <20210812085846.2628-6-dawei.chien@mediatek.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20210812085846.2628-1-dawei.chien@mediatek.com> References: <20210812085846.2628-1-dawei.chien@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Henry Chen add support for mt6873 Signed-off-by: Henry Chen --- drivers/soc/mediatek/mtk-dvfsrc.c | 114 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 114 insertions(+) diff --git a/drivers/soc/mediatek/mtk-dvfsrc.c b/drivers/soc/mediatek/mtk-dvfsrc.c index 6ef167cf55bd..1f053367eabe 100644 --- a/drivers/soc/mediatek/mtk-dvfsrc.c +++ b/drivers/soc/mediatek/mtk-dvfsrc.c @@ -102,6 +102,16 @@ static const int mt8183_regs[] = { [DVFSRC_SW_BW] = 0x160, }; +static const int mt6873_regs[] = { + [DVFSRC_SW_REQ] = 0xC, + [DVFSRC_LEVEL] = 0xD44, + [DVFSRC_SW_PEAK_BW] = 0x278, + [DVFSRC_SW_BW] = 0x26C, + [DVFSRC_SW_HRT_BW] = 0x290, + [DVFSRC_TARGET_LEVEL] = 0xD48, + [DVFSRC_VCORE_REQUEST] = 0x6C, +}; + static const struct dvfsrc_opp *get_current_opp(struct mtk_dvfsrc *dvfsrc) { int level; @@ -127,6 +137,78 @@ static int dvfsrc_wait_for_vcore_level(struct mtk_dvfsrc *dvfsrc, u32 level) POLL_TIMEOUT); } +static int mt6873_get_target_level(struct mtk_dvfsrc *dvfsrc) +{ + return dvfsrc_read(dvfsrc, DVFSRC_TARGET_LEVEL); +} + +static int mt6873_get_current_level(struct mtk_dvfsrc *dvfsrc) +{ + u32 curr_level; + + /* HW level 0 is begin from 0x1, and max opp is 0x1*/ + curr_level = ffs(dvfsrc_read(dvfsrc, DVFSRC_LEVEL)); + if (curr_level > dvfsrc->curr_opps->num_opp) + curr_level = 0; + else + curr_level = dvfsrc->curr_opps->num_opp - curr_level; + + return curr_level; +} + +static int mt6873_wait_for_opp_level(struct mtk_dvfsrc *dvfsrc, u32 level) +{ + const struct dvfsrc_opp *target, *curr; + + target = &dvfsrc->curr_opps->opps[level]; + return readx_poll_timeout_atomic(get_current_opp, dvfsrc, curr, + curr->dram_opp >= target->dram_opp, + STARTUP_TIME, POLL_TIMEOUT); +} + +static u32 mt6873_get_vcore_level(struct mtk_dvfsrc *dvfsrc) +{ + return (dvfsrc_read(dvfsrc, DVFSRC_SW_REQ) >> 4) & 0x7; +} + +static u32 mt6873_get_vcp_level(struct mtk_dvfsrc *dvfsrc) +{ + return (dvfsrc_read(dvfsrc, DVFSRC_VCORE_REQUEST) >> 12) & 0x7; +} + +static void mt6873_set_dram_bw(struct mtk_dvfsrc *dvfsrc, u64 bw) +{ + bw = div_u64(kbps_to_mbps(bw), 100); + bw = min_t(u64, bw, 0xFF); + dvfsrc_write(dvfsrc, DVFSRC_SW_BW, bw); +} + +static void mt6873_set_dram_peak_bw(struct mtk_dvfsrc *dvfsrc, u64 bw) +{ + bw = div_u64(kbps_to_mbps(bw), 100); + bw = min_t(u64, bw, 0xFF); + dvfsrc_write(dvfsrc, DVFSRC_SW_PEAK_BW, bw); +} + +static void mt6873_set_dram_hrtbw(struct mtk_dvfsrc *dvfsrc, u64 bw) +{ + bw = div_u64((kbps_to_mbps(bw) + 29), 30); + bw = min_t(u64, bw, 0x3FF); + dvfsrc_write(dvfsrc, DVFSRC_SW_HRT_BW, bw); +} + +static void mt6873_set_vcore_level(struct mtk_dvfsrc *dvfsrc, u32 level) +{ + spin_lock(&dvfsrc->req_lock); + dvfsrc_rmw(dvfsrc, DVFSRC_SW_REQ, level, 0x7, 4); + spin_unlock(&dvfsrc->req_lock); +} + +static void mt6873_set_vscp_level(struct mtk_dvfsrc *dvfsrc, u32 level) +{ + dvfsrc_rmw(dvfsrc, DVFSRC_VCORE_REQUEST, level, 0x7, 12); +} + static int mt8183_wait_for_opp_level(struct mtk_dvfsrc *dvfsrc, u32 level) { const struct dvfsrc_opp *target, *curr; @@ -377,6 +459,35 @@ static const struct dvfsrc_soc_data mt8183_data = { .wait_for_vcore_level = dvfsrc_wait_for_vcore_level, }; +static const struct dvfsrc_opp dvfsrc_opp_mt6873_lp4[] = { + {0, 0}, {1, 0}, {2, 0}, {3, 0}, + {0, 1}, {1, 1}, {2, 1}, {3, 1}, + {0, 2}, {1, 2}, {2, 2}, {3, 2}, + {1, 3}, {2, 3}, {3, 3}, {1, 4}, + {2, 4}, {3, 4}, {2, 5}, {3, 5}, + {3, 6}, +}; + +static const struct dvfsrc_opp_desc dvfsrc_opp_mt6873_desc[] = { + DVFSRC_OPP_DESC(dvfsrc_opp_mt6873_lp4), +}; + +static const struct dvfsrc_soc_data mt6873_data = { + .opps_desc = dvfsrc_opp_mt6873_desc, + .regs = mt6873_regs, + .get_target_level = mt6873_get_target_level, + .get_current_level = mt6873_get_current_level, + .get_vcore_level = mt6873_get_vcore_level, + .get_vcp_level = mt6873_get_vcp_level, + .set_dram_bw = mt6873_set_dram_bw, + .set_dram_peak_bw = mt6873_set_dram_peak_bw, + .set_dram_hrtbw = mt6873_set_dram_hrtbw, + .set_vcore_level = mt6873_set_vcore_level, + .set_vscp_level = mt6873_set_vscp_level, + .wait_for_opp_level = mt6873_wait_for_opp_level, + .wait_for_vcore_level = dvfsrc_wait_for_vcore_level, +}; + static int mtk_dvfsrc_remove(struct platform_device *pdev) { struct mtk_dvfsrc *dvfsrc = platform_get_drvdata(pdev); @@ -391,6 +502,9 @@ static const struct of_device_id mtk_dvfsrc_of_match[] = { { .compatible = "mediatek,mt8183-dvfsrc", .data = &mt8183_data, + }, { + .compatible = "mediatek,mt6873-dvfsrc", + .data = &mt6873_data, }, { /* sentinel */ }, From patchwork Thu Aug 12 08:58:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dawei Chien X-Patchwork-Id: 12432969 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CD081C04FE3 for ; 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Thu, 12 Aug 2021 17:00:22 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 12 Aug 2021 17:00:22 +0800 From: Dawei Chien To: Georgi Djakov , Rob Herring , Matthias Brugger , Stephen Boyd , Ryan Case CC: Mark Rutland , Nicolas Boichat , , , , , , Fan Chen , Arvin Wang , James Liao , Dawei Chien Subject: [V11,PATCH 06/19] soc: mediatek: add support for mt8195 Date: Thu, 12 Aug 2021 16:58:33 +0800 Message-ID: <20210812085846.2628-7-dawei.chien@mediatek.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20210812085846.2628-1-dawei.chien@mediatek.com> References: <20210812085846.2628-1-dawei.chien@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org add support for mt8195 Signed-off-by: Dawei Chien --- drivers/soc/mediatek/mtk-dvfsrc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/soc/mediatek/mtk-dvfsrc.c b/drivers/soc/mediatek/mtk-dvfsrc.c index 1f053367eabe..692846d8b233 100644 --- a/drivers/soc/mediatek/mtk-dvfsrc.c +++ b/drivers/soc/mediatek/mtk-dvfsrc.c @@ -505,6 +505,9 @@ static const struct of_device_id mtk_dvfsrc_of_match[] = { }, { .compatible = "mediatek,mt6873-dvfsrc", .data = &mt6873_data, + }, { + .compatible = "mediatek,mt8195-dvfsrc", + .data = &mt6873_data, }, { /* sentinel */ }, From patchwork Thu Aug 12 08:58:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dawei Chien X-Patchwork-Id: 12432985 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 40693C19F41 for ; Thu, 12 Aug 2021 09:00:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1D9806103A for ; Thu, 12 Aug 2021 09:00:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235811AbhHLJBE (ORCPT ); Thu, 12 Aug 2021 05:01:04 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:59886 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S235669AbhHLJAx (ORCPT ); Thu, 12 Aug 2021 05:00:53 -0400 X-UUID: 0014268683284210bb911c7b62a3af57-20210812 X-UUID: 0014268683284210bb911c7b62a3af57-20210812 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 2119477959; Thu, 12 Aug 2021 17:00:23 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 12 Aug 2021 17:00:22 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 12 Aug 2021 17:00:22 +0800 From: Dawei Chien To: Georgi Djakov , Rob Herring , Matthias Brugger , Stephen Boyd , Ryan Case CC: Mark Rutland , Nicolas Boichat , , , , , , Fan Chen , Arvin Wang , James Liao , Dawei Chien , Henry Chen Subject: [V11,PATCH 07/19] arm64: dts: mt8183: add dvfsrc related nodes Date: Thu, 12 Aug 2021 16:58:34 +0800 Message-ID: <20210812085846.2628-8-dawei.chien@mediatek.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20210812085846.2628-1-dawei.chien@mediatek.com> References: <20210812085846.2628-1-dawei.chien@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Henry Chen Enable dvfsrc on mt8183 platform. Signed-off-by: Henry Chen --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index f90df6439c08..7ad4cf646579 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -583,6 +583,11 @@ #clock-cells = <1>; }; + ddr_emi: dvfsrc@10012000 { + compatible = "mediatek,mt8183-dvfsrc"; + reg = <0 0x10012000 0 0x1000>; + }; + pwrap: pwrap@1000d000 { compatible = "mediatek,mt8183-pwrap"; reg = <0 0x1000d000 0 0x1000>; From patchwork Thu Aug 12 08:58:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dawei Chien X-Patchwork-Id: 12432975 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8C7B5C4338F for ; Thu, 12 Aug 2021 09:00:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7119C6109D for ; Thu, 12 Aug 2021 09:00:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235724AbhHLJA4 (ORCPT ); Thu, 12 Aug 2021 05:00:56 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:59814 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S235618AbhHLJAw (ORCPT ); Thu, 12 Aug 2021 05:00:52 -0400 X-UUID: f2b3055771334a0f84d6091939cf67f6-20210812 X-UUID: f2b3055771334a0f84d6091939cf67f6-20210812 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 124246465; Thu, 12 Aug 2021 17:00:22 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs02n1.mediatek.inc (172.21.101.77) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 12 Aug 2021 17:00:22 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 12 Aug 2021 17:00:22 +0800 From: Dawei Chien To: Georgi Djakov , Rob Herring , Matthias Brugger , Stephen Boyd , Ryan Case CC: Mark Rutland , Nicolas Boichat , , , , , , Fan Chen , Arvin Wang , James Liao , Dawei Chien , Henry Chen Subject: [V11,PATCH 08/19] arm64: dts: mt8192: add dvfsrc related nodes Date: Thu, 12 Aug 2021 16:58:35 +0800 Message-ID: <20210812085846.2628-9-dawei.chien@mediatek.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20210812085846.2628-1-dawei.chien@mediatek.com> References: <20210812085846.2628-1-dawei.chien@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Henry Chen Enable dvfsrc on mt8192 platform. Signed-off-by: Henry Chen Signed-off-by: Dawei Chien --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 9757138a8bbd..c70a3bf744fa 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -282,6 +282,12 @@ #interrupt-cells = <2>; }; + ddr_emi: dvfsrc@10012000 { + compatible = "mediatek,mt8192-dvfsrc", + "mediatek,mt6873-dvfsrc"; + reg = <0 0x10012000 0 0x1000>; + }; + systimer: timer@10017000 { compatible = "mediatek,mt8192-timer", "mediatek,mt6765-timer"; From patchwork Thu Aug 12 08:58:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dawei Chien X-Patchwork-Id: 12432977 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C957EC19F33 for ; Thu, 12 Aug 2021 09:00:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A4EC9610A4 for ; Thu, 12 Aug 2021 09:00:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235727AbhHLJA5 (ORCPT ); Thu, 12 Aug 2021 05:00:57 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:59814 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S235660AbhHLJAx (ORCPT ); Thu, 12 Aug 2021 05:00:53 -0400 X-UUID: 6d08e8e1e9a5451388c863166fb9e31e-20210812 X-UUID: 6d08e8e1e9a5451388c863166fb9e31e-20210812 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 523768297; Thu, 12 Aug 2021 17:00:23 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 12 Aug 2021 17:00:22 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 12 Aug 2021 17:00:22 +0800 From: Dawei Chien To: Georgi Djakov , Rob Herring , Matthias Brugger , Stephen Boyd , Ryan Case CC: Mark Rutland , Nicolas Boichat , , , , , , Fan Chen , Arvin Wang , James Liao , Dawei Chien Subject: [V11,PATCH 09/19] arm64: dts: mt8195: add dvfsrc related nodes Date: Thu, 12 Aug 2021 16:58:36 +0800 Message-ID: <20210812085846.2628-10-dawei.chien@mediatek.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20210812085846.2628-1-dawei.chien@mediatek.com> References: <20210812085846.2628-1-dawei.chien@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Enable dvfsrc on mt8195 platform. Signed-off-by: Dawei Chien --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index c146a91c6272..19430f324ee1 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -686,6 +686,11 @@ #clock-cells = <1>; }; + ddr_emi: dvfsrc@10012000 { + compatible = "mediatek,mt8195-dvfsrc"; + reg = <0 0x10012000 0 0x1000>; + }; + systimer: timer@10017000 { compatible = "mediatek,mt8195-timer", "mediatek,mt6765-timer"; reg = <0 0x10017000 0 0x1000>; From patchwork Thu Aug 12 08:58:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dawei Chien X-Patchwork-Id: 12433001 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 83404C41537 for ; Thu, 12 Aug 2021 09:00:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 63DEF6103A for ; Thu, 12 Aug 2021 09:00:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235746AbhHLJA7 (ORCPT ); Thu, 12 Aug 2021 05:00:59 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:59814 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S235683AbhHLJAy (ORCPT ); Thu, 12 Aug 2021 05:00:54 -0400 X-UUID: d08153c9055048598303121539400723-20210812 X-UUID: d08153c9055048598303121539400723-20210812 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1282640428; Thu, 12 Aug 2021 17:00:24 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs02n2.mediatek.inc (172.21.101.101) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 12 Aug 2021 17:00:22 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 12 Aug 2021 17:00:22 +0800 From: Dawei Chien To: Georgi Djakov , Rob Herring , Matthias Brugger , Stephen Boyd , Ryan Case CC: Mark Rutland , Nicolas Boichat , , , , , , Fan Chen , Arvin Wang , James Liao , Dawei Chien , Henry Chen Subject: [V11,PATCH 10/19] dt-bindings: interconnect: add MT6873 interconnect dt-bindings Date: Thu, 12 Aug 2021 16:58:37 +0800 Message-ID: <20210812085846.2628-11-dawei.chien@mediatek.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20210812085846.2628-1-dawei.chien@mediatek.com> References: <20210812085846.2628-1-dawei.chien@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Henry Chen Add interconnect provider dt-bindings for MT6873. Signed-off-by: Henry Chen Reviewed-by: Rob Herring --- include/dt-bindings/interconnect/mtk,mt6873-emi.h | 41 +++++++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 include/dt-bindings/interconnect/mtk,mt6873-emi.h diff --git a/include/dt-bindings/interconnect/mtk,mt6873-emi.h b/include/dt-bindings/interconnect/mtk,mt6873-emi.h new file mode 100644 index 000000000000..0b20011df010 --- /dev/null +++ b/include/dt-bindings/interconnect/mtk,mt6873-emi.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (c) 2021 MediaTek Inc. + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_MTK_MT6873_EMI_H +#define __DT_BINDINGS_INTERCONNECT_MTK_MT6873_EMI_H + +#define MT6873_SLAVE_DDR_EMI 0 +#define MT6873_MASTER_MCUSYS 1 +#define MT6873_MASTER_GPUSYS 2 +#define MT6873_MASTER_MMSYS 3 +#define MT6873_MASTER_MM_VPU 4 +#define MT6873_MASTER_MM_DISP 5 +#define MT6873_MASTER_MM_VDEC 6 +#define MT6873_MASTER_MM_VENC 7 +#define MT6873_MASTER_MM_CAM 8 +#define MT6873_MASTER_MM_IMG 9 +#define MT6873_MASTER_MM_MDP 10 +#define MT6873_MASTER_VPUSYS 11 +#define MT6873_MASTER_VPU_0 12 +#define MT6873_MASTER_VPU_1 13 +#define MT6873_MASTER_MDLASYS 14 +#define MT6873_MASTER_MDLA_0 15 +#define MT6873_MASTER_UFS 16 +#define MT6873_MASTER_PCIE 17 +#define MT6873_MASTER_USB 18 +#define MT6873_MASTER_DBGIF 19 +#define MT6873_SLAVE_HRT_DDR_EMI 20 +#define MT6873_MASTER_HRT_MMSYS 21 +#define MT6873_MASTER_HRT_MM_DISP 22 +#define MT6873_MASTER_HRT_MM_VDEC 23 +#define MT6873_MASTER_HRT_MM_VENC 24 +#define MT6873_MASTER_HRT_MM_CAM 25 +#define MT6873_MASTER_HRT_MM_IMG 26 +#define MT6873_MASTER_HRT_MM_MDP 27 +#define MT6873_MASTER_HRT_DBGIF 28 +#define MT6873_MASTER_WIFI 29 +#define MT6873_MASTER_BT 30 +#define MT6873_MASTER_NETSYS 31 +#endif From patchwork Thu Aug 12 08:58:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dawei Chien X-Patchwork-Id: 12432973 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9C7E3C43214 for ; Thu, 12 Aug 2021 09:00:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7D2AD6103A for ; Thu, 12 Aug 2021 09:00:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235700AbhHLJAy (ORCPT ); Thu, 12 Aug 2021 05:00:54 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:59856 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S235642AbhHLJAw (ORCPT ); Thu, 12 Aug 2021 05:00:52 -0400 X-UUID: 4f4b54ccfd684bd39521850dc22d145e-20210812 X-UUID: 4f4b54ccfd684bd39521850dc22d145e-20210812 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1248039440; Thu, 12 Aug 2021 17:00:23 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 12 Aug 2021 17:00:23 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 12 Aug 2021 17:00:23 +0800 From: Dawei Chien To: Georgi Djakov , Rob Herring , Matthias Brugger , Stephen Boyd , Ryan Case CC: Mark Rutland , Nicolas Boichat , , , , , , Fan Chen , Arvin Wang , James Liao , Dawei Chien Subject: [V11,PATCH 11/19] dt-bindings: interconnect: add MT8195 interconnect dt-bindings Date: Thu, 12 Aug 2021 16:58:38 +0800 Message-ID: <20210812085846.2628-12-dawei.chien@mediatek.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20210812085846.2628-1-dawei.chien@mediatek.com> References: <20210812085846.2628-1-dawei.chien@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add interconnect provider dt-bindings for MT8195 Signed-off-by: Dawei Chien Acked-by: Rob Herring Reviewed-by: AngeloGioacchino Del Regno --- include/dt-bindings/interconnect/mtk,mt8195-emi.h | 42 +++++++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 include/dt-bindings/interconnect/mtk,mt8195-emi.h diff --git a/include/dt-bindings/interconnect/mtk,mt8195-emi.h b/include/dt-bindings/interconnect/mtk,mt8195-emi.h new file mode 100644 index 000000000000..c7e8b805f8bd --- /dev/null +++ b/include/dt-bindings/interconnect/mtk,mt8195-emi.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2020 MediaTek Inc. + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_MTK_MT8195_EMI_H +#define __DT_BINDINGS_INTERCONNECT_MTK_MT8195_EMI_H + +#define MT8195_SLAVE_DDR_EMI 0 +#define MT8195_MASTER_MCUSYS 1 +#define MT8195_MASTER_GPUSYS 2 +#define MT8195_MASTER_MMSYS 3 +#define MT8195_MASTER_MM_VPU 4 +#define MT8195_MASTER_MM_DISP 5 +#define MT8195_MASTER_MM_VDEC 6 +#define MT8195_MASTER_MM_VENC 7 +#define MT8195_MASTER_MM_CAM 8 +#define MT8195_MASTER_MM_IMG 9 +#define MT8195_MASTER_MM_MDP 10 +#define MT8195_MASTER_VPUSYS 11 +#define MT8195_MASTER_VPU_0 12 +#define MT8195_MASTER_VPU_1 13 +#define MT8195_MASTER_MDLASYS 14 +#define MT8195_MASTER_MDLA_0 15 +#define MT8195_MASTER_UFS 16 +#define MT8195_MASTER_PCIE_0 17 +#define MT8195_MASTER_PCIE_1 18 +#define MT8195_MASTER_USB 19 +#define MT8195_MASTER_DBGIF 20 +#define MT8195_SLAVE_HRT_DDR_EMI 21 +#define MT8195_MASTER_HRT_MMSYS 22 +#define MT8195_MASTER_HRT_MM_DISP 23 +#define MT8195_MASTER_HRT_MM_VDEC 24 +#define MT8195_MASTER_HRT_MM_VENC 25 +#define MT8195_MASTER_HRT_MM_CAM 26 +#define MT8195_MASTER_HRT_MM_IMG 27 +#define MT8195_MASTER_HRT_MM_MDP 28 +#define MT8195_MASTER_HRT_DBGIF 29 +#define MT8195_MASTER_WIFI 30 +#define MT8195_MASTER_BT 31 +#define MT8195_MASTER_NETSYS 32 +#endif From patchwork Thu Aug 12 08:58:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dawei Chien X-Patchwork-Id: 12432995 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 388DDC19F3E for ; Thu, 12 Aug 2021 09:00:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 126EA610CF for ; Thu, 12 Aug 2021 09:00:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235779AbhHLJBC (ORCPT ); Thu, 12 Aug 2021 05:01:02 -0400 Received: from mailgw01.mediatek.com ([60.244.123.138]:37472 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S235667AbhHLJAx (ORCPT ); Thu, 12 Aug 2021 05:00:53 -0400 X-UUID: 4be9800d0f304232ba09e191a5831ef7-20210812 X-UUID: 4be9800d0f304232ba09e191a5831ef7-20210812 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1071554181; Thu, 12 Aug 2021 17:00:24 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 12 Aug 2021 17:00:23 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 12 Aug 2021 17:00:23 +0800 From: Dawei Chien To: Georgi Djakov , Rob Herring , Matthias Brugger , Stephen Boyd , Ryan Case CC: Mark Rutland , Nicolas Boichat , , , , , , Fan Chen , Arvin Wang , James Liao , Dawei Chien , Henry Chen Subject: [V11,PATCH 12/19] interconnect: mediatek: Add interconnect provider driver Date: Thu, 12 Aug 2021 16:58:39 +0800 Message-ID: <20210812085846.2628-13-dawei.chien@mediatek.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20210812085846.2628-1-dawei.chien@mediatek.com> References: <20210812085846.2628-1-dawei.chien@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Henry Chen Introduce Mediatek MT6873/MT8183/MT8192 specific provider driver using the interconnect framework. ICC provider ICC Nodes ---- ---- --------- |CPU | |--- |VPU | ----- | |----- ---- | ---- |DRAM |--|DRAM | ---- | ---- | |--|scheduler|----- |GPU | |--- |DISP| | |--|(EMI) | ---- | ---- | |--| | ----- | ---- ----- | |----- |MMSYS|--|--- |VDEC| --------- ----- | ---- /|\ | ---- |change DRAM freq |--- |VENC| ---------- | ---- | DVFSR | | | | | ---- ---------- |--- |IMG | | ---- | ---- |--- |CAM | ---- Signed-off-by: Henry Chen Reviewed-by: Georgi Djakov --- drivers/interconnect/Kconfig | 1 + drivers/interconnect/Makefile | 1 + drivers/interconnect/mediatek/Kconfig | 13 ++ drivers/interconnect/mediatek/Makefile | 3 + drivers/interconnect/mediatek/mtk-emi.c | 331 ++++++++++++++++++++++++++++++++ 5 files changed, 349 insertions(+) create mode 100644 drivers/interconnect/mediatek/Kconfig create mode 100644 drivers/interconnect/mediatek/Makefile create mode 100644 drivers/interconnect/mediatek/mtk-emi.c diff --git a/drivers/interconnect/Kconfig b/drivers/interconnect/Kconfig index d637a89d4695..da91f847aabd 100644 --- a/drivers/interconnect/Kconfig +++ b/drivers/interconnect/Kconfig @@ -12,6 +12,7 @@ menuconfig INTERCONNECT if INTERCONNECT source "drivers/interconnect/imx/Kconfig" +source "drivers/interconnect/mediatek/Kconfig" source "drivers/interconnect/qcom/Kconfig" source "drivers/interconnect/samsung/Kconfig" diff --git a/drivers/interconnect/Makefile b/drivers/interconnect/Makefile index 97d393fd638d..d697500d99f0 100644 --- a/drivers/interconnect/Makefile +++ b/drivers/interconnect/Makefile @@ -5,5 +5,6 @@ icc-core-objs := core.o bulk.o obj-$(CONFIG_INTERCONNECT) += icc-core.o obj-$(CONFIG_INTERCONNECT_IMX) += imx/ +obj-$(CONFIG_INTERCONNECT_MTK) += mediatek/ obj-$(CONFIG_INTERCONNECT_QCOM) += qcom/ obj-$(CONFIG_INTERCONNECT_SAMSUNG) += samsung/ diff --git a/drivers/interconnect/mediatek/Kconfig b/drivers/interconnect/mediatek/Kconfig new file mode 100644 index 000000000000..ec98d6a80f55 --- /dev/null +++ b/drivers/interconnect/mediatek/Kconfig @@ -0,0 +1,13 @@ +config INTERCONNECT_MTK + bool "Mediatek Network-on-Chip interconnect drivers" + depends on ARCH_MEDIATEK || COMPILE_TEST + help + Support for Mediatek's Network-on-Chip interconnect hardware. + +config INTERCONNECT_MTK_EMI + tristate "Mediatek EMI interconnect driver" + depends on INTERCONNECT_MTK + depends on (MTK_DVFSRC && OF) || COMPILE_TEST + help + This is a driver for the Mediatek Network-on-Chip on DVFSRC-based + platforms. diff --git a/drivers/interconnect/mediatek/Makefile b/drivers/interconnect/mediatek/Makefile new file mode 100644 index 000000000000..353842b2c273 --- /dev/null +++ b/drivers/interconnect/mediatek/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-$(CONFIG_INTERCONNECT_MTK_EMI) += mtk-emi.o \ No newline at end of file diff --git a/drivers/interconnect/mediatek/mtk-emi.c b/drivers/interconnect/mediatek/mtk-emi.c new file mode 100644 index 000000000000..8d650be62b90 --- /dev/null +++ b/drivers/interconnect/mediatek/mtk-emi.c @@ -0,0 +1,331 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +enum mtk_icc_name { + SLAVE_DDR_EMI, + MASTER_MCUSYS, + MASTER_GPUSYS, + MASTER_MMSYS, + MASTER_MM_VPU, + MASTER_MM_DISP, + MASTER_MM_VDEC, + MASTER_MM_VENC, + MASTER_MM_CAM, + MASTER_MM_IMG, + MASTER_MM_MDP, + MASTER_VPUSYS, + MASTER_VPU_PORT_0, + MASTER_VPU_PORT_1, + MASTER_MDLASYS, + MASTER_MDLA_PORT_0, + MASTER_UFS, + MASTER_PCIE, + MASTER_USB, + MASTER_WIFI, + MASTER_BT, + MASTER_NETSYS, + MASTER_DBGIF, + + SLAVE_HRT_DDR_EMI, + MASTER_HRT_MMSYS, + MASTER_HRT_MM_DISP, + MASTER_HRT_MM_VDEC, + MASTER_HRT_MM_VENC, + MASTER_HRT_MM_CAM, + MASTER_HRT_MM_IMG, + MASTER_HRT_MM_MDP, + MASTER_HRT_DBGIF, +}; + +#define MT8183_MAX_LINKS 1 + +/** + * struct mtk_icc_node - Mediatek specific interconnect nodes + * @name: the node name used in debugfs + * @ep : the type of this endpoint + * @id: a unique node identifier + * @links: an array of nodes where we can go next while traversing + * @num_links: the total number of @links + * @sum_avg: current sum aggregate value of all avg bw kBps requests + * @max_peak: current max aggregate value of all peak bw kBps requests + */ +struct mtk_icc_node { + unsigned char *name; + int ep; + u16 id; + u16 links[MT8183_MAX_LINKS]; + u16 num_links; + u64 sum_avg; + u64 max_peak; +}; + +struct mtk_icc_desc { + struct mtk_icc_node **nodes; + size_t num_nodes; +}; + +#define DEFINE_MNODE(_name, _id, _ep, ...) \ + static struct mtk_icc_node _name = { \ + .name = #_name, \ + .id = _id, \ + .ep = _ep, \ + .num_links = ARRAY_SIZE(((int[]){ __VA_ARGS__ })), \ + .links = { __VA_ARGS__ }, \ +} + +DEFINE_MNODE(ddr_emi, SLAVE_DDR_EMI, 1); +DEFINE_MNODE(mcusys, MASTER_MCUSYS, 0, SLAVE_DDR_EMI); +DEFINE_MNODE(gpu, MASTER_GPUSYS, 0, SLAVE_DDR_EMI); +DEFINE_MNODE(mmsys, MASTER_MMSYS, 0, SLAVE_DDR_EMI); +DEFINE_MNODE(mm_vpu, MASTER_MM_VPU, 0, MASTER_MMSYS); +DEFINE_MNODE(mm_disp, MASTER_MM_DISP, 0, MASTER_MMSYS); +DEFINE_MNODE(mm_vdec, MASTER_MM_VDEC, 0, MASTER_MMSYS); +DEFINE_MNODE(mm_venc, MASTER_MM_VENC, 0, MASTER_MMSYS); +DEFINE_MNODE(mm_cam, MASTER_MM_CAM, 0, MASTER_MMSYS); +DEFINE_MNODE(mm_img, MASTER_MM_IMG, 0, MASTER_MMSYS); +DEFINE_MNODE(mm_mdp, MASTER_MM_MDP, 0, MASTER_MMSYS); +DEFINE_MNODE(vpusys, MASTER_VPUSYS, 0, SLAVE_DDR_EMI); +DEFINE_MNODE(vpu_port_0, MASTER_VPU_PORT_0, 0, MASTER_VPUSYS); +DEFINE_MNODE(vpu_port_1, MASTER_VPU_PORT_1, 0, MASTER_VPUSYS); +DEFINE_MNODE(mdlasys, MASTER_MDLASYS, 0, SLAVE_DDR_EMI); +DEFINE_MNODE(mdla_port_0, MASTER_MDLA_PORT_0, 0, MASTER_MDLASYS); +DEFINE_MNODE(ufs, MASTER_UFS, 0, SLAVE_DDR_EMI); +DEFINE_MNODE(pcie, MASTER_PCIE, 0, SLAVE_DDR_EMI); +DEFINE_MNODE(usb, MASTER_USB, 0, SLAVE_DDR_EMI); +DEFINE_MNODE(wifi, MASTER_WIFI, 0, SLAVE_DDR_EMI); +DEFINE_MNODE(bt, MASTER_BT, 0, SLAVE_DDR_EMI); +DEFINE_MNODE(netsys, MASTER_NETSYS, 0, SLAVE_DDR_EMI); +DEFINE_MNODE(dbgif, MASTER_DBGIF, 0, SLAVE_DDR_EMI); + +DEFINE_MNODE(hrt_ddr_emi, SLAVE_HRT_DDR_EMI, 2); +DEFINE_MNODE(hrt_mmsys, MASTER_HRT_MMSYS, 0, SLAVE_HRT_DDR_EMI); +DEFINE_MNODE(hrt_mm_disp, MASTER_HRT_MM_DISP, 0, MASTER_HRT_MMSYS); +DEFINE_MNODE(hrt_mm_vdec, MASTER_HRT_MM_VDEC, 0, MASTER_HRT_MMSYS); +DEFINE_MNODE(hrt_mm_venc, MASTER_HRT_MM_VENC, 0, MASTER_HRT_MMSYS); +DEFINE_MNODE(hrt_mm_cam, MASTER_HRT_MM_CAM, 0, MASTER_HRT_MMSYS); +DEFINE_MNODE(hrt_mm_img, MASTER_HRT_MM_IMG, 0, MASTER_HRT_MMSYS); +DEFINE_MNODE(hrt_mm_mdp, MASTER_HRT_MM_MDP, 0, MASTER_HRT_MMSYS); +DEFINE_MNODE(hrt_dbgif, MASTER_HRT_DBGIF, 0, SLAVE_HRT_DDR_EMI); + +static struct mtk_icc_node *mt8183_icc_nodes[] = { + [MT8183_SLAVE_DDR_EMI] = &ddr_emi, + [MT8183_MASTER_MCUSYS] = &mcusys, + [MT8183_MASTER_GPU] = &gpu, + [MT8183_MASTER_MMSYS] = &mmsys, + [MT8183_MASTER_MM_VPU] = &mm_vpu, + [MT8183_MASTER_MM_DISP] = &mm_disp, + [MT8183_MASTER_MM_VDEC] = &mm_vdec, + [MT8183_MASTER_MM_VENC] = &mm_venc, + [MT8183_MASTER_MM_CAM] = &mm_cam, + [MT8183_MASTER_MM_IMG] = &mm_img, + [MT8183_MASTER_MM_MDP] = &mm_mdp, +}; + +static const struct mtk_icc_desc mt8183_icc = { + .nodes = mt8183_icc_nodes, + .num_nodes = ARRAY_SIZE(mt8183_icc_nodes), +}; + +static struct mtk_icc_node *mt6873_icc_nodes[] = { + [MT6873_SLAVE_DDR_EMI] = &ddr_emi, + [MT6873_MASTER_MCUSYS] = &mcusys, + [MT6873_MASTER_GPUSYS] = &gpu, + [MT6873_MASTER_MMSYS] = &mmsys, + [MT6873_MASTER_MM_VPU] = &mm_vpu, + [MT6873_MASTER_MM_DISP] = &mm_disp, + [MT6873_MASTER_MM_VDEC] = &mm_vdec, + [MT6873_MASTER_MM_VENC] = &mm_venc, + [MT6873_MASTER_MM_CAM] = &mm_cam, + [MT6873_MASTER_MM_IMG] = &mm_img, + [MT6873_MASTER_MM_MDP] = &mm_mdp, + [MT6873_MASTER_VPUSYS] = &vpusys, + [MT6873_MASTER_VPU_0] = &vpu_port_0, + [MT6873_MASTER_VPU_1] = &vpu_port_1, + [MT6873_MASTER_MDLASYS] = &mdlasys, + [MT6873_MASTER_MDLA_0] = &mdla_port_0, + [MT6873_MASTER_UFS] = &ufs, + [MT6873_MASTER_PCIE] = &pcie, + [MT6873_MASTER_USB] = &usb, + [MT6873_MASTER_WIFI] = &wifi, + [MT6873_MASTER_BT] = &bt, + [MT6873_MASTER_NETSYS] = &netsys, + [MT6873_MASTER_DBGIF] = &dbgif, + + [MT6873_SLAVE_HRT_DDR_EMI] = &hrt_ddr_emi, + [MT6873_MASTER_HRT_MMSYS] = &hrt_mmsys, + [MT6873_MASTER_HRT_MM_DISP] = &hrt_mm_disp, + [MT6873_MASTER_HRT_MM_VDEC] = &hrt_mm_vdec, + [MT6873_MASTER_HRT_MM_VENC] = &hrt_mm_venc, + [MT6873_MASTER_HRT_MM_CAM] = &hrt_mm_cam, + [MT6873_MASTER_HRT_MM_IMG] = &hrt_mm_img, + [MT6873_MASTER_HRT_MM_MDP] = &hrt_mm_mdp, + [MT6873_MASTER_HRT_DBGIF] = &hrt_dbgif, +}; + +static struct mtk_icc_desc mt6873_icc = { + .nodes = mt6873_icc_nodes, + .num_nodes = ARRAY_SIZE(mt6873_icc_nodes), +}; + +static const struct of_device_id emi_icc_of_match[] = { + { .compatible = "mediatek,mt8183-dvfsrc", .data = &mt8183_icc }, + { .compatible = "mediatek,mt8192-dvfsrc", .data = &mt6873_icc }, + { .compatible = "mediatek,mt6873-dvfsrc", .data = &mt6873_icc }, + { }, +}; +MODULE_DEVICE_TABLE(of, emi_icc_of_match); + +static int emi_icc_aggregate(struct icc_node *node, u32 tag, u32 avg_bw, + u32 peak_bw, u32 *agg_avg, u32 *agg_peak) +{ + struct mtk_icc_node *in; + + in = node->data; + + *agg_avg += avg_bw; + *agg_peak = max_t(u32, *agg_peak, peak_bw); + + in->sum_avg = *agg_avg; + in->max_peak = *agg_peak; + + return 0; +} + +static int emi_icc_set(struct icc_node *src, struct icc_node *dst) +{ + int ret = 0; + struct mtk_icc_node *node; + + node = dst->data; + + if (node->ep == 1) { + mtk_dvfsrc_send_request(src->provider->dev, + MTK_DVFSRC_CMD_PEAK_BW_REQUEST, + node->max_peak); + mtk_dvfsrc_send_request(src->provider->dev, + MTK_DVFSRC_CMD_BW_REQUEST, + node->sum_avg); + } else if (node->ep == 2) { + mtk_dvfsrc_send_request(src->provider->dev, + MTK_DVFSRC_CMD_HRTBW_REQUEST, + node->sum_avg); + } + + return ret; +} + +static int emi_icc_remove(struct platform_device *pdev); +static int emi_icc_probe(struct platform_device *pdev) +{ + const struct of_device_id *match; + const struct mtk_icc_desc *desc; + struct device *dev = &pdev->dev; + struct icc_node *node; + struct icc_onecell_data *data; + struct icc_provider *provider; + struct mtk_icc_node **mnodes; + size_t num_nodes, i, j; + int ret; + + match = of_match_node(emi_icc_of_match, dev->parent->of_node); + + if (!match) { + dev_err(dev, "invalid compatible string\n"); + return -ENODEV; + } + + desc = match->data; + mnodes = desc->nodes; + num_nodes = desc->num_nodes; + + provider = devm_kzalloc(dev, sizeof(*provider), GFP_KERNEL); + if (!provider) + return -ENOMEM; + + data = devm_kzalloc(dev, struct_size(data, nodes, num_nodes), + GFP_KERNEL); + if (!data) + return -ENOMEM; + + provider->dev = pdev->dev.parent; + provider->set = emi_icc_set; + provider->aggregate = emi_icc_aggregate; + provider->xlate = of_icc_xlate_onecell; + INIT_LIST_HEAD(&provider->nodes); + provider->data = data; + + ret = icc_provider_add(provider); + if (ret) { + dev_err(&pdev->dev, "error adding interconnect provider\n"); + return ret; + } + + for (i = 0; i < num_nodes; i++) { + node = icc_node_create(mnodes[i]->id); + if (IS_ERR(node)) { + ret = PTR_ERR(node); + goto err; + } + + node->name = mnodes[i]->name; + node->data = mnodes[i]; + icc_node_add(node, provider); + + for (j = 0; j < mnodes[i]->num_links; j++) + icc_link_create(node, mnodes[i]->links[j]); + + data->nodes[i] = node; + } + data->num_nodes = num_nodes; + + platform_set_drvdata(pdev, provider); + + return 0; +err: + icc_nodes_remove(provider); + icc_provider_del(provider); + return ret; +} + +static int emi_icc_remove(struct platform_device *pdev) +{ + struct icc_provider *provider = platform_get_drvdata(pdev); + + icc_nodes_remove(provider); + return icc_provider_del(provider); +} + +static struct platform_driver emi_icc_driver = { + .probe = emi_icc_probe, + .remove = emi_icc_remove, + .driver = { + .name = "mediatek-emi-icc", + }, +}; + +static int __init mtk_emi_icc_init(void) +{ + return platform_driver_register(&emi_icc_driver); +} +subsys_initcall(mtk_emi_icc_init); + +static void __exit mtk_emi_icc_exit(void) +{ + platform_driver_unregister(&emi_icc_driver); +} +module_exit(mtk_emi_icc_exit); + +MODULE_AUTHOR("Henry Chen "); +MODULE_LICENSE("GPL v2"); From patchwork Thu Aug 12 08:58:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dawei Chien X-Patchwork-Id: 12432997 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 47F5AC25AE7 for ; Thu, 12 Aug 2021 09:00:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2462A6103E for ; Thu, 12 Aug 2021 09:00:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235621AbhHLJBE (ORCPT ); Thu, 12 Aug 2021 05:01:04 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:59856 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S235673AbhHLJAx (ORCPT ); Thu, 12 Aug 2021 05:00:53 -0400 X-UUID: e64626d5736242249cb9de2e36a5cf71-20210812 X-UUID: e64626d5736242249cb9de2e36a5cf71-20210812 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 2095382644; Thu, 12 Aug 2021 17:00:23 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 12 Aug 2021 17:00:23 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 12 Aug 2021 17:00:23 +0800 From: Dawei Chien To: Georgi Djakov , Rob Herring , Matthias Brugger , Stephen Boyd , Ryan Case CC: Mark Rutland , Nicolas Boichat , , , , , , Fan Chen , Arvin Wang , James Liao , Dawei Chien Subject: [V11,PATCH 13/19] interconnect: mediatek: add support for mt8195 Date: Thu, 12 Aug 2021 16:58:40 +0800 Message-ID: <20210812085846.2628-14-dawei.chien@mediatek.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20210812085846.2628-1-dawei.chien@mediatek.com> References: <20210812085846.2628-1-dawei.chien@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org add platform data of mt8195 Signed-off-by: Dawei Chien Reviewed-by: AngeloGioachino Del Regno --- drivers/interconnect/mediatek/mtk-emi.c | 51 +++++++++++++++++++++++++++++++-- 1 file changed, 48 insertions(+), 3 deletions(-) diff --git a/drivers/interconnect/mediatek/mtk-emi.c b/drivers/interconnect/mediatek/mtk-emi.c index 8d650be62b90..379dab77ebfd 100644 --- a/drivers/interconnect/mediatek/mtk-emi.c +++ b/drivers/interconnect/mediatek/mtk-emi.c @@ -12,6 +12,7 @@ #include #include #include +#include enum mtk_icc_name { SLAVE_DDR_EMI, @@ -31,7 +32,8 @@ enum mtk_icc_name { MASTER_MDLASYS, MASTER_MDLA_PORT_0, MASTER_UFS, - MASTER_PCIE, + MASTER_PCIE_0, + MASTER_PCIE_1, MASTER_USB, MASTER_WIFI, MASTER_BT, @@ -102,7 +104,8 @@ DEFINE_MNODE(vpu_port_1, MASTER_VPU_PORT_1, 0, MASTER_VPUSYS); DEFINE_MNODE(mdlasys, MASTER_MDLASYS, 0, SLAVE_DDR_EMI); DEFINE_MNODE(mdla_port_0, MASTER_MDLA_PORT_0, 0, MASTER_MDLASYS); DEFINE_MNODE(ufs, MASTER_UFS, 0, SLAVE_DDR_EMI); -DEFINE_MNODE(pcie, MASTER_PCIE, 0, SLAVE_DDR_EMI); +DEFINE_MNODE(pcie_0, MASTER_PCIE_0, 0, SLAVE_DDR_EMI); +DEFINE_MNODE(pcie_1, MASTER_PCIE_1, 0, SLAVE_DDR_EMI); DEFINE_MNODE(usb, MASTER_USB, 0, SLAVE_DDR_EMI); DEFINE_MNODE(wifi, MASTER_WIFI, 0, SLAVE_DDR_EMI); DEFINE_MNODE(bt, MASTER_BT, 0, SLAVE_DDR_EMI); @@ -156,7 +159,7 @@ static struct mtk_icc_node *mt6873_icc_nodes[] = { [MT6873_MASTER_MDLASYS] = &mdlasys, [MT6873_MASTER_MDLA_0] = &mdla_port_0, [MT6873_MASTER_UFS] = &ufs, - [MT6873_MASTER_PCIE] = &pcie, + [MT6873_MASTER_PCIE] = &pcie_0, [MT6873_MASTER_USB] = &usb, [MT6873_MASTER_WIFI] = &wifi, [MT6873_MASTER_BT] = &bt, @@ -179,10 +182,52 @@ static struct mtk_icc_desc mt6873_icc = { .num_nodes = ARRAY_SIZE(mt6873_icc_nodes), }; +static struct mtk_icc_node *mt8195_icc_nodes[] = { + [MT8195_SLAVE_DDR_EMI] = &ddr_emi, + [MT8195_MASTER_MCUSYS] = &mcusys, + [MT8195_MASTER_GPUSYS] = &gpu, + [MT8195_MASTER_MMSYS] = &mmsys, + [MT8195_MASTER_MM_VPU] = &mm_vpu, + [MT8195_MASTER_MM_DISP] = &mm_disp, + [MT8195_MASTER_MM_VDEC] = &mm_vdec, + [MT8195_MASTER_MM_VENC] = &mm_venc, + [MT8195_MASTER_MM_CAM] = &mm_cam, + [MT8195_MASTER_MM_IMG] = &mm_img, + [MT8195_MASTER_MM_MDP] = &mm_mdp, + [MT8195_MASTER_VPUSYS] = &vpusys, + [MT8195_MASTER_VPU_0] = &vpu_port_0, + [MT8195_MASTER_VPU_1] = &vpu_port_1, + [MT8195_MASTER_MDLASYS] = &mdlasys, + [MT8195_MASTER_MDLA_0] = &mdla_port_0, + [MT8195_MASTER_UFS] = &ufs, + [MT8195_MASTER_PCIE_0] = &pcie_0, + [MT8195_MASTER_PCIE_1] = &pcie_1, + [MT8195_MASTER_USB] = &usb, + [MT8195_MASTER_WIFI] = &wifi, + [MT8195_MASTER_BT] = &bt, + [MT8195_MASTER_NETSYS] = &netsys, + [MT8195_MASTER_DBGIF] = &dbgif, + [MT8195_SLAVE_HRT_DDR_EMI] = &hrt_ddr_emi, + [MT8195_MASTER_HRT_MMSYS] = &hrt_mmsys, + [MT8195_MASTER_HRT_MM_DISP] = &hrt_mm_disp, + [MT8195_MASTER_HRT_MM_VDEC] = &hrt_mm_vdec, + [MT8195_MASTER_HRT_MM_VENC] = &hrt_mm_venc, + [MT8195_MASTER_HRT_MM_CAM] = &hrt_mm_cam, + [MT8195_MASTER_HRT_MM_IMG] = &hrt_mm_img, + [MT8195_MASTER_HRT_MM_MDP] = &hrt_mm_mdp, + [MT8195_MASTER_HRT_DBGIF] = &hrt_dbgif, +}; + +static struct mtk_icc_desc mt8195_icc = { + .nodes = mt8195_icc_nodes, + .num_nodes = ARRAY_SIZE(mt8195_icc_nodes), +}; + static const struct of_device_id emi_icc_of_match[] = { { .compatible = "mediatek,mt8183-dvfsrc", .data = &mt8183_icc }, { .compatible = "mediatek,mt8192-dvfsrc", .data = &mt6873_icc }, { .compatible = "mediatek,mt6873-dvfsrc", .data = &mt6873_icc }, + { .compatible = "mediatek,mt8195-dvfsrc", .data = &mt8195_icc }, { }, }; MODULE_DEVICE_TABLE(of, emi_icc_of_match); From patchwork Thu Aug 12 08:58:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dawei Chien X-Patchwork-Id: 12432971 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4AF8FC41537 for ; Thu, 12 Aug 2021 09:00:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 242AB610A5 for ; Thu, 12 Aug 2021 09:00:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235695AbhHLJAy (ORCPT ); Thu, 12 Aug 2021 05:00:54 -0400 Received: from mailgw01.mediatek.com ([60.244.123.138]:37410 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S235640AbhHLJAw (ORCPT ); Thu, 12 Aug 2021 05:00:52 -0400 X-UUID: fbd0b11f1bc74afb8c0d166959dae109-20210812 X-UUID: fbd0b11f1bc74afb8c0d166959dae109-20210812 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1784395742; Thu, 12 Aug 2021 17:00:24 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 12 Aug 2021 17:00:23 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 12 Aug 2021 17:00:23 +0800 From: Dawei Chien To: Georgi Djakov , Rob Herring , Matthias Brugger , Stephen Boyd , Ryan Case CC: Mark Rutland , Nicolas Boichat , , , , , , Fan Chen , Arvin Wang , James Liao , Dawei Chien Subject: [V11,PATCH 14/19] interconnect: mediatek: add initial bandwidth Date: Thu, 12 Aug 2021 16:58:41 +0800 Message-ID: <20210812085846.2628-15-dawei.chien@mediatek.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20210812085846.2628-1-dawei.chien@mediatek.com> References: <20210812085846.2628-1-dawei.chien@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org support get_bw function for suitable initial bandwidth Signed-off-by: Dawei Chien --- drivers/interconnect/mediatek/mtk-emi.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/interconnect/mediatek/mtk-emi.c b/drivers/interconnect/mediatek/mtk-emi.c index 379dab77ebfd..80e2707698be 100644 --- a/drivers/interconnect/mediatek/mtk-emi.c +++ b/drivers/interconnect/mediatek/mtk-emi.c @@ -271,6 +271,14 @@ static int emi_icc_set(struct icc_node *src, struct icc_node *dst) return ret; } +static int emi_icc_get_bw(struct icc_node *node, u32 *avg, u32 *peak) +{ + *avg = 0; + *peak = 0; + + return 0; +} + static int emi_icc_remove(struct platform_device *pdev); static int emi_icc_probe(struct platform_device *pdev) { @@ -308,6 +316,7 @@ static int emi_icc_probe(struct platform_device *pdev) provider->set = emi_icc_set; provider->aggregate = emi_icc_aggregate; provider->xlate = of_icc_xlate_onecell; + provider->get_bw = emi_icc_get_bw; INIT_LIST_HEAD(&provider->nodes); provider->data = data; From patchwork Thu Aug 12 08:58:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dawei Chien X-Patchwork-Id: 12432989 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EE9F4C19F39 for ; Thu, 12 Aug 2021 09:00:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C7A63610E9 for ; Thu, 12 Aug 2021 09:00:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235823AbhHLJBF (ORCPT ); Thu, 12 Aug 2021 05:01:05 -0400 Received: from mailgw01.mediatek.com ([60.244.123.138]:37280 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S235664AbhHLJAx (ORCPT ); Thu, 12 Aug 2021 05:00:53 -0400 X-UUID: c736e56cd2ea4d2a92e0bb40cb1b388c-20210812 X-UUID: c736e56cd2ea4d2a92e0bb40cb1b388c-20210812 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 312176054; Thu, 12 Aug 2021 17:00:25 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 12 Aug 2021 17:00:23 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 12 Aug 2021 17:00:23 +0800 From: Dawei Chien To: Georgi Djakov , Rob Herring , Matthias Brugger , Stephen Boyd , Ryan Case CC: Mark Rutland , Nicolas Boichat , , , , , , Fan Chen , Arvin Wang , James Liao , Dawei Chien Subject: [V11,PATCH 15/19] regulator: mediatek: add support for mt8195 Date: Thu, 12 Aug 2021 16:58:42 +0800 Message-ID: <20210812085846.2628-16-dawei.chien@mediatek.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20210812085846.2628-1-dawei.chien@mediatek.com> References: <20210812085846.2628-1-dawei.chien@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org add platform data on mt8195 Signed-off-by: Dawei Chien Reviewed-by: AngeloGioacchino Del Regno --- drivers/regulator/mtk-dvfsrc-regulator.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/regulator/mtk-dvfsrc-regulator.c b/drivers/regulator/mtk-dvfsrc-regulator.c index d3d876198d6e..1bd6e67b1de5 100644 --- a/drivers/regulator/mtk-dvfsrc-regulator.c +++ b/drivers/regulator/mtk-dvfsrc-regulator.c @@ -140,6 +140,25 @@ static const struct dvfsrc_regulator_init_data regulator_mt6873_data = { .regulator_info = &mt6873_regulators[0], }; +static const unsigned int mt8195_voltages[] = { + 550000, + 600000, + 650000, + 750000, +}; + +static struct dvfsrc_regulator mt8195_regulators[] = { + MT_DVFSRC_REGULAR("dvfsrc-vcore", VCORE, + mt8195_voltages), + MT_DVFSRC_REGULAR("dvfsrc-vscp", VSCP, + mt8195_voltages), +}; + +static const struct dvfsrc_regulator_init_data regulator_mt8195_data = { + .size = ARRAY_SIZE(mt8195_regulators), + .regulator_info = &mt8195_regulators[0], +}; + static const struct of_device_id mtk_dvfsrc_regulator_match[] = { { .compatible = "mediatek,mt8183-dvfsrc", @@ -150,6 +169,10 @@ static const struct of_device_id mtk_dvfsrc_regulator_match[] = { }, { .compatible = "mediatek,mt6873-dvfsrc", .data = ®ulator_mt6873_data, + }, { + .compatible = "mediatek,mt8195-dvfsrc", + .data = ®ulator_mt8195_data, + }, { }, { /* sentinel */ }, From patchwork Thu Aug 12 08:58:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dawei Chien X-Patchwork-Id: 12432993 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 47F18C04FE3 for ; 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Thu, 12 Aug 2021 17:00:23 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 12 Aug 2021 17:00:23 +0800 From: Dawei Chien To: Georgi Djakov , Rob Herring , Matthias Brugger , Stephen Boyd , Ryan Case CC: Mark Rutland , Nicolas Boichat , , , , , , Fan Chen , Arvin Wang , James Liao , Dawei Chien , Henry Chen Subject: [V11,PATCH 16/19] arm64: dts: mt8183: add dvfsrc related nodes Date: Thu, 12 Aug 2021 16:58:43 +0800 Message-ID: <20210812085846.2628-17-dawei.chien@mediatek.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20210812085846.2628-1-dawei.chien@mediatek.com> References: <20210812085846.2628-1-dawei.chien@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Henry Chen Add DDR EMI provider dictating dram interconnect bus performance found on MT8192-based platforms Signed-off-by: Henry Chen --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 7ad4cf646579..86f85c34c88a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -7,6 +7,7 @@ #include #include +#include #include #include #include @@ -586,6 +587,7 @@ ddr_emi: dvfsrc@10012000 { compatible = "mediatek,mt8183-dvfsrc"; reg = <0 0x10012000 0 0x1000>; + #interconnect-cells = <1>; }; pwrap: pwrap@1000d000 { From patchwork Thu Aug 12 08:58:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dawei Chien X-Patchwork-Id: 12432991 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 847CEC19F3D for ; Thu, 12 Aug 2021 09:00:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 661116103E for ; Thu, 12 Aug 2021 09:00:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235686AbhHLJAx (ORCPT ); Thu, 12 Aug 2021 05:00:53 -0400 Received: from mailgw01.mediatek.com ([60.244.123.138]:37472 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S235628AbhHLJAw (ORCPT ); Thu, 12 Aug 2021 05:00:52 -0400 X-UUID: 302aaa6d0a1b4fbbad973bb98b502324-20210812 X-UUID: 302aaa6d0a1b4fbbad973bb98b502324-20210812 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1543116344; Thu, 12 Aug 2021 17:00:25 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 12 Aug 2021 17:00:24 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 12 Aug 2021 17:00:24 +0800 From: Dawei Chien To: Georgi Djakov , Rob Herring , Matthias Brugger , Stephen Boyd , Ryan Case CC: Mark Rutland , Nicolas Boichat , , , , , , Fan Chen , Arvin Wang , James Liao , Dawei Chien , Henry Chen Subject: [V11,PATCH 17/19] arm64: dts: mt8192: add dvfsrc related nodes Date: Thu, 12 Aug 2021 16:58:44 +0800 Message-ID: <20210812085846.2628-18-dawei.chien@mediatek.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20210812085846.2628-1-dawei.chien@mediatek.com> References: <20210812085846.2628-1-dawei.chien@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Henry Chen Add DDR EMI provider dictating dram interconnect bus performance found on MT8183-based platforms Signed-off-by: Henry Chen Signed-off-by: Dawei Chien --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index c70a3bf744fa..ab3dabcc722e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -5,6 +5,7 @@ */ /dts-v1/; +#include #include #include #include @@ -286,6 +287,7 @@ compatible = "mediatek,mt8192-dvfsrc", "mediatek,mt6873-dvfsrc"; reg = <0 0x10012000 0 0x1000>; + #interconnect-cells = <1>; }; systimer: timer@10017000 { From patchwork Thu Aug 12 08:58:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dawei Chien X-Patchwork-Id: 12432981 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3BA5EC19F36 for ; Thu, 12 Aug 2021 09:00:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1B6B66112E for ; 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Thu, 12 Aug 2021 17:00:24 +0800 From: Dawei Chien To: Georgi Djakov , Rob Herring , Matthias Brugger , Stephen Boyd , Ryan Case CC: Mark Rutland , Nicolas Boichat , , , , , , Fan Chen , Arvin Wang , James Liao , Dawei Chien , Henry Chen Subject: [V11,PATCH 18/19] arm64: dts: mt8192: add dvfsrc regulator nodes Date: Thu, 12 Aug 2021 16:58:45 +0800 Message-ID: <20210812085846.2628-19-dawei.chien@mediatek.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20210812085846.2628-1-dawei.chien@mediatek.com> References: <20210812085846.2628-1-dawei.chien@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Henry Chen Add dvfsrc regulator nodes which is for MT8192-based platforms Signed-off-by: Henry Chen --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index ab3dabcc722e..6aad5ff0646c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -288,6 +288,12 @@ "mediatek,mt6873-dvfsrc"; reg = <0 0x10012000 0 0x1000>; #interconnect-cells = <1>; + dvfsrc_vcore: dvfsrc-vcore { + regulator-name = "dvfsrc-vcore"; + regulator-min-microvolt = <575000>; + regulator-max-microvolt = <725000>; + regulator-always-on; + }; }; systimer: timer@10017000 { From patchwork Thu Aug 12 08:58:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dawei Chien X-Patchwork-Id: 12432983 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 951BFC3F6A3 for ; Thu, 12 Aug 2021 09:00:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 77B786103A for ; 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Thu, 12 Aug 2021 17:00:24 +0800 From: Dawei Chien To: Georgi Djakov , Rob Herring , Matthias Brugger , Stephen Boyd , Ryan Case CC: Mark Rutland , Nicolas Boichat , , , , , , Fan Chen , Arvin Wang , James Liao , Dawei Chien Subject: [V11,PATCH 19/19] arm64: dts: mt8195: add dvfsrc related nodes Date: Thu, 12 Aug 2021 16:58:46 +0800 Message-ID: <20210812085846.2628-20-dawei.chien@mediatek.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20210812085846.2628-1-dawei.chien@mediatek.com> References: <20210812085846.2628-1-dawei.chien@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add DDR EMI provider dictating dram interconnect bus performance found on MT8195-based platforms Signed-off-by: Dawei Chien --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 19430f324ee1..b010aed83906 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -6,6 +6,7 @@ /dts-v1/; #include +#include #include #include #include @@ -689,6 +690,7 @@ ddr_emi: dvfsrc@10012000 { compatible = "mediatek,mt8195-dvfsrc"; reg = <0 0x10012000 0 0x1000>; + #interconnect-cells = <1>; }; systimer: timer@10017000 {