From patchwork Fri Aug 13 21:12:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raghavendra Rao Ananta X-Patchwork-Id: 12436195 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-26.3 required=3.0 tests=BAYES_00,DKIMWL_WL_MED, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT,USER_IN_DEF_DKIM_WL autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B5D2FC4338F for ; Fri, 13 Aug 2021 21:12:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8E9846109D for ; Fri, 13 Aug 2021 21:12:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234805AbhHMVM5 (ORCPT ); Fri, 13 Aug 2021 17:12:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45610 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234768AbhHMVM4 (ORCPT ); Fri, 13 Aug 2021 17:12:56 -0400 Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com [IPv6:2607:f8b0:4864:20::b49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 87190C061756 for ; Fri, 13 Aug 2021 14:12:29 -0700 (PDT) Received: by mail-yb1-xb49.google.com with SMTP id n200-20020a25d6d10000b02905935ac4154aso10300230ybg.23 for ; Fri, 13 Aug 2021 14:12:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=sybk7YcBeZufJ2AiOux9y0QLju0ZjmiMoQ+rDeqF05I=; b=LJO5U00ZjaOZ215Q3zQBNAPbMmqLU4kJbRYeMS0C3oR9Q0pS36G9P72tHYnL9f1TmL eYQtnM3qkeMEicbovSeP50ZrM2B4Np2JYkPEvunq2dUIfENdFZ6WwmmWce5QmsnmA5Yq uRyfhUD58L5wJfyrxi+LZwfuf8b0+BGTDjTkWEkbvgyPao9BFLbHpzjXr7ZcRY/OJuWb yR3u7arud7z7b3q+ApZGI0ojHzeCHi9oNV9STxe2ldebvsT5G3mTIDv/VRIxQ5AwvJoF mDMepVoQek8NI1KclrY1V+3lfCc823x0+5eK1b/OJvdkyXV7fz/7wW60yRevcXCZr7VG 0/fQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=sybk7YcBeZufJ2AiOux9y0QLju0ZjmiMoQ+rDeqF05I=; b=EkDh0Rk16P++rRc/BW7vC7Mu7NIiDQCwgiLXpIKEOznw017oO8H+EVMmm/gC10DGxq gwZLuPmAE00MfLuS7oL4klYY33GK+jOXDfK/wb3g5s9yx2yajhp89CUEWYNhWXeO8CKq wlA1/rsX5xPvGp36J/UmBK9c+ffYAuLAYh+kbYgtSUyJTjmATPfnH89QjkbDHnPxnjaX UmnNObPEy6Hxp8vhJFyFHNy/x+9+L0J5h2d9hLkUZ0pcNvx2JSkMYxegYFMvANSoT7mA Pih54vBBj/BRWrUmyPU+F4l4aj8hvYjjIGT4MKNZ3HmqxAccjN7LnXeXdMVz4ulfMcgh jJqw== X-Gm-Message-State: AOAM531s0Yt0HMtrNvg1uAd5e+CO4ULnzPQ+ex1pkimu2LWzQ7Tdzkyf 34aCx8Zh3zduLC56dcs3lNkAC1PTIkeO X-Google-Smtp-Source: ABdhPJxmtYDI1q+46n5THoeKsu7C2PelKcdfRaw5GLTlL9837eljYe1WdU4FvJftPG+amvHn+6hOD64bw2YW X-Received: from rananta-virt.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:1bcc]) (user=rananta job=sendgmr) by 2002:a25:25ce:: with SMTP id l197mr5713620ybl.255.1628889148791; Fri, 13 Aug 2021 14:12:28 -0700 (PDT) Date: Fri, 13 Aug 2021 21:12:02 +0000 In-Reply-To: <20210813211211.2983293-1-rananta@google.com> Message-Id: <20210813211211.2983293-2-rananta@google.com> Mime-Version: 1.0 References: <20210813211211.2983293-1-rananta@google.com> X-Mailer: git-send-email 2.33.0.rc1.237.g0d66db33f3-goog Subject: [PATCH 01/10] KVM: arm64: selftests: Add MMIO readl/writel support From: Raghavendra Rao Ananta To: Paolo Bonzini , Marc Zyngier Cc: Alexandru Elisei , Suzuki K Poulose , James Morse , Peter Shier , Ricardo Koller , Oliver Upton , Reiji Watanabe , Jing Zhang , Raghavendra Rao Anata , kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Define the readl() and writel() functions for the guests to access (4-byte) the MMIO region. The routines, and their dependents, are inspired from the kernel's arch/arm64/include/asm/io.h and arch/arm64/include/asm/barrier.h. Signed-off-by: Raghavendra Rao Ananta --- .../selftests/kvm/include/aarch64/processor.h | 45 ++++++++++++++++++- 1 file changed, 44 insertions(+), 1 deletion(-) diff --git a/tools/testing/selftests/kvm/include/aarch64/processor.h b/tools/testing/selftests/kvm/include/aarch64/processor.h index 27dc5c2e56b9..14f68bf55036 100644 --- a/tools/testing/selftests/kvm/include/aarch64/processor.h +++ b/tools/testing/selftests/kvm/include/aarch64/processor.h @@ -127,6 +127,49 @@ void vm_install_sync_handler(struct kvm_vm *vm, val; \ }) -#define isb() asm volatile("isb" : : : "memory") +#define isb() asm volatile("isb" : : : "memory") +#define dsb(opt) asm volatile("dsb " #opt : : : "memory") +#define dmb(opt) asm volatile("dmb " #opt : : : "memory") + +#define dma_wmb() dmb(oshst) +#define __iowmb() dma_wmb() + +#define dma_rmb() dmb(oshld) + +#define __iormb(v) \ +({ \ + unsigned long tmp; \ + \ + dma_rmb(); \ + \ + /* \ + * Courtesy of arch/arm64/include/asm/io.h: \ + * Create a dummy control dependency from the IO read to any \ + * later instructions. This ensures that a subsequent call \ + * to udelay() will be ordered due to the ISB in __delay(). \ + */ \ + asm volatile("eor %0, %1, %1\n" \ + "cbnz %0, ." \ + : "=r" (tmp) : "r" ((unsigned long)(v)) \ + : "memory"); \ +}) + +static __always_inline void __raw_writel(u32 val, volatile void *addr) +{ + asm volatile("str %w0, [%1]" : : "rZ" (val), "r" (addr)); +} + +static __always_inline u32 __raw_readl(const volatile void *addr) +{ + u32 val; + asm volatile("ldr %w0, [%1]" : "=r" (val) : "r" (addr)); + return val; +} + +#define writel_relaxed(v,c) ((void)__raw_writel((__force u32)cpu_to_le32(v),(c))) +#define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32)__raw_readl(c)); __r; }) + +#define writel(v,c) ({ __iowmb(); writel_relaxed((v),(c));}) +#define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(__v); __v; }) #endif /* SELFTEST_KVM_PROCESSOR_H */ From patchwork Fri Aug 13 21:12:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raghavendra Rao Ananta X-Patchwork-Id: 12436199 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-26.3 required=3.0 tests=BAYES_00,DKIMWL_WL_MED, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT,USER_IN_DEF_DKIM_WL autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 00CCAC4338F for ; Fri, 13 Aug 2021 21:12:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C810F610E9 for ; Fri, 13 Aug 2021 21:12:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234838AbhHMVNA (ORCPT ); Fri, 13 Aug 2021 17:13:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45624 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234547AbhHMVM7 (ORCPT ); Fri, 13 Aug 2021 17:12:59 -0400 Received: from mail-pj1-x104a.google.com (mail-pj1-x104a.google.com [IPv6:2607:f8b0:4864:20::104a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7687EC061756 for ; Fri, 13 Aug 2021 14:12:32 -0700 (PDT) Received: by mail-pj1-x104a.google.com with SMTP id h21-20020a17090adb95b029017797967ffbso8586154pjv.5 for ; Fri, 13 Aug 2021 14:12:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=xPoIZjuWep0XnVjE3RZ+lF+QPEA9z7qXvcODMX5rYnc=; b=tLRfwvEqQSqyt/QVk9wx8D1i5roaNJZj6Y5mrjVxRY1cOOFHxbrnZv08XP9BH1L505 05zkQ7DDsCBnd64vOSatbSX7cA8NSLqLruoPgASiB/BO1N2h6DZRagt1p4QxemUYGpf8 pFeogUFdUJgq3Nvf0WICqVvniiaK9AQW4t0+qXpXB5AfXgw/YUR57FXcBRFk6emIyfRE /bW1BmjYPUuzPzqKaumRv++9fULqs4udzSu66BBt2d3b3tH4uNyKZFJPyCDG+RlyGzpt C/OSN8S6lvFDoJZp03cISdKkVneS4Nn3S7zrGvVHVYSzyHyNDizFt5H9kcG0JxxG4FjL G5sg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=xPoIZjuWep0XnVjE3RZ+lF+QPEA9z7qXvcODMX5rYnc=; b=gOPF13wQBdrv1tGsNEY94PL9/oxBUx94+b6jFtc44sXN6pfQ6ix/1dUkuQsHOQMvpp MLOOC8IsrMQ8w1FdrO3DsG24feoYxMHKDdoufb1gfRRWNc6ODwItGARe4Z/WKkZcgYhQ yBmciflAsUlds5vCu1odsd9sKoAWFBm9gVJI7QxRSnskOXxCsiNnC19Ox31PaGPX3xbo tIZ/TdWbTcdSUUk53Q8ra/Y6E5tneHShIcDP/ceXNJwt/nKP7DKpfA89d9KT57s/cTCZ zsMjwwEYnXJlpXaRZz7sw0GsvPXb+6hZpCEWIYCICvZt73Sj/Lqaq6XPPGziIVgWf88I 8eHQ== X-Gm-Message-State: AOAM530L9u+4gAfpM/1puZKVU6Thing5EhIVu2CYkb9kuZezqwTnOPD6 xtzT09boCoXeIALHSO0N8vgo2YjdtOGJ X-Google-Smtp-Source: ABdhPJzbmFEd2uQqU/4nZgMWFmmHA0gDdgA66TV1ZI72XcP1aFw7BHbaSHbuUfx6jZt0qaPY36m5ZWdfn0jK X-Received: from rananta-virt.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:1bcc]) (user=rananta job=sendgmr) by 2002:a17:902:ea91:b0:12d:7aa6:1e46 with SMTP id x17-20020a170902ea9100b0012d7aa61e46mr3558910plb.58.1628889151981; Fri, 13 Aug 2021 14:12:31 -0700 (PDT) Date: Fri, 13 Aug 2021 21:12:03 +0000 In-Reply-To: <20210813211211.2983293-1-rananta@google.com> Message-Id: <20210813211211.2983293-3-rananta@google.com> Mime-Version: 1.0 References: <20210813211211.2983293-1-rananta@google.com> X-Mailer: git-send-email 2.33.0.rc1.237.g0d66db33f3-goog Subject: [PATCH 02/10] KVM: arm64: selftests: Add write_sysreg_s and read_sysreg_s From: Raghavendra Rao Ananta To: Paolo Bonzini , Marc Zyngier Cc: Alexandru Elisei , Suzuki K Poulose , James Morse , Peter Shier , Ricardo Koller , Oliver Upton , Reiji Watanabe , Jing Zhang , Raghavendra Rao Anata , kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org For register names that are unsupported by the assembler or the ones without architectural names, add the macros write_sysreg_s and read_sysreg_s to support them. The functionality is derived from kvm-unit-tests and kernel's arch/arm64/include/asm/sysreg.h. Signed-off-by: Raghavendra Rao Ananta --- .../selftests/kvm/include/aarch64/processor.h | 61 +++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/tools/testing/selftests/kvm/include/aarch64/processor.h b/tools/testing/selftests/kvm/include/aarch64/processor.h index 14f68bf55036..b4bbce837288 100644 --- a/tools/testing/selftests/kvm/include/aarch64/processor.h +++ b/tools/testing/selftests/kvm/include/aarch64/processor.h @@ -115,6 +115,67 @@ void vm_install_exception_handler(struct kvm_vm *vm, void vm_install_sync_handler(struct kvm_vm *vm, int vector, int ec, handler_fn handler); +/* + * ARMv8 ARM reserves the following encoding for system registers: + * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview", + * C5.2, version:ARM DDI 0487A.f) + * [20-19] : Op0 + * [18-16] : Op1 + * [15-12] : CRn + * [11-8] : CRm + * [7-5] : Op2 + */ +#define Op0_shift 19 +#define Op0_mask 0x3 +#define Op1_shift 16 +#define Op1_mask 0x7 +#define CRn_shift 12 +#define CRn_mask 0xf +#define CRm_shift 8 +#define CRm_mask 0xf +#define Op2_shift 5 +#define Op2_mask 0x7 + +/* + * When accessed from guests, the ARM64_SYS_REG() doesn't work since it + * generates a different encoding for additional KVM processing, and is + * only suitable for userspace to access the register via ioctls. + * Hence, define a 'pure' sys_reg() here to generate the encodings as per spec. + */ +#define sys_reg(op0, op1, crn, crm, op2) \ + (((op0) << Op0_shift) | ((op1) << Op1_shift) | \ + ((crn) << CRn_shift) | ((crm) << CRm_shift) | \ + ((op2) << Op2_shift)) + +asm( +" .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n" +" .equ .L__reg_num_x\\num, \\num\n" +" .endr\n" +" .equ .L__reg_num_xzr, 31\n" +"\n" +" .macro mrs_s, rt, sreg\n" +" .inst 0xd5200000|(\\sreg)|(.L__reg_num_\\rt)\n" +" .endm\n" +"\n" +" .macro msr_s, sreg, rt\n" +" .inst 0xd5000000|(\\sreg)|(.L__reg_num_\\rt)\n" +" .endm\n" +); + +/* + * read_sysreg_s() and write_sysreg_s()'s 'reg' has to be encoded via sys_reg() + */ +#define read_sysreg_s(reg) ({ \ + u64 __val; \ + asm volatile("mrs_s %0, "__stringify(reg) : "=r" (__val)); \ + __val; \ +}) + +#define write_sysreg_s(reg, val) do { \ + u64 __val = (u64)val; \ + asm volatile("msr_s "__stringify(reg) ", %x0" : : "rZ" (__val));\ +} while (0) + #define write_sysreg(reg, val) \ ({ \ u64 __val = (u64)(val); \ From patchwork Fri Aug 13 21:12:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raghavendra Rao Ananta X-Patchwork-Id: 12436197 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-26.3 required=3.0 tests=BAYES_00,DKIMWL_WL_MED, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT,USER_IN_DEF_DKIM_WL autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 04799C432BE for ; Fri, 13 Aug 2021 21:12:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E1FBA610E9 for ; Fri, 13 Aug 2021 21:12:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234867AbhHMVND (ORCPT ); Fri, 13 Aug 2021 17:13:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45638 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234547AbhHMVNC (ORCPT ); Fri, 13 Aug 2021 17:13:02 -0400 Received: from mail-qk1-x749.google.com (mail-qk1-x749.google.com [IPv6:2607:f8b0:4864:20::749]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 37F8CC061756 for ; Fri, 13 Aug 2021 14:12:35 -0700 (PDT) Received: by mail-qk1-x749.google.com with SMTP id b4-20020a3799040000b02903b899a4309cso8260902qke.14 for ; Fri, 13 Aug 2021 14:12:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=i0gC3YpOlYGFveSBqO/xZNra4rgAWDR79DWIZ6oDj6o=; b=s5Ktat8XOcezUVnJb1WS/qHIUWUy9yBdjTN5bhE6i0fMGjZYCkwSbxqDUwud+MdaqI dk+Zn+RkrsOIY2CeFggqpVheqoDLAYFUIkYmtjScPsc+VSl0awgPlkE9cbjjaN2c74Hb 0N7En1twzTQQ1D2vqEPO2tnAa2zH8LuA94yv19XCVKzmow5wCaAPjo8h1A8Jm415QD0B wy/JG7ZSJxXDmVOsUfPqOMNZeL9lV5d/drVQKTfkSNvDOPB9GDBwbboSwEvZPwbV6/12 4hsuaOo8hX7Kr3txQkKfPNAO7cudiUrRu5z8/2U73CwmgqnsNFfYUc0u9ZBUwZGVIWeu oCVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=i0gC3YpOlYGFveSBqO/xZNra4rgAWDR79DWIZ6oDj6o=; b=WC2KDA6mkIhmqgOhoDC5BcCXNMNJeTXXi0QS7KZmo9TXAJoMNqK1c0HeeuqejTftZi ZzKFUfbkQzur0X9vKDPu3dN8TD++J1fx8iEdkluEOfewC3P842lL03Dxhugz5pytfDVO 710H9X84Oz9qyhf/ndIILcbRUg9itKp2QfldzP2I7fw4lL7nhp7NSw5fs4q5TZFDOE0g S8ZUtlgwF1OsavxQtgr0Vr0Pb24nqbut3TYANj48g2uHzpEEulTT4/zJa3QDnpbGO/rM luiu2FeLRia4unQtWTmJstVDpOhTVVME+JDc4mLVEfxRFvp0N8q8gQEXXFQ1QH3mmUnL i0UQ== X-Gm-Message-State: AOAM530sEjjfyFVAZ5IU/zPZoKRKT8jK+iFrCLVHcGBUPbAx4R/Qe7lm m9Rk6jFOr9IL+bHJcXNUJsEqoN7W7N4m X-Google-Smtp-Source: ABdhPJypOuxC0xiAvWzRKcX6FUG1sO4EVFhTLrKIh/dzhKC+66Hb60+6xtglfO5h44/z9YkcWOomkfrGI10A X-Received: from rananta-virt.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:1bcc]) (user=rananta job=sendgmr) by 2002:a05:6214:62c:: with SMTP id a12mr4731968qvx.49.1628889154400; Fri, 13 Aug 2021 14:12:34 -0700 (PDT) Date: Fri, 13 Aug 2021 21:12:04 +0000 In-Reply-To: <20210813211211.2983293-1-rananta@google.com> Message-Id: <20210813211211.2983293-4-rananta@google.com> Mime-Version: 1.0 References: <20210813211211.2983293-1-rananta@google.com> X-Mailer: git-send-email 2.33.0.rc1.237.g0d66db33f3-goog Subject: [PATCH 03/10] KVM: arm64: selftests: Add support for cpu_relax From: Raghavendra Rao Ananta To: Paolo Bonzini , Marc Zyngier Cc: Alexandru Elisei , Suzuki K Poulose , James Morse , Peter Shier , Ricardo Koller , Oliver Upton , Reiji Watanabe , Jing Zhang , Raghavendra Rao Anata , kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Implement the guest helper routine, cpu_relax(), to yield the processor to other tasks. The function was derived from arch/arm64/include/asm/vdso/processor.h. Signed-off-by: Raghavendra Rao Ananta --- tools/testing/selftests/kvm/include/aarch64/processor.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/tools/testing/selftests/kvm/include/aarch64/processor.h b/tools/testing/selftests/kvm/include/aarch64/processor.h index b4bbce837288..c83ff99282ed 100644 --- a/tools/testing/selftests/kvm/include/aarch64/processor.h +++ b/tools/testing/selftests/kvm/include/aarch64/processor.h @@ -188,6 +188,11 @@ asm( val; \ }) +static inline void cpu_relax(void) +{ + asm volatile("yield" ::: "memory"); +} + #define isb() asm volatile("isb" : : : "memory") #define dsb(opt) asm volatile("dsb " #opt : : : "memory") #define dmb(opt) asm volatile("dmb " #opt : : : "memory") From patchwork Fri Aug 13 21:12:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raghavendra Rao Ananta X-Patchwork-Id: 12436201 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-26.3 required=3.0 tests=BAYES_00,DKIMWL_WL_MED, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT,USER_IN_DEF_DKIM_WL autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 15B32C4338F for ; Fri, 13 Aug 2021 21:12:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E04A4610E9 for ; Fri, 13 Aug 2021 21:12:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234873AbhHMVNF (ORCPT ); Fri, 13 Aug 2021 17:13:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45648 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234855AbhHMVNE (ORCPT ); Fri, 13 Aug 2021 17:13:04 -0400 Received: from mail-pl1-x649.google.com (mail-pl1-x649.google.com [IPv6:2607:f8b0:4864:20::649]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3D8EEC0617AF for ; Fri, 13 Aug 2021 14:12:37 -0700 (PDT) Received: by mail-pl1-x649.google.com with SMTP id w23-20020a170902d71700b0012d8286e44bso1028816ply.3 for ; Fri, 13 Aug 2021 14:12:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=ImD1K6W7q85b9plMlOYBF1Iglgh9e6yeR/4CNYhFQRg=; b=CZFVMacm4oRYM5riU6/kN8e+8QOv4ScQvNs7LSvfERJ4elKZRbXW+cb8Ajm1AP7A30 RlwtBzLAGwJRbBQWXxizFVNyyhNotO7OsTweXQX2WsecNIfppBRrIGEldPfIqtK9rgBN q7lpifCkdvblOQzMIvdIsuToYogD0ih5pb8s6uGOzcaKoRfNg1CbXQA8AL2yutqZVz2n 8t0Yb2b/6OxkhH7s4fpA/CBTuUYvc2vf1xbJRoEEZeWlyn3rmztALV6Z/xF4qjv3pcjb 6rMgBz/c/geaxKZAZbK/g/LH+ddcynHYz4byTRGuv7/ja26tgAFuvg2zc8H6ed7fUDXE zxeA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=ImD1K6W7q85b9plMlOYBF1Iglgh9e6yeR/4CNYhFQRg=; b=KsCPN3toWUvs+vFieQ+f/6erQNzT+rmgZIOGwNbu6gkqb29aHL2ZoNfbwFY2TQtjWq S0ZUE8IQ1MDTwhNjAMBseiLsLIwNJ+Q/oVKXZe07D1ruN7n2HydCXAOvv8t5nHXwYTvy vGmC6LaAwP2WepIFQJp3TMWTkjz0PwJH+P2LW+UEpc+fVuOd6skZAOGGRPlLMBM8pLIs ZovXkBylKxoHAC6YW0AGzW4dk9YJBxzJoNr1ErpvlKbzTs54LJ09IIJMq2ZdhbRlU6Fa EgWOrBteoyAgsZkbuA2Vn4x45AYK8QQ8iJgMyT53rzU8g6vLq4A2R672DOCkh/NWMY1w 5wNA== X-Gm-Message-State: AOAM531Uy4Jm5pOe7dJw2zoyZZ8eLjplcZ3JDPHsUQhTI/ua38Jwv6Cq 2ugparXNo5Sw/ZOKSz1Mft6OYiWVXDPn X-Google-Smtp-Source: ABdhPJz7Stco5O4WRJcJOWee+TYY1OyxYEHxh5Gszj92Xn7xpZ+r+S55XXaa2Tso8A7V93Qrha+yjd75ByH2 X-Received: from rananta-virt.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:1bcc]) (user=rananta job=sendgmr) by 2002:a17:903:1243:b029:107:eca4:d5bf with SMTP id u3-20020a1709031243b0290107eca4d5bfmr3528610plh.15.1628889156661; Fri, 13 Aug 2021 14:12:36 -0700 (PDT) Date: Fri, 13 Aug 2021 21:12:05 +0000 In-Reply-To: <20210813211211.2983293-1-rananta@google.com> Message-Id: <20210813211211.2983293-5-rananta@google.com> Mime-Version: 1.0 References: <20210813211211.2983293-1-rananta@google.com> X-Mailer: git-send-email 2.33.0.rc1.237.g0d66db33f3-goog Subject: [PATCH 04/10] KVM: arm64: selftests: Add basic support for arch_timers From: Raghavendra Rao Ananta To: Paolo Bonzini , Marc Zyngier Cc: Alexandru Elisei , Suzuki K Poulose , James Morse , Peter Shier , Ricardo Koller , Oliver Upton , Reiji Watanabe , Jing Zhang , Raghavendra Rao Anata , kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Add a minimalistic library support to access the virtual timers, that can be used for simple timing functionalities, such as introducing delays in the guest. Signed-off-by: Raghavendra Rao Ananta --- .../kvm/include/aarch64/arch_timer.h | 138 ++++++++++++++++++ 1 file changed, 138 insertions(+) create mode 100644 tools/testing/selftests/kvm/include/aarch64/arch_timer.h diff --git a/tools/testing/selftests/kvm/include/aarch64/arch_timer.h b/tools/testing/selftests/kvm/include/aarch64/arch_timer.h new file mode 100644 index 000000000000..e6144ab95348 --- /dev/null +++ b/tools/testing/selftests/kvm/include/aarch64/arch_timer.h @@ -0,0 +1,138 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * ARM Generic Interrupt Controller (GIC) specific defines + */ + +#ifndef SELFTEST_KVM_ARCH_TIMER_H +#define SELFTEST_KVM_ARCH_TIMER_H + +#include + +#include "processor.h" + +enum arch_timer { + VIRTUAL, + PHYSICAL, +}; + +#define CTL_ENABLE (1 << 0) +#define CTL_ISTATUS (1 << 2) +#define CTL_IMASK (1 << 1) + +#define msec_to_cycles(msec) \ + (timer_get_cntfrq() * (uint64_t)(msec) / 1000) + +#define usec_to_cycles(usec) \ + (timer_get_cntfrq() * (uint64_t)(usec) / 1000000) + +#define cycles_to_usec(cycles) \ + ((uint64_t)(cycles) * 1000000 / timer_get_cntfrq()) + +static inline uint32_t timer_get_cntfrq(void) +{ + return read_sysreg(cntfrq_el0); +} + +static inline uint64_t timer_get_cntct(enum arch_timer timer) +{ + isb(); + + switch (timer) { + case VIRTUAL: + return read_sysreg(cntvct_el0); + case PHYSICAL: + return read_sysreg(cntpct_el0); + default: + GUEST_ASSERT_1(0, timer); + } + + /* We should not reach here */ + return 0; +} + +static inline void timer_set_cval(enum arch_timer timer, uint64_t cval) +{ + switch (timer) { + case VIRTUAL: + return write_sysreg(cntv_cval_el0, cval); + case PHYSICAL: + return write_sysreg(cntp_cval_el0, cval); + default: + GUEST_ASSERT_1(0, timer); + } + + isb(); +} + +static inline uint64_t timer_get_cval(enum arch_timer timer) +{ + switch (timer) { + case VIRTUAL: + return read_sysreg(cntv_cval_el0); + case PHYSICAL: + return read_sysreg(cntp_cval_el0); + default: + GUEST_ASSERT_1(0, timer); + } + + /* We should not reach here */ + return 0; +} + +static inline void timer_set_tval(enum arch_timer timer, uint32_t tval) +{ + switch (timer) { + case VIRTUAL: + return write_sysreg(cntv_tval_el0, tval); + case PHYSICAL: + return write_sysreg(cntp_tval_el0, tval); + default: + GUEST_ASSERT_1(0, timer); + } + + isb(); +} + +static inline void timer_set_ctl(enum arch_timer timer, uint32_t ctl) +{ + switch (timer) { + case VIRTUAL: + return write_sysreg(cntv_ctl_el0, ctl); + case PHYSICAL: + return write_sysreg(cntp_ctl_el0, ctl); + default: + GUEST_ASSERT_1(0, timer); + } + + isb(); +} + +static inline uint32_t timer_get_ctl(enum arch_timer timer) +{ + switch (timer) { + case VIRTUAL: + return read_sysreg(cntv_ctl_el0); + case PHYSICAL: + return read_sysreg(cntp_ctl_el0); + default: + GUEST_ASSERT_1(0, timer); + } + + /* We should not reach here */ + return 0; +} + +static inline void timer_set_next_cval_ms(enum arch_timer timer, uint32_t msec) +{ + uint64_t now_ct = timer_get_cntct(timer); + uint64_t next_ct = now_ct + msec_to_cycles(msec); + + timer_set_cval(timer, next_ct); +} + +static inline void timer_set_next_tval_ms(enum arch_timer timer, uint32_t msec) +{ + timer_set_tval(timer, msec_to_cycles(msec)); +} + +#endif /* SELFTEST_KVM_ARCH_TIMER_H */ From patchwork Fri Aug 13 21:12:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raghavendra Rao Ananta X-Patchwork-Id: 12436203 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-26.3 required=3.0 tests=BAYES_00,DKIMWL_WL_MED, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT,USER_IN_DEF_DKIM_WL autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4AA3DC432BE for ; Fri, 13 Aug 2021 21:12:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 32203610E9 for ; Fri, 13 Aug 2021 21:12:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234887AbhHMVNH (ORCPT ); Fri, 13 Aug 2021 17:13:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45664 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234855AbhHMVNG (ORCPT ); Fri, 13 Aug 2021 17:13:06 -0400 Received: from mail-pj1-x104a.google.com (mail-pj1-x104a.google.com [IPv6:2607:f8b0:4864:20::104a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 94871C0617AD for ; Fri, 13 Aug 2021 14:12:39 -0700 (PDT) Received: by mail-pj1-x104a.google.com with SMTP id ns7-20020a17090b250700b0017942fa12a8so1972235pjb.6 for ; Fri, 13 Aug 2021 14:12:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=JcHymXf2ERbzAFxFFXQtQ/oPOCBg0VdgmGHaGoYCh8I=; b=CWKvMvq482YcNTRILLKxrh/xXxR9laMMXd5epUlsTlwgqwSaX6jxASp2d+jPJJHATO uq70iG5BIugJ6LTQ/N2CA7kNudIDf8jJOq/Mbeq72/1jYBoPwBj47fTLtm7ZYZ3UHWgj LXD5RMu1CojOoWF8rcnS78THeu4/0Aohx6EMP0HZc8Ps0Zk+qQTVPDS7U6/VXSXlbPZJ MjtBHGnHlUOfk96OBdhBl4berWwQsylBeu4KtAOyoCtCXEftrQk+hdqlCoLRPcYIV2va rR0J/hpsbfkRpmGM9c+uIbBOYxu6mjORsohBqt1WNdT5lSCYEoBSYWpOvv5dKH1WGhF0 jlLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=JcHymXf2ERbzAFxFFXQtQ/oPOCBg0VdgmGHaGoYCh8I=; b=KAnBvK7i5UlCiGBCQ/N8RI8heAxE7CATvrxjrBXSXjepyC1+viFk0+NrFKHWWnCpEa n9iwUR9nx2JgjR6y+GTz2pBPtb+DN5Q3JPpp1aohIuKCf7Ur6AEn+dJ6ucbXXIzyz3lp nnQAtjFl4fCiGktQUT3P/TphJ0gSFExJOPhKTepflK9DrA+14cKF4CqK8wthcN5riKCR hZxsMlQ39MD9I+/TF3cPzPzLOG0Ev1t71zMuOy/oRonvlfkDtlCv8xe9kiYHVknzsDiJ 7iveAh8TCyvhn2e+EGysLfXK6Z19X2CU3ALlrEJpjLQeWNYqAN/BBBoTvBLjnLngmA54 +Vuw== X-Gm-Message-State: AOAM530lOQBh60M1FWmLZcA0svmtfUMyr+aIOx9OgNmVbxyWITC+G9Na v5UdMHbMxgfIBpwHdTOidyzlVDzWRApe X-Google-Smtp-Source: ABdhPJxkQK9wa8EAKeJUZV8Gv80qxslUu0aDGjvZsi5a5rtCn9QS93AjUmOYIEaffTe0zniAjkpecuN6BdRu X-Received: from rananta-virt.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:1bcc]) (user=rananta job=sendgmr) by 2002:a17:902:7584:b0:12d:8cb5:c7b8 with SMTP id j4-20020a170902758400b0012d8cb5c7b8mr3462236pll.84.1628889159142; Fri, 13 Aug 2021 14:12:39 -0700 (PDT) Date: Fri, 13 Aug 2021 21:12:06 +0000 In-Reply-To: <20210813211211.2983293-1-rananta@google.com> Message-Id: <20210813211211.2983293-6-rananta@google.com> Mime-Version: 1.0 References: <20210813211211.2983293-1-rananta@google.com> X-Mailer: git-send-email 2.33.0.rc1.237.g0d66db33f3-goog Subject: [PATCH 05/10] KVM: arm64: selftests: Add basic support to generate delays From: Raghavendra Rao Ananta To: Paolo Bonzini , Marc Zyngier Cc: Alexandru Elisei , Suzuki K Poulose , James Morse , Peter Shier , Ricardo Koller , Oliver Upton , Reiji Watanabe , Jing Zhang , Raghavendra Rao Anata , kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Add udelay() support to generate a delay in the guest. The routines are derived and simplified from kernel's arch/arm64/lib/delay.c. Signed-off-by: Raghavendra Rao Ananta --- .../selftests/kvm/include/aarch64/delay.h | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 tools/testing/selftests/kvm/include/aarch64/delay.h diff --git a/tools/testing/selftests/kvm/include/aarch64/delay.h b/tools/testing/selftests/kvm/include/aarch64/delay.h new file mode 100644 index 000000000000..329e4f5079ea --- /dev/null +++ b/tools/testing/selftests/kvm/include/aarch64/delay.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * ARM simple delay routines + */ + +#ifndef SELFTEST_KVM_ARM_DELAY_H +#define SELFTEST_KVM_ARM_DELAY_H + +#include "arch_timer.h" + +static inline void __delay(uint64_t cycles) +{ + enum arch_timer timer = VIRTUAL; + uint64_t start = timer_get_cntct(timer); + + while ((timer_get_cntct(timer) - start) < cycles) + cpu_relax(); +} + +static inline void udelay(unsigned long usec) +{ + __delay(usec_to_cycles(usec)); +} + +#endif /* SELFTEST_KVM_ARM_DELAY_H */ From patchwork Fri Aug 13 21:12:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raghavendra Rao Ananta X-Patchwork-Id: 12436205 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-26.3 required=3.0 tests=BAYES_00,DKIMWL_WL_MED, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT,USER_IN_DEF_DKIM_WL autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B5FE7C4338F for ; Fri, 13 Aug 2021 21:12:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9BF6D6109E for ; Fri, 13 Aug 2021 21:12:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234921AbhHMVNK (ORCPT ); Fri, 13 Aug 2021 17:13:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45676 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234913AbhHMVNJ (ORCPT ); Fri, 13 Aug 2021 17:13:09 -0400 Received: from mail-qv1-xf49.google.com (mail-qv1-xf49.google.com [IPv6:2607:f8b0:4864:20::f49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 36C02C061756 for ; Fri, 13 Aug 2021 14:12:42 -0700 (PDT) Received: by mail-qv1-xf49.google.com with SMTP id n14-20020a0c9d4e0000b0290354a5f8c800so8040710qvf.17 for ; Fri, 13 Aug 2021 14:12:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=hVS0vPea/E7ymOuCPsOem1y67EWYYT9eWBeHAHepsoY=; b=r0k0+ikMP+nOEPjnHb3kh0VDZqt0D+H2nuLUBq14wDIIrLdIEvXnBOSas2Lnh/OyL4 CXCi+1wjWGm+uuzR/+F4+YThArIna/irnOVVvryV+4tMHygQrOUqPqZi8WdxKxJCssC3 GGElclHOo5x66fTisjkXmEvYKFvnK4UYX2rmblaHoaGqTnyhSr03Ife5Q1WvN/6wBlD4 OT8YA8Le1w4fIoD/xTImcX8RrfIzUdwICHA6GscI1DM5iBC0lySuSVTjLB24pJz5dVcL zlwSYVMEvXdGNUEMSQLHiOeOEvpDdtEH8bg+WJBxGKBxUetDL3jnYAt9sBdzbaWmG3IB xXWg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=hVS0vPea/E7ymOuCPsOem1y67EWYYT9eWBeHAHepsoY=; b=HPTzNOufZiLYa2Q8LBzY8KItSpG6CAcyos7Zu7oG27UePqRbySO11MRKUdxtXL5ZCo KUrts94NGW6fQtXbu8Ad1jyQFnNaWsi0UoNdUZDMiU1K3JfUfm33DPUltZccxoGHMLtU WPEylkTJxSlLDe1N3kpbocA9T1a3vO8zT5X+q0SxIVYboP7U26Jb37rrLoJjMsE71lFk HHMn2kYlvqeIpu95+uxZtV56akH5LJzQ+ZD4RSqrSb4xV8cyPI4QcIxn6Bhb9R2PZEuy mPenT/9lnnJqktMSqvITOMCsJmZKPFpau/39hGHnsgaiVQHnN7ADhAlhrPft1ra0LJ5m wcDQ== X-Gm-Message-State: AOAM530bPl/sG8FbKsAa14p5EOpbqrZ2Fd7YkQKsm6Qm7XJ7DSxpEVxu T6dk8CB+TI61FK9H1RqiPn6pV56yvcCZ X-Google-Smtp-Source: ABdhPJxjPFd/WGD8GEReOFcK3uuVRxEQIBB7zBhKOuKFdJXYU7cQwfdP28cvL37njnXSkd6SSW2+Pj0+Dz7M X-Received: from rananta-virt.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:1bcc]) (user=rananta job=sendgmr) by 2002:a05:6214:ca2:: with SMTP id s2mr4551920qvs.35.1628889161419; Fri, 13 Aug 2021 14:12:41 -0700 (PDT) Date: Fri, 13 Aug 2021 21:12:07 +0000 In-Reply-To: <20210813211211.2983293-1-rananta@google.com> Message-Id: <20210813211211.2983293-7-rananta@google.com> Mime-Version: 1.0 References: <20210813211211.2983293-1-rananta@google.com> X-Mailer: git-send-email 2.33.0.rc1.237.g0d66db33f3-goog Subject: [PATCH 06/10] KVM: arm64: selftests: Add support to disable and enable local IRQs From: Raghavendra Rao Ananta To: Paolo Bonzini , Marc Zyngier Cc: Alexandru Elisei , Suzuki K Poulose , James Morse , Peter Shier , Ricardo Koller , Oliver Upton , Reiji Watanabe , Jing Zhang , Raghavendra Rao Anata , kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Add functions local_irq_enable() and local_irq_disable() to enable and disable the IRQs from the guest, respectively. Signed-off-by: Raghavendra Rao Ananta --- .../testing/selftests/kvm/include/aarch64/processor.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/tools/testing/selftests/kvm/include/aarch64/processor.h b/tools/testing/selftests/kvm/include/aarch64/processor.h index c83ff99282ed..ae7a079ae180 100644 --- a/tools/testing/selftests/kvm/include/aarch64/processor.h +++ b/tools/testing/selftests/kvm/include/aarch64/processor.h @@ -238,4 +238,14 @@ static __always_inline u32 __raw_readl(const volatile void *addr) #define writel(v,c) ({ __iowmb(); writel_relaxed((v),(c));}) #define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(__v); __v; }) +static inline void local_irq_enable(void) +{ + asm volatile("msr daifclr, #3" : : : "memory"); +} + +static inline void local_irq_disable(void) +{ + asm volatile("msr daifset, #3" : : : "memory"); +} + #endif /* SELFTEST_KVM_PROCESSOR_H */ From patchwork Fri Aug 13 21:12:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raghavendra Rao Ananta X-Patchwork-Id: 12436207 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-26.3 required=3.0 tests=BAYES_00,DKIMWL_WL_MED, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT,USER_IN_DEF_DKIM_WL autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BFD93C4338F for ; Fri, 13 Aug 2021 21:12:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A660D610CC for ; Fri, 13 Aug 2021 21:12:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234915AbhHMVNM (ORCPT ); Fri, 13 Aug 2021 17:13:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45694 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234879AbhHMVNL (ORCPT ); Fri, 13 Aug 2021 17:13:11 -0400 Received: from mail-pl1-x64a.google.com (mail-pl1-x64a.google.com [IPv6:2607:f8b0:4864:20::64a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 550EDC061756 for ; Fri, 13 Aug 2021 14:12:44 -0700 (PDT) Received: by mail-pl1-x64a.google.com with SMTP id u12-20020a170902e80c00b0012da2362222so394486plg.8 for ; Fri, 13 Aug 2021 14:12:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=X215a34XlYY9pGUGC8FkhsQTh0Gsxzcj/XXjeeVpyoQ=; b=MhG5TU2H2ct2ePotEwsSicyPDViGj0p0dNgvzvpHXfmVNKqBmc1ZjQmPtVVAonuJde BU+CeTRJkh0LBh+ubPpNFVTSxgKARa20AUTl8UQiMdHKXlAEYg7RnMQBmXry/Jq7tX6E HyjPLsCcwyg3Zm1H7xPkB/no+Ap0vtPMhCs6M7l5NmkCSDM3W+D9gq/VGH4//+udAhr5 ZNR5VqLEllVpwMz9aoouLjSaz6VtfrwP4iv5p7fAAyZO0G3qasezZh7DVxHXqG67ICIg Q3oz6prc8gemBfCQX6JsypAqCGtUl0xbSekKnIyYMTtb6sBPimMXP1uueLUXJ7ixrNba liOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=X215a34XlYY9pGUGC8FkhsQTh0Gsxzcj/XXjeeVpyoQ=; b=uF1ukMRsnn0ryEk9vm6r0VOR9+ounRRw4nZX7GAe+cecAZ5fxH1FKjHkXRi6ZASDVL bZT5I5F3Vk6TdHPTXEQ58gUdAj9TeUFXSnoYuyP99JlecoaiYKbrf0nuHbHPplMg16vQ 6GMmlgtRdejnREYOezUezaaluz86qK0O7Glz6FCG91OXUc5ddL0GmYX3SBq+expUuFIA Qb/sSeX4UtrZNBaNH4MmNrLjtXYHEaAndAM9N/N+GzzAYI940jYI7/m+lcaXR/jqsGj1 l6R/3wCpJiajH/oHdyfyGIJFDg4BhYXCuuCnXC3FsKuv2nFbQPwGUyCecSehwQVf9Utl 9LPw== X-Gm-Message-State: AOAM530zd/IvR/TnsGxFf4ps/ylNwNYMhhYIJ/f9RF2GA0yrq8k+gn8+ VzSOjGi0qDyLGpwTz7+zpzSRhzh4yzJN X-Google-Smtp-Source: ABdhPJwH9oPaXtIBXMnqXUclGdeHpy/TJgguUlPX0A6ayjUbxiIAsAwI3OwGGCxv8ROPipGomDhawmTskznH X-Received: from rananta-virt.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:1bcc]) (user=rananta job=sendgmr) by 2002:a17:90a:de16:: with SMTP id m22mr4506677pjv.54.1628889163792; Fri, 13 Aug 2021 14:12:43 -0700 (PDT) Date: Fri, 13 Aug 2021 21:12:08 +0000 In-Reply-To: <20210813211211.2983293-1-rananta@google.com> Message-Id: <20210813211211.2983293-8-rananta@google.com> Mime-Version: 1.0 References: <20210813211211.2983293-1-rananta@google.com> X-Mailer: git-send-email 2.33.0.rc1.237.g0d66db33f3-goog Subject: [PATCH 07/10] KVM: arm64: selftests: Add support to get the vcpuid from MPIDR_EL1 From: Raghavendra Rao Ananta To: Paolo Bonzini , Marc Zyngier Cc: Alexandru Elisei , Suzuki K Poulose , James Morse , Peter Shier , Ricardo Koller , Oliver Upton , Reiji Watanabe , Jing Zhang , Raghavendra Rao Anata , kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org At times, such as when in the interrupt handler, the guest wants to get the vCPU-id that it's running on. As a result, introduce get_vcpuid() that parses the MPIDR_EL1 and returns the vcpuid to the requested caller. Signed-off-by: Raghavendra Rao Ananta --- .../selftests/kvm/include/aarch64/processor.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/tools/testing/selftests/kvm/include/aarch64/processor.h b/tools/testing/selftests/kvm/include/aarch64/processor.h index ae7a079ae180..e9342e63d05d 100644 --- a/tools/testing/selftests/kvm/include/aarch64/processor.h +++ b/tools/testing/selftests/kvm/include/aarch64/processor.h @@ -248,4 +248,23 @@ static inline void local_irq_disable(void) asm volatile("msr daifset, #3" : : : "memory"); } +#define MPIDR_LEVEL_BITS 8 +#define MPIDR_LEVEL_SHIFT(level) (MPIDR_LEVEL_BITS * level) +#define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1) +#define MPIDR_AFFINITY_LEVEL(mpidr, level) \ + ((mpidr >> MPIDR_LEVEL_SHIFT(level)) & MPIDR_LEVEL_MASK) + +static inline uint32_t get_vcpuid(void) +{ + uint32_t vcpuid = 0; + uint64_t mpidr = read_sysreg(mpidr_el1); + + /* KVM limits only 16 vCPUs at level 0 */ + vcpuid = mpidr & 0x0f; + vcpuid |= MPIDR_AFFINITY_LEVEL(mpidr, 1) << 4; + vcpuid |= MPIDR_AFFINITY_LEVEL(mpidr, 2) << 12; + + return vcpuid; +} + #endif /* SELFTEST_KVM_PROCESSOR_H */ From patchwork Fri Aug 13 21:12:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raghavendra Rao Ananta X-Patchwork-Id: 12436209 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-26.3 required=3.0 tests=BAYES_00,DKIMWL_WL_MED, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT,USER_IN_DEF_DKIM_WL autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DBEEEC4338F for ; Fri, 13 Aug 2021 21:12:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BF7D3610CC for ; Fri, 13 Aug 2021 21:12:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234950AbhHMVNO (ORCPT ); Fri, 13 Aug 2021 17:13:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45712 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234934AbhHMVNN (ORCPT ); Fri, 13 Aug 2021 17:13:13 -0400 Received: from mail-pj1-x104a.google.com (mail-pj1-x104a.google.com [IPv6:2607:f8b0:4864:20::104a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6F67DC061756 for ; Fri, 13 Aug 2021 14:12:46 -0700 (PDT) Received: by mail-pj1-x104a.google.com with SMTP id gc3-20020a17090b3103b0290178c33479a3so998403pjb.7 for ; Fri, 13 Aug 2021 14:12:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=wYh8smn48aXYYcSZU2IfL26LMTAImxlTzaqpMoQB+vI=; b=iIGAVHZKcKykf2UqiNJ/VKf7aiay1nVLZHYOH8PaIA8fPmijWDk+FHZsqqA1SiHX1t P+ZdTARp1CHBoyv6p3tP0h77nFP0nImCCGLPusXOJimW2BlBJ7ge9ulg4sbg7sIPHzIE EcbnAXDoIhPtUK749za3Ou+LVywp2EKagHgVYHInRj39M9zUKkxzOx6QGK+xUHzDF/5W xV6ujJ9gZojENTSzqheUUk6LJaXSzTvR/ufOk8Gi+IoEI4fXdchr84z9es0nrmSwGmZT PYAQE9UKwZIs5nMxlKSLnuBvCHO6mgErDKed8ZcgUDSNC7NYvBt92cfdBp+SCvfoPCio s16w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=wYh8smn48aXYYcSZU2IfL26LMTAImxlTzaqpMoQB+vI=; b=CHiX39ujKGQCDhFxlKsxSUtLSbLG2gXmBviNPy43SLKdH8i5rQooum3GCOzZ7f5mBl +FZVyi73vQiDO8+EnUKN3YQLL36JiBrmjBQXJJs/YZcPuiineFUUnaw9g3v+jMoSaEB/ YyC7TfVXhSHUCLoRcDAcrx8MnsWVIQyXaBhDUxBjWiRzIUpmz1jSc6hAmtq3lFpXwwLB uJKFzXQlhCKYcsjJ3ohh7/34ii93iG94WpST60McaF5kqV7OZNo9vCrzJptd7c+PAxlq uf2hQcoxR3zr8mIgzapnF/vBOpHFzADyFDbLoqgw4keP7ImMSiQcIjMgHRN3Ron0cN93 HF5g== X-Gm-Message-State: AOAM532yLabTVEQRJD7eAd6ja7mybvhVtvnoizoZo72RhvAR+YDIg2dx wnl+8fCqtBQN0iTH4jVJlDIE9mzW1ng5 X-Google-Smtp-Source: ABdhPJzUyv3Nks/6akzkm7bz9MQ715ZbZPPEn21lRfbkNUcq/rc2orF4f9CipW4kCxAi5eDudD/vFX39FKh3 X-Received: from rananta-virt.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:1bcc]) (user=rananta job=sendgmr) by 2002:a62:ee16:0:b029:2fe:ffcf:775a with SMTP id e22-20020a62ee160000b02902feffcf775amr4111078pfi.59.1628889165936; Fri, 13 Aug 2021 14:12:45 -0700 (PDT) Date: Fri, 13 Aug 2021 21:12:09 +0000 In-Reply-To: <20210813211211.2983293-1-rananta@google.com> Message-Id: <20210813211211.2983293-9-rananta@google.com> Mime-Version: 1.0 References: <20210813211211.2983293-1-rananta@google.com> X-Mailer: git-send-email 2.33.0.rc1.237.g0d66db33f3-goog Subject: [PATCH 08/10] KVM: arm64: selftests: Add light-weight spinlock support From: Raghavendra Rao Ananta To: Paolo Bonzini , Marc Zyngier Cc: Alexandru Elisei , Suzuki K Poulose , James Morse , Peter Shier , Ricardo Koller , Oliver Upton , Reiji Watanabe , Jing Zhang , Raghavendra Rao Anata , kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Add a simpler version of spinlock support for ARM64 for the guests to use. The implementation is loosely based on the spinlock implementation in kvm-unit-tests. Signed-off-by: Raghavendra Rao Ananta --- tools/testing/selftests/kvm/Makefile | 2 +- .../selftests/kvm/include/aarch64/spinlock.h | 13 +++++++++ .../selftests/kvm/lib/aarch64/spinlock.c | 27 +++++++++++++++++++ 3 files changed, 41 insertions(+), 1 deletion(-) create mode 100644 tools/testing/selftests/kvm/include/aarch64/spinlock.h create mode 100644 tools/testing/selftests/kvm/lib/aarch64/spinlock.c diff --git a/tools/testing/selftests/kvm/Makefile b/tools/testing/selftests/kvm/Makefile index 5832f510a16c..8f6d82b570bd 100644 --- a/tools/testing/selftests/kvm/Makefile +++ b/tools/testing/selftests/kvm/Makefile @@ -35,7 +35,7 @@ endif LIBKVM = lib/assert.c lib/elf.c lib/io.c lib/kvm_util.c lib/rbtree.c lib/sparsebit.c lib/test_util.c lib/guest_modes.c lib/perf_test_util.c LIBKVM_x86_64 = lib/x86_64/apic.c lib/x86_64/processor.c lib/x86_64/vmx.c lib/x86_64/svm.c lib/x86_64/ucall.c lib/x86_64/handlers.S -LIBKVM_aarch64 = lib/aarch64/processor.c lib/aarch64/ucall.c lib/aarch64/handlers.S +LIBKVM_aarch64 = lib/aarch64/processor.c lib/aarch64/ucall.c lib/aarch64/handlers.S lib/aarch64/spinlock.c LIBKVM_s390x = lib/s390x/processor.c lib/s390x/ucall.c lib/s390x/diag318_test_handler.c TEST_GEN_PROGS_x86_64 = x86_64/cr4_cpuid_sync_test diff --git a/tools/testing/selftests/kvm/include/aarch64/spinlock.h b/tools/testing/selftests/kvm/include/aarch64/spinlock.h new file mode 100644 index 000000000000..cf0984106d14 --- /dev/null +++ b/tools/testing/selftests/kvm/include/aarch64/spinlock.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef SELFTEST_KVM_ARM64_SPINLOCK_H +#define SELFTEST_KVM_ARM64_SPINLOCK_H + +struct spinlock { + int v; +}; + +extern void spin_lock(struct spinlock *lock); +extern void spin_unlock(struct spinlock *lock); + +#endif /* SELFTEST_KVM_ARM64_SPINLOCK_H */ diff --git a/tools/testing/selftests/kvm/lib/aarch64/spinlock.c b/tools/testing/selftests/kvm/lib/aarch64/spinlock.c new file mode 100644 index 000000000000..6d66a3dac237 --- /dev/null +++ b/tools/testing/selftests/kvm/lib/aarch64/spinlock.c @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * ARM64 Spinlock support + */ +#include + +#include "spinlock.h" + +void spin_lock(struct spinlock *lock) +{ + uint32_t val, res; + + asm volatile( + "1: ldaxr %w0, [%2]\n" + " cbnz %w0, 1b\n" + " mov %w0, #1\n" + " stxr %w1, %w0, [%2]\n" + " cbnz %w1, 1b\n" + : "=&r" (val), "=&r" (res) + : "r" (&lock->v) + : "memory"); +} + +void spin_unlock(struct spinlock *lock) +{ + asm volatile("stlr wzr, [%0]\n" : : "r" (&lock->v) : "memory"); +} From patchwork Fri Aug 13 21:12:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raghavendra Rao Ananta X-Patchwork-Id: 12436211 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-26.3 required=3.0 tests=BAYES_00,DKIMWL_WL_MED, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT,USER_IN_DEF_DKIM_WL autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A7AD9C4338F for ; Fri, 13 Aug 2021 21:12:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 90D3F610E9 for ; Fri, 13 Aug 2021 21:12:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234970AbhHMVNR (ORCPT ); Fri, 13 Aug 2021 17:13:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45726 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234879AbhHMVNQ (ORCPT ); Fri, 13 Aug 2021 17:13:16 -0400 Received: from mail-qt1-x849.google.com (mail-qt1-x849.google.com [IPv6:2607:f8b0:4864:20::849]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 14837C061756 for ; Fri, 13 Aug 2021 14:12:49 -0700 (PDT) Received: by mail-qt1-x849.google.com with SMTP id w19-20020ac87e930000b029025a2609eb04so7178970qtj.17 for ; Fri, 13 Aug 2021 14:12:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=20nnTTofiyqiR0MYfZASFsaMi6XXnagQj9CoOJhUpDE=; b=W84r/WbQROS97TfVSzR/YWI5jrvoVQIor7OTEG2eA8scgwi6fnei0IYdTS1MGbj76N QokpLDlar9C6AVMiqvbbm1/mloOB83x/LZQD151PDruMkLeCsQYqjK5Z4nzU67aTH95U oPBBWW2JYxiAx8Sy0xlOm6WwCZMVHWIB2iVCEmFuyxpWKtY08vApJqBM+rOsrZ2V2opS 0JXOtNnSJTb1g1WbWINAFSpClV2quCxYfaWDbZHhZBBURjo/OPTIfG5qbtiycQrVVVOa 6qFUdg/GxGzFkRg/HbO53y/7WpUWIjrEAlKPel2viFF9eTFyJQJOmnMCoXddqcJz7fbC kL5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=20nnTTofiyqiR0MYfZASFsaMi6XXnagQj9CoOJhUpDE=; b=RXPlXU4ORUq5XuDhe6CSc1k/vhTLmxLKOyW7cE7IwCUhklFZOuyC7EgEZuJO/bWQZe WrqXqai0OrdUAnFnfaV+giCKSHOUoYwGWl4ovKDL8czva+yMSyHwqu0J1oH9v9zbajMF s4m2HQ/qIyWacMfgOBiNzREdXYfgUT5VaqkMsvjwGGyh2arNszyb6RlmymJFgpzK+twA 2ouxikM6ItA8QgFzJmJkvNKZS/Xzq0t7G9Va4faOwHTgfd1WvQckCQetksDaNNwCCDjD 5yqn6fTTearb/6xe9k/Hysm9VtDWuSx9IlE61tvPUeRIOjZ9cuJdUKQqeF+BMo84XS7P UhIg== X-Gm-Message-State: AOAM532ZNknSXG4mCrOifybMcHfeW7JLkHWi/lA/0G5xTD+K7ygOd+4x Yi6pHX7EzqHx0YeM3KIXcNbsTExP6fSw X-Google-Smtp-Source: ABdhPJzFdC9Lp1Aof6lwk0Nd4+MR6B98F4B6JWSWiJ8WNpEGCWM6lNXNx7ogyrerhNAr+tGrT1kxwPnwg5Ar X-Received: from rananta-virt.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:1bcc]) (user=rananta job=sendgmr) by 2002:a05:6214:500b:: with SMTP id jo11mr4507843qvb.52.1628889168220; Fri, 13 Aug 2021 14:12:48 -0700 (PDT) Date: Fri, 13 Aug 2021 21:12:10 +0000 In-Reply-To: <20210813211211.2983293-1-rananta@google.com> Message-Id: <20210813211211.2983293-10-rananta@google.com> Mime-Version: 1.0 References: <20210813211211.2983293-1-rananta@google.com> X-Mailer: git-send-email 2.33.0.rc1.237.g0d66db33f3-goog Subject: [PATCH 09/10] KVM: arm64: selftests: Add basic GICv3 support From: Raghavendra Rao Ananta To: Paolo Bonzini , Marc Zyngier Cc: Alexandru Elisei , Suzuki K Poulose , James Morse , Peter Shier , Ricardo Koller , Oliver Upton , Reiji Watanabe , Jing Zhang , Raghavendra Rao Anata , kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Add basic support for ARM Generic Interrupt Controller v3. The support provides guests to setup interrupts. The work is inspired from kvm-unit-tests and the kernel's GIC driver (drivers/irqchip/irq-gic-v3.c). Signed-off-by: Raghavendra Rao Ananta --- tools/testing/selftests/kvm/Makefile | 2 +- .../selftests/kvm/include/aarch64/gic.h | 21 ++ tools/testing/selftests/kvm/lib/aarch64/gic.c | 93 +++++++ .../selftests/kvm/lib/aarch64/gic_private.h | 21 ++ .../selftests/kvm/lib/aarch64/gic_v3.c | 240 ++++++++++++++++++ .../selftests/kvm/lib/aarch64/gic_v3.h | 70 +++++ 6 files changed, 446 insertions(+), 1 deletion(-) create mode 100644 tools/testing/selftests/kvm/include/aarch64/gic.h create mode 100644 tools/testing/selftests/kvm/lib/aarch64/gic.c create mode 100644 tools/testing/selftests/kvm/lib/aarch64/gic_private.h create mode 100644 tools/testing/selftests/kvm/lib/aarch64/gic_v3.c create mode 100644 tools/testing/selftests/kvm/lib/aarch64/gic_v3.h diff --git a/tools/testing/selftests/kvm/Makefile b/tools/testing/selftests/kvm/Makefile index 8f6d82b570bd..a170166334a3 100644 --- a/tools/testing/selftests/kvm/Makefile +++ b/tools/testing/selftests/kvm/Makefile @@ -35,7 +35,7 @@ endif LIBKVM = lib/assert.c lib/elf.c lib/io.c lib/kvm_util.c lib/rbtree.c lib/sparsebit.c lib/test_util.c lib/guest_modes.c lib/perf_test_util.c LIBKVM_x86_64 = lib/x86_64/apic.c lib/x86_64/processor.c lib/x86_64/vmx.c lib/x86_64/svm.c lib/x86_64/ucall.c lib/x86_64/handlers.S -LIBKVM_aarch64 = lib/aarch64/processor.c lib/aarch64/ucall.c lib/aarch64/handlers.S lib/aarch64/spinlock.c +LIBKVM_aarch64 = lib/aarch64/processor.c lib/aarch64/ucall.c lib/aarch64/handlers.S lib/aarch64/spinlock.c lib/aarch64/gic.c lib/aarch64/gic_v3.c LIBKVM_s390x = lib/s390x/processor.c lib/s390x/ucall.c lib/s390x/diag318_test_handler.c TEST_GEN_PROGS_x86_64 = x86_64/cr4_cpuid_sync_test diff --git a/tools/testing/selftests/kvm/include/aarch64/gic.h b/tools/testing/selftests/kvm/include/aarch64/gic.h new file mode 100644 index 000000000000..85dd1e53048e --- /dev/null +++ b/tools/testing/selftests/kvm/include/aarch64/gic.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * ARM Generic Interrupt Controller (GIC) specific defines + */ + +#ifndef SELFTEST_KVM_GIC_H +#define SELFTEST_KVM_GIC_H + +enum gic_type { + GIC_V3, + GIC_TYPE_MAX, +}; + +void gic_init(enum gic_type type, unsigned int nr_cpus, + void *dist_base, void *redist_base); +void gic_irq_enable(unsigned int intid); +void gic_irq_disable(unsigned int intid); +unsigned int gic_get_and_ack_irq(void); +void gic_set_eoi(unsigned int intid); + +#endif /* SELFTEST_KVM_GIC_H */ diff --git a/tools/testing/selftests/kvm/lib/aarch64/gic.c b/tools/testing/selftests/kvm/lib/aarch64/gic.c new file mode 100644 index 000000000000..b0b67f5aeaa6 --- /dev/null +++ b/tools/testing/selftests/kvm/lib/aarch64/gic.c @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * ARM Generic Interrupt Controller (GIC) support + */ + +#include +#include +#include + +#include "kvm_util.h" + +#include +#include "gic_private.h" +#include "processor.h" +#include "spinlock.h" + +static const struct gic_common_ops *gic_common_ops; +static struct spinlock gic_lock; + +static void gic_cpu_init(unsigned int cpu, void *redist_base) +{ + gic_common_ops->gic_cpu_init(cpu, redist_base); +} + +static void +gic_dist_init(enum gic_type type, unsigned int nr_cpus, void *dist_base) +{ + const struct gic_common_ops *gic_ops; + + spin_lock(&gic_lock); + + /* Distributor initialization is needed only once per VM */ + if (gic_common_ops) { + spin_unlock(&gic_lock); + return; + } + + if (type == GIC_V3) + gic_ops = &gicv3_ops; + + gic_ops->gic_init(nr_cpus, dist_base); + gic_common_ops = gic_ops; + + /* Make sure that the initialized data is visible to all the vCPUs */ + dsb(sy); + + spin_unlock(&gic_lock); +} + +void gic_init(enum gic_type type, unsigned int nr_cpus, + void *dist_base, void *redist_base) +{ + uint32_t cpu = get_vcpuid(); + + GUEST_ASSERT(type < GIC_TYPE_MAX); + GUEST_ASSERT(dist_base); + GUEST_ASSERT(redist_base); + GUEST_ASSERT(nr_cpus); + + gic_dist_init(type, nr_cpus, dist_base); + gic_cpu_init(cpu, redist_base); +} + +void gic_irq_enable(unsigned int intid) +{ + GUEST_ASSERT(gic_common_ops); + gic_common_ops->gic_irq_enable(intid); +} + +void gic_irq_disable(unsigned int intid) +{ + GUEST_ASSERT(gic_common_ops); + gic_common_ops->gic_irq_disable(intid); +} + +unsigned int gic_get_and_ack_irq(void) +{ + uint64_t irqstat; + unsigned int intid; + + GUEST_ASSERT(gic_common_ops); + + irqstat = gic_common_ops->gic_read_iar(); + intid = irqstat & GENMASK(23, 0); + + return intid; +} + +void gic_set_eoi(unsigned int intid) +{ + GUEST_ASSERT(gic_common_ops); + gic_common_ops->gic_write_eoir(intid); +} diff --git a/tools/testing/selftests/kvm/lib/aarch64/gic_private.h b/tools/testing/selftests/kvm/lib/aarch64/gic_private.h new file mode 100644 index 000000000000..d81d739433dc --- /dev/null +++ b/tools/testing/selftests/kvm/lib/aarch64/gic_private.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * ARM Generic Interrupt Controller (GIC) private defines that's only + * shared among the GIC library code. + */ + +#ifndef SELFTEST_KVM_GIC_PRIVATE_H +#define SELFTEST_KVM_GIC_PRIVATE_H + +struct gic_common_ops { + void (*gic_init)(unsigned int nr_cpus, void *dist_base); + void (*gic_cpu_init)(unsigned int cpu, void *redist_base); + void (*gic_irq_enable)(unsigned int intid); + void (*gic_irq_disable)(unsigned int intid); + uint64_t (*gic_read_iar)(void); + void (*gic_write_eoir)(uint32_t irq); +}; + +extern const struct gic_common_ops gicv3_ops; + +#endif /* SELFTEST_KVM_GIC_PRIVATE_H */ diff --git a/tools/testing/selftests/kvm/lib/aarch64/gic_v3.c b/tools/testing/selftests/kvm/lib/aarch64/gic_v3.c new file mode 100644 index 000000000000..4b635ca6a8cb --- /dev/null +++ b/tools/testing/selftests/kvm/lib/aarch64/gic_v3.c @@ -0,0 +1,240 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * ARM Generic Interrupt Controller (GIC) v3 support + */ + +#include + +#include "kvm_util.h" +#include "processor.h" +#include "delay.h" + +#include "gic_v3.h" +#include "gic_private.h" + +struct gicv3_data { + void *dist_base; + void *redist_base[GICV3_MAX_CPUS]; + unsigned int nr_cpus; + unsigned int nr_spis; +}; + +#define sgi_base_from_redist(redist_base) (redist_base + SZ_64K) + +enum gicv3_intid_range { + SGI_RANGE, + PPI_RANGE, + SPI_RANGE, + INVALID_RANGE, +}; + +static struct gicv3_data gicv3_data; + +static void gicv3_gicd_wait_for_rwp(void) +{ + unsigned int count = 100000; /* 1s */ + + while (readl(gicv3_data.dist_base + GICD_CTLR) & GICD_CTLR_RWP) { + GUEST_ASSERT(count--); + udelay(10); + } +} + +static void gicv3_gicr_wait_for_rwp(void *redist_base) +{ + unsigned int count = 100000; /* 1s */ + + while (readl(redist_base + GICR_CTLR) & GICR_CTLR_RWP) { + GUEST_ASSERT(count--); + udelay(10); + } +} + +static enum gicv3_intid_range get_intid_range(unsigned int intid) +{ + switch (intid) { + case 0 ... 15: + return SGI_RANGE; + case 16 ... 31: + return PPI_RANGE; + case 32 ... 1019: + return SPI_RANGE; + } + + /* We should not be reaching here */ + GUEST_ASSERT(0); + + return INVALID_RANGE; +} + +static uint64_t gicv3_read_iar(void) +{ + uint64_t irqstat = read_sysreg_s(SYS_ICC_IAR1_EL1); + + dsb(sy); + return irqstat; +} + +static void gicv3_write_eoir(uint32_t irq) +{ + write_sysreg_s(SYS_ICC_EOIR1_EL1, irq); + isb(); +} + +static void +gicv3_config_irq(unsigned int intid, unsigned int offset) +{ + uint32_t cpu = get_vcpuid(); + uint32_t mask = 1 << (intid % 32); + enum gicv3_intid_range intid_range = get_intid_range(intid); + void *reg; + + /* We care about 'cpu' only for SGIs or PPIs */ + if (intid_range == SGI_RANGE || intid_range == PPI_RANGE) { + GUEST_ASSERT(cpu < gicv3_data.nr_cpus); + + reg = sgi_base_from_redist(gicv3_data.redist_base[cpu]) + + offset; + writel(mask, reg); + gicv3_gicr_wait_for_rwp(gicv3_data.redist_base[cpu]); + } else if (intid_range == SPI_RANGE) { + reg = gicv3_data.dist_base + offset + (intid / 32) * 4; + writel(mask, reg); + gicv3_gicd_wait_for_rwp(); + } else { + GUEST_ASSERT(0); + } +} + +static void gicv3_irq_enable(unsigned int intid) +{ + gicv3_config_irq(intid, GICD_ISENABLER); +} + +static void gicv3_irq_disable(unsigned int intid) +{ + gicv3_config_irq(intid, GICD_ICENABLER); +} + +static void gicv3_enable_redist(void *redist_base) +{ + uint32_t val = readl(redist_base + GICR_WAKER); + unsigned int count = 100000; /* 1s */ + + val &= ~GICR_WAKER_ProcessorSleep; + writel(val, redist_base + GICR_WAKER); + + /* Wait until the processor is 'active' */ + while (readl(redist_base + GICR_WAKER) & GICR_WAKER_ChildrenAsleep) { + GUEST_ASSERT(count--); + udelay(10); + } +} + +static inline void *gicr_base_gpa_cpu(void *redist_base, uint32_t cpu) +{ + /* Align all the redistributors sequentially */ + return redist_base + cpu * SZ_64K * 2; +} + +static void gicv3_cpu_init(unsigned int cpu, void *redist_base) +{ + void *sgi_base; + unsigned int i; + void *redist_base_cpu; + + GUEST_ASSERT(cpu < gicv3_data.nr_cpus); + + redist_base_cpu = gicr_base_gpa_cpu(redist_base, cpu); + sgi_base = sgi_base_from_redist(redist_base_cpu); + + gicv3_enable_redist(redist_base_cpu); + + /* + * Mark all the SGI and PPI interrupts as non-secure Group-1. + * Also, deactivate and disable them. + */ + writel(~0, sgi_base + GICR_IGROUPR0); + writel(~0, sgi_base + GICR_ICACTIVER0); + writel(~0, sgi_base + GICR_ICENABLER0); + + /* Set a default priority for all the SGIs and PPIs */ + for (i = 0; i < 32; i += 4) + writel(GICD_INT_DEF_PRI_X4, + sgi_base + GICR_IPRIORITYR0 + i); + + gicv3_gicr_wait_for_rwp(redist_base_cpu); + + /* Enable the GIC system register (ICC_*) access */ + write_sysreg_s(SYS_ICC_SRE_EL1, + read_sysreg_s(SYS_ICC_SRE_EL1) | ICC_SRE_EL1_SRE); + + /* Set a default priority threshold */ + write_sysreg_s(SYS_ICC_PMR_EL1, ICC_PMR_DEF_PRIO); + + /* Enable non-secure Group-1 interrupts */ + write_sysreg_s(SYS_ICC_GRPEN1_EL1, ICC_IGRPEN1_EL1_ENABLE); + + gicv3_data.redist_base[cpu] = redist_base_cpu; +} + +static void gicv3_dist_init(void) +{ + void *dist_base = gicv3_data.dist_base; + unsigned int i; + + /* Disable the distributor until we set things up */ + writel(0, dist_base + GICD_CTLR); + gicv3_gicd_wait_for_rwp(); + + /* + * Mark all the SPI interrupts as non-secure Group-1. + * Also, deactivate and disable them. + */ + for (i = 32; i < gicv3_data.nr_spis; i += 32) { + writel(~0, dist_base + GICD_IGROUPR + i / 8); + writel(~0, dist_base + GICD_ICACTIVER + i / 8); + writel(~0, dist_base + GICD_ICENABLER + i / 8); + } + + /* Set a default priority for all the SPIs */ + for (i = 32; i < gicv3_data.nr_spis; i += 4) + writel(GICD_INT_DEF_PRI_X4, + dist_base + GICD_IPRIORITYR + i); + + /* Wait for the settings to sync-in */ + gicv3_gicd_wait_for_rwp(); + + /* Finally, enable the distributor globally with ARE */ + writel(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | + GICD_CTLR_ENABLE_G1, dist_base + GICD_CTLR); + gicv3_gicd_wait_for_rwp(); +} + +static void gicv3_init(unsigned int nr_cpus, void *dist_base) +{ + GUEST_ASSERT(nr_cpus <= GICV3_MAX_CPUS); + + gicv3_data.nr_cpus = nr_cpus; + gicv3_data.dist_base = dist_base; + gicv3_data.nr_spis = GICD_TYPER_SPIS( + readl(gicv3_data.dist_base + GICD_TYPER)); + if (gicv3_data.nr_spis > 1020) + gicv3_data.nr_spis = 1020; + + /* + * Initialize only the distributor for now. + * The redistributor and CPU interfaces are initialized + * later for every PE. + */ + gicv3_dist_init(); +} + +const struct gic_common_ops gicv3_ops = { + .gic_init = gicv3_init, + .gic_cpu_init = gicv3_cpu_init, + .gic_irq_enable = gicv3_irq_enable, + .gic_irq_disable = gicv3_irq_disable, + .gic_read_iar = gicv3_read_iar, + .gic_write_eoir = gicv3_write_eoir, +}; diff --git a/tools/testing/selftests/kvm/lib/aarch64/gic_v3.h b/tools/testing/selftests/kvm/lib/aarch64/gic_v3.h new file mode 100644 index 000000000000..d41195e347b3 --- /dev/null +++ b/tools/testing/selftests/kvm/lib/aarch64/gic_v3.h @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * ARM Generic Interrupt Controller (GIC) v3 specific defines + */ + +#ifndef SELFTEST_KVM_GICV3_H +#define SELFTEST_KVM_GICV3_H + +#include "processor.h" + +/* + * Distributor registers + */ +#define GICD_CTLR 0x0000 +#define GICD_TYPER 0x0004 +#define GICD_IGROUPR 0x0080 +#define GICD_ISENABLER 0x0100 +#define GICD_ICENABLER 0x0180 +#define GICD_ICACTIVER 0x0380 +#define GICD_IPRIORITYR 0x0400 + +/* + * The assumption is that the guest runs in a non-secure mode. + * The following bits of GICD_CTLR are defined accordingly. + */ +#define GICD_CTLR_RWP (1U << 31) +#define GICD_CTLR_nASSGIreq (1U << 8) +#define GICD_CTLR_ARE_NS (1U << 4) +#define GICD_CTLR_ENABLE_G1A (1U << 1) +#define GICD_CTLR_ENABLE_G1 (1U << 0) + +#define GICD_TYPER_SPIS(typer) ((((typer) & 0x1f) + 1) * 32) +#define GICD_INT_DEF_PRI_X4 0xa0a0a0a0 + +/* + * Redistributor registers + */ +#define GICR_CTLR 0x000 +#define GICR_WAKER 0x014 + +#define GICR_CTLR_RWP (1U << 3) + +#define GICR_WAKER_ProcessorSleep (1U << 1) +#define GICR_WAKER_ChildrenAsleep (1U << 2) + +/* + * Redistributor registers, offsets from SGI base + */ +#define GICR_IGROUPR0 GICD_IGROUPR +#define GICR_ISENABLER0 GICD_ISENABLER +#define GICR_ICENABLER0 GICD_ICENABLER +#define GICR_ICACTIVER0 GICD_ICACTIVER +#define GICR_IPRIORITYR0 GICD_IPRIORITYR + +/* CPU interface registers */ +#define SYS_ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0) +#define SYS_ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0) +#define SYS_ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1) +#define SYS_ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5) +#define SYS_ICC_GRPEN1_EL1 sys_reg(3, 0, 12, 12, 7) + +#define ICC_PMR_DEF_PRIO 0xf0 + +#define ICC_SRE_EL1_SRE (1U << 0) + +#define ICC_IGRPEN1_EL1_ENABLE (1U << 0) + +#define GICV3_MAX_CPUS 512 + +#endif /* SELFTEST_KVM_GICV3_H */ From patchwork Fri Aug 13 21:12:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raghavendra Rao Ananta X-Patchwork-Id: 12436213 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-26.3 required=3.0 tests=BAYES_00,DKIMWL_WL_MED, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT,USER_IN_DEF_DKIM_WL autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id ADC24C432BE for ; Fri, 13 Aug 2021 21:12:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9020E6109D for ; Fri, 13 Aug 2021 21:12:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234965AbhHMVNS (ORCPT ); Fri, 13 Aug 2021 17:13:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45740 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234869AbhHMVNR (ORCPT ); Fri, 13 Aug 2021 17:13:17 -0400 Received: from mail-pj1-x1049.google.com (mail-pj1-x1049.google.com [IPv6:2607:f8b0:4864:20::1049]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C2572C0617AD for ; Fri, 13 Aug 2021 14:12:50 -0700 (PDT) Received: by mail-pj1-x1049.google.com with SMTP id ns7-20020a17090b250700b0017942fa12a8so1972474pjb.6 for ; Fri, 13 Aug 2021 14:12:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=G8SpNklEDZWajysk0gZLosfORko9hc4kc79cXySk3Ng=; b=te995Ch00FZ0gjGdkMGLgFbe7TXP7g1Rv/GrpzPLtcdaGIyNy9lkgzoGVjBP/QR0N+ UlYyALrPXx+ZoOh4sfBGfXNduaHACoxiZNgbAEExvDwcfc99H8G8mZN7dfWIIscV+3XO Z5OizBSHllnL1eIxV08NfClj2ucUAFdOPkQx3Bd51XaFEzbF+qvTrtx7h+wH+hwp5e+/ BicFzNKd2FPGGeHmMGqcUt0oiEdxDIbLMBOIZI4N7leG2ncLegZF8vZ42ja7gnt/GNch sx177eayKyEFCKEbvCm8GezLatcMffem/tArPTvQTFHXbkS976aTp/xNt0h6se3btnRN cEUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=G8SpNklEDZWajysk0gZLosfORko9hc4kc79cXySk3Ng=; b=fdYglozPVWY9/1sEIvTj186Xpzma+UEbeVhL+6wbN6blpIhjvtJL55SIPact/OQ9Ht 8PWbteBNvQadsbGGyfnZb6jch23XntCnK6ipQmavaVLfc0oY74++9/YCC9S6o2XhMtgg jFeTQH6AK38NGpEvRDeaxfvhXiFerprS1DUw+XaXCbQjo+2X5nED+ILsLEadErNMonjS xFw4E6OhY3mqG4A5XhXOw96XOFsS0IdmiRjOhwgNgf6NtDCEzbPDRTSlzAinvSo5058d Mdk4ArM1VQY/9sZeZqFhIwCtf24IcNK9VDPmH4mWUX1EWroXp5BSUFtkpTGSrX/GckfK 6TIA== X-Gm-Message-State: AOAM530JkCXZZd7gO2eb/MMrjoM23Aety3rl46Uw5fEUn2Pupb0NwjIp QIPMrdFI+XXo9jMHM1n4cW7Y8GkBPDnK X-Google-Smtp-Source: ABdhPJyMjF8bW4sy6zLMrThCIRtDh7EctW3PLnLa7CBRv24Q/pJlM+2FIWfX//7yqYfZuRgRYtFb2urVUM8N X-Received: from rananta-virt.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:1bcc]) (user=rananta job=sendgmr) by 2002:a17:90a:9308:: with SMTP id p8mr4388738pjo.119.1628889170335; Fri, 13 Aug 2021 14:12:50 -0700 (PDT) Date: Fri, 13 Aug 2021 21:12:11 +0000 In-Reply-To: <20210813211211.2983293-1-rananta@google.com> Message-Id: <20210813211211.2983293-11-rananta@google.com> Mime-Version: 1.0 References: <20210813211211.2983293-1-rananta@google.com> X-Mailer: git-send-email 2.33.0.rc1.237.g0d66db33f3-goog Subject: [PATCH 10/10] KVM: arm64: selftests: Add arch_timer test From: Raghavendra Rao Ananta To: Paolo Bonzini , Marc Zyngier Cc: Alexandru Elisei , Suzuki K Poulose , James Morse , Peter Shier , Ricardo Koller , Oliver Upton , Reiji Watanabe , Jing Zhang , Raghavendra Rao Anata , kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Add a KVM selftest to validate the arch_timer functionality. Primarily, the test sets up periodic timer interrupts and validates the basic architectural expectations upon its receipt. The test provides command-line options to configure the period of the timer, number of iterations, and number of vCPUs. Signed-off-by: Raghavendra Rao Ananta --- tools/testing/selftests/kvm/.gitignore | 1 + tools/testing/selftests/kvm/Makefile | 1 + .../selftests/kvm/aarch64/arch_timer.c | 382 ++++++++++++++++++ 3 files changed, 384 insertions(+) create mode 100644 tools/testing/selftests/kvm/aarch64/arch_timer.c diff --git a/tools/testing/selftests/kvm/.gitignore b/tools/testing/selftests/kvm/.gitignore index 0709af0144c8..5f6cf0c76cf8 100644 --- a/tools/testing/selftests/kvm/.gitignore +++ b/tools/testing/selftests/kvm/.gitignore @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only +/aarch64/arch_timer /aarch64/debug-exceptions /aarch64/get-reg-list /aarch64/vgic_init diff --git a/tools/testing/selftests/kvm/Makefile b/tools/testing/selftests/kvm/Makefile index a170166334a3..62a2c3e4b50c 100644 --- a/tools/testing/selftests/kvm/Makefile +++ b/tools/testing/selftests/kvm/Makefile @@ -84,6 +84,7 @@ TEST_GEN_PROGS_x86_64 += set_memory_region_test TEST_GEN_PROGS_x86_64 += steal_time TEST_GEN_PROGS_x86_64 += kvm_binary_stats_test +TEST_GEN_PROGS_aarch64 += aarch64/arch_timer TEST_GEN_PROGS_aarch64 += aarch64/debug-exceptions TEST_GEN_PROGS_aarch64 += aarch64/get-reg-list TEST_GEN_PROGS_aarch64 += aarch64/vgic_init diff --git a/tools/testing/selftests/kvm/aarch64/arch_timer.c b/tools/testing/selftests/kvm/aarch64/arch_timer.c new file mode 100644 index 000000000000..88333fe1e567 --- /dev/null +++ b/tools/testing/selftests/kvm/aarch64/arch_timer.c @@ -0,0 +1,382 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * arch_timer.c - Tests the aarch64 timer IRQ functionality + * + * The test validates both the virtual and physical timer IRQs using + * CVAL and TVAL registers. This consitutes the four stages in the test. + * The guest's main thread configures the timer interrupt for a stage + * and waits for it to fire, with a timeout equal to the timer period. + * It asserts that the timeout doesn't exceed the timer period. + * + * On the other hand, upon receipt of an interrupt, the guest's interrupt + * handler validates the interrupt by checking if the architectural state + * is in compliance with the specifications. + * + * The test provides command-line options to configure the timer's + * period (-p), number of vCPUs (-n), and iterations per stage (-i). + * + * Copyright (c) 2021, Google LLC. + */ + +#define _GNU_SOURCE + +#include +#include +#include +#include + +#include "kvm_util.h" +#include "processor.h" +#include "delay.h" +#include "arch_timer.h" +#include "gic.h" + +#define NR_VCPUS_DEF 4 +#define NR_TEST_ITERS_DEF 5 +#define TIMER_TEST_PERIOD_MS_DEF 10 +#define TIMER_TEST_ERR_MARGIN_US 100 + +struct test_args { + int nr_vcpus; + int nr_iter; + int timer_period_ms; +}; + +static struct test_args test_args = { + .nr_vcpus = NR_VCPUS_DEF, + .nr_iter = NR_TEST_ITERS_DEF, + .timer_period_ms = TIMER_TEST_PERIOD_MS_DEF, +}; + +#define msecs_to_usecs(msec) ((msec) * 1000LL) + +#define VTIMER_IRQ 27 +#define PTIMER_IRQ 30 + +#define REDIST_REGION_ATTR_ADDR(count, base, flags, index) \ + (((uint64_t)(count) << 52) | \ + ((uint64_t)((base) >> 16) << 16) | \ + ((uint64_t)(flags) << 12) | \ + index) + +#define GICD_BASE_GPA 0x8000000ULL +#define GICR_BASE_GPA 0x80A0000ULL + +enum guest_stage { + GUEST_STAGE_VTIMER_CVAL = 1, + GUEST_STAGE_VTIMER_TVAL, + GUEST_STAGE_PTIMER_CVAL, + GUEST_STAGE_PTIMER_TVAL, + GUEST_STAGE_MAX, +}; + +/* Sahred variables between host and guest */ +struct test_vcpu_shared_data { + int nr_iter; + enum guest_stage guest_stage; + uint64_t xcnt; +}; + +struct test_vcpu { + uint32_t vcpuid; + pthread_t pt_vcpu_run; + struct kvm_vm *vm; +}; + +static struct test_vcpu test_vcpu[KVM_MAX_VCPUS]; +static struct test_vcpu_shared_data vcpu_shared_data[KVM_MAX_VCPUS]; + +static void +guest_configure_timer_action(struct test_vcpu_shared_data *shared_data) +{ + switch (shared_data->guest_stage) { + case GUEST_STAGE_VTIMER_CVAL: + timer_set_next_cval_ms(VIRTUAL, test_args.timer_period_ms); + shared_data->xcnt = timer_get_cntct(VIRTUAL); + timer_set_ctl(VIRTUAL, CTL_ENABLE); + break; + case GUEST_STAGE_VTIMER_TVAL: + timer_set_next_tval_ms(VIRTUAL, test_args.timer_period_ms); + shared_data->xcnt = timer_get_cntct(VIRTUAL); + timer_set_ctl(VIRTUAL, CTL_ENABLE); + break; + case GUEST_STAGE_PTIMER_CVAL: + timer_set_next_cval_ms(PHYSICAL, test_args.timer_period_ms); + shared_data->xcnt = timer_get_cntct(PHYSICAL); + timer_set_ctl(PHYSICAL, CTL_ENABLE); + break; + case GUEST_STAGE_PTIMER_TVAL: + timer_set_next_tval_ms(PHYSICAL, test_args.timer_period_ms); + shared_data->xcnt = timer_get_cntct(PHYSICAL); + timer_set_ctl(PHYSICAL, CTL_ENABLE); + break; + default: + GUEST_ASSERT(0); + } +} + +static void guest_validate_irq(unsigned int intid, + struct test_vcpu_shared_data *shared_data) +{ + enum guest_stage stage = shared_data->guest_stage; + uint64_t xcnt = 0, xcnt_diff_us, cval = 0; + unsigned long xctl = 0; + unsigned int timer_irq = 0; + + if (stage == GUEST_STAGE_VTIMER_CVAL || + stage == GUEST_STAGE_VTIMER_TVAL) { + xctl = timer_get_ctl(VIRTUAL); + timer_set_ctl(VIRTUAL, CTL_IMASK); + xcnt = timer_get_cntct(VIRTUAL); + cval = timer_get_cval(VIRTUAL); + timer_irq = VTIMER_IRQ; + } else if (stage == GUEST_STAGE_PTIMER_CVAL || + stage == GUEST_STAGE_PTIMER_TVAL) { + xctl = timer_get_ctl(PHYSICAL); + timer_set_ctl(PHYSICAL, CTL_IMASK); + xcnt = timer_get_cntct(PHYSICAL); + cval = timer_get_cval(PHYSICAL); + timer_irq = PTIMER_IRQ; + } else { + GUEST_ASSERT(0); + } + + xcnt_diff_us = cycles_to_usec(xcnt - shared_data->xcnt); + + /* Make sure we are dealing with the correct timer IRQ */ + GUEST_ASSERT_2(intid == timer_irq, intid, timer_irq); + + /* Basic 'timer codition met' check */ + GUEST_ASSERT_3(xcnt >= cval, xcnt, cval, xcnt_diff_us); + GUEST_ASSERT_1(xctl & CTL_ISTATUS, xctl); +} + +static void guest_irq_handler(struct ex_regs *regs) +{ + unsigned int intid = gic_get_and_ack_irq(); + uint32_t cpu = get_vcpuid(); + struct test_vcpu_shared_data *shared_data = &vcpu_shared_data[cpu]; + + guest_validate_irq(intid, shared_data); + + WRITE_ONCE(shared_data->nr_iter, shared_data->nr_iter + 1); + + gic_set_eoi(intid); +} + +static void guest_run_stage(struct test_vcpu_shared_data *shared_data, + enum guest_stage stage) +{ + uint32_t irq_iter, config_iter; + + shared_data->guest_stage = stage; + shared_data->nr_iter = 0; + + for (config_iter = 0; config_iter < test_args.nr_iter; config_iter++) { + /* Setup the next interrupt */ + guest_configure_timer_action(shared_data); + + /* Setup a timeout for the interrupt to arrive */ + udelay(msecs_to_usecs(test_args.timer_period_ms) + + TIMER_TEST_ERR_MARGIN_US); + + irq_iter = READ_ONCE(shared_data->nr_iter); + GUEST_ASSERT_2(config_iter + 1 == irq_iter, + config_iter + 1, irq_iter); + }; +} + +static void guest_code(void) +{ + uint32_t cpu = get_vcpuid(); + struct test_vcpu_shared_data *shared_data = &vcpu_shared_data[cpu]; + + local_irq_disable(); + + gic_init(GIC_V3, test_args.nr_vcpus, + (void *)GICD_BASE_GPA, (void *)GICR_BASE_GPA); + + timer_set_ctl(VIRTUAL, CTL_IMASK); + timer_set_ctl(PHYSICAL, CTL_IMASK); + + gic_irq_enable(VTIMER_IRQ); + gic_irq_enable(PTIMER_IRQ); + local_irq_enable(); + + guest_run_stage(shared_data, GUEST_STAGE_VTIMER_CVAL); + guest_run_stage(shared_data, GUEST_STAGE_VTIMER_TVAL); + guest_run_stage(shared_data, GUEST_STAGE_PTIMER_CVAL); + guest_run_stage(shared_data, GUEST_STAGE_PTIMER_TVAL); + + GUEST_DONE(); +} + +static void *test_vcpu_run(void *arg) +{ + struct ucall uc; + struct test_vcpu *vcpu = arg; + struct kvm_vm *vm = vcpu->vm; + uint32_t vcpuid = vcpu->vcpuid; + struct test_vcpu_shared_data *shared_data = &vcpu_shared_data[vcpuid]; + + vcpu_run(vm, vcpuid); + + switch (get_ucall(vm, vcpuid, &uc)) { + case UCALL_SYNC: + case UCALL_DONE: + break; + case UCALL_ABORT: + sync_global_from_guest(vm, *shared_data); + TEST_ASSERT(false, + "%s at %s:%ld\n\tvalues: %lu, %lu; %lu, vcpu: %u; stage: %u; iter: %u", + (const char *)uc.args[0], __FILE__, uc.args[1], + uc.args[2], uc.args[3], uc.args[4], vcpuid, + shared_data->guest_stage, shared_data->nr_iter); + break; + default: + TEST_FAIL("Unexpected guest exit\n"); + } + + return NULL; +} + +static void test_run(struct kvm_vm *vm) +{ + int i, ret; + + for (i = 0; i < test_args.nr_vcpus; i++) { + ret = pthread_create(&test_vcpu[i].pt_vcpu_run, NULL, + test_vcpu_run, &test_vcpu[i]); + TEST_ASSERT(!ret, "Failed to create vCPU-%d pthread\n", i); + } + + for (i = 0; i < test_args.nr_vcpus; i++) + pthread_join(test_vcpu[i].pt_vcpu_run, NULL); +} + +static void test_vm_setup_gic(struct kvm_vm *vm, unsigned int n_gicr_pages) +{ + uint64_t addr; + int gic_fd; + + gic_fd = kvm_create_device(vm, KVM_DEV_TYPE_ARM_VGIC_V3, false); + + addr = GICD_BASE_GPA; + kvm_device_access(gic_fd, KVM_DEV_ARM_VGIC_GRP_ADDR, + KVM_VGIC_V3_ADDR_TYPE_DIST, &addr, true); + virt_pg_map(vm, GICD_BASE_GPA, GICD_BASE_GPA); + + addr = REDIST_REGION_ATTR_ADDR(test_args.nr_vcpus, GICR_BASE_GPA, 0, 0); + kvm_device_access(gic_fd, KVM_DEV_ARM_VGIC_GRP_ADDR, + KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION, &addr, true); + virt_map(vm, GICR_BASE_GPA, GICR_BASE_GPA, n_gicr_pages); + + kvm_device_access(gic_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, + KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true); +} + +static struct kvm_vm *test_vm_create(void) +{ + struct kvm_vm *vm; + unsigned int i, n_gicr_pages; + int nr_vcpus = test_args.nr_vcpus; + + /* Reserve additional pages for GICR MMIO based on nr_vcpus */ + n_gicr_pages = vm_calc_num_guest_pages(VM_MODE_DEFAULT, + 2 * SZ_64K * nr_vcpus); + + vm = vm_create_default_with_vcpus(nr_vcpus, n_gicr_pages, 0, + guest_code, NULL); + + vm_init_descriptor_tables(vm); + vm_install_exception_handler(vm, VECTOR_IRQ_CURRENT, guest_irq_handler); + + for (i = 0; i < nr_vcpus; i++) { + vcpu_init_descriptor_tables(vm, i); + + test_vcpu[i].vcpuid = i; + test_vcpu[i].vm = vm; + } + + ucall_init(vm, NULL); + test_vm_setup_gic(vm, n_gicr_pages); + + /* Make all the test's cmdline args visible to the guest */ + sync_global_to_guest(vm, test_args); + + return vm; +} + +static void test_print_help(char *name) +{ + pr_info("Usage: %s [-h] [-n nr_vcpus] [-i iterations] [-p timer_period_ms]\n", + name); + pr_info("\t-n: Number of vCPUs to configure (default: %u; max: %u)\n", + NR_VCPUS_DEF, KVM_MAX_VCPUS); + pr_info("\t-i: Number of iterations per stage (default: %u)\n", + NR_TEST_ITERS_DEF); + pr_info("\t-p: Periodicity (in ms) of the guest timer (default: %u)\n", + TIMER_TEST_PERIOD_MS_DEF); + pr_info("\t-h: print this help screen\n"); +} + +static bool parse_args(int argc, char *argv[]) +{ + int opt; + + while ((opt = getopt(argc, argv, "hn:i:p:")) != -1) { + switch (opt) { + case 'n': + test_args.nr_vcpus = atoi(optarg); + if (test_args.nr_vcpus <= 0) { + pr_info("Positive value needed for -n\n"); + goto err; + } else if (test_args.nr_vcpus > KVM_MAX_VCPUS) { + pr_info("Max allowed vCPUs: %u\n", + KVM_MAX_VCPUS); + goto err; + } + break; + case 'i': + test_args.nr_iter = atoi(optarg); + if (test_args.nr_iter <= 0) { + pr_info("Positive value needed for -i\n"); + goto err; + } + break; + case 'p': + test_args.timer_period_ms = atoi(optarg); + if (test_args.timer_period_ms <= 0) { + pr_info("Positive value needed for -p\n"); + goto err; + } + break; + case 'h': + default: + goto err; + } + } + + return true; + +err: + test_print_help(argv[0]); + return false; +} + +int main(int argc, char *argv[]) +{ + struct kvm_vm *vm; + + /* Tell stdout not to buffer its content */ + setbuf(stdout, NULL); + + if (!parse_args(argc, argv)) + exit(KSFT_SKIP); + + vm = test_vm_create(); + test_run(vm); + kvm_vm_free(vm); + + return 0; +}