From patchwork Mon Aug 16 04:52:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Siddiqui, Ayaz A" X-Patchwork-Id: 12437725 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D615FC4338F for ; Mon, 16 Aug 2021 04:55:56 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A21B5613AC for ; Mon, 16 Aug 2021 04:55:56 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org A21B5613AC Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 02C0D8995F; Mon, 16 Aug 2021 04:55:56 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id EBCB989BCD for ; Mon, 16 Aug 2021 04:55:42 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10077"; a="215823999" X-IronPort-AV: E=Sophos;i="5.84,324,1620716400"; d="scan'208";a="215823999" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Aug 2021 21:55:42 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.84,324,1620716400"; d="scan'208";a="422739342" Received: from ayazahma-nuc8i7beh.iind.intel.com ([10.145.162.59]) by orsmga006.jf.intel.com with ESMTP; 15 Aug 2021 21:55:40 -0700 From: Ayaz A Siddiqui To: intel-gfx@lists.freedesktop.org Cc: Ayaz A Siddiqui , CQ Tang Date: Mon, 16 Aug 2021 10:22:25 +0530 Message-Id: <20210816045229.423234-2-ayaz.siddiqui@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210816045229.423234-1-ayaz.siddiqui@intel.com> References: <20210816045229.423234-1-ayaz.siddiqui@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH V2 1/5] drm/i915/gt: Add support of mocs propagation X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Now there are lots of Command and registers that require mocs index programming. So propagating mocs_index from mocs to gt so that it can be used directly without having platform-specific checks. Signed-off-by: Ayaz A Siddiqui Reviewed-by: CQ Tang --- drivers/gpu/drm/i915/gt/intel_gt_types.h | 4 ++++ drivers/gpu/drm/i915/gt/intel_mocs.c | 10 ++++++++++ 2 files changed, 14 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h index a81e21bf1bd1a..88601a2d2c229 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h @@ -192,6 +192,10 @@ struct intel_gt { unsigned long mslice_mask; } info; + + struct i915_mocs_index_gt { + u8 uc_index; + } mocs; }; enum intel_gt_scratch_field { diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c index 582c4423b95d6..10cc508c1a4f6 100644 --- a/drivers/gpu/drm/i915/gt/intel_mocs.c +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c @@ -22,6 +22,7 @@ struct drm_i915_mocs_table { unsigned int size; unsigned int n_entries; const struct drm_i915_mocs_entry *table; + u8 uc_index; }; /* Defines for the tables (XXX_MOCS_0 - XXX_MOCS_63) */ @@ -340,6 +341,8 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915, { unsigned int flags; + memset(table, 0, sizeof(struct drm_i915_mocs_table)); + if (IS_DG1(i915)) { table->size = ARRAY_SIZE(dg1_mocs_table); table->table = dg1_mocs_table; @@ -504,6 +507,12 @@ static u32 global_mocs_offset(void) return i915_mmio_reg_offset(GEN12_GLOBAL_MOCS(0)); } +static void set_mocs_index(struct intel_gt *gt, + struct drm_i915_mocs_table *table) +{ + gt->mocs.uc_index = table->uc_index; +} + void intel_mocs_init(struct intel_gt *gt) { struct drm_i915_mocs_table table; @@ -515,6 +524,7 @@ void intel_mocs_init(struct intel_gt *gt) flags = get_mocs_settings(gt->i915, &table); if (flags & HAS_GLOBAL_MOCS) __init_mocs_table(gt->uncore, &table, global_mocs_offset()); + set_mocs_index(gt, &table); } #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) From patchwork Mon Aug 16 04:52:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Siddiqui, Ayaz A" X-Patchwork-Id: 12437731 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1E6B8C4338F for ; Mon, 16 Aug 2021 04:56:03 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DAB1661880 for ; Mon, 16 Aug 2021 04:56:02 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org DAB1661880 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5A7E589BD5; Mon, 16 Aug 2021 04:56:00 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id ED30589BD4 for ; Mon, 16 Aug 2021 04:55:45 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10077"; a="215824001" X-IronPort-AV: E=Sophos;i="5.84,324,1620716400"; d="scan'208";a="215824001" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Aug 2021 21:55:45 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.84,324,1620716400"; d="scan'208";a="422739350" Received: from ayazahma-nuc8i7beh.iind.intel.com ([10.145.162.59]) by orsmga006.jf.intel.com with ESMTP; 15 Aug 2021 21:55:42 -0700 From: Ayaz A Siddiqui To: intel-gfx@lists.freedesktop.org Cc: Srinivasan Shanmugam , Ayaz A Siddiqui , Chris Wilson , Matt Roper Date: Mon, 16 Aug 2021 10:22:26 +0530 Message-Id: <20210816045229.423234-3-ayaz.siddiqui@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210816045229.423234-1-ayaz.siddiqui@intel.com> References: <20210816045229.423234-1-ayaz.siddiqui@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH V2 2/5] drm/i915/gt: Use cmd_cctl override for platforms >= gen12 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Srinivasan Shanmugam Program CMD_CCTL to use a mocs entry for uncached access. This controls memory accesses by CS as it reads instructions from the ring and batch buffers. v2: Added CMD_CCTL in guc_mmio_regset_init(), so that this register can restored after engine reset. Signed-off-by: Srinivasan Shanmugam Signed-off-by: Ayaz A Siddiqui Cc: Chris Wilson Cc: Matt Roper --- drivers/gpu/drm/i915/gt/intel_mocs.c | 96 ++++++++++++++++++++++ drivers/gpu/drm/i915/gt/selftest_mocs.c | 49 +++++++++++ drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 1 + drivers/gpu/drm/i915/i915_reg.h | 16 ++++ 4 files changed, 162 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c index 10cc508c1a4f6..92141cf6f9a79 100644 --- a/drivers/gpu/drm/i915/gt/intel_mocs.c +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c @@ -25,6 +25,15 @@ struct drm_i915_mocs_table { u8 uc_index; }; +struct drm_i915_aux_table { + const char *name; + i915_reg_t offset; + u32 value; + u32 readmask; + bool skip_check; + struct drm_i915_aux_table *next; +}; + /* Defines for the tables (XXX_MOCS_0 - XXX_MOCS_63) */ #define _LE_CACHEABILITY(value) ((value) << 0) #define _LE_TGT_CACHE(value) ((value) << 2) @@ -336,6 +345,86 @@ static bool has_mocs(const struct drm_i915_private *i915) return !IS_DGFX(i915); } +static struct drm_i915_aux_table * +add_aux_reg(struct drm_i915_aux_table *aux, + const char *name, + i915_reg_t offset, + u32 value, + u32 read, + bool skip_check) + +{ + struct drm_i915_aux_table *x; + + x = kmalloc(sizeof(*x), GFP_ATOMIC); + if (!x) { + DRM_ERROR("Failed to allocate aux reg '%s'\n", name); + return aux; + } + + x->name = name; + x->offset = offset; + x->value = value; + x->readmask = read; + x->skip_check = skip_check; + + x->next = aux; + return x; +} + +static struct drm_i915_aux_table * +add_cmd_cctl_override(struct drm_i915_aux_table *aux, u8 idx) +{ + return add_aux_reg(aux, + "CMD_CCTL", + RING_CMD_CCTL(0), + CMD_CCTL_MOCS_OVERRIDE(idx, idx), + CMD_CCTL_WRITE_OVERRIDE_MASK | CMD_CCTL_READ_OVERRIDE_MASK, + false); +} + +static const struct drm_i915_aux_table * +build_aux_regs(const struct intel_engine_cs *engine, + const struct drm_i915_mocs_table *mocs) +{ + struct drm_i915_aux_table *aux = NULL; + + if (GRAPHICS_VER(engine->i915) >= 12 && + !drm_WARN_ONCE(&engine->i915->drm, !mocs->uc_index, + "Platform that should have UC index defined and does not\n")) { + /* + * Index-0 does not operate as an uncached value as believed, + * but causes invalid write cycles. Steer CMD_CCTL to another + * uncached index. + */ + aux = add_cmd_cctl_override(aux, mocs->uc_index); + } + + return aux; +} + +static void +free_aux_regs(const struct drm_i915_aux_table *aux) +{ + while (aux) { + struct drm_i915_aux_table *next = aux->next; + + kfree(aux); + aux = next; + } +} + +static void apply_aux_regs(struct intel_engine_cs *engine, + const struct drm_i915_aux_table *aux) +{ + while (aux) { + intel_uncore_write_fw(engine->uncore, + _MMIO(engine->mmio_base + i915_mmio_reg_offset(aux->offset)), + aux->value); + aux = aux->next; + } +} + static unsigned int get_mocs_settings(const struct drm_i915_private *i915, struct drm_i915_mocs_table *table) { @@ -347,10 +436,12 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915, table->size = ARRAY_SIZE(dg1_mocs_table); table->table = dg1_mocs_table; table->n_entries = GEN9_NUM_MOCS_ENTRIES; + table->uc_index = 1; } else if (GRAPHICS_VER(i915) >= 12) { table->size = ARRAY_SIZE(tgl_mocs_table); table->table = tgl_mocs_table; table->n_entries = GEN9_NUM_MOCS_ENTRIES; + table->uc_index = 3; } else if (GRAPHICS_VER(i915) == 11) { table->size = ARRAY_SIZE(icl_mocs_table); table->table = icl_mocs_table; @@ -484,6 +575,7 @@ static void init_l3cc_table(struct intel_engine_cs *engine, void intel_mocs_init_engine(struct intel_engine_cs *engine) { + const struct drm_i915_aux_table *aux; struct drm_i915_mocs_table table; unsigned int flags; @@ -500,6 +592,10 @@ void intel_mocs_init_engine(struct intel_engine_cs *engine) if (flags & HAS_RENDER_L3CC && engine->class == RENDER_CLASS) init_l3cc_table(engine, &table); + + aux = build_aux_regs(engine, &table); + apply_aux_regs(engine, aux); + free_aux_regs(aux); } static u32 global_mocs_offset(void) diff --git a/drivers/gpu/drm/i915/gt/selftest_mocs.c b/drivers/gpu/drm/i915/gt/selftest_mocs.c index 13d25bf2a94aa..21fa0a1be28bd 100644 --- a/drivers/gpu/drm/i915/gt/selftest_mocs.c +++ b/drivers/gpu/drm/i915/gt/selftest_mocs.c @@ -155,6 +155,47 @@ static int read_l3cc_table(struct i915_request *rq, return read_regs(rq, addr, (table->n_entries + 1) / 2, offset); } +static int read_aux_regs(struct i915_request *rq, + const struct drm_i915_aux_table *r, + u32 *offset) +{ + int err; + + while (r) { + err = read_regs(rq, + rq->engine->mmio_base + i915_mmio_reg_offset(r->offset), 1, + offset); + if (err) + return err; + + r = r->next; + } + + return 0; +} + +static int check_aux_regs(struct intel_engine_cs *engine, + const struct drm_i915_aux_table *r, + u32 **vaddr) +{ + while (r) { + u32 expect = r->value & r->readmask; + u32 masked_value = **vaddr & r->readmask; + + if (!r->skip_check && masked_value != expect) { + pr_err("%s: Invalid entry %s[%x]=0x%x, relevant bits were 0x%x vs expected 0x%x\n", + engine->name, r->name, + i915_mmio_reg_offset(r->offset), **vaddr, + masked_value, expect); + return -EINVAL; + } + ++*vaddr; + r = r->next; + } + + return 0; +} + static int check_mocs_table(struct intel_engine_cs *engine, const struct drm_i915_mocs_table *table, u32 **vaddr) @@ -216,6 +257,7 @@ static int check_mocs_engine(struct live_mocs *arg, struct intel_context *ce) { struct i915_vma *vma = arg->scratch; + const struct drm_i915_aux_table *aux; struct i915_request *rq; u32 offset; u32 *vaddr; @@ -223,6 +265,8 @@ static int check_mocs_engine(struct live_mocs *arg, memset32(arg->vaddr, STACK_MAGIC, PAGE_SIZE / sizeof(u32)); + aux = build_aux_regs(ce->engine, &arg->table); + rq = intel_context_create_request(ce); if (IS_ERR(rq)) return PTR_ERR(rq); @@ -239,6 +283,8 @@ static int check_mocs_engine(struct live_mocs *arg, err = read_mocs_table(rq, arg->mocs, &offset); if (!err && ce->engine->class == RENDER_CLASS) err = read_l3cc_table(rq, arg->l3cc, &offset); + if (!err) + err = read_aux_regs(rq, aux, &offset); offset -= i915_ggtt_offset(vma); GEM_BUG_ON(offset > PAGE_SIZE); @@ -252,10 +298,13 @@ static int check_mocs_engine(struct live_mocs *arg, err = check_mocs_table(ce->engine, arg->mocs, &vaddr); if (!err && ce->engine->class == RENDER_CLASS) err = check_l3cc_table(ce->engine, arg->l3cc, &vaddr); + if (!err) + err = check_aux_regs(ce->engine, aux, &vaddr); if (err) return err; GEM_BUG_ON(arg->vaddr + offset != vaddr); + free_aux_regs(aux); return 0; } diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c index 6926919bcac6b..99166c82912ca 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c @@ -254,6 +254,7 @@ static void guc_mmio_regset_init(struct temp_regset *regset, GUC_MMIO_REG_ADD(regset, RING_MODE_GEN7(base), true); GUC_MMIO_REG_ADD(regset, RING_HWS_PGA(base), false); GUC_MMIO_REG_ADD(regset, RING_IMR(base), false); + GUC_MMIO_REG_ADD(regset, RING_CMD_CCTL(base), true); for (i = 0, wa = wal->list; i < wal->count; i++, wa++) GUC_MMIO_REG_ADD(regset, wa->reg, wa->masked_reg); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 664970f2bc62a..c8e2ca1b20796 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2551,6 +2551,22 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define RING_HWS_PGA(base) _MMIO((base) + 0x80) #define RING_ID(base) _MMIO((base) + 0x8c) #define RING_HWS_PGA_GEN6(base) _MMIO((base) + 0x2080) + +#define RING_CMD_CCTL(base) _MMIO((base) + 0xc4) +/* + * CMD_CCTL read/write fields take a MOCS value and _not_ a table index. + * The lsb of each can be considered a separate enabling bit for encryption. + * 6:0 == default MOCS value for reads => 6:1 == table index for reads. + * 13:7 == default MOCS value for writes => 13:8 == table index for writes. + * 15:14 == Reserved => 31:30 are set to 0. + */ +#define CMD_CCTL_WRITE_OVERRIDE_MASK REG_GENMASK(13, 7) +#define CMD_CCTL_READ_OVERRIDE_MASK REG_GENMASK(6, 0) +#define CMD_CCTL_MOCS_OVERRIDE(write, read) \ + _MASKED_FIELD(CMD_CCTL_WRITE_OVERRIDE_MASK | CMD_CCTL_READ_OVERRIDE_MASK, \ + REG_FIELD_PREP(CMD_CCTL_WRITE_OVERRIDE_MASK, (write) << 1) | \ + REG_FIELD_PREP(CMD_CCTL_READ_OVERRIDE_MASK, (read) << 1)) + #define RING_RESET_CTL(base) _MMIO((base) + 0xd0) #define RESET_CTL_CAT_ERROR REG_BIT(2) #define RESET_CTL_READY_TO_RESET REG_BIT(1) From patchwork Mon Aug 16 04:52:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Siddiqui, Ayaz A" X-Patchwork-Id: 12437727 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B67C5C4338F for ; Mon, 16 Aug 2021 04:55:59 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 82CD0613B1 for ; Mon, 16 Aug 2021 04:55:59 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 82CD0613B1 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E48BC89BD4; Mon, 16 Aug 2021 04:55:56 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0CAD789BD5 for ; Mon, 16 Aug 2021 04:55:55 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10077"; a="215824002" X-IronPort-AV: E=Sophos;i="5.84,324,1620716400"; d="scan'208";a="215824002" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Aug 2021 21:55:47 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.84,324,1620716400"; d="scan'208";a="422739353" Received: from ayazahma-nuc8i7beh.iind.intel.com ([10.145.162.59]) by orsmga006.jf.intel.com with ESMTP; 15 Aug 2021 21:55:45 -0700 From: Ayaz A Siddiqui To: intel-gfx@lists.freedesktop.org Cc: Apoorva Singh , Ayaz A Siddiqui Date: Mon, 16 Aug 2021 10:22:27 +0530 Message-Id: <20210816045229.423234-4-ayaz.siddiqui@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210816045229.423234-1-ayaz.siddiqui@intel.com> References: <20210816045229.423234-1-ayaz.siddiqui@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH V2 3/5] drm/i915/gt: Set BLIT_CCTL reg to un-cached X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Apoorva Singh Blitter commands which does not have MOCS fields rely on cacheability of BlitterCacheControlRegister which was mapped to index 0 by default.Once we changed the MOCS value of index 0 to L3 WB, tests like gem_linear_blits started failing due to change in cacheability from UC to WB. Program and place the BlitterCacheControlRegister in build_aux_regs(). Signed-off-by: Apoorva Singh Signed-off-by: Ayaz A Siddiqui --- drivers/gpu/drm/i915/gt/intel_mocs.c | 13 +++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 7 +++++++ 2 files changed, 20 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c index 92141cf6f9a79..df3c5d550c46a 100644 --- a/drivers/gpu/drm/i915/gt/intel_mocs.c +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c @@ -372,6 +372,17 @@ add_aux_reg(struct drm_i915_aux_table *aux, return x; } +static struct drm_i915_aux_table * +add_blit_cctl_override(struct drm_i915_aux_table *aux, u8 idx) +{ + return add_aux_reg(aux, + "BLIT_CCTL", + BLIT_CCTL(0), + BLIT_CCTL_MOCS(idx, idx), + BLIT_CCTL_DST_MOCS_MASK | BLIT_CCTL_SRC_MOCS_MASK, + true); +} + static struct drm_i915_aux_table * add_cmd_cctl_override(struct drm_i915_aux_table *aux, u8 idx) { @@ -398,6 +409,8 @@ build_aux_regs(const struct intel_engine_cs *engine, * uncached index. */ aux = add_cmd_cctl_override(aux, mocs->uc_index); + if (engine->class == COPY_ENGINE_CLASS && mocs->uc_index) + aux = add_blit_cctl_override(aux, mocs->uc_index); } return aux; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index c8e2ca1b20796..de3cc9d66ffaa 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2567,6 +2567,13 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) REG_FIELD_PREP(CMD_CCTL_WRITE_OVERRIDE_MASK, (write) << 1) | \ REG_FIELD_PREP(CMD_CCTL_READ_OVERRIDE_MASK, (read) << 1)) +#define BLIT_CCTL(base) _MMIO((base) + 0x204) +#define BLIT_CCTL_DST_MOCS_MASK REG_GENMASK(14, 8) +#define BLIT_CCTL_SRC_MOCS_MASK REG_GENMASK(6, 0) +#define BLIT_CCTL_DST_MOCS_SHIFT 8 +#define BLIT_CCTL_MOCS(dst, src) \ + ((((dst) << 1) << BLIT_CCTL_DST_MOCS_SHIFT) | ((src) << 1)) + #define RING_RESET_CTL(base) _MMIO((base) + 0xd0) #define RESET_CTL_CAT_ERROR REG_BIT(2) #define RESET_CTL_READY_TO_RESET REG_BIT(1) From patchwork Mon Aug 16 04:52:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Siddiqui, Ayaz A" X-Patchwork-Id: 12437733 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3E94CC4338F for ; Mon, 16 Aug 2021 04:56:10 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 07148613B1 for ; Mon, 16 Aug 2021 04:56:10 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 07148613B1 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6968D89BE8; Mon, 16 Aug 2021 04:56:09 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5950289BCD for ; Mon, 16 Aug 2021 04:55:55 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10077"; a="215824005" X-IronPort-AV: E=Sophos;i="5.84,324,1620716400"; d="scan'208";a="215824005" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Aug 2021 21:55:48 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.84,324,1620716400"; d="scan'208";a="422739358" Received: from ayazahma-nuc8i7beh.iind.intel.com ([10.145.162.59]) by orsmga006.jf.intel.com with ESMTP; 15 Aug 2021 21:55:47 -0700 From: Ayaz A Siddiqui To: intel-gfx@lists.freedesktop.org Cc: Ayaz A Siddiqui Date: Mon, 16 Aug 2021 10:22:28 +0530 Message-Id: <20210816045229.423234-5-ayaz.siddiqui@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210816045229.423234-1-ayaz.siddiqui@intel.com> References: <20210816045229.423234-1-ayaz.siddiqui@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH V2 4/5] drm/i915/gt: Initialize unused MOCS entries with device specific values X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" During to creation mocs table,used field of drm_i915_mocs_entry is being checked, if used field is 0, then it will check values of index 1. All the unspecified indexes of xxx_mocs_table[] will contain control value and l3cc value of index I915_MOCS_PTE if its initialized. This patch is intended to provide capability to program device specific control value and l3cc value index which can be used for all the unspecified indexes of MOCS table. Signed-off-by: Ayaz A Siddiqui --- drivers/gpu/drm/i915/gt/intel_mocs.c | 38 +++++++++++++++------------- 1 file changed, 20 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c index df3c5d550c46a..cf00537ba4acc 100644 --- a/drivers/gpu/drm/i915/gt/intel_mocs.c +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c @@ -23,6 +23,7 @@ struct drm_i915_mocs_table { unsigned int n_entries; const struct drm_i915_mocs_entry *table; u8 uc_index; + u8 unused_entries_index; }; struct drm_i915_aux_table { @@ -99,17 +100,23 @@ struct drm_i915_aux_table { * Entries not part of the following tables are undefined as far as * userspace is concerned and shouldn't be relied upon. For Gen < 12 * they will be initialized to PTE. Gen >= 12 onwards don't have a setting for - * PTE and will be initialized to an invalid value. + * PTE and will be initialized L3 WB to catch accidental use of reserved and + * unused mocs indexes. * * The last few entries are reserved by the hardware. For ICL+ they * should be initialized according to bspec and never used, for older * platforms they should never be written to. * - * NOTE: These tables are part of bspec and defined as part of hardware + * NOTE1: These tables are part of bspec and defined as part of hardware * interface for ICL+. For older platforms, they are part of kernel * ABI. It is expected that, for specific hardware platform, existing * entries will remain constant and the table will only be updated by * adding new entries, filling unused positions. + * + * NOTE2: For GEN >= 12, reserved and unspecified MOCS indices have been + * set to L3 WB. These reserved entries should never be used, they + * may be changed to low performant variants with better coherency + * in the future if more entries are needed. */ #define GEN9_MOCS_ENTRIES \ MOCS_ENTRY(I915_MOCS_UNCACHED, \ @@ -292,17 +299,9 @@ static const struct drm_i915_mocs_entry icl_mocs_table[] = { }; static const struct drm_i915_mocs_entry dg1_mocs_table[] = { - /* Error */ - MOCS_ENTRY(0, 0, L3_0_DIRECT), /* UC */ MOCS_ENTRY(1, 0, L3_1_UC), - - /* Reserved */ - MOCS_ENTRY(2, 0, L3_0_DIRECT), - MOCS_ENTRY(3, 0, L3_0_DIRECT), - MOCS_ENTRY(4, 0, L3_0_DIRECT), - /* WB - L3 */ MOCS_ENTRY(5, 0, L3_3_WB), /* WB - L3 50% */ @@ -450,6 +449,7 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915, table->table = dg1_mocs_table; table->n_entries = GEN9_NUM_MOCS_ENTRIES; table->uc_index = 1; + table->unused_entries_index = 5; } else if (GRAPHICS_VER(i915) >= 12) { table->size = ARRAY_SIZE(tgl_mocs_table); table->table = tgl_mocs_table; @@ -500,16 +500,17 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915, } /* - * Get control_value from MOCS entry taking into account when it's not used: - * I915_MOCS_PTE's value is returned in this case. + * Get control_value from MOCS entry taking into account when it's not used + * then if unused_entries_index is non-zero then its value will be returned + * otherwise I915_MOCS_PTE's value is returned in this case. */ static u32 get_entry_control(const struct drm_i915_mocs_table *table, unsigned int index) { if (index < table->size && table->table[index].used) return table->table[index].control_value; - - return table->table[I915_MOCS_PTE].control_value; + index = table->unused_entries_index ? : I915_MOCS_PTE; + return table->table[index].control_value; } #define for_each_mocs(mocs, t, i) \ @@ -550,16 +551,17 @@ static void init_mocs_table(struct intel_engine_cs *engine, } /* - * Get l3cc_value from MOCS entry taking into account when it's not used: - * I915_MOCS_PTE's value is returned in this case. + * Get l3cc_value from MOCS entry taking into account when it's not used + * then if unused_entries_index is not zero then its value will be returned + * otherwise I915_MOCS_PTE's value is returned in this case. */ static u16 get_entry_l3cc(const struct drm_i915_mocs_table *table, unsigned int index) { if (index < table->size && table->table[index].used) return table->table[index].l3cc_value; - - return table->table[I915_MOCS_PTE].l3cc_value; + index = table->unused_entries_index ? : I915_MOCS_PTE; + return table->table[index].l3cc_value; } static u32 l3cc_combine(u16 low, u16 high) From patchwork Mon Aug 16 04:52:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Siddiqui, Ayaz A" X-Patchwork-Id: 12437729 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BF899C432BE for ; Mon, 16 Aug 2021 04:56:01 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6278B61880 for ; Mon, 16 Aug 2021 04:56:01 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 6278B61880 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B82B689BCD; Mon, 16 Aug 2021 04:55:56 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5998D89BDB for ; Mon, 16 Aug 2021 04:55:55 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10077"; a="215824008" X-IronPort-AV: E=Sophos;i="5.84,324,1620716400"; d="scan'208";a="215824008" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Aug 2021 21:55:50 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.84,324,1620716400"; d="scan'208";a="422739365" Received: from ayazahma-nuc8i7beh.iind.intel.com ([10.145.162.59]) by orsmga006.jf.intel.com with ESMTP; 15 Aug 2021 21:55:49 -0700 From: Ayaz A Siddiqui To: intel-gfx@lists.freedesktop.org Cc: Ayaz A Siddiqui , Chris P Wilson , Lucas De Marchi Date: Mon, 16 Aug 2021 10:22:29 +0530 Message-Id: <20210816045229.423234-6-ayaz.siddiqui@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210816045229.423234-1-ayaz.siddiqui@intel.com> References: <20210816045229.423234-1-ayaz.siddiqui@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH V2 5/5] drm/i95/adl: Define MOCS table for Alderlake X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" In order to program unused and reserved mocs entries to L3_WB, we need to create a separate mocs table for alderlake. This patch will also covers wa_1608975824. Cc: Chris P Wilson Cc: Lucas De Marchi Signed-off-by: Ayaz A Siddiqui Reviewed-by: Matt Roper --- drivers/gpu/drm/i915/gt/intel_mocs.c | 41 +++++++++++++++++++++++++++- 1 file changed, 40 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c index cf00537ba4acc..f76e2a2b3ea82 100644 --- a/drivers/gpu/drm/i915/gt/intel_mocs.c +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c @@ -323,6 +323,39 @@ static const struct drm_i915_mocs_entry dg1_mocs_table[] = { MOCS_ENTRY(63, 0, L3_1_UC), }; +static const struct drm_i915_mocs_entry adl_mocs_table[] = { + /* wa_1608975824 */ + MOCS_ENTRY(0, + LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + + GEN11_MOCS_ENTRIES, + /* Implicitly enable L1 - HDC:L1 + L3 + LLC */ + MOCS_ENTRY(48, + LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + /* Implicitly enable L1 - HDC:L1 + L3 */ + MOCS_ENTRY(49, + LE_1_UC | LE_TC_1_LLC, + L3_3_WB), + /* Implicitly enable L1 - HDC:L1 + LLC */ + MOCS_ENTRY(50, + LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_1_UC), + /* Implicitly enable L1 - HDC:L1 */ + MOCS_ENTRY(51, + LE_1_UC | LE_TC_1_LLC, + L3_1_UC), + /* HW Special Case (CCS) */ + MOCS_ENTRY(60, + LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_1_UC), + /* HW Special Case (Displayable) */ + MOCS_ENTRY(61, + LE_1_UC | LE_TC_1_LLC, + L3_3_WB), +}; + enum { HAS_GLOBAL_MOCS = BIT(0), HAS_ENGINE_MOCS = BIT(1), @@ -444,7 +477,13 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915, memset(table, 0, sizeof(struct drm_i915_mocs_table)); - if (IS_DG1(i915)) { + if (IS_ALDERLAKE_S(i915) || IS_ALDERLAKE_P(i915)) { + table->size = ARRAY_SIZE(adl_mocs_table); + table->table = adl_mocs_table; + table->n_entries = GEN9_NUM_MOCS_ENTRIES; + table->uc_index = 3; + table->unused_entries_index = 2; + } else if (IS_DG1(i915)) { table->size = ARRAY_SIZE(dg1_mocs_table); table->table = dg1_mocs_table; table->n_entries = GEN9_NUM_MOCS_ENTRIES;