From patchwork Mon Aug 16 16:50:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shaik Sajida Bhanu X-Patchwork-Id: 12438965 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 190EBC4338F for ; Mon, 16 Aug 2021 16:51:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 04E2D60F55 for ; Mon, 16 Aug 2021 16:51:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231325AbhHPQwI (ORCPT ); Mon, 16 Aug 2021 12:52:08 -0400 Received: from alexa-out.qualcomm.com ([129.46.98.28]:34369 "EHLO alexa-out.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230420AbhHPQwE (ORCPT ); Mon, 16 Aug 2021 12:52:04 -0400 Received: from ironmsg07-lv.qualcomm.com ([10.47.202.151]) by alexa-out.qualcomm.com with ESMTP; 16 Aug 2021 09:51:32 -0700 X-QCInternal: smtphost Received: from ironmsg01-blr.qualcomm.com ([10.86.208.130]) by ironmsg07-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; 16 Aug 2021 09:51:30 -0700 X-QCInternal: smtphost Received: from c-sbhanu-linux.qualcomm.com ([10.242.50.201]) by ironmsg01-blr.qualcomm.com with ESMTP; 16 Aug 2021 22:20:54 +0530 Received: by c-sbhanu-linux.qualcomm.com (Postfix, from userid 2344807) id 85E1D51AA; Mon, 16 Aug 2021 22:20:53 +0530 (IST) From: Shaik Sajida Bhanu To: adrian.hunter@intel.com, ulf.hansson@linaro.org, robh+dt@kernel.org Cc: asutoshd@codeaurora.org, stummala@codeaurora.org, pragalla@codeaurora.org, nitirawa@codeaurora.org, rampraka@codeaurora.org, sayalil@codeaurora.org, sartgarg@codeaurora.org, cang@codeaurora.org, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, agross@kernel.org, bjorn.andersson@linaro.org, Shaik Sajida Bhanu Subject: [PATCH V1] arm64: dts: qcom: sc7180: Use maximum drive strength values for eMMC Date: Mon, 16 Aug 2021 22:20:50 +0530 Message-Id: <1629132650-26277-1-git-send-email-sbhanu@codeaurora.org> X-Mailer: git-send-email 2.7.4 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The current drive strength values are not sufficient on non discrete boards and this leads to CRC errors during switching to HS400 enhanced strobe mode. Hardware simulation results on non discrete boards shows up that use the maximum drive strength values for data and command lines could helps in avoiding these CRC errors. So, update data and command line drive strength values to maximum. Signed-off-by: Shaik Sajida Bhanu Reviewed-by: Douglas Anderson --- arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index 0f2b3c0..79d7aa6 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -1524,13 +1524,13 @@ ap_spi_fp: &spi10 { pinconf-cmd { pins = "sdc1_cmd"; bias-pull-up; - drive-strength = <10>; + drive-strength = <16>; }; pinconf-data { pins = "sdc1_data"; bias-pull-up; - drive-strength = <10>; + drive-strength = <16>; }; pinconf-rclk {