From patchwork Mon Aug 16 16:58:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kammela, Gayatri" X-Patchwork-Id: 12438973 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 14FA8C432BE for ; Mon, 16 Aug 2021 17:02:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E946360E76 for ; Mon, 16 Aug 2021 17:02:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231320AbhHPRCt (ORCPT ); Mon, 16 Aug 2021 13:02:49 -0400 Received: from mga12.intel.com ([192.55.52.136]:11939 "EHLO mga12.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230204AbhHPRCs (ORCPT ); Mon, 16 Aug 2021 13:02:48 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10078"; a="195483033" X-IronPort-AV: E=Sophos;i="5.84,326,1620716400"; d="scan'208";a="195483033" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Aug 2021 10:02:16 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.84,326,1620716400"; d="scan'208";a="509814887" Received: from otcpl-manager.jf.intel.com (HELO localhost.localdomain) ([10.54.39.234]) by fmsmga004.fm.intel.com with ESMTP; 16 Aug 2021 10:02:15 -0700 From: Gayatri Kammela To: platform-driver-x86@vger.kernel.org Cc: mgross@linux.intel.com, hdegoede@redhat.com, irenic.rajneesh@gmail.com, andriy.shevchenko@linux.intel.com, vicamo.yang@canonical.com, srinivas.pandruvada@intel.com, david.e.box@intel.com, chao.qin@intel.com, linux-kernel@vger.kernel.org, tamar.mashiah@intel.com, gregkh@linuxfoundation.org, rajatja@google.com, Shyam-sundar.S-k@amd.com, Alexander.Deucher@amd.com, mlimonci@amd.com, Gayatri Kammela , Andy Shevchenko Subject: [PATCH v7 1/5] platform/x86/intel: intel_pmc_core: Move intel_pmc_core* files to pmc subfolder Date: Mon, 16 Aug 2021 09:58:30 -0700 Message-Id: <81b6292e50af54fb7eeabfefde6f4a3d283b0b96.1629091915.git.gayatri.kammela@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: platform-driver-x86@vger.kernel.org As part of collecting Intel x86 specific drivers in their own folder, move intel_pmc_core* files to its own subfolder there. Cc: Chao Qin Cc: Srinivas Pandruvada Cc: David Box Cc: You-Sheng Yang Cc: Hans de Goede Suggested-by: Andy Shevchenko Acked-by: Rajneesh Bhardwaj Reviewed-by: Andy Shevchenko Signed-off-by: Gayatri Kammela --- MAINTAINERS | 2 +- drivers/platform/x86/Kconfig | 21 ------------------ drivers/platform/x86/Makefile | 1 - drivers/platform/x86/intel/Kconfig | 1 + drivers/platform/x86/intel/Makefile | 1 + drivers/platform/x86/intel/pmc/Kconfig | 22 +++++++++++++++++++ drivers/platform/x86/intel/pmc/Makefile | 6 +++++ .../{intel_pmc_core.c => intel/pmc/core.c} | 2 +- .../{intel_pmc_core.h => intel/pmc/core.h} | 0 .../pmc/core_platform.c} | 0 10 files changed, 32 insertions(+), 24 deletions(-) create mode 100644 drivers/platform/x86/intel/pmc/Kconfig create mode 100644 drivers/platform/x86/intel/pmc/Makefile rename drivers/platform/x86/{intel_pmc_core.c => intel/pmc/core.c} (99%) rename drivers/platform/x86/{intel_pmc_core.h => intel/pmc/core.h} (100%) rename drivers/platform/x86/{intel_pmc_core_pltdrv.c => intel/pmc/core_platform.c} (100%) diff --git a/MAINTAINERS b/MAINTAINERS index fd25e4ecf0b9..5e118faf8018 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -9477,7 +9477,7 @@ M: David E Box L: platform-driver-x86@vger.kernel.org S: Maintained F: Documentation/ABI/testing/sysfs-platform-intel-pmc -F: drivers/platform/x86/intel_pmc_core* +F: drivers/platform/x86/intel/pmc/core* INTEL PMIC GPIO DRIVERS M: Andy Shevchenko diff --git a/drivers/platform/x86/Kconfig b/drivers/platform/x86/Kconfig index d12db6c316ea..c4ee38eba44b 100644 --- a/drivers/platform/x86/Kconfig +++ b/drivers/platform/x86/Kconfig @@ -1187,27 +1187,6 @@ config INTEL_MRFLD_PWRBTN To compile this driver as a module, choose M here: the module will be called intel_mrfld_pwrbtn. -config INTEL_PMC_CORE - tristate "Intel PMC Core driver" - depends on PCI - depends on ACPI - help - The Intel Platform Controller Hub for Intel Core SoCs provides access - to Power Management Controller registers via various interfaces. This - driver can utilize debugging capabilities and supported features as - exposed by the Power Management Controller. It also may perform some - tasks in the PMC in order to enable transition into the SLPS0 state. - It should be selected on all Intel platforms supported by the driver. - - Supported features: - - SLP_S0_RESIDENCY counter - - PCH IP Power Gating status - - LTR Ignore / LTR Show - - MPHY/PLL gating status (Sunrisepoint PCH only) - - SLPS0 Debug registers (Cannonlake/Icelake PCH) - - Low Power Mode registers (Tigerlake and beyond) - - PMC quirks as needed to enable SLPS0/S0ix - config INTEL_PMT_CLASS tristate help diff --git a/drivers/platform/x86/Makefile b/drivers/platform/x86/Makefile index 7ee369aab10d..43d36f8c36f1 100644 --- a/drivers/platform/x86/Makefile +++ b/drivers/platform/x86/Makefile @@ -128,7 +128,6 @@ obj-$(CONFIG_INTEL_UNCORE_FREQ_CONTROL) += intel-uncore-frequency.o obj-$(CONFIG_INTEL_BXTWC_PMIC_TMU) += intel_bxtwc_tmu.o obj-$(CONFIG_INTEL_CHTDC_TI_PWRBTN) += intel_chtdc_ti_pwrbtn.o obj-$(CONFIG_INTEL_MRFLD_PWRBTN) += intel_mrfld_pwrbtn.o -obj-$(CONFIG_INTEL_PMC_CORE) += intel_pmc_core.o intel_pmc_core_pltdrv.o obj-$(CONFIG_INTEL_PMT_CLASS) += intel_pmt_class.o obj-$(CONFIG_INTEL_PMT_TELEMETRY) += intel_pmt_telemetry.o obj-$(CONFIG_INTEL_PMT_CRASHLOG) += intel_pmt_crashlog.o diff --git a/drivers/platform/x86/intel/Kconfig b/drivers/platform/x86/intel/Kconfig index f2eef337eb98..8ca021785f67 100644 --- a/drivers/platform/x86/intel/Kconfig +++ b/drivers/platform/x86/intel/Kconfig @@ -18,5 +18,6 @@ if X86_PLATFORM_DRIVERS_INTEL source "drivers/platform/x86/intel/int33fe/Kconfig" source "drivers/platform/x86/intel/int3472/Kconfig" +source "drivers/platform/x86/intel/pmc/Kconfig" endif # X86_PLATFORM_DRIVERS_INTEL diff --git a/drivers/platform/x86/intel/Makefile b/drivers/platform/x86/intel/Makefile index 0653055942d5..49962f4dfdec 100644 --- a/drivers/platform/x86/intel/Makefile +++ b/drivers/platform/x86/intel/Makefile @@ -6,3 +6,4 @@ obj-$(CONFIG_INTEL_CHT_INT33FE) += int33fe/ obj-$(CONFIG_INTEL_SKL_INT3472) += int3472/ +obj-$(CONFIG_INTEL_PMC_CORE) += pmc/ diff --git a/drivers/platform/x86/intel/pmc/Kconfig b/drivers/platform/x86/intel/pmc/Kconfig new file mode 100644 index 000000000000..c16fc9b2611c --- /dev/null +++ b/drivers/platform/x86/intel/pmc/Kconfig @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config INTEL_PMC_CORE + tristate "Intel PMC Core driver" + depends on PCI + depends on ACPI + help + The Intel Platform Controller Hub for Intel Core SoCs provides access + to Power Management Controller registers via various interfaces. This + driver can utilize debugging capabilities and supported features as + exposed by the Power Management Controller. It also may perform some + tasks in the PMC in order to enable transition into the SLPS0 state. + It should be selected on all Intel platforms supported by the driver. + + Supported features: + - SLP_S0_RESIDENCY counter + - PCH IP Power Gating status + - LTR Ignore / LTR Show + - MPHY/PLL gating status (Sunrise Point PCH only) + - SLPS0 Debug registers (Cannon Lake/Ice Lake PCH) + - Low Power Mode registers (Tiger Lake and beyond) + - PMC quirks as needed to enable SLPS0/S0ix diff --git a/drivers/platform/x86/intel/pmc/Makefile b/drivers/platform/x86/intel/pmc/Makefile new file mode 100644 index 000000000000..c92e66846a4a --- /dev/null +++ b/drivers/platform/x86/intel/pmc/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0 +# + +obj-$(CONFIG_INTEL_PMC_CORE) += intel_pmc_core.o +intel_pmc_core-objs := core.o \ + core_platform.o diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel/pmc/core.c similarity index 99% rename from drivers/platform/x86/intel_pmc_core.c rename to drivers/platform/x86/intel/pmc/core.c index b0e486a6bdfb..f9de78b08e5d 100644 --- a/drivers/platform/x86/intel_pmc_core.c +++ b/drivers/platform/x86/intel/pmc/core.c @@ -31,7 +31,7 @@ #include #include -#include "intel_pmc_core.h" +#include "core.h" #define ACPI_S0IX_DSM_UUID "57a6512e-3979-4e9d-9708-ff13b2508972" #define ACPI_GET_LOW_MODE_REGISTERS 1 diff --git a/drivers/platform/x86/intel_pmc_core.h b/drivers/platform/x86/intel/pmc/core.h similarity index 100% rename from drivers/platform/x86/intel_pmc_core.h rename to drivers/platform/x86/intel/pmc/core.h diff --git a/drivers/platform/x86/intel_pmc_core_pltdrv.c b/drivers/platform/x86/intel/pmc/core_platform.c similarity index 100% rename from drivers/platform/x86/intel_pmc_core_pltdrv.c rename to drivers/platform/x86/intel/pmc/core_platform.c From patchwork Mon Aug 16 16:58:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kammela, Gayatri" X-Patchwork-Id: 12438975 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AA14CC4320A for ; Mon, 16 Aug 2021 17:02:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 90D4F60E76 for ; Mon, 16 Aug 2021 17:02:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229587AbhHPRCu (ORCPT ); Mon, 16 Aug 2021 13:02:50 -0400 Received: from mga12.intel.com ([192.55.52.136]:11939 "EHLO mga12.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231604AbhHPRCu (ORCPT ); Mon, 16 Aug 2021 13:02:50 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10078"; a="195483047" X-IronPort-AV: E=Sophos;i="5.84,326,1620716400"; d="scan'208";a="195483047" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Aug 2021 10:02:18 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.84,326,1620716400"; d="scan'208";a="509814899" Received: from otcpl-manager.jf.intel.com (HELO localhost.localdomain) ([10.54.39.234]) by fmsmga004.fm.intel.com with ESMTP; 16 Aug 2021 10:02:17 -0700 From: Gayatri Kammela To: platform-driver-x86@vger.kernel.org Cc: mgross@linux.intel.com, hdegoede@redhat.com, irenic.rajneesh@gmail.com, andriy.shevchenko@linux.intel.com, vicamo.yang@canonical.com, srinivas.pandruvada@intel.com, david.e.box@intel.com, chao.qin@intel.com, linux-kernel@vger.kernel.org, tamar.mashiah@intel.com, gregkh@linuxfoundation.org, rajatja@google.com, Shyam-sundar.S-k@amd.com, Alexander.Deucher@amd.com, mlimonci@amd.com, Gayatri Kammela , Andy Shevchenko Subject: [PATCH v7 2/5] platform/x86/intel: pmc/core: Add Alderlake support to pmc core driver Date: Mon, 16 Aug 2021 09:58:31 -0700 Message-Id: <8b32e168f8e69dd00aabfb2e4383db78f22b123b.1629091915.git.gayatri.kammela@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: platform-driver-x86@vger.kernel.org Add Alder Lake client and mobile support to pmc core driver. Cc: Chao Qin Cc: Srinivas Pandruvada Cc: Andy Shevchenko Cc: David Box Tested-by: You-Sheng Yang Acked-by: Rajneesh Bhardwaj Reviewed-by: Hans de Goede Reviewed-by: Andy Shevchenko Signed-off-by: Gayatri Kammela --- drivers/platform/x86/intel/pmc/core.c | 68 +++++++++++++++++++++++++++ drivers/platform/x86/intel/pmc/core.h | 2 + 2 files changed, 70 insertions(+) diff --git a/drivers/platform/x86/intel/pmc/core.c b/drivers/platform/x86/intel/pmc/core.c index f9de78b08e5d..d4be15897d04 100644 --- a/drivers/platform/x86/intel/pmc/core.c +++ b/drivers/platform/x86/intel/pmc/core.c @@ -645,6 +645,73 @@ static void pmc_core_get_tgl_lpm_reqs(struct platform_device *pdev) ACPI_FREE(out_obj); } +/* Alder Lake: PGD PFET Enable Ack Status Register(s) bitmap */ +static const struct pmc_bit_map adl_pfear_map[] = { + {"SPI/eSPI", BIT(2)}, + {"XHCI", BIT(3)}, + {"SPA", BIT(4)}, + {"SPB", BIT(5)}, + {"SPC", BIT(6)}, + {"GBE", BIT(7)}, + + {"SATA", BIT(0)}, + {"HDA_PGD0", BIT(1)}, + {"HDA_PGD1", BIT(2)}, + {"HDA_PGD2", BIT(3)}, + {"HDA_PGD3", BIT(4)}, + {"SPD", BIT(5)}, + {"LPSS", BIT(6)}, + + {"SMB", BIT(0)}, + {"ISH", BIT(1)}, + {"ITH", BIT(3)}, + + {"XDCI", BIT(1)}, + {"DCI", BIT(2)}, + {"CSE", BIT(3)}, + {"CSME_KVM", BIT(4)}, + {"CSME_PMT", BIT(5)}, + {"CSME_CLINK", BIT(6)}, + {"CSME_PTIO", BIT(7)}, + + {"CSME_USBR", BIT(0)}, + {"CSME_SUSRAM", BIT(1)}, + {"CSME_SMT1", BIT(2)}, + {"CSME_SMS2", BIT(4)}, + {"CSME_SMS1", BIT(5)}, + {"CSME_RTC", BIT(6)}, + {"CSME_PSF", BIT(7)}, + + {"CNVI", BIT(3)}, + + {"HDA_PGD4", BIT(2)}, + {"HDA_PGD5", BIT(3)}, + {"HDA_PGD6", BIT(4)}, + {} +}; + +static const struct pmc_bit_map *ext_adl_pfear_map[] = { + /* + * Check intel_pmc_core_ids[] users of cnp_reg_map for + * a list of core SoCs using this. + */ + adl_pfear_map, + NULL +}; + +static const struct pmc_reg_map adl_reg_map = { + .pfear_sts = ext_adl_pfear_map, + .slp_s0_offset = ADL_PMC_SLP_S0_RES_COUNTER_OFFSET, + .slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP, + .msr_sts = msr_map, + .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET, + .regmap_length = CNP_PMC_MMIO_REG_LEN, + .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A, + .ppfear_buckets = CNP_PPFEAR_NUM_ENTRIES, + .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET, + .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT, +}; + static inline u32 pmc_core_reg_read(struct pmc_dev *pmcdev, int reg_offset) { return readl(pmcdev->regbase + reg_offset); @@ -1574,6 +1641,7 @@ static const struct x86_cpu_id intel_pmc_core_ids[] = { X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L, &icl_reg_map), X86_MATCH_INTEL_FAM6_MODEL(ROCKETLAKE, &tgl_reg_map), X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, &tgl_reg_map), + X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE, &adl_reg_map), {} }; diff --git a/drivers/platform/x86/intel/pmc/core.h b/drivers/platform/x86/intel/pmc/core.h index e8dae9c6c45f..c0ca20b32c6b 100644 --- a/drivers/platform/x86/intel/pmc/core.h +++ b/drivers/platform/x86/intel/pmc/core.h @@ -197,6 +197,8 @@ enum ppfear_regs { #define TGL_NUM_IP_IGN_ALLOWED 23 #define TGL_PMC_LPM_RES_COUNTER_STEP_X2 61 /* 30.5us * 2 */ +#define ADL_PMC_SLP_S0_RES_COUNTER_OFFSET 0x1098 + /* * Tigerlake Power Management Controller register offsets */ From patchwork Mon Aug 16 16:58:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kammela, Gayatri" X-Patchwork-Id: 12438977 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9CC7BC432BE for ; Mon, 16 Aug 2021 17:02:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7DC0960E76 for ; Mon, 16 Aug 2021 17:02:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232346AbhHPRCx (ORCPT ); Mon, 16 Aug 2021 13:02:53 -0400 Received: from mga12.intel.com ([192.55.52.136]:11939 "EHLO mga12.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231969AbhHPRCv (ORCPT ); Mon, 16 Aug 2021 13:02:51 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10078"; a="195483054" X-IronPort-AV: E=Sophos;i="5.84,326,1620716400"; d="scan'208";a="195483054" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Aug 2021 10:02:19 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.84,326,1620716400"; d="scan'208";a="509814913" Received: from otcpl-manager.jf.intel.com (HELO localhost.localdomain) ([10.54.39.234]) by fmsmga004.fm.intel.com with ESMTP; 16 Aug 2021 10:02:19 -0700 From: Gayatri Kammela To: platform-driver-x86@vger.kernel.org Cc: mgross@linux.intel.com, hdegoede@redhat.com, irenic.rajneesh@gmail.com, andriy.shevchenko@linux.intel.com, vicamo.yang@canonical.com, srinivas.pandruvada@intel.com, david.e.box@intel.com, chao.qin@intel.com, linux-kernel@vger.kernel.org, tamar.mashiah@intel.com, gregkh@linuxfoundation.org, rajatja@google.com, Shyam-sundar.S-k@amd.com, Alexander.Deucher@amd.com, mlimonci@amd.com, Gayatri Kammela , Andy Shevchenko Subject: [PATCH v7 3/5] platform/x86/intel: pmc/core: Add Latency Tolerance Reporting (LTR) support to Alder Lake Date: Mon, 16 Aug 2021 09:58:32 -0700 Message-Id: <5ca3ea090b53a9bf918b055447ab5c8ef2925cc4.1629091915.git.gayatri.kammela@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: platform-driver-x86@vger.kernel.org Add support to show the Latency Tolerance Reporting for the IPs on the Alder Lake PCH as reported by the PMC. This LTR support on Alder Lake is slightly different from the Cannon lake PCH that is being reused by all platforms till Tiger Lake. Cc: Chao Qin Cc: Srinivas Pandruvada Cc: Andy Shevchenko Cc: David Box Tested-by: You-Sheng Yang Acked-by: Rajneesh Bhardwaj Reviewed-by: Hans de Goede Reviewed-by: Andy Shevchenko Signed-off-by: Gayatri Kammela --- drivers/platform/x86/intel/pmc/core.c | 39 +++++++++++++++++++++++++++ drivers/platform/x86/intel/pmc/core.h | 2 ++ 2 files changed, 41 insertions(+) diff --git a/drivers/platform/x86/intel/pmc/core.c b/drivers/platform/x86/intel/pmc/core.c index d4be15897d04..f2646fdf6c90 100644 --- a/drivers/platform/x86/intel/pmc/core.c +++ b/drivers/platform/x86/intel/pmc/core.c @@ -699,10 +699,48 @@ static const struct pmc_bit_map *ext_adl_pfear_map[] = { NULL }; +static const struct pmc_bit_map adl_ltr_show_map[] = { + {"SOUTHPORT_A", CNP_PMC_LTR_SPA}, + {"SOUTHPORT_B", CNP_PMC_LTR_SPB}, + {"SATA", CNP_PMC_LTR_SATA}, + {"GIGABIT_ETHERNET", CNP_PMC_LTR_GBE}, + {"XHCI", CNP_PMC_LTR_XHCI}, + {"SOUTHPORT_F", ADL_PMC_LTR_SPF}, + {"ME", CNP_PMC_LTR_ME}, + /* EVA is Enterprise Value Add, doesn't really exist on PCH */ + {"SATA1", CNP_PMC_LTR_EVA}, + {"SOUTHPORT_C", CNP_PMC_LTR_SPC}, + {"HD_AUDIO", CNP_PMC_LTR_AZ}, + {"CNV", CNP_PMC_LTR_CNV}, + {"LPSS", CNP_PMC_LTR_LPSS}, + {"SOUTHPORT_D", CNP_PMC_LTR_SPD}, + {"SOUTHPORT_E", CNP_PMC_LTR_SPE}, + {"SATA2", CNP_PMC_LTR_CAM}, + {"ESPI", CNP_PMC_LTR_ESPI}, + {"SCC", CNP_PMC_LTR_SCC}, + {"ISH", CNP_PMC_LTR_ISH}, + {"UFSX2", CNP_PMC_LTR_UFSX2}, + {"EMMC", CNP_PMC_LTR_EMMC}, + /* + * Check intel_pmc_core_ids[] users of cnp_reg_map for + * a list of core SoCs using this. + */ + {"WIGIG", ICL_PMC_LTR_WIGIG}, + {"THC0", TGL_PMC_LTR_THC0}, + {"THC1", TGL_PMC_LTR_THC1}, + {"SOUTHPORT_G", CNP_PMC_LTR_RESERVED}, + + /* Below two cannot be used for LTR_IGNORE */ + {"CURRENT_PLATFORM", CNP_PMC_LTR_CUR_PLT}, + {"AGGREGATED_SYSTEM", CNP_PMC_LTR_CUR_ASLT}, + {} +}; + static const struct pmc_reg_map adl_reg_map = { .pfear_sts = ext_adl_pfear_map, .slp_s0_offset = ADL_PMC_SLP_S0_RES_COUNTER_OFFSET, .slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP, + .ltr_show_sts = adl_ltr_show_map, .msr_sts = msr_map, .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET, .regmap_length = CNP_PMC_MMIO_REG_LEN, @@ -710,6 +748,7 @@ static const struct pmc_reg_map adl_reg_map = { .ppfear_buckets = CNP_PPFEAR_NUM_ENTRIES, .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET, .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT, + .ltr_ignore_max = ADL_NUM_IP_IGN_ALLOWED, }; static inline u32 pmc_core_reg_read(struct pmc_dev *pmcdev, int reg_offset) diff --git a/drivers/platform/x86/intel/pmc/core.h b/drivers/platform/x86/intel/pmc/core.h index c0ca20b32c6b..45b352ece6db 100644 --- a/drivers/platform/x86/intel/pmc/core.h +++ b/drivers/platform/x86/intel/pmc/core.h @@ -197,6 +197,8 @@ enum ppfear_regs { #define TGL_NUM_IP_IGN_ALLOWED 23 #define TGL_PMC_LPM_RES_COUNTER_STEP_X2 61 /* 30.5us * 2 */ +#define ADL_PMC_LTR_SPF 0x1C00 +#define ADL_NUM_IP_IGN_ALLOWED 23 #define ADL_PMC_SLP_S0_RES_COUNTER_OFFSET 0x1098 /* From patchwork Mon Aug 16 16:58:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kammela, Gayatri" X-Patchwork-Id: 12438981 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6EB73C432BE for ; Mon, 16 Aug 2021 17:02:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 536BE60E76 for ; Mon, 16 Aug 2021 17:02:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232762AbhHPRC5 (ORCPT ); Mon, 16 Aug 2021 13:02:57 -0400 Received: from mga12.intel.com ([192.55.52.136]:11949 "EHLO mga12.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232164AbhHPRCx (ORCPT ); Mon, 16 Aug 2021 13:02:53 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10078"; a="195483068" X-IronPort-AV: E=Sophos;i="5.84,326,1620716400"; d="scan'208";a="195483068" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Aug 2021 10:02:20 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.84,326,1620716400"; d="scan'208";a="509814925" Received: from otcpl-manager.jf.intel.com (HELO localhost.localdomain) ([10.54.39.234]) by fmsmga004.fm.intel.com with ESMTP; 16 Aug 2021 10:02:20 -0700 From: Gayatri Kammela To: platform-driver-x86@vger.kernel.org Cc: mgross@linux.intel.com, hdegoede@redhat.com, irenic.rajneesh@gmail.com, andriy.shevchenko@linux.intel.com, vicamo.yang@canonical.com, srinivas.pandruvada@intel.com, david.e.box@intel.com, chao.qin@intel.com, linux-kernel@vger.kernel.org, tamar.mashiah@intel.com, gregkh@linuxfoundation.org, rajatja@google.com, Shyam-sundar.S-k@amd.com, Alexander.Deucher@amd.com, mlimonci@amd.com, Gayatri Kammela , Andy Shevchenko Subject: [PATCH v7 4/5] platform/x86/intel: pmc/core: Add Alder Lake low power mode support for pmc core Date: Mon, 16 Aug 2021 09:58:33 -0700 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: platform-driver-x86@vger.kernel.org Alder Lake has 14 status registers that are memory mapped. These registers show the status of the low power mode requirements. The registers are latched on every C10 entry or exit and on every s0ix.y entry/exit. Accessing these registers is useful for debugging any low power related activities. Thus, add debugfs entry to access low power mode status registers. Cc: Chao Qin Cc: Srinivas Pandruvada Cc: Andy Shevchenko Cc: David Box Tested-by: You-Sheng Yang Acked-by: Rajneesh Bhardwaj Reviewed-by: Hans de Goede Reviewed-by: Andy Shevchenko Signed-off-by: Gayatri Kammela --- drivers/platform/x86/intel/pmc/core.c | 194 ++++++++++++++++++++++++++ drivers/platform/x86/intel/pmc/core.h | 13 ++ 2 files changed, 207 insertions(+) diff --git a/drivers/platform/x86/intel/pmc/core.c b/drivers/platform/x86/intel/pmc/core.c index f2646fdf6c90..e645ede591d8 100644 --- a/drivers/platform/x86/intel/pmc/core.c +++ b/drivers/platform/x86/intel/pmc/core.c @@ -736,6 +736,189 @@ static const struct pmc_bit_map adl_ltr_show_map[] = { {} }; +static const struct pmc_bit_map adl_clocksource_status_map[] = { + {"CLKPART1_OFF_STS", BIT(0)}, + {"CLKPART2_OFF_STS", BIT(1)}, + {"CLKPART3_OFF_STS", BIT(2)}, + {"CLKPART4_OFF_STS", BIT(3)}, + {"CLKPART5_OFF_STS", BIT(4)}, + {"CLKPART6_OFF_STS", BIT(5)}, + {"CLKPART7_OFF_STS", BIT(6)}, + {"CLKPART8_OFF_STS", BIT(7)}, + {"PCIE0PLL_OFF_STS", BIT(10)}, + {"PCIE1PLL_OFF_STS", BIT(11)}, + {"PCIE2PLL_OFF_STS", BIT(12)}, + {"PCIE3PLL_OFF_STS", BIT(13)}, + {"PCIE4PLL_OFF_STS", BIT(14)}, + {"PCIE5PLL_OFF_STS", BIT(15)}, + {"PCIE6PLL_OFF_STS", BIT(16)}, + {"USB2PLL_OFF_STS", BIT(18)}, + {"OCPLL_OFF_STS", BIT(22)}, + {"AUDIOPLL_OFF_STS", BIT(23)}, + {"GBEPLL_OFF_STS", BIT(24)}, + {"Fast_XTAL_Osc_OFF_STS", BIT(25)}, + {"AC_Ring_Osc_OFF_STS", BIT(26)}, + {"MC_Ring_Osc_OFF_STS", BIT(27)}, + {"SATAPLL_OFF_STS", BIT(29)}, + {"USB3PLL_OFF_STS", BIT(31)}, + {} +}; + +static const struct pmc_bit_map adl_power_gating_status_0_map[] = { + {"PMC_PGD0_PG_STS", BIT(0)}, + {"DMI_PGD0_PG_STS", BIT(1)}, + {"ESPISPI_PGD0_PG_STS", BIT(2)}, + {"XHCI_PGD0_PG_STS", BIT(3)}, + {"SPA_PGD0_PG_STS", BIT(4)}, + {"SPB_PGD0_PG_STS", BIT(5)}, + {"SPC_PGD0_PG_STS", BIT(6)}, + {"GBE_PGD0_PG_STS", BIT(7)}, + {"SATA_PGD0_PG_STS", BIT(8)}, + {"DSP_PGD0_PG_STS", BIT(9)}, + {"DSP_PGD1_PG_STS", BIT(10)}, + {"DSP_PGD2_PG_STS", BIT(11)}, + {"DSP_PGD3_PG_STS", BIT(12)}, + {"SPD_PGD0_PG_STS", BIT(13)}, + {"LPSS_PGD0_PG_STS", BIT(14)}, + {"SMB_PGD0_PG_STS", BIT(16)}, + {"ISH_PGD0_PG_STS", BIT(17)}, + {"NPK_PGD0_PG_STS", BIT(19)}, + {"PECI_PGD0_PG_STS", BIT(21)}, + {"XDCI_PGD0_PG_STS", BIT(25)}, + {"EXI_PGD0_PG_STS", BIT(26)}, + {"CSE_PGD0_PG_STS", BIT(27)}, + {"KVMCC_PGD0_PG_STS", BIT(28)}, + {"PMT_PGD0_PG_STS", BIT(29)}, + {"CLINK_PGD0_PG_STS", BIT(30)}, + {"PTIO_PGD0_PG_STS", BIT(31)}, + {} +}; + +static const struct pmc_bit_map adl_power_gating_status_1_map[] = { + {"USBR0_PGD0_PG_STS", BIT(0)}, + {"SMT1_PGD0_PG_STS", BIT(2)}, + {"CSMERTC_PGD0_PG_STS", BIT(6)}, + {"CSMEPSF_PGD0_PG_STS", BIT(7)}, + {"CNVI_PGD0_PG_STS", BIT(19)}, + {"DSP_PGD4_PG_STS", BIT(26)}, + {"SPG_PGD0_PG_STS", BIT(27)}, + {"SPE_PGD0_PG_STS", BIT(28)}, + {} +}; + +static const struct pmc_bit_map adl_power_gating_status_2_map[] = { + {"THC0_PGD0_PG_STS", BIT(7)}, + {"THC1_PGD0_PG_STS", BIT(8)}, + {"SPF_PGD0_PG_STS", BIT(14)}, + {} +}; + +static const struct pmc_bit_map adl_d3_status_0_map[] = { + {"ISH_D3_STS", BIT(2)}, + {"LPSS_D3_STS", BIT(3)}, + {"XDCI_D3_STS", BIT(4)}, + {"XHCI_D3_STS", BIT(5)}, + {"SPA_D3_STS", BIT(12)}, + {"SPB_D3_STS", BIT(13)}, + {"SPC_D3_STS", BIT(14)}, + {"SPD_D3_STS", BIT(15)}, + {"SPE_D3_STS", BIT(16)}, + {"DSP_D3_STS", BIT(19)}, + {"SATA_D3_STS", BIT(20)}, + {"DMI_D3_STS", BIT(22)}, + {} +}; + +static const struct pmc_bit_map adl_d3_status_1_map[] = { + {"GBE_D3_STS", BIT(19)}, + {"CNVI_D3_STS", BIT(27)}, + {} +}; + +static const struct pmc_bit_map adl_d3_status_2_map[] = { + {"CSMERTC_D3_STS", BIT(1)}, + {"CSE_D3_STS", BIT(4)}, + {"KVMCC_D3_STS", BIT(5)}, + {"USBR0_D3_STS", BIT(6)}, + {"SMT1_D3_STS", BIT(8)}, + {"PTIO_D3_STS", BIT(16)}, + {"PMT_D3_STS", BIT(17)}, + {} +}; + +static const struct pmc_bit_map adl_d3_status_3_map[] = { + {"THC0_D3_STS", BIT(14)}, + {"THC1_D3_STS", BIT(15)}, + {} +}; + +static const struct pmc_bit_map adl_vnn_req_status_0_map[] = { + {"ISH_VNN_REQ_STS", BIT(2)}, + {"ESPISPI_VNN_REQ_STS", BIT(18)}, + {"DSP_VNN_REQ_STS", BIT(19)}, + {} +}; + +static const struct pmc_bit_map adl_vnn_req_status_1_map[] = { + {"NPK_VNN_REQ_STS", BIT(4)}, + {"EXI_VNN_REQ_STS", BIT(9)}, + {"GBE_VNN_REQ_STS", BIT(19)}, + {"SMB_VNN_REQ_STS", BIT(25)}, + {"CNVI_VNN_REQ_STS", BIT(27)}, + {} +}; + +static const struct pmc_bit_map adl_vnn_req_status_2_map[] = { + {"CSMERTC_VNN_REQ_STS", BIT(1)}, + {"CSE_VNN_REQ_STS", BIT(4)}, + {"SMT1_VNN_REQ_STS", BIT(8)}, + {"CLINK_VNN_REQ_STS", BIT(14)}, + {"GPIOCOM4_VNN_REQ_STS", BIT(20)}, + {"GPIOCOM3_VNN_REQ_STS", BIT(21)}, + {"GPIOCOM2_VNN_REQ_STS", BIT(22)}, + {"GPIOCOM1_VNN_REQ_STS", BIT(23)}, + {"GPIOCOM0_VNN_REQ_STS", BIT(24)}, + {} +}; + +static const struct pmc_bit_map adl_vnn_req_status_3_map[] = { + {"GPIOCOM5_VNN_REQ_STS", BIT(11)}, + {} +}; + +static const struct pmc_bit_map adl_vnn_misc_status_map[] = { + {"CPU_C10_REQ_STS", BIT(0)}, + {"PCIe_LPM_En_REQ_STS", BIT(3)}, + {"ITH_REQ_STS", BIT(5)}, + {"CNVI_REQ_STS", BIT(6)}, + {"ISH_REQ_STS", BIT(7)}, + {"USB2_SUS_PG_Sys_REQ_STS", BIT(10)}, + {"PCIe_Clk_REQ_STS", BIT(12)}, + {"MPHY_Core_DL_REQ_STS", BIT(16)}, + {"Break-even_En_REQ_STS", BIT(17)}, + {"MPHY_SUS_REQ_STS", BIT(22)}, + {"xDCI_attached_REQ_STS", BIT(24)}, + {} +}; + +static const struct pmc_bit_map *adl_lpm_maps[] = { + adl_clocksource_status_map, + adl_power_gating_status_0_map, + adl_power_gating_status_1_map, + adl_power_gating_status_2_map, + adl_d3_status_0_map, + adl_d3_status_1_map, + adl_d3_status_2_map, + adl_d3_status_3_map, + adl_vnn_req_status_0_map, + adl_vnn_req_status_1_map, + adl_vnn_req_status_2_map, + adl_vnn_req_status_3_map, + adl_vnn_misc_status_map, + tgl_signal_status_map, + NULL +}; + static const struct pmc_reg_map adl_reg_map = { .pfear_sts = ext_adl_pfear_map, .slp_s0_offset = ADL_PMC_SLP_S0_RES_COUNTER_OFFSET, @@ -749,6 +932,17 @@ static const struct pmc_reg_map adl_reg_map = { .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET, .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT, .ltr_ignore_max = ADL_NUM_IP_IGN_ALLOWED, + .lpm_num_modes = ADL_LPM_NUM_MODES, + .lpm_num_maps = ADL_LPM_NUM_MAPS, + .lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2, + .etr3_offset = ETR3_OFFSET, + .lpm_sts_latch_en_offset = ADL_LPM_STATUS_LATCH_EN_OFFSET, + .lpm_priority_offset = ADL_LPM_PRI_OFFSET, + .lpm_en_offset = ADL_LPM_EN_OFFSET, + .lpm_residency_offset = ADL_LPM_RESIDENCY_OFFSET, + .lpm_sts = adl_lpm_maps, + .lpm_status_offset = ADL_LPM_STATUS_OFFSET, + .lpm_live_status_offset = ADL_LPM_LIVE_STATUS_OFFSET, }; static inline u32 pmc_core_reg_read(struct pmc_dev *pmcdev, int reg_offset) diff --git a/drivers/platform/x86/intel/pmc/core.h b/drivers/platform/x86/intel/pmc/core.h index 45b352ece6db..333e25981e8e 100644 --- a/drivers/platform/x86/intel/pmc/core.h +++ b/drivers/platform/x86/intel/pmc/core.h @@ -222,6 +222,18 @@ enum ppfear_regs { /* Extended Test Mode Register LPM bits (TGL and later */ #define ETR3_CLEAR_LPM_EVENTS BIT(28) +/* Alder Lake Power Management Controller register offsets */ +#define ADL_LPM_EN_OFFSET 0x179C +#define ADL_LPM_RESIDENCY_OFFSET 0x17A4 +#define ADL_LPM_NUM_MODES 2 +#define ADL_LPM_NUM_MAPS 14 + +/* Alder Lake Low Power Mode debug registers */ +#define ADL_LPM_STATUS_OFFSET 0x170C +#define ADL_LPM_PRI_OFFSET 0x17A0 +#define ADL_LPM_STATUS_LATCH_EN_OFFSET 0x1704 +#define ADL_LPM_LIVE_STATUS_OFFSET 0x1764 + const char *pmc_lpm_modes[] = { "S0i2.0", "S0i2.1", @@ -281,6 +293,7 @@ struct pmc_reg_map { const u32 pm_vric1_offset; /* Low Power Mode registers */ const int lpm_num_maps; + const int lpm_num_modes; const int lpm_res_counter_step_x2; const u32 lpm_sts_latch_en_offset; const u32 lpm_en_offset; From patchwork Mon Aug 16 16:58:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kammela, Gayatri" X-Patchwork-Id: 12438979 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 64BC1C4338F for ; Mon, 16 Aug 2021 17:02:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 440D960F38 for ; Mon, 16 Aug 2021 17:02:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232645AbhHPRCz (ORCPT ); Mon, 16 Aug 2021 13:02:55 -0400 Received: from mga12.intel.com ([192.55.52.136]:11939 "EHLO mga12.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231604AbhHPRCy (ORCPT ); Mon, 16 Aug 2021 13:02:54 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10078"; a="195483079" X-IronPort-AV: E=Sophos;i="5.84,326,1620716400"; d="scan'208";a="195483079" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Aug 2021 10:02:22 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.84,326,1620716400"; d="scan'208";a="509814937" Received: from otcpl-manager.jf.intel.com (HELO localhost.localdomain) ([10.54.39.234]) by fmsmga004.fm.intel.com with ESMTP; 16 Aug 2021 10:02:21 -0700 From: Gayatri Kammela To: platform-driver-x86@vger.kernel.org Cc: mgross@linux.intel.com, hdegoede@redhat.com, irenic.rajneesh@gmail.com, andriy.shevchenko@linux.intel.com, vicamo.yang@canonical.com, srinivas.pandruvada@intel.com, david.e.box@intel.com, chao.qin@intel.com, linux-kernel@vger.kernel.org, tamar.mashiah@intel.com, gregkh@linuxfoundation.org, rajatja@google.com, Shyam-sundar.S-k@amd.com, Alexander.Deucher@amd.com, mlimonci@amd.com, "David E. Box" , Andy Shevchenko Subject: [PATCH v7 5/5] platform/x86/intel: pmc/core: Add GBE Package C10 fix for Alder Lake PCH Date: Mon, 16 Aug 2021 09:58:34 -0700 Message-Id: <9168e8bd687f2d0d5eb0ed116e08d0764eadf7b3.1629091915.git.gayatri.kammela@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: platform-driver-x86@vger.kernel.org From: "David E. Box" Alder PCH uses the same Gigabit Ethernet (GBE) device as Tiger Lake PCH which cannot achieve PC10 without ignoring the PMC GBE LTR. Add this work around for Alder Lake PCH as well. Cc: Chao Qin Cc: Srinivas Pandruvada Cc: Andy Shevchenko Tested-by: You-Sheng Yang Acked-by: Rajneesh Bhardwaj Reviewed-by: Hans de Goede Reviewed-by: Andy Shevchenko Signed-off-by: David E. Box --- drivers/platform/x86/intel/pmc/core.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/platform/x86/intel/pmc/core.c b/drivers/platform/x86/intel/pmc/core.c index e645ede591d8..7c4bf7d22fd5 100644 --- a/drivers/platform/x86/intel/pmc/core.c +++ b/drivers/platform/x86/intel/pmc/core.c @@ -1983,10 +1983,10 @@ static int pmc_core_probe(struct platform_device *pdev) pmc_core_get_tgl_lpm_reqs(pdev); /* - * On TGL, due to a hardware limitation, the GBE LTR blocks PC10 when - * a cable is attached. Tell the PMC to ignore it. + * On TGL and ADL, due to a hardware limitation, the GBE LTR blocks PC10 + * when a cable is attached. Tell the PMC to ignore it. */ - if (pmcdev->map == &tgl_reg_map) { + if (pmcdev->map == &tgl_reg_map || pmcdev->map == &adl_reg_map) { dev_dbg(&pdev->dev, "ignoring GBE LTR\n"); pmc_core_send_ltr_ignore(pmcdev, 3); }