From patchwork Fri Dec 7 09:12:01 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lisovskiy, Stanislav" X-Patchwork-Id: 10717705 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DB2B613BF for ; Fri, 7 Dec 2018 09:12:09 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CACF72E900 for ; Fri, 7 Dec 2018 09:12:09 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id BF4B42E94A; Fri, 7 Dec 2018 09:12:09 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id C53362E945 for ; Fri, 7 Dec 2018 09:12:08 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 479E96E6F5; Fri, 7 Dec 2018 09:12:07 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id BD4676E6F5 for ; Fri, 7 Dec 2018 09:12:04 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Dec 2018 01:12:04 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,324,1539673200"; d="scan'208";a="123806349" Received: from slisovsk-lenovo-ideapad-720s-13ikb.fi.intel.com ([10.237.72.122]) by fmsmga002.fm.intel.com with ESMTP; 07 Dec 2018 01:12:02 -0800 From: Stanislav Lisovskiy To: intel-gfx@lists.freedesktop.org Date: Fri, 7 Dec 2018 11:12:01 +0200 Message-Id: <20181207091201.9695-1-stanislav.lisovskiy@intel.com> X-Mailer: git-send-email 2.17.1 Subject: [Intel-gfx] [PATCH v2] drm/i915/icl: Fix pipe config mismatch warnings X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com, ville.syrjala@intel.com MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Fixes hblank, vblank, vsync_start/vsync_end, hsync_start//hsync_end, pipe_bpp, port clock, pixel rate mismatches for dsi which happen during pipe_config comparation in intel_atomic_check. v2: Removed duplicate code, unused variables and unneeded const modifier for pipe_config. Signed-off-by: Stanislav Lisovskiy --- drivers/gpu/drm/i915/icl_dsi.c | 90 +++++++++++++++++++++++++++++----- 1 file changed, 78 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c index 4dd793b78996..951c9823b971 100644 --- a/drivers/gpu/drm/i915/icl_dsi.c +++ b/drivers/gpu/drm/i915/icl_dsi.c @@ -760,13 +760,6 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, vsync_end = adjusted_mode->crtc_vsync_end; vsync_shift = hsync_start - htotal / 2; - if (intel_dsi->dual_link) { - hactive /= 2; - if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) - hactive += intel_dsi->pixel_overlap; - htotal /= 2; - } - /* minimum hactive as per bspec: 256 pixels */ if (adjusted_mode->crtc_hdisplay < 256) DRM_ERROR("hactive is less then 256 pixels\n"); @@ -794,11 +787,6 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, if (hback_porch < 16) DRM_ERROR("hback porch < 16 pixels\n"); - if (intel_dsi->dual_link) { - hsync_start /= 2; - hsync_end /= 2; - } - for_each_dsi_port(port, intel_dsi->ports) { dsi_trans = dsi_port_to_transcoder(port); I915_WRITE(HSYNC(dsi_trans), @@ -844,6 +832,61 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, } } +static +void +gen11_dsi_calc_transcoder_timings(struct intel_encoder *encoder, + struct intel_crtc_state *pipe_config) +{ + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); + struct drm_display_mode *adjusted_mode = + &pipe_config->base.adjusted_mode; + /* horizontal timings */ + u16 htotal, hactive, hsync_start, hsync_end, hsync_size; + u16 hfront_porch, hback_porch; + /* vertical timings */ + u16 vtotal, vactive, vsync_start, vsync_end, vsync_shift; + + hactive = adjusted_mode->crtc_hdisplay; + htotal = adjusted_mode->crtc_htotal; + hsync_start = adjusted_mode->crtc_hsync_start; + hsync_end = adjusted_mode->crtc_hsync_end; + hsync_size = hsync_end - hsync_start; + hfront_porch = (adjusted_mode->crtc_hsync_start - + adjusted_mode->crtc_hdisplay); + hback_porch = (adjusted_mode->crtc_htotal - + adjusted_mode->crtc_hsync_end); + vactive = adjusted_mode->crtc_vdisplay; + vtotal = adjusted_mode->crtc_vtotal; + vsync_start = adjusted_mode->crtc_vsync_start; + vsync_end = adjusted_mode->crtc_vsync_end; + vsync_shift = hsync_start - htotal / 2; + + if (intel_dsi->dual_link) { + hactive /= 2; + if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) + hactive += intel_dsi->pixel_overlap; + htotal /= 2; + } + + /* TRANS_HSYNC register to be programmed only for video mode */ + if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) { + + if (intel_dsi->dual_link) { + hsync_start /= 2; + hsync_end /= 2; + } + } + + adjusted_mode->crtc_hdisplay = hactive; + adjusted_mode->crtc_htotal = htotal; + adjusted_mode->crtc_hsync_start = hsync_start; + adjusted_mode->crtc_hsync_end = hsync_end; + adjusted_mode->crtc_vdisplay = vactive; + adjusted_mode->crtc_vtotal = vtotal; + adjusted_mode->crtc_vsync_start = vsync_start; + adjusted_mode->crtc_vsync_end = vsync_end; +} + static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); @@ -1169,6 +1212,9 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder, { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); + struct drm_display_mode *adjusted_mode = + &pipe_config->base.adjusted_mode; + u32 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); u32 pll_id; /* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */ @@ -1176,6 +1222,19 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder, pipe_config->port_clock = cnl_calc_wrpll_link(dev_priv, pll_id); pipe_config->base.adjusted_mode.crtc_clock = intel_dsi->pclk; pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); + pipe_config->pipe_bpp = bpp; + + if (intel_dsi->dual_link) { + adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay * 2; + adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal * 2; + } else { + adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay; + adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal; + } + + adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay; + adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal; + } static bool gen11_dsi_compute_config(struct intel_encoder *encoder, @@ -1204,6 +1263,13 @@ static bool gen11_dsi_compute_config(struct intel_encoder *encoder, pipe_config->clock_set = true; pipe_config->port_clock = intel_dsi_bitrate(intel_dsi) / 5; + pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; + + if (intel_dsi->dual_link) { + pipe_config->base.adjusted_mode.crtc_clock /= 2; + } + + gen11_dsi_calc_transcoder_timings(encoder, pipe_config); return true; }