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[84.90.178.246]) by smtp.gmail.com with ESMTPSA id o14sm3150409wrw.17.2021.08.19.07.51.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Aug 2021 07:51:16 -0700 (PDT) From: Lukas Bulwahn To: Tomas Winkler Cc: Arnd Bergmann , Greg Kroah-Hartman , Bjorn Helgaas , linux-pci@vger.kernel.org, Ionel-Catalin Mititelu , Jiri Kosina , linux-kernel@vger.kernel.org, Lukas Bulwahn Subject: [PATCH] mei: improve Denverton HSM & IFSI support Date: Thu, 19 Aug 2021 16:51:14 +0200 Message-Id: <20210819145114.21074-1-lukas.bulwahn@gmail.com> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The Intel Denverton chip provides HSM & IFSI. In order to access HSM & IFSI at the same time, provide two HECI hardware IDs for accessing. Suggested-by: Ionel-Catalin Mititelu Signed-off-by: Lukas Bulwahn --- Tomas, please pick this quick helpful extension for the hardware. drivers/misc/mei/hw-me-regs.h | 3 ++- drivers/misc/mei/pci-me.c | 1 + drivers/pci/quirks.c | 3 +++ 3 files changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/misc/mei/hw-me-regs.h b/drivers/misc/mei/hw-me-regs.h index cb34925e10f1..c1c41912bb72 100644 --- a/drivers/misc/mei/hw-me-regs.h +++ b/drivers/misc/mei/hw-me-regs.h @@ -68,7 +68,8 @@ #define MEI_DEV_ID_BXT_M 0x1A9A /* Broxton M */ #define MEI_DEV_ID_APL_I 0x5A9A /* Apollo Lake I */ -#define MEI_DEV_ID_DNV_IE 0x19E5 /* Denverton IE */ +#define MEI_DEV_ID_DNV_IE 0x19E5 /* Denverton for HECI1 - IFSI */ +#define MEI_DEV_ID_DNV_IE_2 0x19E6 /* Denverton 2 for HECI2 - HSM */ #define MEI_DEV_ID_GLK 0x319A /* Gemini Lake */ diff --git a/drivers/misc/mei/pci-me.c b/drivers/misc/mei/pci-me.c index c3393b383e59..30827cd2a1c2 100644 --- a/drivers/misc/mei/pci-me.c +++ b/drivers/misc/mei/pci-me.c @@ -77,6 +77,7 @@ static const struct pci_device_id mei_me_pci_tbl[] = { {MEI_PCI_DEVICE(MEI_DEV_ID_APL_I, MEI_ME_PCH8_CFG)}, {MEI_PCI_DEVICE(MEI_DEV_ID_DNV_IE, MEI_ME_PCH8_CFG)}, + {MEI_PCI_DEVICE(MEI_DEV_ID_DNV_IE_2, MEI_ME_PCH8_SPS_CFG)}, {MEI_PCI_DEVICE(MEI_DEV_ID_GLK, MEI_ME_PCH8_CFG)}, diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 6899d6b198af..2ab767ef8469 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -4842,6 +4842,9 @@ static const struct pci_dev_acs_enabled { { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs }, { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs }, { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_rciep_acs }, + /* Denverton */ + { PCI_VENDOR_ID_INTEL, 0x19e5, pci_quirk_mf_endpoint_acs }, + { PCI_VENDOR_ID_INTEL, 0x19e6, pci_quirk_mf_endpoint_acs }, /* QCOM QDF2xxx root ports */ { PCI_VENDOR_ID_QCOM, 0x0400, pci_quirk_qcom_rp_acs }, { PCI_VENDOR_ID_QCOM, 0x0401, pci_quirk_qcom_rp_acs },