From patchwork Mon Aug 23 16:40:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 12453189 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6CC83C432BE for ; Mon, 23 Aug 2021 16:41:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5404461406 for ; Mon, 23 Aug 2021 16:41:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230154AbhHWQlq (ORCPT ); Mon, 23 Aug 2021 12:41:46 -0400 Received: from mail.kernel.org ([198.145.29.99]:37272 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229904AbhHWQlp (ORCPT ); Mon, 23 Aug 2021 12:41:45 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 105C7613B1; Mon, 23 Aug 2021 16:41:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1629736863; bh=cEI+qg5LiFT/MsVm3juyQ/F0QofSoSmzQNAz+sFwK+M=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VneIWHy9+of7BwhH4vDz9D8npklTIPXWHDLOwbRSoGn6oUWAVKXbkx722Td0Ntzkb PVqsnohDZKW5lr1e6IX2yPfsKkykdqbNxJIjW3nMAFXpGUgbvieFYi+IzKxGrM3gOr bhMv/J5eq99dAZWiQv24w/KI+k+bayyj7ouR8tfJ0rr3ckY6pv0+MGHO60AF8LXjDJ Q0f/VSq+Ow2Tv1Yp0CZLF8bJWF+4EjMgSPQh1GP0lOnnasal8sv7XPUvy3oIvNBdmp E/+47t12KriOP3MaSPNssRBXlV2EzeT6BYzWVgtNp0iMFbu108S8CFXF7Tv1bnTjPM s4EBnXRh6m/0w== Received: by pali.im (Postfix) id 24CCA251E; Mon, 23 Aug 2021 18:41:01 +0200 (CEST) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: Lorenzo Pieralisi , Thomas Petazzoni , Bjorn Helgaas , Rob Herring Cc: =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , =?utf-8?q?Marek_Be?= =?utf-8?q?h=C3=BAn?= , "Marc Zyngier" , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/3] PCI: aardvark: Fix reading MSI interrupt number Date: Mon, 23 Aug 2021 18:40:31 +0200 Message-Id: <20210823164033.27491-2-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210823164033.27491-1-pali@kernel.org> References: <20210815103624.19528-1-pali@kernel.org> <20210823164033.27491-1-pali@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Experiments showed that in register PCIE_MSI_PAYLOAD_REG is stored number of the last received MSI interrupt and not number of MSI interrupt which belongs to msi_idx bit. Therefore this implies that aardvark HW can cache only bits [4:0] of received MSI interrupts with effectively means that it supports only MSI interrupts with numbers 0-31. Do not read PCIE_MSI_PAYLOAD_REG register for determining MSI interrupt number. Instead ensure that pci-aardvark.c configures only MSI numbers in range 0-31 and then msi_idx contains correct received MSI number. Signed-off-by: Pali Rohár Cc: stable@vger.kernel.org --- drivers/pci/controller/pci-aardvark.c | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index 48fbfa7eb24c..81c4a9ff91a3 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -1232,7 +1232,6 @@ static void advk_pcie_remove_irq_domain(struct advk_pcie *pcie) static void advk_pcie_handle_msi(struct advk_pcie *pcie) { u32 msi_val, msi_mask, msi_status, msi_idx; - u16 msi_data; int virq; msi_mask = advk_readl(pcie, PCIE_MSI_MASK_REG); @@ -1243,17 +1242,13 @@ static void advk_pcie_handle_msi(struct advk_pcie *pcie) if (!(BIT(msi_idx) & msi_status)) continue; - /* - * msi_idx contains bits [4:0] of the msi_data and msi_data - * contains 16bit MSI interrupt number from MSI inner domain - */ advk_writel(pcie, BIT(msi_idx), PCIE_MSI_STATUS_REG); - msi_data = advk_readl(pcie, PCIE_MSI_PAYLOAD_REG) & PCIE_MSI_DATA_MASK; - virq = irq_find_mapping(pcie->msi_inner_domain, msi_data); + + virq = irq_find_mapping(pcie->msi_inner_domain, msi_idx); if (virq) generic_handle_irq(virq); else - dev_err_ratelimited(&pcie->pdev->dev, "unexpected MSI 0x%04hx\n", msi_data); + dev_err_ratelimited(&pcie->pdev->dev, "unexpected MSI 0x%02x\n", msi_idx); } advk_writel(pcie, PCIE_ISR0_MSI_INT_PENDING, From patchwork Mon Aug 23 16:40:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 12453193 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 95B8AC43214 for ; Mon, 23 Aug 2021 16:41:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 800A0613B1 for ; Mon, 23 Aug 2021 16:41:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230298AbhHWQls (ORCPT ); Mon, 23 Aug 2021 12:41:48 -0400 Received: from mail.kernel.org ([198.145.29.99]:37358 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230281AbhHWQlr (ORCPT ); Mon, 23 Aug 2021 12:41:47 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 502D1613E6; Mon, 23 Aug 2021 16:41:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1629736864; bh=dWR4jlQ/UFvfKF+DH7OfQ3Tzq7QBMMw9jwa5eR2m/yw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=DVuEaKjjwiaY8IQIO9HhckEcFM/XaPdtH15ouR2HfdjA0tTVakL0pf5etfwK0boWE uoALyMIce31Qsn3yNWdqdUmeMMTIy/Hw0ie2LMFypZ+7UyvfOARosdu1zl7oWLiMlq m7TYoqIf1Qu/1AmcVQXpsv0UJVPZKwGlR9dZzW+EadrSJw0WRjJM31Biu9936mzGqU q9kOzftLnKw3XPvIJebpYGR7j08/IvfFOFWjz2iKFFJ82f04VZ7HuLwbAPZ8JjsNDg Wo0ZtHG5A5msHTPPLT9pQU1A6yKIZ4CNllHLxODxcsotwT8VwRoqRI4lSbngW2ZBx1 nY18djZKoF4yA== Received: by pali.im (Postfix) id 6831F251F; Mon, 23 Aug 2021 18:41:02 +0200 (CEST) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: Lorenzo Pieralisi , Thomas Petazzoni , Bjorn Helgaas , Rob Herring Cc: =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , =?utf-8?q?Marek_Be?= =?utf-8?q?h=C3=BAn?= , "Marc Zyngier" , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/3] PCI: aardvark: Fix masking MSI interrupts Date: Mon, 23 Aug 2021 18:40:32 +0200 Message-Id: <20210823164033.27491-3-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210823164033.27491-1-pali@kernel.org> References: <20210815103624.19528-1-pali@kernel.org> <20210823164033.27491-1-pali@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Masking of individual MSI interrupts is done via PCIE_MSI_MASK_REG register. At the driver probe time mask all MSI interrupts and then let kernel IRQ chip code to unmask particular MSI interrupt when needed. Signed-off-by: Pali Rohár Cc: stable@vger.kernel.org # f21a8b1b6837 ("PCI: aardvark: Move to MSI handling using generic MSI support") --- Changes in v2: * Guard register updates by raw spin lock --- drivers/pci/controller/pci-aardvark.c | 52 ++++++++++++++++++++++++--- 1 file changed, 48 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index 81c4a9ff91a3..0e81d7f37465 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -241,6 +241,7 @@ struct advk_pcie { struct irq_domain *msi_inner_domain; struct irq_chip msi_bottom_irq_chip; struct irq_chip msi_irq_chip; + raw_spinlock_t msi_irq_lock; struct msi_domain_info msi_domain_info; DECLARE_BITMAP(msi_used, MSI_IRQ_NUM); struct mutex msi_used_lock; @@ -481,12 +482,10 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG); advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG); - /* Disable All ISR0/1 Sources */ + /* Disable All ISR0/1 and MSI Sources */ advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_MASK_REG); advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG); - - /* Unmask all MSIs */ - advk_writel(pcie, ~(u32)PCIE_MSI_ALL_MASK, PCIE_MSI_MASK_REG); + advk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_MASK_REG); /* Unmask summary MSI interrupt */ reg = advk_readl(pcie, PCIE_ISR0_MASK_REG); @@ -1051,6 +1050,46 @@ static int advk_msi_set_affinity(struct irq_data *irq_data, return -EINVAL; } +static void advk_msi_irq_mask(struct irq_data *d) +{ + struct advk_pcie *pcie = d->domain->host_data; + irq_hw_number_t hwirq = irqd_to_hwirq(d); + unsigned long flags; + u32 mask; + + raw_spin_lock_irqsave(&pcie->msi_irq_lock, flags); + mask = advk_readl(pcie, PCIE_MSI_MASK_REG); + mask |= BIT(hwirq); + advk_writel(pcie, mask, PCIE_MSI_MASK_REG); + raw_spin_unlock_irqrestore(&pcie->msi_irq_lock, flags); +} + +static void advk_msi_irq_unmask(struct irq_data *d) +{ + struct advk_pcie *pcie = d->domain->host_data; + irq_hw_number_t hwirq = irqd_to_hwirq(d); + unsigned long flags; + u32 mask; + + raw_spin_lock_irqsave(&pcie->msi_irq_lock, flags); + mask = advk_readl(pcie, PCIE_MSI_MASK_REG); + mask &= ~BIT(hwirq); + advk_writel(pcie, mask, PCIE_MSI_MASK_REG); + raw_spin_unlock_irqrestore(&pcie->msi_irq_lock, flags); +} + +static void advk_msi_top_irq_mask(struct irq_data *d) +{ + pci_msi_mask_irq(d); + irq_chip_mask_parent(d); +} + +static void advk_msi_top_irq_unmask(struct irq_data *d) +{ + pci_msi_unmask_irq(d); + irq_chip_unmask_parent(d); +} + static int advk_msi_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, unsigned int nr_irqs, void *args) @@ -1143,6 +1182,7 @@ static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie) struct irq_chip *bottom_ic, *msi_ic; struct msi_domain_info *msi_di; + raw_spin_lock_init(&pcie->msi_irq_lock); mutex_init(&pcie->msi_used_lock); bottom_ic = &pcie->msi_bottom_irq_chip; @@ -1150,9 +1190,13 @@ static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie) bottom_ic->name = "MSI"; bottom_ic->irq_compose_msi_msg = advk_msi_irq_compose_msi_msg; bottom_ic->irq_set_affinity = advk_msi_set_affinity; + bottom_ic->irq_mask = advk_msi_irq_mask; + bottom_ic->irq_unmask = advk_msi_irq_unmask; msi_ic = &pcie->msi_irq_chip; msi_ic->name = "advk-MSI"; + msi_ic->irq_mask = advk_msi_top_irq_mask; + msi_ic->irq_unmask = advk_msi_top_irq_unmask; msi_di = &pcie->msi_domain_info; msi_di->flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | From patchwork Mon Aug 23 16:40:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 12453191 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 67ED9C4320E for ; Mon, 23 Aug 2021 16:41:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4979B61401 for ; Mon, 23 Aug 2021 16:41:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230289AbhHWQlr (ORCPT ); Mon, 23 Aug 2021 12:41:47 -0400 Received: from mail.kernel.org ([198.145.29.99]:37304 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230174AbhHWQlq (ORCPT ); Mon, 23 Aug 2021 12:41:46 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id E5356613CD; Mon, 23 Aug 2021 16:41:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1629736864; bh=5HNjyxwbp2jWfyQHnbfEn3lq/+lQ4qFD7jbtEyHitV0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=hv6v1BKEgvaUGaswp1pQqZB1BxWaljsjLf+e8DLYgnfJxKdhm9Pdf8cgZKgqNUEC5 WlHitgS+lF5HmPvE5DKbXie1c2f8fs94VzoIKhvNUS++OiecuVd9GQ6Hc+mPzYP3uK ztluzf4T72jYOLTd3jZv5erMdl68WmSmgV9AfaYaXCHvvJkEPMGooI5nT3HLwQGxcv 4ngXq4XlDNmT/nzs9EIbwFGY+tXvar/LMINGEc92zh/Cs7DIuJx1tANzIia7GKAUMW JGXWa2qhE0k/d7I1EUkYfOyxXdLVMUL5a0WDhIXhTFrGwK/5mfnBgT4vfFKniS/+Aa L971zI4g2QKbA== Received: by pali.im (Postfix) id A83FCFC2; Mon, 23 Aug 2021 18:41:03 +0200 (CEST) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: Lorenzo Pieralisi , Thomas Petazzoni , Bjorn Helgaas , Rob Herring Cc: =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , =?utf-8?q?Marek_Be?= =?utf-8?q?h=C3=BAn?= , "Marc Zyngier" , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 3/3] PCI: aardvark: Enable MSI-X support Date: Mon, 23 Aug 2021 18:40:33 +0200 Message-Id: <20210823164033.27491-4-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210823164033.27491-1-pali@kernel.org> References: <20210815103624.19528-1-pali@kernel.org> <20210823164033.27491-1-pali@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org According to PCI 3.0 specification, sending both MSI and MSI-X interrupts is done by DWORD memory write operation to doorbell message address. The write operation for MSI has zero upper 16 bits and the MSI interrupt number in the lower 16 bits. The write operation for MSI-X contains a 32-bit value from MSI-X table. As driver supports and assigns only interrupt numbers from range 0..31, enable also MSI-X support. Testing proved that kernel can correctly receive MSI-X interrupts from PCIe cards which supports both MSI and MSI-X interrupts. Signed-off-by: Pali Rohár Reviewed-by: Marek Behún Cc: stable@vger.kernel.org --- drivers/pci/controller/pci-aardvark.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index 0e81d7f37465..2c944a04fba8 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -1200,7 +1200,7 @@ static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie) msi_di = &pcie->msi_domain_info; msi_di->flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | - MSI_FLAG_MULTI_PCI_MSI; + MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX; msi_di->chip = msi_ic; pcie->msi_inner_domain =