From patchwork Tue Aug 24 10:09:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Finn Thain X-Patchwork-Id: 12454505 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6616DC4320A for ; Tue, 24 Aug 2021 10:15:20 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DBC1561184 for ; Tue, 24 Aug 2021 10:15:18 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org DBC1561184 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=linux-m68k.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:34590 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mITSg-0000ae-0o for qemu-devel@archiver.kernel.org; Tue, 24 Aug 2021 06:15:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51792) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mITRa-0006iA-4q; Tue, 24 Aug 2021 06:14:10 -0400 Received: from wout2-smtp.messagingengine.com ([64.147.123.25]:35823) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mITRY-00045u-Jq; Tue, 24 Aug 2021 06:14:09 -0400 Received: from compute5.internal (compute5.nyi.internal [10.202.2.45]) by mailout.west.internal (Postfix) with ESMTP id C371B3200A90; Tue, 24 Aug 2021 06:14:06 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute5.internal (MEProxy); Tue, 24 Aug 2021 06:14:07 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-proxy:x-me-proxy:x-me-sender :x-me-sender:x-sasl-enc; s=fm3; bh=GOyQvIBmoqlEWKUC1L3vnBey+rGNz lW1F/+LDP21SMU=; b=GW0kkZ7IfcXNLIuhoIXwGLAEh2cksnqyihBNn8wXm9p0i Ys1Q8xZLAqGzCqHZVdlPS+PXZVqP/sMitzeOeJb2YkoTqum9zXoLoohIzcdzX2JY ARkF9VS6U/+cnenuerBu3FwfjWhzogcex84zLWnx5z8G2GyWIskEpH4y4DOCwU56 5pGK1CxI/4X/2ZL9C5PjIVIyB+IZIQM811Lc5rZTBN2zWxLFNFf4kwcCmcpHKeSK Rn03ctiFRTsL6gWlTi4/CQ4Ow1KnYkmRJKoT0uWIH0wnbHPS4e45L4wRSG+BXuA0 hKbVTiCu5mYVD4MNWNtgqxAFD4uxNT3MjMDwwmgVw== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvtddruddtjedgvdehucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhepvffkjghfhffuffestddtredttddttdenucfhrhhomhephfhinhhnucfvhhgr ihhnuceofhhthhgrihhnsehlihhnuhigqdhmieekkhdrohhrgheqnecuggftrfgrthhtvg hrnhephfetledtgeffuedujedvteevgfdtudeufeekvdfhveekkefhgfevtdfhveeuueet necuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehmrghilhhfrhhomhepfhhthh grihhnsehlihhnuhigqdhmieekkhdrohhrgh X-ME-Proxy: Received: by mail.messagingengine.com (Postfix) with ESMTPA; Tue, 24 Aug 2021 06:14:03 -0400 (EDT) To: Mark Cave-Ayland , David Gibson , Greg Kurz Message-Id: <9b78e8c6e453feab6275d04bf503051645770d85.1629799776.git.fthain@linux-m68k.org> In-Reply-To: References: From: Finn Thain Subject: [RFC 01/10] hw/mos6522: Remove get_load_time() methods and functions Date: Tue, 24 Aug 2021 20:09:36 +1000 Received-SPF: none client-ip=64.147.123.25; envelope-from=fthain@linux-m68k.org; helo=wout2-smtp.messagingengine.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, Laurent Vivier , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" This code appears to be unnecessary. Signed-off-by: Finn Thain Reviewed-by: Philippe Mathieu-Daudé --- hw/misc/mos6522.c | 22 +--------------------- 1 file changed, 1 insertion(+), 21 deletions(-) diff --git a/hw/misc/mos6522.c b/hw/misc/mos6522.c index 1c57332b40..a478c1ca43 100644 --- a/hw/misc/mos6522.c +++ b/hw/misc/mos6522.c @@ -63,17 +63,6 @@ static uint64_t get_counter_value(MOS6522State *s, MOS6522Timer *ti) } } -static uint64_t get_load_time(MOS6522State *s, MOS6522Timer *ti) -{ - MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(s); - - if (ti->index == 0) { - return mdc->get_timer1_load_time(s, ti); - } else { - return mdc->get_timer2_load_time(s, ti); - } -} - static unsigned int get_counter(MOS6522State *s, MOS6522Timer *ti) { int64_t d; @@ -98,7 +87,7 @@ static unsigned int get_counter(MOS6522State *s, MOS6522Timer *ti) static void set_counter(MOS6522State *s, MOS6522Timer *ti, unsigned int val) { trace_mos6522_set_counter(1 + ti->index, val); - ti->load_time = get_load_time(s, ti); + ti->load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); ti->counter_value = val; if (ti->index == 0) { mos6522_timer1_update(s, ti, ti->load_time); @@ -208,13 +197,6 @@ static uint64_t mos6522_get_counter_value(MOS6522State *s, MOS6522Timer *ti) ti->frequency, NANOSECONDS_PER_SECOND); } -static uint64_t mos6522_get_load_time(MOS6522State *s, MOS6522Timer *ti) -{ - uint64_t load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); - - return load_time; -} - static void mos6522_portA_write(MOS6522State *s) { qemu_log_mask(LOG_UNIMP, "portA_write unimplemented\n"); @@ -518,8 +500,6 @@ static void mos6522_class_init(ObjectClass *oc, void *data) mdc->update_irq = mos6522_update_irq; mdc->get_timer1_counter_value = mos6522_get_counter_value; mdc->get_timer2_counter_value = mos6522_get_counter_value; - mdc->get_timer1_load_time = mos6522_get_load_time; - mdc->get_timer2_load_time = mos6522_get_load_time; } static const TypeInfo mos6522_type_info = { From patchwork Tue Aug 24 10:09:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Finn Thain X-Patchwork-Id: 12454507 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C1D31C4320A for ; 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Tue, 24 Aug 2021 06:14:13 -0400 (EDT) To: Mark Cave-Ayland , David Gibson , Greg Kurz Message-Id: <0f0fe91d4b1878000260bea3bb44bcb61525ae13.1629799776.git.fthain@linux-m68k.org> In-Reply-To: References: From: Finn Thain Subject: [RFC 02/10] hw/mos6522: Remove get_counter_value() methods and functions Date: Tue, 24 Aug 2021 20:09:36 +1000 Received-SPF: none client-ip=64.147.123.25; envelope-from=fthain@linux-m68k.org; helo=wout2-smtp.messagingengine.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, Laurent Vivier , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" This code appears to be unnecessary. Also, these routines don't return the counter value but a time interval between counter values, so they are misnamed. Signed-off-by: Finn Thain Reviewed-by: Philippe Mathieu-Daudé --- hw/misc/mos6522.c | 22 ++-------------------- 1 file changed, 2 insertions(+), 20 deletions(-) diff --git a/hw/misc/mos6522.c b/hw/misc/mos6522.c index a478c1ca43..ff246b5437 100644 --- a/hw/misc/mos6522.c +++ b/hw/misc/mos6522.c @@ -52,23 +52,13 @@ static void mos6522_update_irq(MOS6522State *s) } } -static uint64_t get_counter_value(MOS6522State *s, MOS6522Timer *ti) -{ - MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(s); - - if (ti->index == 0) { - return mdc->get_timer1_counter_value(s, ti); - } else { - return mdc->get_timer2_counter_value(s, ti); - } -} - static unsigned int get_counter(MOS6522State *s, MOS6522Timer *ti) { int64_t d; unsigned int counter; - d = get_counter_value(s, ti); + d = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - ti->load_time, + ti->frequency, NANOSECONDS_PER_SECOND); if (ti->index == 0) { /* the timer goes down from latch to -1 (period of latch + 2) */ @@ -191,12 +181,6 @@ static void mos6522_set_sr_int(MOS6522State *s) mos6522_update_irq(s); } -static uint64_t mos6522_get_counter_value(MOS6522State *s, MOS6522Timer *ti) -{ - return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - ti->load_time, - ti->frequency, NANOSECONDS_PER_SECOND); -} - static void mos6522_portA_write(MOS6522State *s) { qemu_log_mask(LOG_UNIMP, "portA_write unimplemented\n"); @@ -498,8 +482,6 @@ static void mos6522_class_init(ObjectClass *oc, void *data) mdc->portB_write = mos6522_portB_write; mdc->portA_write = mos6522_portA_write; mdc->update_irq = mos6522_update_irq; - mdc->get_timer1_counter_value = mos6522_get_counter_value; - mdc->get_timer2_counter_value = mos6522_get_counter_value; } static const TypeInfo mos6522_type_info = { From patchwork Tue Aug 24 10:09:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Finn Thain X-Patchwork-Id: 12454513 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A84EFC4338F for ; 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Tue, 24 Aug 2021 06:14:23 -0400 (EDT) To: Mark Cave-Ayland , David Gibson , Greg Kurz Message-Id: <920eddc0e99bf57e7ac540502f863f222c401d2f.1629799776.git.fthain@linux-m68k.org> In-Reply-To: References: From: Finn Thain Subject: [RFC 03/10] hw/mos6522: Remove redundant mos6522_timer1_update() calls Date: Tue, 24 Aug 2021 20:09:36 +1000 Received-SPF: none client-ip=64.147.123.25; envelope-from=fthain@linux-m68k.org; helo=wout2-smtp.messagingengine.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, Laurent Vivier , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Reads and writes to the TL and TC registers have no immediate effect on a running timer, with the exception of a write to TCH. Hence these mos6522_timer_update() calls are not needed. Signed-off-by: Finn Thain --- hw/misc/mos6522.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/hw/misc/mos6522.c b/hw/misc/mos6522.c index ff246b5437..1d4a56077e 100644 --- a/hw/misc/mos6522.c +++ b/hw/misc/mos6522.c @@ -234,7 +234,6 @@ uint64_t mos6522_read(void *opaque, hwaddr addr, unsigned size) val = s->timers[0].latch & 0xff; break; case VIA_REG_T1LH: - /* XXX: check this */ val = (s->timers[0].latch >> 8) & 0xff; break; case VIA_REG_T2CL: @@ -303,8 +302,6 @@ void mos6522_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) break; case VIA_REG_T1CL: s->timers[0].latch = (s->timers[0].latch & 0xff00) | val; - mos6522_timer1_update(s, &s->timers[0], - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); break; case VIA_REG_T1CH: s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8); @@ -313,14 +310,10 @@ void mos6522_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) break; case VIA_REG_T1LL: s->timers[0].latch = (s->timers[0].latch & 0xff00) | val; - mos6522_timer1_update(s, &s->timers[0], - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); break; case VIA_REG_T1LH: s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8); s->ifr &= ~T1_INT; - mos6522_timer1_update(s, &s->timers[0], - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); break; case VIA_REG_T2CL: s->timers[1].latch = (s->timers[1].latch & 0xff00) | val; From patchwork Tue Aug 24 10:09:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Finn Thain X-Patchwork-Id: 12454509 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C8CD8C4338F for ; Tue, 24 Aug 2021 10:16:05 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7ED9E611CB for ; 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Tue, 24 Aug 2021 06:14:33 -0400 (EDT) To: Mark Cave-Ayland , David Gibson , Greg Kurz Message-Id: In-Reply-To: References: From: Finn Thain Subject: [RFC 04/10] hw/mos6522: Rename timer callback functions Date: Tue, 24 Aug 2021 20:09:36 +1000 Received-SPF: none client-ip=64.147.123.25; envelope-from=fthain@linux-m68k.org; helo=wout2-smtp.messagingengine.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, Laurent Vivier , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" This improves readability. Signed-off-by: Finn Thain Reviewed-by: Philippe Mathieu-Daudé --- hw/misc/mos6522.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/hw/misc/mos6522.c b/hw/misc/mos6522.c index 1d4a56077e..c0d6bee4cc 100644 --- a/hw/misc/mos6522.c +++ b/hw/misc/mos6522.c @@ -154,7 +154,7 @@ static void mos6522_timer2_update(MOS6522State *s, MOS6522Timer *ti, } } -static void mos6522_timer1(void *opaque) +static void mos6522_timer1_expired(void *opaque) { MOS6522State *s = opaque; MOS6522Timer *ti = &s->timers[0]; @@ -164,7 +164,7 @@ static void mos6522_timer1(void *opaque) mos6522_update_irq(s); } -static void mos6522_timer2(void *opaque) +static void mos6522_timer2_expired(void *opaque) { MOS6522State *s = opaque; MOS6522Timer *ti = &s->timers[1]; @@ -445,8 +445,10 @@ static void mos6522_init(Object *obj) s->timers[i].index = i; } - s->timers[0].timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, mos6522_timer1, s); - s->timers[1].timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, mos6522_timer2, s); + s->timers[0].timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, + mos6522_timer1_expired, s); + s->timers[1].timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, + mos6522_timer2_expired, s); } static void mos6522_finalize(Object *obj) From patchwork Tue Aug 24 10:09:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Finn Thain X-Patchwork-Id: 12454511 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D8CE8C4338F for ; Tue, 24 Aug 2021 10:17:17 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A729360238 for ; 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Tue, 24 Aug 2021 06:14:42 -0400 (EDT) To: Mark Cave-Ayland , David Gibson , Greg Kurz Message-Id: In-Reply-To: References: From: Finn Thain Subject: [RFC 05/10] hw/mos6522: Don't clear T1 interrupt flag on latch write Date: Tue, 24 Aug 2021 20:09:36 +1000 Received-SPF: none client-ip=64.147.123.25; envelope-from=fthain@linux-m68k.org; helo=wout2-smtp.messagingengine.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, Laurent Vivier , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The Synertek datasheet says, "A write to T1L-H loads an 8-bit count value into the latch. A read of T1L-H transfers the contents of the latch to the data bus. Neither operation has an affect [sic] on the interrupt flag." Signed-off-by: Finn Thain --- hw/misc/mos6522.c | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/misc/mos6522.c b/hw/misc/mos6522.c index c0d6bee4cc..ffff8991f4 100644 --- a/hw/misc/mos6522.c +++ b/hw/misc/mos6522.c @@ -313,7 +313,6 @@ void mos6522_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) break; case VIA_REG_T1LH: s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8); - s->ifr &= ~T1_INT; break; case VIA_REG_T2CL: s->timers[1].latch = (s->timers[1].latch & 0xff00) | val; From patchwork Tue Aug 24 10:09:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Finn Thain X-Patchwork-Id: 12454517 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 27BE5C4338F for ; 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Tue, 24 Aug 2021 06:14:50 -0400 (EDT) To: Mark Cave-Ayland , David Gibson , Greg Kurz Message-Id: <45c9d15c51076bba431e5593dbfcbcca2e1dc09a.1629799776.git.fthain@linux-m68k.org> In-Reply-To: References: From: Finn Thain Subject: [RFC 06/10] hw/mos6522: Implement oneshot mode Date: Tue, 24 Aug 2021 20:09:36 +1000 Received-SPF: none client-ip=64.147.123.25; envelope-from=fthain@linux-m68k.org; helo=wout2-smtp.messagingengine.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, Laurent Vivier , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Finn Thain --- hw/misc/mos6522.c | 19 ++++++++++++------- include/hw/misc/mos6522.h | 3 +++ 2 files changed, 15 insertions(+), 7 deletions(-) diff --git a/hw/misc/mos6522.c b/hw/misc/mos6522.c index ffff8991f4..5b1657ac0d 100644 --- a/hw/misc/mos6522.c +++ b/hw/misc/mos6522.c @@ -79,6 +79,7 @@ static void set_counter(MOS6522State *s, MOS6522Timer *ti, unsigned int val) trace_mos6522_set_counter(1 + ti->index, val); ti->load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); ti->counter_value = val; + ti->oneshot_fired = false; if (ti->index == 0) { mos6522_timer1_update(s, ti, ti->load_time); } else { @@ -133,7 +134,8 @@ static void mos6522_timer1_update(MOS6522State *s, MOS6522Timer *ti, return; } ti->next_irq_time = get_next_irq_time(s, ti, current_time); - if ((s->ier & T1_INT) == 0 || (s->acr & T1MODE) != T1MODE_CONT) { + if ((s->ier & T1_INT) == 0 || + ((s->acr & T1MODE) == T1MODE_ONESHOT && ti->oneshot_fired)) { timer_del(ti->timer); } else { timer_mod(ti->timer, ti->next_irq_time); @@ -147,7 +149,7 @@ static void mos6522_timer2_update(MOS6522State *s, MOS6522Timer *ti, return; } ti->next_irq_time = get_next_irq_time(s, ti, current_time); - if ((s->ier & T2_INT) == 0) { + if ((s->ier & T2_INT) == 0 || (s->acr & T2MODE) || ti->oneshot_fired) { timer_del(ti->timer); } else { timer_mod(ti->timer, ti->next_irq_time); @@ -159,6 +161,7 @@ static void mos6522_timer1_expired(void *opaque) MOS6522State *s = opaque; MOS6522Timer *ti = &s->timers[0]; + ti->oneshot_fired = true; mos6522_timer1_update(s, ti, ti->next_irq_time); s->ifr |= T1_INT; mos6522_update_irq(s); @@ -169,6 +172,7 @@ static void mos6522_timer2_expired(void *opaque) MOS6522State *s = opaque; MOS6522Timer *ti = &s->timers[1]; + ti->oneshot_fired = true; mos6522_timer2_update(s, ti, ti->next_irq_time); s->ifr |= T2_INT; mos6522_update_irq(s); @@ -198,10 +202,12 @@ uint64_t mos6522_read(void *opaque, hwaddr addr, unsigned size) int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); if (now >= s->timers[0].next_irq_time) { + s->timers[0].oneshot_fired = true; mos6522_timer1_update(s, &s->timers[0], now); s->ifr |= T1_INT; } if (now >= s->timers[1].next_irq_time) { + s->timers[1].oneshot_fired = true; mos6522_timer2_update(s, &s->timers[1], now); s->ifr |= T2_INT; } @@ -279,6 +285,7 @@ void mos6522_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) { MOS6522State *s = opaque; MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(s); + int64_t now; trace_mos6522_write(addr, val); @@ -318,9 +325,6 @@ void mos6522_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) s->timers[1].latch = (s->timers[1].latch & 0xff00) | val; break; case VIA_REG_T2CH: - /* To ensure T2 generates an interrupt on zero crossing with the - common timer code, write the value directly from the latch to - the counter */ s->timers[1].latch = (s->timers[1].latch & 0xff) | (val << 8); s->ifr &= ~T2_INT; set_counter(s, &s->timers[1], s->timers[1].latch); @@ -330,8 +334,9 @@ void mos6522_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) break; case VIA_REG_ACR: s->acr = val; - mos6522_timer1_update(s, &s->timers[0], - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); + now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + mos6522_timer1_update(s, &s->timers[0], now); + mos6522_timer2_update(s, &s->timers[1], now); break; case VIA_REG_PCR: s->pcr = val; diff --git a/include/hw/misc/mos6522.h b/include/hw/misc/mos6522.h index fc95d22b0f..94b1dc324c 100644 --- a/include/hw/misc/mos6522.h +++ b/include/hw/misc/mos6522.h @@ -50,8 +50,10 @@ #define T1_INT 0x40 /* Timer 1 interrupt */ /* Bits in ACR */ +#define T2MODE 0x20 /* Timer 2 mode */ #define T1MODE 0xc0 /* Timer 1 mode */ #define T1MODE_CONT 0x40 /* continuous interrupts */ +#define T1MODE_ONESHOT 0x00 /* timed interrupt */ /* VIA registers */ #define VIA_REG_B 0x00 @@ -83,6 +85,7 @@ typedef struct MOS6522Timer { int64_t next_irq_time; uint64_t frequency; QEMUTimer *timer; + bool oneshot_fired; } MOS6522Timer; /** From patchwork Tue Aug 24 10:09:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Finn Thain X-Patchwork-Id: 12454515 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 69E59C4338F for ; Tue, 24 Aug 2021 10:17:37 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3107260238 for ; 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Tue, 24 Aug 2021 06:15:01 -0400 (EDT) To: Mark Cave-Ayland , David Gibson , Greg Kurz Message-Id: In-Reply-To: References: From: Finn Thain Subject: [RFC 07/10] hw/mos6522: Fix initial timer counter reload Date: Tue, 24 Aug 2021 20:09:36 +1000 Received-SPF: none client-ip=64.147.123.25; envelope-from=fthain@linux-m68k.org; helo=wout2-smtp.messagingengine.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, Laurent Vivier , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The first reload of timer 1 is early by half of a clock cycle as it gets measured from a falling edge. By contrast, the succeeding reloads are measured from rising edge to rising edge. Neglecting that complication, the behaviour of the counter should be the same from one reload to the next. The sequence is always: N, N-1, N-2, ... 2, 1, 0, -1, N, N-1, N-2, ... But at the first reload, the present driver does this instead: N, N-1, N-2, ... 2, 1, 0, -1, N-1, N-2, ... Fix this deviation for both timer 1 and timer 2, and allow for the fact that on a real 6522 the timer 2 counter is not reloaded when it wraps. Signed-off-by: Finn Thain --- hw/misc/mos6522.c | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/hw/misc/mos6522.c b/hw/misc/mos6522.c index 5b1657ac0d..0a241fe9f8 100644 --- a/hw/misc/mos6522.c +++ b/hw/misc/mos6522.c @@ -63,15 +63,16 @@ static unsigned int get_counter(MOS6522State *s, MOS6522Timer *ti) if (ti->index == 0) { /* the timer goes down from latch to -1 (period of latch + 2) */ if (d <= (ti->counter_value + 1)) { - counter = (ti->counter_value - d) & 0xffff; + counter = ti->counter_value - d; } else { - counter = (d - (ti->counter_value + 1)) % (ti->latch + 2); - counter = (ti->latch - counter) & 0xffff; + int64_t d_post_reload = d - (ti->counter_value + 2); + /* XXX this calculation assumes that ti->latch has not changed */ + counter = ti->latch - (d_post_reload % (ti->latch + 2)); } } else { - counter = (ti->counter_value - d) & 0xffff; + counter = ti->counter_value - d; } - return counter; + return counter & 0xffff; } static void set_counter(MOS6522State *s, MOS6522Timer *ti, unsigned int val) @@ -103,11 +104,13 @@ static int64_t get_next_irq_time(MOS6522State *s, MOS6522Timer *ti, /* the timer goes down from latch to -1 (period of latch + 2) */ if (d <= (ti->counter_value + 1)) { - counter = (ti->counter_value - d) & 0xffff; + counter = ti->counter_value - d; } else { - counter = (d - (ti->counter_value + 1)) % (ti->latch + 2); - counter = (ti->latch - counter) & 0xffff; + int64_t d_post_reload = d - (ti->counter_value + 2); + /* XXX this calculation assumes that ti->latch has not changed */ + counter = ti->latch - (d_post_reload % (ti->latch + 2)); } + counter &= 0xffff; /* Note: we consider the irq is raised on 0 */ if (counter == 0xffff) { From patchwork Tue Aug 24 10:09:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Finn Thain X-Patchwork-Id: 12454543 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9BE3DC4338F for ; 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Tue, 24 Aug 2021 06:15:09 -0400 (EDT) To: Mark Cave-Ayland , David Gibson , Greg Kurz Message-Id: In-Reply-To: References: From: Finn Thain Subject: [RFC 08/10] hw/mos6522: Call mos6522_update_irq() when appropriate Date: Tue, 24 Aug 2021 20:09:36 +1000 Received-SPF: none client-ip=64.147.123.25; envelope-from=fthain@linux-m68k.org; helo=wout2-smtp.messagingengine.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, Laurent Vivier , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" It necessary to call mos6522_update_irq() when the interrupt flags change and unnecessary when they haven't. Signed-off-by: Finn Thain Reviewed-by: Philippe Mathieu-Daudé --- hw/misc/mos6522.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/misc/mos6522.c b/hw/misc/mos6522.c index 0a241fe9f8..0dd3ccf945 100644 --- a/hw/misc/mos6522.c +++ b/hw/misc/mos6522.c @@ -208,11 +208,13 @@ uint64_t mos6522_read(void *opaque, hwaddr addr, unsigned size) s->timers[0].oneshot_fired = true; mos6522_timer1_update(s, &s->timers[0], now); s->ifr |= T1_INT; + mos6522_update_irq(s); } if (now >= s->timers[1].next_irq_time) { s->timers[1].oneshot_fired = true; mos6522_timer2_update(s, &s->timers[1], now); s->ifr |= T2_INT; + mos6522_update_irq(s); } switch (addr) { case VIA_REG_B: @@ -237,7 +239,6 @@ uint64_t mos6522_read(void *opaque, hwaddr addr, unsigned size) break; case VIA_REG_T1CH: val = get_counter(s, &s->timers[0]) >> 8; - mos6522_update_irq(s); break; case VIA_REG_T1LL: val = s->timers[0].latch & 0xff; From patchwork Tue Aug 24 10:09:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Finn Thain X-Patchwork-Id: 12454541 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E8BABC4320A for ; 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Tue, 24 Aug 2021 06:15:18 -0400 (EDT) To: Mark Cave-Ayland , David Gibson , Greg Kurz Message-Id: <21f20ab5a100e4947d840080114f3f0511aade86.1629799776.git.fthain@linux-m68k.org> In-Reply-To: References: From: Finn Thain Subject: [RFC 09/10] hw/mos6522: Avoid using discrepant QEMU clock values Date: Tue, 24 Aug 2021 20:09:36 +1000 Received-SPF: none client-ip=64.147.123.25; envelope-from=fthain@linux-m68k.org; helo=wout2-smtp.messagingengine.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, Laurent Vivier , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" mos6522_read() and mos6522_write() may call various functions to determine timer irq state, timer counter value and QEMUTimer deadline. All called functions must use the same value for the present time. Signed-off-by: Finn Thain Reviewed-by: Philippe Mathieu-Daudé --- hw/misc/mos6522.c | 51 +++++++++++++++++++++++++---------------------- 1 file changed, 27 insertions(+), 24 deletions(-) diff --git a/hw/misc/mos6522.c b/hw/misc/mos6522.c index 0dd3ccf945..23a440b64f 100644 --- a/hw/misc/mos6522.c +++ b/hw/misc/mos6522.c @@ -39,9 +39,9 @@ /* XXX: implement all timer modes */ static void mos6522_timer1_update(MOS6522State *s, MOS6522Timer *ti, - int64_t current_time); + int64_t now); static void mos6522_timer2_update(MOS6522State *s, MOS6522Timer *ti, - int64_t current_time); + int64_t now); static void mos6522_update_irq(MOS6522State *s) { @@ -52,12 +52,12 @@ static void mos6522_update_irq(MOS6522State *s) } } -static unsigned int get_counter(MOS6522State *s, MOS6522Timer *ti) +static unsigned int get_counter(MOS6522State *s, MOS6522Timer *ti, int64_t now) { int64_t d; unsigned int counter; - d = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - ti->load_time, + d = muldiv64(now - ti->load_time, ti->frequency, NANOSECONDS_PER_SECOND); if (ti->index == 0) { @@ -89,7 +89,7 @@ static void set_counter(MOS6522State *s, MOS6522Timer *ti, unsigned int val) } static int64_t get_next_irq_time(MOS6522State *s, MOS6522Timer *ti, - int64_t current_time) + int64_t now) { int64_t d, next_time; unsigned int counter; @@ -99,7 +99,7 @@ static int64_t get_next_irq_time(MOS6522State *s, MOS6522Timer *ti, } /* current counter value */ - d = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - ti->load_time, + d = muldiv64(now - ti->load_time, ti->frequency, NANOSECONDS_PER_SECOND); /* the timer goes down from latch to -1 (period of latch + 2) */ @@ -123,20 +123,19 @@ static int64_t get_next_irq_time(MOS6522State *s, MOS6522Timer *ti, trace_mos6522_get_next_irq_time(ti->latch, d, next_time - d); next_time = muldiv64(next_time, NANOSECONDS_PER_SECOND, ti->frequency) + ti->load_time; - - if (next_time <= current_time) { - next_time = current_time + 1; - } return next_time; } static void mos6522_timer1_update(MOS6522State *s, MOS6522Timer *ti, - int64_t current_time) + int64_t now) { if (!ti->timer) { return; } - ti->next_irq_time = get_next_irq_time(s, ti, current_time); + ti->next_irq_time = get_next_irq_time(s, ti, now); + if (ti->next_irq_time <= now) { + ti->next_irq_time = now + 1; + } if ((s->ier & T1_INT) == 0 || ((s->acr & T1MODE) == T1MODE_ONESHOT && ti->oneshot_fired)) { timer_del(ti->timer); @@ -146,12 +145,15 @@ static void mos6522_timer1_update(MOS6522State *s, MOS6522Timer *ti, } static void mos6522_timer2_update(MOS6522State *s, MOS6522Timer *ti, - int64_t current_time) + int64_t now) { if (!ti->timer) { return; } - ti->next_irq_time = get_next_irq_time(s, ti, current_time); + ti->next_irq_time = get_next_irq_time(s, ti, now); + if (ti->next_irq_time <= now) { + ti->next_irq_time = now + 1; + } if ((s->ier & T2_INT) == 0 || (s->acr & T2MODE) || ti->oneshot_fired) { timer_del(ti->timer); } else { @@ -163,9 +165,10 @@ static void mos6522_timer1_expired(void *opaque) { MOS6522State *s = opaque; MOS6522Timer *ti = &s->timers[0]; + int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); ti->oneshot_fired = true; - mos6522_timer1_update(s, ti, ti->next_irq_time); + mos6522_timer1_update(s, ti, now); s->ifr |= T1_INT; mos6522_update_irq(s); } @@ -174,9 +177,10 @@ static void mos6522_timer2_expired(void *opaque) { MOS6522State *s = opaque; MOS6522Timer *ti = &s->timers[1]; + int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); ti->oneshot_fired = true; - mos6522_timer2_update(s, ti, ti->next_irq_time); + mos6522_timer2_update(s, ti, now); s->ifr |= T2_INT; mos6522_update_irq(s); } @@ -233,12 +237,12 @@ uint64_t mos6522_read(void *opaque, hwaddr addr, unsigned size) val = s->dira; break; case VIA_REG_T1CL: - val = get_counter(s, &s->timers[0]) & 0xff; + val = get_counter(s, &s->timers[0], now) & 0xff; s->ifr &= ~T1_INT; mos6522_update_irq(s); break; case VIA_REG_T1CH: - val = get_counter(s, &s->timers[0]) >> 8; + val = get_counter(s, &s->timers[0], now) >> 8; break; case VIA_REG_T1LL: val = s->timers[0].latch & 0xff; @@ -247,12 +251,12 @@ uint64_t mos6522_read(void *opaque, hwaddr addr, unsigned size) val = (s->timers[0].latch >> 8) & 0xff; break; case VIA_REG_T2CL: - val = get_counter(s, &s->timers[1]) & 0xff; + val = get_counter(s, &s->timers[1], now) & 0xff; s->ifr &= ~T2_INT; mos6522_update_irq(s); break; case VIA_REG_T2CH: - val = get_counter(s, &s->timers[1]) >> 8; + val = get_counter(s, &s->timers[1], now) >> 8; break; case VIA_REG_SR: val = s->sr; @@ -360,10 +364,9 @@ void mos6522_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) } mos6522_update_irq(s); /* if IER is modified starts needed timers */ - mos6522_timer1_update(s, &s->timers[0], - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); - mos6522_timer2_update(s, &s->timers[1], - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); + now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + mos6522_timer1_update(s, &s->timers[0], now); + mos6522_timer2_update(s, &s->timers[1], now); break; default: g_assert_not_reached(); From patchwork Tue Aug 24 10:09:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Finn Thain X-Patchwork-Id: 12454547 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B8D10C432BE for ; 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Tue, 24 Aug 2021 06:15:29 -0400 (EDT) To: Mark Cave-Ayland , David Gibson , Greg Kurz Message-Id: In-Reply-To: References: From: Finn Thain Subject: [RFC 10/10] hw/mos6522: Synchronize timer interrupt and timer counter Date: Tue, 24 Aug 2021 20:09:36 +1000 Received-SPF: none client-ip=64.147.123.25; envelope-from=fthain@linux-m68k.org; helo=wout2-smtp.messagingengine.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, Laurent Vivier , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" We rely on a QEMUTimer callback to set the interrupt flag, and this races with counter register accesses, such that the guest might see the counter reloaded but might not see the interrupt flagged. According to the datasheet, a real 6522 device counts down to FFFF, then raises the relevant IRQ. After the FFFF count, the counter reloads from the latch (for timer 1) or continues to decrement thru FFFE (for timer 2). Therefore, the guest operating system may read zero from T1CH and infer that the counter has not yet wrapped (given another full count hasn't yet elapsed.) Similarly, the guest may find the timer interrupt flag to be set and infer that the counter is non-zero (given another full count hasn't yet elapsed). Synchronize the timer counter and interrupt flag such that the guest will observe the correct sequence of states. (It's still not right, because in reality it's not possible to access the registers more than once per "phase 2" clock cycle.) Eliminate the duplication of logic in get_counter() and get_next_irq_time() by calling the former before the latter. Note that get_counter() is called prior to changing the latch. This is because get_counter() may need to use the old latch value in order to reload the counter. Signed-off-by: Finn Thain --- hw/misc/mos6522.c | 154 ++++++++++++++++++++------------------ hw/misc/trace-events | 2 +- include/hw/misc/mos6522.h | 8 +- 3 files changed, 88 insertions(+), 76 deletions(-) diff --git a/hw/misc/mos6522.c b/hw/misc/mos6522.c index 23a440b64f..bd5df4963b 100644 --- a/hw/misc/mos6522.c +++ b/hw/misc/mos6522.c @@ -52,26 +52,58 @@ static void mos6522_update_irq(MOS6522State *s) } } +static void mos6522_timer_raise_irq(MOS6522State *s, MOS6522Timer *ti) +{ + if (ti->state == irq) { + return; + } + ti->state = irq; + if (ti->index == 0) { + s->ifr |= T1_INT; + } else { + s->ifr |= T2_INT; + } + mos6522_update_irq(s); +} + static unsigned int get_counter(MOS6522State *s, MOS6522Timer *ti, int64_t now) { int64_t d; unsigned int counter; - + bool reload; + + /* + * Timer 1 counts down from the latch value to -1 (period of latch + 2), + * then raises its interrupt and reloads. + * Timer 2 counts down from the latch value to -1, then raises its + * interrupt and continues to -2 and so on without any further interrupts. + * (In reality, the first count should be measured from the falling edge + * of the "phase two" clock, making its period N + 1.5. The subsequent + * counts have period N + 2. This detail has been ignored here.) + */ d = muldiv64(now - ti->load_time, ti->frequency, NANOSECONDS_PER_SECOND); - if (ti->index == 0) { - /* the timer goes down from latch to -1 (period of latch + 2) */ - if (d <= (ti->counter_value + 1)) { - counter = ti->counter_value - d; - } else { - int64_t d_post_reload = d - (ti->counter_value + 2); - /* XXX this calculation assumes that ti->latch has not changed */ - counter = ti->latch - (d_post_reload % (ti->latch + 2)); - } - } else { - counter = ti->counter_value - d; + reload = (d >= ti->counter_value + 2); + + if (ti->index == 0 && reload) { + int64_t more_reloads; + + d -= ti->counter_value + 2; + more_reloads = d / (ti->latch + 2); + d -= more_reloads * (ti->latch + 2); + ti->load_time += muldiv64(ti->counter_value + 2 + + more_reloads * (ti->latch + 2), + NANOSECONDS_PER_SECOND, ti->frequency); + ti->counter_value = ti->latch; } + + counter = ti->counter_value - d; + + if (reload) { + mos6522_timer_raise_irq(s, ti); + } + return counter & 0xffff; } @@ -80,7 +112,7 @@ static void set_counter(MOS6522State *s, MOS6522Timer *ti, unsigned int val) trace_mos6522_set_counter(1 + ti->index, val); ti->load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); ti->counter_value = val; - ti->oneshot_fired = false; + ti->state = decrement; if (ti->index == 0) { mos6522_timer1_update(s, ti, ti->load_time); } else { @@ -91,38 +123,15 @@ static void set_counter(MOS6522State *s, MOS6522Timer *ti, unsigned int val) static int64_t get_next_irq_time(MOS6522State *s, MOS6522Timer *ti, int64_t now) { - int64_t d, next_time; - unsigned int counter; + int64_t next_time; if (ti->frequency == 0) { return INT64_MAX; } - /* current counter value */ - d = muldiv64(now - ti->load_time, - ti->frequency, NANOSECONDS_PER_SECOND); - - /* the timer goes down from latch to -1 (period of latch + 2) */ - if (d <= (ti->counter_value + 1)) { - counter = ti->counter_value - d; - } else { - int64_t d_post_reload = d - (ti->counter_value + 2); - /* XXX this calculation assumes that ti->latch has not changed */ - counter = ti->latch - (d_post_reload % (ti->latch + 2)); - } - counter &= 0xffff; - - /* Note: we consider the irq is raised on 0 */ - if (counter == 0xffff) { - next_time = d + ti->latch + 1; - } else if (counter == 0) { - next_time = d + ti->latch + 2; - } else { - next_time = d + counter; - } - trace_mos6522_get_next_irq_time(ti->latch, d, next_time - d); - next_time = muldiv64(next_time, NANOSECONDS_PER_SECOND, ti->frequency) + - ti->load_time; + next_time = ti->load_time + muldiv64(ti->counter_value + 2, + NANOSECONDS_PER_SECOND, ti->frequency); + trace_mos6522_get_next_irq_time(ti->latch, ti->load_time, next_time); return next_time; } @@ -132,12 +141,10 @@ static void mos6522_timer1_update(MOS6522State *s, MOS6522Timer *ti, if (!ti->timer) { return; } + get_counter(s, ti, now); ti->next_irq_time = get_next_irq_time(s, ti, now); - if (ti->next_irq_time <= now) { - ti->next_irq_time = now + 1; - } if ((s->ier & T1_INT) == 0 || - ((s->acr & T1MODE) == T1MODE_ONESHOT && ti->oneshot_fired)) { + ((s->acr & T1MODE) == T1MODE_ONESHOT && ti->state >= irq)) { timer_del(ti->timer); } else { timer_mod(ti->timer, ti->next_irq_time); @@ -150,11 +157,9 @@ static void mos6522_timer2_update(MOS6522State *s, MOS6522Timer *ti, if (!ti->timer) { return; } + get_counter(s, ti, now); ti->next_irq_time = get_next_irq_time(s, ti, now); - if (ti->next_irq_time <= now) { - ti->next_irq_time = now + 1; - } - if ((s->ier & T2_INT) == 0 || (s->acr & T2MODE) || ti->oneshot_fired) { + if ((s->ier & T2_INT) == 0 || (s->acr & T2MODE) || ti->state >= irq) { timer_del(ti->timer); } else { timer_mod(ti->timer, ti->next_irq_time); @@ -167,10 +172,7 @@ static void mos6522_timer1_expired(void *opaque) MOS6522Timer *ti = &s->timers[0]; int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); - ti->oneshot_fired = true; mos6522_timer1_update(s, ti, now); - s->ifr |= T1_INT; - mos6522_update_irq(s); } static void mos6522_timer2_expired(void *opaque) @@ -179,10 +181,7 @@ static void mos6522_timer2_expired(void *opaque) MOS6522Timer *ti = &s->timers[1]; int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); - ti->oneshot_fired = true; mos6522_timer2_update(s, ti, now); - s->ifr |= T2_INT; - mos6522_update_irq(s); } static void mos6522_set_sr_int(MOS6522State *s) @@ -208,18 +207,6 @@ uint64_t mos6522_read(void *opaque, hwaddr addr, unsigned size) uint32_t val; int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); - if (now >= s->timers[0].next_irq_time) { - s->timers[0].oneshot_fired = true; - mos6522_timer1_update(s, &s->timers[0], now); - s->ifr |= T1_INT; - mos6522_update_irq(s); - } - if (now >= s->timers[1].next_irq_time) { - s->timers[1].oneshot_fired = true; - mos6522_timer2_update(s, &s->timers[1], now); - s->ifr |= T2_INT; - mos6522_update_irq(s); - } switch (addr) { case VIA_REG_B: val = s->b; @@ -238,8 +225,11 @@ uint64_t mos6522_read(void *opaque, hwaddr addr, unsigned size) break; case VIA_REG_T1CL: val = get_counter(s, &s->timers[0], now) & 0xff; - s->ifr &= ~T1_INT; - mos6522_update_irq(s); + if (s->timers[0].state >= irq) { + s->timers[0].state = irq_cleared; + s->ifr &= ~T1_INT; + mos6522_update_irq(s); + } break; case VIA_REG_T1CH: val = get_counter(s, &s->timers[0], now) >> 8; @@ -252,8 +242,11 @@ uint64_t mos6522_read(void *opaque, hwaddr addr, unsigned size) break; case VIA_REG_T2CL: val = get_counter(s, &s->timers[1], now) & 0xff; - s->ifr &= ~T2_INT; - mos6522_update_irq(s); + if (s->timers[1].state >= irq) { + s->timers[1].state = irq_cleared; + s->ifr &= ~T2_INT; + mos6522_update_irq(s); + } break; case VIA_REG_T2CH: val = get_counter(s, &s->timers[1], now) >> 8; @@ -293,7 +286,7 @@ void mos6522_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) { MOS6522State *s = opaque; MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(s); - int64_t now; + int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); trace_mos6522_write(addr, val); @@ -316,6 +309,7 @@ void mos6522_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) s->dira = val; break; case VIA_REG_T1CL: + get_counter(s, &s->timers[0], now); s->timers[0].latch = (s->timers[0].latch & 0xff00) | val; break; case VIA_REG_T1CH: @@ -324,12 +318,15 @@ void mos6522_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) set_counter(s, &s->timers[0], s->timers[0].latch); break; case VIA_REG_T1LL: + get_counter(s, &s->timers[0], now); s->timers[0].latch = (s->timers[0].latch & 0xff00) | val; break; case VIA_REG_T1LH: + get_counter(s, &s->timers[0], now); s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8); break; case VIA_REG_T2CL: + get_counter(s, &s->timers[1], now); s->timers[1].latch = (s->timers[1].latch & 0xff00) | val; break; case VIA_REG_T2CH: @@ -342,7 +339,6 @@ void mos6522_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) break; case VIA_REG_ACR: s->acr = val; - now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); mos6522_timer1_update(s, &s->timers[0], now); mos6522_timer2_update(s, &s->timers[1], now); break; @@ -350,7 +346,18 @@ void mos6522_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) s->pcr = val; break; case VIA_REG_IFR: - /* reset bits */ + if (val & T1_INT) { + get_counter(s, &s->timers[0], now); + if ((s->ifr & T1_INT) && s->timers[0].state == irq) { + s->timers[0].state = irq_cleared; + } + } + if (val & T2_INT) { + get_counter(s, &s->timers[1], now); + if ((s->ifr & T2_INT) && s->timers[1].state == irq) { + s->timers[1].state = irq_cleared; + } + } s->ifr &= ~val; mos6522_update_irq(s); break; @@ -364,7 +371,6 @@ void mos6522_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) } mos6522_update_irq(s); /* if IER is modified starts needed timers */ - now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); mos6522_timer1_update(s, &s->timers[0], now); mos6522_timer2_update(s, &s->timers[1], now); break; diff --git a/hw/misc/trace-events b/hw/misc/trace-events index d0a89eb059..6c1bb02150 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -103,7 +103,7 @@ imx7_gpr_write(uint64_t offset, uint64_t value) "addr 0x%08" PRIx64 "value 0x%08 # mos6522.c mos6522_set_counter(int index, unsigned int val) "T%d.counter=%d" -mos6522_get_next_irq_time(uint16_t latch, int64_t d, int64_t delta) "latch=%d counter=0x%"PRId64 " delta_next=0x%"PRId64 +mos6522_get_next_irq_time(uint16_t latch, int64_t load_time, int64_t next_time) "latch=%d counter=%" PRId64 " next_time=%" PRId64 mos6522_set_sr_int(void) "set sr_int" mos6522_write(uint64_t addr, uint64_t val) "reg=0x%"PRIx64 " val=0x%"PRIx64 mos6522_read(uint64_t addr, unsigned val) "reg=0x%"PRIx64 " val=0x%x" diff --git a/include/hw/misc/mos6522.h b/include/hw/misc/mos6522.h index 94b1dc324c..4dbba6b273 100644 --- a/include/hw/misc/mos6522.h +++ b/include/hw/misc/mos6522.h @@ -73,6 +73,12 @@ #define VIA_REG_IER 0x0e #define VIA_REG_ANH 0x0f +enum timer_state { + decrement, + irq, + irq_cleared, +}; + /** * MOS6522Timer: * @counter_value: counter value at load time @@ -85,7 +91,7 @@ typedef struct MOS6522Timer { int64_t next_irq_time; uint64_t frequency; QEMUTimer *timer; - bool oneshot_fired; + enum timer_state state; } MOS6522Timer; /**