From patchwork Tue Aug 24 10:40:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Tanure X-Patchwork-Id: 12454613 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0B931C4338F for ; Tue, 24 Aug 2021 10:41:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E0A1361262 for ; Tue, 24 Aug 2021 10:41:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236287AbhHXKlp (ORCPT ); Tue, 24 Aug 2021 06:41:45 -0400 Received: from mx0a-001ae601.pphosted.com ([67.231.149.25]:13026 "EHLO mx0b-001ae601.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S236339AbhHXKlp (ORCPT ); Tue, 24 Aug 2021 06:41:45 -0400 Received: from pps.filterd (m0077473.ppops.net [127.0.0.1]) by mx0a-001ae601.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 17O9TXwm032200; Tue, 24 Aug 2021 05:40:57 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cirrus.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=PODMain02222019; bh=Urxhl4Qb0IuVZhyqVJZPru/u7ztljcpWWn3GCaoqzrA=; b=fCOn+upUJU9gVw2WB92CuVqbvmpUMO3HsTKsQ15NG2z9Jjnu51hPYffsS+Rf6kYhKydA k0HSvZeUrT7UZKLbQZulHI877wnT5cFhS1PextT6i/rRNBU8a+sQ6aXMPXTGjTQpu7FI bxIVXxBlzCxbgpzqtcQfbMRcvDRtW/XtAFkGBh9FxVUhQ5UYx8N6eNxvZH/m1oHA1VR3 X3ZkWHNXEqDmG4Klh/eaNU8h4EBJiidAuvnF5OI2qr3C6xYmUfLDjapC87w7IS47D7MO yy35D+Kka3psjKeWXFam+NeLUgDJi82unm7i0zvNC67SH/kl3VW+XrLjrricc7VA1atj Qw== Received: from ediex02.ad.cirrus.com ([87.246.76.36]) by mx0a-001ae601.pphosted.com with ESMTP id 3amjmq8wmc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT); Tue, 24 Aug 2021 05:40:57 -0500 Received: from EDIEX01.ad.cirrus.com (198.61.84.80) by EDIEX02.ad.cirrus.com (198.61.84.81) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2242.12; Tue, 24 Aug 2021 11:40:55 +0100 Received: from ediswmail.ad.cirrus.com (198.61.86.93) by EDIEX01.ad.cirrus.com (198.61.84.80) with Microsoft SMTP Server id 15.1.2242.12 via Frontend Transport; Tue, 24 Aug 2021 11:40:55 +0100 Received: from aryzen.ad.cirrus.com (unknown [198.61.65.58]) by ediswmail.ad.cirrus.com (Postfix) with ESMTP id 23E072BA; Tue, 24 Aug 2021 10:40:49 +0000 (UTC) From: Lucas Tanure To: Mark Brown , Greg Kroah-Hartman , "Rafael J . Wysocki" , Sanjay R Mehta , Nehal Bakulchandra Shah CC: , , , Lucas Tanure Subject: [PATCH 1/9] regmap: spi: Set regmap max raw r/w from max_transfer_size Date: Tue, 24 Aug 2021 11:40:33 +0100 Message-ID: <20210824104041.708945-2-tanureal@opensource.cirrus.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210824104041.708945-1-tanureal@opensource.cirrus.com> References: <20210824104041.708945-1-tanureal@opensource.cirrus.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: oMLmr4mPeWacfxMOAEzYu65nb8i0--Dd X-Proofpoint-GUID: oMLmr4mPeWacfxMOAEzYu65nb8i0--Dd X-Proofpoint-Spam-Reason: safe Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Set regmap raw read/write from spi max_transfer_size so regmap_raw_read/write can split the access into chunks Signed-off-by: Lucas Tanure --- drivers/base/regmap/regmap-spi.c | 34 ++++++++++++++++++++++++++++---- 1 file changed, 30 insertions(+), 4 deletions(-) diff --git a/drivers/base/regmap/regmap-spi.c b/drivers/base/regmap/regmap-spi.c index c1894e93c378..603a4c1c2066 100644 --- a/drivers/base/regmap/regmap-spi.c +++ b/drivers/base/regmap/regmap-spi.c @@ -109,13 +109,35 @@ static const struct regmap_bus regmap_spi = { .val_format_endian_default = REGMAP_ENDIAN_BIG, }; +static const struct regmap_bus *regmap_get_spi_bus(struct spi_device *spi, + const struct regmap_config *config) +{ + struct spi_master *master = spi->master; + struct regmap_bus *bus = NULL; + + if (master->max_transfer_size) { + bus = kmemdup(®map_spi, sizeof(*bus), GFP_KERNEL); + if (!bus) + return ERR_PTR(-ENOMEM); + bus->free_on_exit = true; + bus->max_raw_read = bus->max_raw_write = master->max_transfer_size(spi); + return bus; + } + + return ®map_spi; +} + struct regmap *__regmap_init_spi(struct spi_device *spi, const struct regmap_config *config, struct lock_class_key *lock_key, const char *lock_name) { - return __regmap_init(&spi->dev, ®map_spi, &spi->dev, config, - lock_key, lock_name); + const struct regmap_bus *bus = regmap_get_spi_bus(spi, config); + + if (IS_ERR(bus)) + return ERR_CAST(bus); + + return __regmap_init(&spi->dev, bus, &spi->dev, config, lock_key, lock_name); } EXPORT_SYMBOL_GPL(__regmap_init_spi); @@ -124,8 +146,12 @@ struct regmap *__devm_regmap_init_spi(struct spi_device *spi, struct lock_class_key *lock_key, const char *lock_name) { - return __devm_regmap_init(&spi->dev, ®map_spi, &spi->dev, config, - lock_key, lock_name); + const struct regmap_bus *bus = regmap_get_spi_bus(spi, config); + + if (IS_ERR(bus)) + return ERR_CAST(bus); + + return __devm_regmap_init(&spi->dev, bus, &spi->dev, config, lock_key, lock_name); } EXPORT_SYMBOL_GPL(__devm_regmap_init_spi); From patchwork Tue Aug 24 10:40:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Tanure X-Patchwork-Id: 12454615 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 01CCAC432BE for ; Tue, 24 Aug 2021 10:41:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E318F60F11 for ; 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Tue, 24 Aug 2021 05:41:00 -0500 Received: from EDIEX01.ad.cirrus.com (198.61.84.80) by EDIEX02.ad.cirrus.com (198.61.84.81) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2242.12; Tue, 24 Aug 2021 11:40:59 +0100 Received: from ediswmail.ad.cirrus.com (198.61.86.93) by EDIEX01.ad.cirrus.com (198.61.84.80) with Microsoft SMTP Server id 15.1.2242.12 via Frontend Transport; Tue, 24 Aug 2021 11:40:59 +0100 Received: from aryzen.ad.cirrus.com (unknown [198.61.65.58]) by ediswmail.ad.cirrus.com (Postfix) with ESMTP id 688622A9; Tue, 24 Aug 2021 10:40:55 +0000 (UTC) From: Lucas Tanure To: Mark Brown , Greg Kroah-Hartman , "Rafael J . Wysocki" , Sanjay R Mehta , Nehal Bakulchandra Shah CC: , , , Lucas Tanure Subject: [PATCH 2/9] spi: core: Add flag for controllers that can't hold cs between transfers Date: Tue, 24 Aug 2021 11:40:34 +0100 Message-ID: <20210824104041.708945-3-tanureal@opensource.cirrus.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210824104041.708945-1-tanureal@opensource.cirrus.com> References: <20210824104041.708945-1-tanureal@opensource.cirrus.com> MIME-Version: 1.0 X-Proofpoint-GUID: mSnUtxGavguZ3TD4NprwGcOxygIMaVnV X-Proofpoint-ORIG-GUID: mSnUtxGavguZ3TD4NprwGcOxygIMaVnV X-Proofpoint-Spam-Reason: safe Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Create a flag for a controller that has an automatic cs selection and can't hold cs activated between transfers Some messages send address and data split between two transfers, see regmap-spi, and without the cs held the data loses it`s meaning Signed-off-by: Lucas Tanure --- include/linux/spi/spi.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h index 8371bca13729..f5b55c237634 100644 --- a/include/linux/spi/spi.h +++ b/include/linux/spi/spi.h @@ -514,6 +514,7 @@ struct spi_controller { #define SPI_CONTROLLER_MUST_TX BIT(4) /* requires tx */ #define SPI_MASTER_GPIO_SS BIT(5) /* GPIO CS must select slave */ +#define SPI_CONTROLLER_CS_PER_TRANSFER BIT(6) /* SPI controller can not hold CS between transfers */ /* flag indicating if the allocation of this struct is devres-managed */ bool devm_allocated; From patchwork Tue Aug 24 10:40:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Tanure X-Patchwork-Id: 12454619 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AC6BCC4320A for ; Tue, 24 Aug 2021 10:41:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 959E861262 for ; Tue, 24 Aug 2021 10:41:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236373AbhHXKlu (ORCPT ); Tue, 24 Aug 2021 06:41:50 -0400 Received: from mx0a-001ae601.pphosted.com ([67.231.149.25]:36010 "EHLO mx0b-001ae601.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S236379AbhHXKls (ORCPT ); Tue, 24 Aug 2021 06:41:48 -0400 Received: from pps.filterd (m0077473.ppops.net [127.0.0.1]) by mx0a-001ae601.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 17OA050R016652; Tue, 24 Aug 2021 05:41:01 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cirrus.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=PODMain02222019; bh=wmJd13U/MiNXR0MpF3vqHT3p3GrmbatpUhQguV8vWF8=; b=ovOIWCkxW7yRmTHDYJc5kamF/EeyASI8hn+fQrRPmDZDP1y/X25XsTOpCHLaLqX+bVaA ixOO6cb+Fj9Ii5YxeEzEUxmWhGaolfFytfO8HCaia0S83GSxuOJWtOpDJ4BauV4P+3U9 Q8yz7UfC/H/JMs0uwMIMX8Kog/wmuP5TwxYxKMowiEggh4vjNJccg4KnCE8vGKVhbpE/ We51CI3UGaH2iZ5z/IfbbCFICRM9/bqSefbMdyd+/awvmR/LxEwNcbdG09+disygX4B7 yomFbZtTWchXG09FqEKeYuOF4UXytCyTNHRbpVhtqcvZxD663UeTG5wIOasnCF7ZvWJJ dQ== Received: from ediex01.ad.cirrus.com ([87.246.76.36]) by mx0a-001ae601.pphosted.com with ESMTP id 3amjmq8wmh-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT); Tue, 24 Aug 2021 05:41:01 -0500 Received: from EDIEX01.ad.cirrus.com (198.61.84.80) by EDIEX01.ad.cirrus.com (198.61.84.80) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2242.12; Tue, 24 Aug 2021 11:40:59 +0100 Received: from ediswmail.ad.cirrus.com (198.61.86.93) by EDIEX01.ad.cirrus.com (198.61.84.80) with Microsoft SMTP Server id 15.1.2242.12 via Frontend Transport; Tue, 24 Aug 2021 11:40:59 +0100 Received: from aryzen.ad.cirrus.com (unknown [198.61.65.58]) by ediswmail.ad.cirrus.com (Postfix) with ESMTP id 431BC2BA; Tue, 24 Aug 2021 10:40:59 +0000 (UTC) From: Lucas Tanure To: Mark Brown , Greg Kroah-Hartman , "Rafael J . Wysocki" , Sanjay R Mehta , Nehal Bakulchandra Shah CC: , , , Lucas Tanure Subject: [PATCH 3/9] regmap: spi: SPI_CONTROLLER_CS_PER_TRANSFER affects max read/write Date: Tue, 24 Aug 2021 11:40:35 +0100 Message-ID: <20210824104041.708945-4-tanureal@opensource.cirrus.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210824104041.708945-1-tanureal@opensource.cirrus.com> References: <20210824104041.708945-1-tanureal@opensource.cirrus.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: pxnmr8H-9zsF7uLpZWYAKrXmKDKXbhu7 X-Proofpoint-GUID: pxnmr8H-9zsF7uLpZWYAKrXmKDKXbhu7 X-Proofpoint-Spam-Reason: safe Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org regmap-spi will split data and address between two transfers in the same message so use addr_affects_max_raw_rw to flag that the number bytes to read or write should be a little less (address + padding size), so that the SPI controller can merge the entire message into a single CS period Signed-off-by: Lucas Tanure --- drivers/base/regmap/regmap-spi.c | 14 ++++++++++++-- drivers/base/regmap/regmap.c | 9 +++++++++ include/linux/regmap.h | 2 ++ 3 files changed, 23 insertions(+), 2 deletions(-) diff --git a/drivers/base/regmap/regmap-spi.c b/drivers/base/regmap/regmap-spi.c index 603a4c1c2066..0c1f2e51c0c7 100644 --- a/drivers/base/regmap/regmap-spi.c +++ b/drivers/base/regmap/regmap-spi.c @@ -115,12 +115,22 @@ static const struct regmap_bus *regmap_get_spi_bus(struct spi_device *spi, struct spi_master *master = spi->master; struct regmap_bus *bus = NULL; - if (master->max_transfer_size) { + if (master->max_transfer_size || (master->flags & SPI_CONTROLLER_CS_PER_TRANSFER)) { bus = kmemdup(®map_spi, sizeof(*bus), GFP_KERNEL); if (!bus) return ERR_PTR(-ENOMEM); bus->free_on_exit = true; - bus->max_raw_read = bus->max_raw_write = master->max_transfer_size(spi); + + /* regmap-spi will split data and address between two transfers in the same message + * so use addr_affects_max_raw_rw to flag that the number bytes to read or write + * should be a little less (address + padding size), so the controller can + * fit both transfers in a single CS period + */ + bus->addr_affects_max_raw_rw = master->flags & SPI_CONTROLLER_CS_PER_TRANSFER; + + if (master->max_transfer_size) + bus->max_raw_read = bus->max_raw_write = master->max_transfer_size(spi); + return bus; } diff --git a/drivers/base/regmap/regmap.c b/drivers/base/regmap/regmap.c index 6ad41d0720ba..31d0949b6c2f 100644 --- a/drivers/base/regmap/regmap.c +++ b/drivers/base/regmap/regmap.c @@ -815,6 +815,15 @@ struct regmap *__regmap_init(struct device *dev, if (bus) { map->max_raw_read = bus->max_raw_read; map->max_raw_write = bus->max_raw_write; + if (bus->addr_affects_max_raw_rw) { + if (map->max_raw_read < map->format.buf_size || + map->max_raw_write < map->format.buf_size) { + ret = -EINVAL; + goto err_name; + } + map->max_raw_read -= (map->format.reg_bytes + map->format.pad_bytes); + map->max_raw_write -= (map->format.reg_bytes + map->format.pad_bytes); + } } map->dev = dev; map->bus = bus; diff --git a/include/linux/regmap.h b/include/linux/regmap.h index 77755196277c..a90d1e270b1f 100644 --- a/include/linux/regmap.h +++ b/include/linux/regmap.h @@ -504,6 +504,7 @@ typedef void (*regmap_hw_free_context)(void *context); * @max_raw_read: Max raw read size that can be used on the bus. * @max_raw_write: Max raw write size that can be used on the bus. * @free_on_exit: kfree this on exit of regmap + * @addr_affects_max_raw_rw: max_raw_[read|write] must include the address and padding preamble */ struct regmap_bus { bool fast_io; @@ -522,6 +523,7 @@ struct regmap_bus { size_t max_raw_read; size_t max_raw_write; bool free_on_exit; + bool addr_affects_max_raw_rw; }; /* From patchwork Tue Aug 24 10:40:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Tanure X-Patchwork-Id: 12454625 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.9 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A83BCC4338F for ; Tue, 24 Aug 2021 10:41:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 93DCD60F11 for ; Tue, 24 Aug 2021 10:41:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236435AbhHXKlw (ORCPT ); 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Tue, 24 Aug 2021 05:41:02 -0500 Received: from EDIEX01.ad.cirrus.com (198.61.84.80) by EDIEX01.ad.cirrus.com (198.61.84.80) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2242.12; Tue, 24 Aug 2021 11:40:59 +0100 Received: from ediswmail.ad.cirrus.com (198.61.86.93) by EDIEX01.ad.cirrus.com (198.61.84.80) with Microsoft SMTP Server id 15.1.2242.12 via Frontend Transport; Tue, 24 Aug 2021 11:40:59 +0100 Received: from aryzen.ad.cirrus.com (unknown [198.61.65.58]) by ediswmail.ad.cirrus.com (Postfix) with ESMTP id 8B5D546E; Tue, 24 Aug 2021 10:40:59 +0000 (UTC) From: Lucas Tanure To: Mark Brown , Greg Kroah-Hartman , "Rafael J . Wysocki" , Sanjay R Mehta , Nehal Bakulchandra Shah CC: , , , Lucas Tanure Subject: [PATCH 4/9] spi: amd: Refactor code to use less spi_master_get_devdata Date: Tue, 24 Aug 2021 11:40:36 +0100 Message-ID: <20210824104041.708945-5-tanureal@opensource.cirrus.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210824104041.708945-1-tanureal@opensource.cirrus.com> References: <20210824104041.708945-1-tanureal@opensource.cirrus.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: rk44ACb3oTlokmSNf-7aVVPRej19ybEN X-Proofpoint-GUID: rk44ACb3oTlokmSNf-7aVVPRej19ybEN X-Proofpoint-Spam-Reason: safe Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Get master data in the start and then just use struct amd_spi as it has the needed variable Signed-off-by: Lucas Tanure --- drivers/spi/spi-amd.c | 94 ++++++++++++++++--------------------------- 1 file changed, 34 insertions(+), 60 deletions(-) diff --git a/drivers/spi/spi-amd.c b/drivers/spi/spi-amd.c index 3cf76096a76d..f23467cf6acd 100644 --- a/drivers/spi/spi-amd.c +++ b/drivers/spi/spi-amd.c @@ -41,85 +41,66 @@ struct amd_spi { u8 chip_select; }; -static inline u8 amd_spi_readreg8(struct spi_master *master, int idx) +static inline u8 amd_spi_readreg8(struct amd_spi *amd_spi, int idx) { - struct amd_spi *amd_spi = spi_master_get_devdata(master); - return ioread8((u8 __iomem *)amd_spi->io_remap_addr + idx); } -static inline void amd_spi_writereg8(struct spi_master *master, int idx, - u8 val) +static inline void amd_spi_writereg8(struct amd_spi *amd_spi, int idx, u8 val) { - struct amd_spi *amd_spi = spi_master_get_devdata(master); - iowrite8(val, ((u8 __iomem *)amd_spi->io_remap_addr + idx)); } -static inline void amd_spi_setclear_reg8(struct spi_master *master, int idx, - u8 set, u8 clear) +static void amd_spi_setclear_reg8(struct amd_spi *amd_spi, int idx, u8 set, u8 clear) { - u8 tmp = amd_spi_readreg8(master, idx); + u8 tmp = amd_spi_readreg8(amd_spi, idx); tmp = (tmp & ~clear) | set; - amd_spi_writereg8(master, idx, tmp); + amd_spi_writereg8(amd_spi, idx, tmp); } -static inline u32 amd_spi_readreg32(struct spi_master *master, int idx) +static inline u32 amd_spi_readreg32(struct amd_spi *amd_spi, int idx) { - struct amd_spi *amd_spi = spi_master_get_devdata(master); - return ioread32((u8 __iomem *)amd_spi->io_remap_addr + idx); } -static inline void amd_spi_writereg32(struct spi_master *master, int idx, - u32 val) +static inline void amd_spi_writereg32(struct amd_spi *amd_spi, int idx, u32 val) { - struct amd_spi *amd_spi = spi_master_get_devdata(master); - iowrite32(val, ((u8 __iomem *)amd_spi->io_remap_addr + idx)); } -static inline void amd_spi_setclear_reg32(struct spi_master *master, int idx, - u32 set, u32 clear) +static inline void amd_spi_setclear_reg32(struct amd_spi *amd_spi, int idx, u32 set, u32 clear) { - u32 tmp = amd_spi_readreg32(master, idx); + u32 tmp = amd_spi_readreg32(amd_spi, idx); tmp = (tmp & ~clear) | set; - amd_spi_writereg32(master, idx, tmp); + amd_spi_writereg32(amd_spi, idx, tmp); } -static void amd_spi_select_chip(struct spi_master *master) +static void amd_spi_select_chip(struct amd_spi *amd_spi) { - struct amd_spi *amd_spi = spi_master_get_devdata(master); - u8 chip_select = amd_spi->chip_select; - - amd_spi_setclear_reg8(master, AMD_SPI_ALT_CS_REG, chip_select, + amd_spi_setclear_reg8(amd_spi, AMD_SPI_ALT_CS_REG, amd_spi->chip_select, AMD_SPI_ALT_CS_MASK); } -static void amd_spi_clear_fifo_ptr(struct spi_master *master) +static void amd_spi_clear_fifo_ptr(struct amd_spi *amd_spi) { - amd_spi_setclear_reg32(master, AMD_SPI_CTRL0_REG, AMD_SPI_FIFO_CLEAR, - AMD_SPI_FIFO_CLEAR); + amd_spi_setclear_reg32(amd_spi, AMD_SPI_CTRL0_REG, AMD_SPI_FIFO_CLEAR, AMD_SPI_FIFO_CLEAR); } -static void amd_spi_set_opcode(struct spi_master *master, u8 cmd_opcode) +static void amd_spi_set_opcode(struct amd_spi *amd_spi, u8 cmd_opcode) { - amd_spi_setclear_reg32(master, AMD_SPI_CTRL0_REG, cmd_opcode, - AMD_SPI_OPCODE_MASK); + amd_spi_setclear_reg32(amd_spi, AMD_SPI_CTRL0_REG, cmd_opcode, AMD_SPI_OPCODE_MASK); } -static inline void amd_spi_set_rx_count(struct spi_master *master, - u8 rx_count) +static inline void amd_spi_set_rx_count(struct amd_spi *amd_spi, u8 rx_count) { - amd_spi_setclear_reg8(master, AMD_SPI_RX_COUNT_REG, rx_count, 0xff); + amd_spi_setclear_reg8(amd_spi, AMD_SPI_RX_COUNT_REG, rx_count, 0xff); } -static inline void amd_spi_set_tx_count(struct spi_master *master, - u8 tx_count) +static inline void amd_spi_set_tx_count(struct amd_spi *amd_spi, u8 tx_count) { - amd_spi_setclear_reg8(master, AMD_SPI_TX_COUNT_REG, tx_count, 0xff); + amd_spi_setclear_reg8(amd_spi, AMD_SPI_TX_COUNT_REG, tx_count, 0xff); } static inline int amd_spi_busy_wait(struct amd_spi *amd_spi) @@ -142,22 +123,18 @@ static inline int amd_spi_busy_wait(struct amd_spi *amd_spi) return 0; } -static void amd_spi_execute_opcode(struct spi_master *master) +static void amd_spi_execute_opcode(struct amd_spi *amd_spi) { - struct amd_spi *amd_spi = spi_master_get_devdata(master); - /* Set ExecuteOpCode bit in the CTRL0 register */ - amd_spi_setclear_reg32(master, AMD_SPI_CTRL0_REG, AMD_SPI_EXEC_CMD, - AMD_SPI_EXEC_CMD); - + amd_spi_setclear_reg32(amd_spi, AMD_SPI_CTRL0_REG, AMD_SPI_EXEC_CMD, AMD_SPI_EXEC_CMD); amd_spi_busy_wait(amd_spi); } static int amd_spi_master_setup(struct spi_device *spi) { - struct spi_master *master = spi->master; + struct amd_spi *amd_spi = spi_master_get_devdata(spi->master); - amd_spi_clear_fifo_ptr(master); + amd_spi_clear_fifo_ptr(amd_spi); return 0; } @@ -185,19 +162,18 @@ static inline int amd_spi_fifo_xfer(struct amd_spi *amd_spi, tx_len = xfer->len - 1; cmd_opcode = *(u8 *)xfer->tx_buf; buf++; - amd_spi_set_opcode(master, cmd_opcode); + amd_spi_set_opcode(amd_spi, cmd_opcode); /* Write data into the FIFO. */ for (i = 0; i < tx_len; i++) { - iowrite8(buf[i], - ((u8 __iomem *)amd_spi->io_remap_addr + + iowrite8(buf[i], ((u8 __iomem *)amd_spi->io_remap_addr + AMD_SPI_FIFO_BASE + i)); } - amd_spi_set_tx_count(master, tx_len); - amd_spi_clear_fifo_ptr(master); + amd_spi_set_tx_count(amd_spi, tx_len); + amd_spi_clear_fifo_ptr(amd_spi); /* Execute command */ - amd_spi_execute_opcode(master); + amd_spi_execute_opcode(amd_spi); } if (m_cmd & AMD_SPI_XFER_RX) { /* @@ -206,15 +182,13 @@ static inline int amd_spi_fifo_xfer(struct amd_spi *amd_spi, */ rx_len = xfer->len; buf = (u8 *)xfer->rx_buf; - amd_spi_set_rx_count(master, rx_len); - amd_spi_clear_fifo_ptr(master); + amd_spi_set_rx_count(amd_spi, rx_len); + amd_spi_clear_fifo_ptr(amd_spi); /* Execute command */ - amd_spi_execute_opcode(master); + amd_spi_execute_opcode(amd_spi); /* Read data from FIFO to receive buffer */ for (i = 0; i < rx_len; i++) - buf[i] = amd_spi_readreg8(master, - AMD_SPI_FIFO_BASE + - tx_len + i); + buf[i] = amd_spi_readreg8(amd_spi, AMD_SPI_FIFO_BASE + tx_len + i); } } @@ -234,7 +208,7 @@ static int amd_spi_master_transfer(struct spi_master *master, struct spi_device *spi = msg->spi; amd_spi->chip_select = spi->chip_select; - amd_spi_select_chip(master); + amd_spi_select_chip(amd_spi); /* * Extract spi_transfers from the spi message and From patchwork Tue Aug 24 10:40:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Tanure X-Patchwork-Id: 12454617 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 05B7AC432BE for ; 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Tue, 24 Aug 2021 05:41:01 -0500 Received: from EDIEX01.ad.cirrus.com (198.61.84.80) by EDIEX02.ad.cirrus.com (198.61.84.81) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2242.12; Tue, 24 Aug 2021 11:41:00 +0100 Received: from ediswmail.ad.cirrus.com (198.61.86.93) by EDIEX01.ad.cirrus.com (198.61.84.80) with Microsoft SMTP Server id 15.1.2242.12 via Frontend Transport; Tue, 24 Aug 2021 11:41:00 +0100 Received: from aryzen.ad.cirrus.com (unknown [198.61.65.58]) by ediswmail.ad.cirrus.com (Postfix) with ESMTP id CDE722BA; Tue, 24 Aug 2021 10:40:59 +0000 (UTC) From: Lucas Tanure To: Mark Brown , Greg Kroah-Hartman , "Rafael J . Wysocki" , Sanjay R Mehta , Nehal Bakulchandra Shah CC: , , , Lucas Tanure Subject: [PATCH 5/9] spi: amd: Refactor amd_spi_busy_wait to use readl_poll_timeout Date: Tue, 24 Aug 2021 11:40:37 +0100 Message-ID: <20210824104041.708945-6-tanureal@opensource.cirrus.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210824104041.708945-1-tanureal@opensource.cirrus.com> References: <20210824104041.708945-1-tanureal@opensource.cirrus.com> MIME-Version: 1.0 X-Proofpoint-GUID: CRKyq3WinKHnFX2jdtYc09eFCfd5ZpSp X-Proofpoint-ORIG-GUID: CRKyq3WinKHnFX2jdtYc09eFCfd5ZpSp X-Proofpoint-Spam-Reason: safe Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org This function can be replaced by readl_poll_timeout Signed-off-by: Lucas Tanure --- drivers/spi/spi-amd.c | 21 +++++---------------- 1 file changed, 5 insertions(+), 16 deletions(-) diff --git a/drivers/spi/spi-amd.c b/drivers/spi/spi-amd.c index f23467cf6acd..9476b283840b 100644 --- a/drivers/spi/spi-amd.c +++ b/drivers/spi/spi-amd.c @@ -12,6 +12,7 @@ #include #include #include +#include #define AMD_SPI_CTRL0_REG 0x00 #define AMD_SPI_EXEC_CMD BIT(16) @@ -103,24 +104,12 @@ static inline void amd_spi_set_tx_count(struct amd_spi *amd_spi, u8 tx_count) amd_spi_setclear_reg8(amd_spi, AMD_SPI_TX_COUNT_REG, tx_count, 0xff); } -static inline int amd_spi_busy_wait(struct amd_spi *amd_spi) +static int amd_spi_busy_wait(struct amd_spi *amd_spi) { - bool spi_busy; - int timeout = 100000; - - /* poll for SPI bus to become idle */ - spi_busy = (ioread32((u8 __iomem *)amd_spi->io_remap_addr + - AMD_SPI_CTRL0_REG) & AMD_SPI_BUSY) == AMD_SPI_BUSY; - while (spi_busy) { - usleep_range(10, 20); - if (timeout-- < 0) - return -ETIMEDOUT; - - spi_busy = (ioread32((u8 __iomem *)amd_spi->io_remap_addr + - AMD_SPI_CTRL0_REG) & AMD_SPI_BUSY) == AMD_SPI_BUSY; - } + u32 val; - return 0; + return readl_poll_timeout(amd_spi->io_remap_addr + AMD_SPI_CTRL0_REG, val, + !(val & AMD_SPI_BUSY), 10, 100000); } static void amd_spi_execute_opcode(struct amd_spi *amd_spi) From patchwork Tue Aug 24 10:40:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Tanure X-Patchwork-Id: 12454623 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.9 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4027CC4320E for ; Tue, 24 Aug 2021 10:41:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 21ADF61262 for ; Tue, 24 Aug 2021 10:41:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236359AbhHXKlv (ORCPT ); Tue, 24 Aug 2021 06:41:51 -0400 Received: from mx0b-001ae601.pphosted.com ([67.231.152.168]:59432 "EHLO mx0b-001ae601.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236388AbhHXKlt (ORCPT ); Tue, 24 Aug 2021 06:41:49 -0400 Received: from pps.filterd (m0077474.ppops.net [127.0.0.1]) by mx0b-001ae601.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 17O9oMhU012561; Tue, 24 Aug 2021 05:41:02 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cirrus.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=PODMain02222019; bh=Y1dzi87RQSLOVgc1XSY6AIdI/7WVI0LjnVnxGx7qTbo=; b=d9MB0pdnOlz72yZbtV5+qLWlb1Cdu51SBr5bTq6VSTQUxcVI92l9cSUbWYSCYuaKguaP WjOTLHk87twmjlKIfd4E+X5VgTbrKiCYMUXCnvqBKDAT3wlZNcMhct9245Zi6xNhh827 xuBCPRkyd2DeQFR/bd2xSVo926UtLjyxADo9EAYejT/d5T/lIVtEdjHyk1kc17CkSsMA RvTYUjYvvkgDc/qMBg+Ya9RmB85mmtTEfPkaRlE2qSxMqIayH8U/njchntu4ie8o2DYf tPyzbhO+a3Dwu1+9B0MGc5GajR0sEiL/pHW7bxp8BnE3gD3eqMhnvjIEqxzyoekulk3q ig== Received: from ediex02.ad.cirrus.com ([87.246.76.36]) by mx0b-001ae601.pphosted.com with ESMTP id 3amxg601k1-3 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT); Tue, 24 Aug 2021 05:41:01 -0500 Received: from EDIEX01.ad.cirrus.com (198.61.84.80) by EDIEX02.ad.cirrus.com (198.61.84.81) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2242.12; Tue, 24 Aug 2021 11:41:00 +0100 Received: from ediswmail.ad.cirrus.com (198.61.86.93) by EDIEX01.ad.cirrus.com (198.61.84.80) with Microsoft SMTP Server id 15.1.2242.12 via Frontend Transport; Tue, 24 Aug 2021 11:41:00 +0100 Received: from aryzen.ad.cirrus.com (unknown [198.61.65.58]) by ediswmail.ad.cirrus.com (Postfix) with ESMTP id 1AC082A9; Tue, 24 Aug 2021 10:41:00 +0000 (UTC) From: Lucas Tanure To: Mark Brown , Greg Kroah-Hartman , "Rafael J . Wysocki" , Sanjay R Mehta , Nehal Bakulchandra Shah CC: , , , Lucas Tanure Subject: [PATCH 6/9] spi: amd: Remove uneeded variable Date: Tue, 24 Aug 2021 11:40:38 +0100 Message-ID: <20210824104041.708945-7-tanureal@opensource.cirrus.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210824104041.708945-1-tanureal@opensource.cirrus.com> References: <20210824104041.708945-1-tanureal@opensource.cirrus.com> MIME-Version: 1.0 X-Proofpoint-GUID: MrbsGSsAFNFFq7jPDiZPQknEJAAaDpae X-Proofpoint-ORIG-GUID: MrbsGSsAFNFFq7jPDiZPQknEJAAaDpae X-Proofpoint-Spam-Reason: safe Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Remove internal cs from amd_spi Signed-off-by: Lucas Tanure --- drivers/spi/spi-amd.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/drivers/spi/spi-amd.c b/drivers/spi/spi-amd.c index 9476b283840b..ebbc64a9fa7b 100644 --- a/drivers/spi/spi-amd.c +++ b/drivers/spi/spi-amd.c @@ -39,7 +39,6 @@ struct amd_spi { void __iomem *io_remap_addr; unsigned long io_base_addr; u32 rom_addr; - u8 chip_select; }; static inline u8 amd_spi_readreg8(struct amd_spi *amd_spi, int idx) @@ -78,10 +77,9 @@ static inline void amd_spi_setclear_reg32(struct amd_spi *amd_spi, int idx, u32 amd_spi_writereg32(amd_spi, idx, tmp); } -static void amd_spi_select_chip(struct amd_spi *amd_spi) +static void amd_spi_select_chip(struct amd_spi *amd_spi, u8 cs) { - amd_spi_setclear_reg8(amd_spi, AMD_SPI_ALT_CS_REG, amd_spi->chip_select, - AMD_SPI_ALT_CS_MASK); + amd_spi_setclear_reg8(amd_spi, AMD_SPI_ALT_CS_REG, cs, AMD_SPI_ALT_CS_MASK); } static void amd_spi_clear_fifo_ptr(struct amd_spi *amd_spi) @@ -196,8 +194,7 @@ static int amd_spi_master_transfer(struct spi_master *master, struct amd_spi *amd_spi = spi_master_get_devdata(master); struct spi_device *spi = msg->spi; - amd_spi->chip_select = spi->chip_select; - amd_spi_select_chip(amd_spi); + amd_spi_select_chip(amd_spi, spi->chip_select); /* * Extract spi_transfers from the spi message and From patchwork Tue Aug 24 10:40:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Tanure X-Patchwork-Id: 12454621 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF5F1C4338F for ; Tue, 24 Aug 2021 10:41:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BD50F61262 for ; Tue, 24 Aug 2021 10:41:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236413AbhHXKlv (ORCPT ); Tue, 24 Aug 2021 06:41:51 -0400 Received: from mx0b-001ae601.pphosted.com ([67.231.152.168]:54182 "EHLO mx0b-001ae601.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236383AbhHXKlt (ORCPT ); Tue, 24 Aug 2021 06:41:49 -0400 Received: from pps.filterd (m0077474.ppops.net [127.0.0.1]) by mx0b-001ae601.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 17O9oMhV012561; Tue, 24 Aug 2021 05:41:02 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cirrus.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=PODMain02222019; bh=xsX6p9puSfXRorYbQx0X/dwTanfMPZQ43pueV+mZkqs=; b=FQzs8GNjLTzhMll0Ty+JbUZY35uvmNDXQkwgge/EXzrsvhCNygsd/6eYpPwRsrVWtyqI MNd7LJlUxSVwFORB4vyZ5/n+yUNSFJDm9iydGhsSyB4lRVPVHm6LJT7UwdFbVjtr9WDb OnF48WrvI9pkiWMjIGJpaPFcm/tJaLBXO/+2S+//CJ9KnEU2Y0qb8AgEV5wxisUaP/Oi Uw8KaMTfY7FMib1qaBdUGR0rcJugFZITnqufP2ZrBgiZOYII9U1o+0tndkNVOlkONtcG huTTDrKY+gB4+qSoTdL6RPe28xEefvCbGhgZY6JpEMxaUuSan9KaH4HMLHNTjzPvkwM2 Fg== Received: from ediex02.ad.cirrus.com ([87.246.76.36]) by mx0b-001ae601.pphosted.com with ESMTP id 3amxg601k1-4 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT); Tue, 24 Aug 2021 05:41:02 -0500 Received: from EDIEX01.ad.cirrus.com (198.61.84.80) by EDIEX02.ad.cirrus.com (198.61.84.81) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2242.12; Tue, 24 Aug 2021 11:41:00 +0100 Received: from ediswmail.ad.cirrus.com (198.61.86.93) by EDIEX01.ad.cirrus.com (198.61.84.80) with Microsoft SMTP Server id 15.1.2242.12 via Frontend Transport; Tue, 24 Aug 2021 11:41:00 +0100 Received: from aryzen.ad.cirrus.com (unknown [198.61.65.58]) by ediswmail.ad.cirrus.com (Postfix) with ESMTP id 5B1D846E; Tue, 24 Aug 2021 10:41:00 +0000 (UTC) From: Lucas Tanure To: Mark Brown , Greg Kroah-Hartman , "Rafael J . Wysocki" , Sanjay R Mehta , Nehal Bakulchandra Shah CC: , , , Lucas Tanure Subject: [PATCH 7/9] spi: amd: Check for idle bus before execute opcode Date: Tue, 24 Aug 2021 11:40:39 +0100 Message-ID: <20210824104041.708945-8-tanureal@opensource.cirrus.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210824104041.708945-1-tanureal@opensource.cirrus.com> References: <20210824104041.708945-1-tanureal@opensource.cirrus.com> MIME-Version: 1.0 X-Proofpoint-GUID: 2S-f3Ix36nQZ-BZ9nG-nXue5ZByLN4mp X-Proofpoint-ORIG-GUID: 2S-f3Ix36nQZ-BZ9nG-nXue5ZByLN4mp X-Proofpoint-Spam-Reason: safe Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Check if the bus is not in use before starting the transfer Also wait after so the READ bytes in the FIFO are ready to be copied Signed-off-by: Lucas Tanure --- drivers/spi/spi-amd.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-amd.c b/drivers/spi/spi-amd.c index ebbc64a9fa7b..75390fcb0481 100644 --- a/drivers/spi/spi-amd.c +++ b/drivers/spi/spi-amd.c @@ -110,11 +110,17 @@ static int amd_spi_busy_wait(struct amd_spi *amd_spi) !(val & AMD_SPI_BUSY), 10, 100000); } -static void amd_spi_execute_opcode(struct amd_spi *amd_spi) +static int amd_spi_execute_opcode(struct amd_spi *amd_spi) { + int ret = amd_spi_busy_wait(amd_spi); + + if (ret) + return ret; + /* Set ExecuteOpCode bit in the CTRL0 register */ amd_spi_setclear_reg32(amd_spi, AMD_SPI_CTRL0_REG, AMD_SPI_EXEC_CMD, AMD_SPI_EXEC_CMD); - amd_spi_busy_wait(amd_spi); + + return amd_spi_busy_wait(amd_spi); } static int amd_spi_master_setup(struct spi_device *spi) From patchwork Tue Aug 24 10:40:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Tanure X-Patchwork-Id: 12454627 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D105AC4320A for ; Tue, 24 Aug 2021 10:41:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B86BE61262 for ; Tue, 24 Aug 2021 10:41:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236455AbhHXKlx (ORCPT ); Tue, 24 Aug 2021 06:41:53 -0400 Received: from mx0a-001ae601.pphosted.com ([67.231.149.25]:23220 "EHLO mx0b-001ae601.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S236398AbhHXKlu (ORCPT ); Tue, 24 Aug 2021 06:41:50 -0400 Received: from pps.filterd (m0077473.ppops.net [127.0.0.1]) by mx0a-001ae601.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 17OA050T016652; Tue, 24 Aug 2021 05:41:03 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cirrus.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=PODMain02222019; bh=bXPtQd8HEeyWR8X7GQzCqp25D8O8/msbik0SSpewS80=; b=eGSahquyMF4truea7sizxDcPXaCHGOTalqZxVraZgk8XwkpB7Sa8NFw09KmxP6QHA8lr UKZEwjfDltbBLTQznW5UH6TWSvxmJNLSHluxnrfVNU8DhfCl9I0LZpF7ZqefyJqv5fXW BTnekxDkJ2RvJ8jd17qcvXyenWTLiAjgSHgByEeeOhfqsMIiuFNvg4QioTT5U0NvBADX Zs7uOzrMJdcd9NoqWzJaxvYhRfe5hATFca8qZvumX33QCidvhXMWlQvyHmhTm38rxKbc 0Cn/inLB7FVC5F3ObFrzSg9PwK05ycJ7+WgjbFNkQDsbSCSNQdSZEKcF1iM6wrQk3Umm cw== Received: from ediex01.ad.cirrus.com ([87.246.76.36]) by mx0a-001ae601.pphosted.com with ESMTP id 3amjmq8wmh-3 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT); Tue, 24 Aug 2021 05:41:03 -0500 Received: from EDIEX01.ad.cirrus.com (198.61.84.80) by EDIEX01.ad.cirrus.com (198.61.84.80) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2242.12; Tue, 24 Aug 2021 11:41:00 +0100 Received: from ediswmail.ad.cirrus.com (198.61.86.93) by EDIEX01.ad.cirrus.com (198.61.84.80) with Microsoft SMTP Server id 15.1.2242.12 via Frontend Transport; Tue, 24 Aug 2021 11:41:00 +0100 Received: from aryzen.ad.cirrus.com (unknown [198.61.65.58]) by ediswmail.ad.cirrus.com (Postfix) with ESMTP id A5E262A9; Tue, 24 Aug 2021 10:41:00 +0000 (UTC) From: Lucas Tanure To: Mark Brown , Greg Kroah-Hartman , "Rafael J . Wysocki" , Sanjay R Mehta , Nehal Bakulchandra Shah CC: , , , Lucas Tanure Subject: [PATCH 8/9] spi: amd: Refactor to overcome 70 bytes per CS limitation Date: Tue, 24 Aug 2021 11:40:40 +0100 Message-ID: <20210824104041.708945-9-tanureal@opensource.cirrus.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210824104041.708945-1-tanureal@opensource.cirrus.com> References: <20210824104041.708945-1-tanureal@opensource.cirrus.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: epGmpNXcnVKqNZ3X9hehhtdArML38hDr X-Proofpoint-GUID: epGmpNXcnVKqNZ3X9hehhtdArML38hDr X-Proofpoint-Spam-Reason: safe Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org AMD SPI controller has 70 bytes for its FIFO and it has an automatic way of controlling it`s internal CS, which can only be activated during the time that the FIFO is being transfered. SPI_MASTER_HALF_DUPLEX here means that it can only read RX bytes after TX bytes were written, and RX+TX must be less than 70. If you write 4 bytes the first byte of read is in position 5 of the FIFO. All of that means that for devices that require an address for reads and writes, the 2 transfers must be put in the same FIFO so the CS can be hold for address and data, otherwise the data would lose it`s meaning. Signed-off-by: Lucas Tanure --- drivers/spi/spi-amd.c | 208 ++++++++++++++++++++++++++++-------------- 1 file changed, 140 insertions(+), 68 deletions(-) diff --git a/drivers/spi/spi-amd.c b/drivers/spi/spi-amd.c index 75390fcb0481..b6308733265e 100644 --- a/drivers/spi/spi-amd.c +++ b/drivers/spi/spi-amd.c @@ -4,7 +4,8 @@ // // Copyright (c) 2020, Advanced Micro Devices, Inc. // -// Author: Sanjay R Mehta +// Authors: Sanjay R Mehta +// Lucas Tanure #include #include @@ -29,6 +30,7 @@ #define AMD_SPI_RX_COUNT_REG 0x4B #define AMD_SPI_STATUS_REG 0x4C +#define AMD_SPI_FIFO_SIZE 70 #define AMD_SPI_MEM_SIZE 200 /* M_CMD OP codes for SPI */ @@ -132,83 +134,152 @@ static int amd_spi_master_setup(struct spi_device *spi) return 0; } -static inline int amd_spi_fifo_xfer(struct amd_spi *amd_spi, - struct spi_master *master, - struct spi_message *message) +static int amd_spi_double_write(struct spi_master *mst, u8 *tx1_buf, u8 tx1_len, u8 *tx2_buf, + u8 tx2_len) { - struct spi_transfer *xfer = NULL; - u8 cmd_opcode; - u8 *buf = NULL; - u32 m_cmd = 0; - u32 i = 0; - u32 tx_len = 0, rx_len = 0; - - list_for_each_entry(xfer, &message->transfers, - transfer_list) { - if (xfer->rx_buf) - m_cmd = AMD_SPI_XFER_RX; - if (xfer->tx_buf) - m_cmd = AMD_SPI_XFER_TX; - - if (m_cmd & AMD_SPI_XFER_TX) { - buf = (u8 *)xfer->tx_buf; - tx_len = xfer->len - 1; - cmd_opcode = *(u8 *)xfer->tx_buf; - buf++; - amd_spi_set_opcode(amd_spi, cmd_opcode); - - /* Write data into the FIFO. */ - for (i = 0; i < tx_len; i++) { - iowrite8(buf[i], ((u8 __iomem *)amd_spi->io_remap_addr + - AMD_SPI_FIFO_BASE + i)); - } + struct amd_spi *amd_spi = spi_master_get_devdata(mst); + int i, ret; - amd_spi_set_tx_count(amd_spi, tx_len); - amd_spi_clear_fifo_ptr(amd_spi); - /* Execute command */ - amd_spi_execute_opcode(amd_spi); - } - if (m_cmd & AMD_SPI_XFER_RX) { - /* - * Store no. of bytes to be received from - * FIFO - */ - rx_len = xfer->len; - buf = (u8 *)xfer->rx_buf; - amd_spi_set_rx_count(amd_spi, rx_len); - amd_spi_clear_fifo_ptr(amd_spi); - /* Execute command */ - amd_spi_execute_opcode(amd_spi); - /* Read data from FIFO to receive buffer */ - for (i = 0; i < rx_len; i++) - buf[i] = amd_spi_readreg8(amd_spi, AMD_SPI_FIFO_BASE + tx_len + i); - } - } + if (tx1_len + tx2_len > AMD_SPI_FIFO_SIZE) + return -EINVAL; - /* Update statistics */ - message->actual_length = tx_len + rx_len + 1; - /* complete the transaction */ - message->status = 0; - spi_finalize_current_message(master); + amd_spi_clear_fifo_ptr(amd_spi); + amd_spi_set_rx_count(amd_spi, 0); - return 0; + amd_spi_set_opcode(amd_spi, tx1_buf[0]); + tx1_len--; + tx1_buf++; + + for (i = 0; i < tx1_len; i++) + amd_spi_writereg8(amd_spi, (u8)(AMD_SPI_FIFO_BASE + i), tx1_buf[i]); + + for (i = 0; i < tx2_len; i++) + amd_spi_writereg8(amd_spi, (u8)(AMD_SPI_FIFO_BASE + tx1_len + i), tx2_buf[i]); + + amd_spi_set_tx_count(amd_spi, tx1_len + tx2_len); + ret = amd_spi_execute_opcode(amd_spi); + + return ret ? ret : tx1_len + 1 + tx2_len; } -static int amd_spi_master_transfer(struct spi_master *master, - struct spi_message *msg) +static int amd_spi_write_read(struct spi_master *mst, u8 *tx_buf, u8 tx_len, u8 *rx_buf, u8 rx_len) { - struct amd_spi *amd_spi = spi_master_get_devdata(master); - struct spi_device *spi = msg->spi; + struct amd_spi *amd_spi = spi_master_get_devdata(mst); + int i, ret; + + if (tx_len + rx_len > AMD_SPI_FIFO_SIZE) + return -EINVAL; + + amd_spi_clear_fifo_ptr(amd_spi); + + if (tx_buf) { + /* Take the first byte to be written and set as opcode */ + amd_spi_set_opcode(amd_spi, tx_buf[0]); + /* Set TX count as the number of bytes to be written less one (opcode byte) */ + tx_len--; + tx_buf++; - amd_spi_select_chip(amd_spi, spi->chip_select); + /* Copy to the FIFO the remaining bytes */ + for (i = 0; i < tx_len; i++) + amd_spi_writereg8(amd_spi, (AMD_SPI_FIFO_BASE + i), tx_buf[i]); - /* - * Extract spi_transfers from the spi message and - * program the controller. + amd_spi_set_tx_count(amd_spi, tx_len); + } + /* Set RX count as the number of bytes that will be read AFTER the TX bytes are sent + * Or set to zero to avoid extra bytes after the write cycle */ - amd_spi_fifo_xfer(amd_spi, master, msg); + amd_spi_set_rx_count(amd_spi, rx_buf ? rx_len : 0); - return 0; + /* Trigger the transfer by executing the opcode */ + ret = amd_spi_execute_opcode(amd_spi); + if (ret) + return ret; + + /* Wait for the SPI bus to be idle and copy the RX bytes from the FIFO from the starting + * position of TX bytes + */ + if (rx_buf) { + for (i = 0; i < rx_len; i++) + rx_buf[i] = amd_spi_readreg8(amd_spi, AMD_SPI_FIFO_BASE + tx_len + i); + } + + return tx_len + 1 + rx_len; +} + +/* amd_spi_master_transfer expects a spi_message with one or two transfers only + * Where a message with one transfer is a single write or read to a device + * And a message with two transfer is an address write followed by a read or + * write data into that address + */ +static int amd_spi_master_transfer(struct spi_master *mst, struct spi_message *msg) +{ + struct amd_spi *amd_spi = spi_master_get_devdata(mst); + struct spi_transfer *xfer, *xfer_n; + struct list_head *pos; + int ret, count = 0; + + list_for_each(pos, &msg->transfers) + count++; + + amd_spi_select_chip(amd_spi, msg->spi->chip_select); + + xfer = list_first_entry(&msg->transfers, struct spi_transfer, transfer_list); + switch (count) { + case 1: + /* This controller can't write and read simultaneously + * It can only write data first and read afterwards + */ + if (xfer->tx_buf && xfer->rx_buf) { + ret = -EINVAL; + dev_err(&mst->dev, "Error. Can't write and read simultaneously\n"); + goto complete; + } + + ret = amd_spi_write_read(mst, (u8 *)xfer->tx_buf, xfer->len, + (u8 *)xfer->rx_buf, xfer->len); + if (ret < 0) + goto complete; + break; + case 2: + xfer_n = list_last_entry(&msg->transfers, struct spi_transfer, transfer_list); + if (xfer->tx_buf && !xfer->rx_buf) { + if (xfer_n->rx_buf && !xfer_n->tx_buf) { + ret = amd_spi_write_read(mst, (u8 *)xfer->tx_buf, xfer->len, + (u8 *)xfer_n->rx_buf, xfer_n->len); + if (ret < 0) + goto complete; + break; + } else if (xfer_n->tx_buf && !xfer_n->rx_buf) { + ret = amd_spi_double_write(mst, (u8 *)xfer->tx_buf, xfer->len, + (u8 *)xfer_n->tx_buf, xfer_n->len); + if (ret < 0) + goto complete; + break; + } + } + ret = -EINVAL; + dev_err(&mst->dev, "Error. Message not supported\n"); + goto complete; + default: + ret = -EINVAL; + dev_err(&mst->dev, "Message with %d transfers is not supported\n", count); + goto complete; + } + + msg->actual_length += ret; + ret = 0; + +complete: + /* complete the transaction */ + msg->status = ret; + spi_finalize_current_message(mst); + + return ret; +} + +static size_t amd_spi_max_transfer_size(struct spi_device *spi) +{ + return AMD_SPI_FIFO_SIZE; } static int amd_spi_probe(struct platform_device *pdev) @@ -238,8 +309,9 @@ static int amd_spi_probe(struct platform_device *pdev) master->bus_num = 0; master->num_chipselect = 4; master->mode_bits = 0; - master->flags = SPI_MASTER_HALF_DUPLEX; + master->flags = SPI_MASTER_HALF_DUPLEX | SPI_CONTROLLER_CS_PER_TRANSFER; master->setup = amd_spi_master_setup; + master->max_transfer_size = amd_spi_max_transfer_size; master->transfer_one_message = amd_spi_master_transfer; /* Register the controller with SPI framework */ From patchwork Tue Aug 24 10:40:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Tanure X-Patchwork-Id: 12454629 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.9 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 729B6C432BE for ; Tue, 24 Aug 2021 10:41:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5C54F60F11 for ; Tue, 24 Aug 2021 10:41:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236488AbhHXKlz (ORCPT ); Tue, 24 Aug 2021 06:41:55 -0400 Received: from mx0b-001ae601.pphosted.com ([67.231.152.168]:45066 "EHLO mx0b-001ae601.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236350AbhHXKlu (ORCPT ); Tue, 24 Aug 2021 06:41:50 -0400 Received: from pps.filterd (m0077474.ppops.net [127.0.0.1]) by mx0b-001ae601.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 17O9oMhW012561; Tue, 24 Aug 2021 05:41:03 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cirrus.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=PODMain02222019; bh=2wUntjv+cBhYZZorzhH9FjfWoIl23/Y/M9545kBYFLc=; b=Uxee53KxMnf/SJghkIkhhHIEip7Ww+G9o0rpWqqg4N3QU/vNuaHkM76fFWzl8jOrnM8P SgJFHhEb9ERDK8AJUhG3LcB5EiFwIwK3v7l51E9ljz3BfuR+iYuPoCyxNTNRdw/UwPo+ 4GQVhYlY9eW0txDJ+EnpZ+NMcnBnqDsXAR9FBVnb8vy1qEC9vDo79koZKzcKta1CYkfO 2Fc/THEyPeFxiVWVz+2d3dy7fYK9JGRXTXfDTqtx21LX+rNA2+mJLKgIX0b7MBXYBdAX UuglWKmaLyI11OP/x/xWM6N+PwrIWvSdZRrlG4mb6VQxT41u/yvtrRbphaPBYJyTVWMq 1w== Received: from ediex02.ad.cirrus.com ([87.246.76.36]) by mx0b-001ae601.pphosted.com with ESMTP id 3amxg601k1-5 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT); Tue, 24 Aug 2021 05:41:02 -0500 Received: from EDIEX01.ad.cirrus.com (198.61.84.80) by EDIEX02.ad.cirrus.com (198.61.84.81) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2242.12; Tue, 24 Aug 2021 11:41:01 +0100 Received: from ediswmail.ad.cirrus.com (198.61.86.93) by EDIEX01.ad.cirrus.com (198.61.84.80) with Microsoft SMTP Server id 15.1.2242.12 via Frontend Transport; Tue, 24 Aug 2021 11:41:01 +0100 Received: from aryzen.ad.cirrus.com (unknown [198.61.65.58]) by ediswmail.ad.cirrus.com (Postfix) with ESMTP id E8D692BA; Tue, 24 Aug 2021 10:41:00 +0000 (UTC) From: Lucas Tanure To: Mark Brown , Greg Kroah-Hartman , "Rafael J . Wysocki" , Sanjay R Mehta , Nehal Bakulchandra Shah CC: , , , Lucas Tanure Subject: [PATCH 9/9] spi: amd: Add support for latest platform Date: Tue, 24 Aug 2021 11:40:41 +0100 Message-ID: <20210824104041.708945-10-tanureal@opensource.cirrus.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210824104041.708945-1-tanureal@opensource.cirrus.com> References: <20210824104041.708945-1-tanureal@opensource.cirrus.com> MIME-Version: 1.0 X-Proofpoint-GUID: TtRVHzYK-d7bQ5uej-E_zrG7FGf4nHJP X-Proofpoint-ORIG-GUID: TtRVHzYK-d7bQ5uej-E_zrG7FGf4nHJP X-Proofpoint-Spam-Reason: safe Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Add support for AMDI0062 controllers Signed-off-by: Nehal Bakulchandra Shah Signed-off-by: Lucas Tanure Reported-by: kernel test robot --- drivers/spi/spi-amd.c | 127 +++++++++++++++++++++++++++++++++--------- 1 file changed, 100 insertions(+), 27 deletions(-) diff --git a/drivers/spi/spi-amd.c b/drivers/spi/spi-amd.c index b6308733265e..cd0b38ead150 100644 --- a/drivers/spi/spi-amd.c +++ b/drivers/spi/spi-amd.c @@ -2,9 +2,10 @@ // // AMD SPI controller driver // -// Copyright (c) 2020, Advanced Micro Devices, Inc. +// Copyright (c) 2020-2021, Advanced Micro Devices, Inc. // // Authors: Sanjay R Mehta +// Nehal Bakulchandra Shah // Lucas Tanure #include @@ -15,32 +16,46 @@ #include #include -#define AMD_SPI_CTRL0_REG 0x00 -#define AMD_SPI_EXEC_CMD BIT(16) -#define AMD_SPI_FIFO_CLEAR BIT(20) -#define AMD_SPI_BUSY BIT(31) +#define AMD_SPI_CTRL0_REG 0x00 +#define AMD_SPI_EXEC_CMD BIT(16) +#define AMD_SPI_FIFO_CLEAR BIT(20) +#define AMD_SPI_BUSY BIT(31) +#define AMD_SPI_ENABLE_REG 0x20 -#define AMD_SPI_OPCODE_MASK 0xFF +#define AMD_SPI_DUMMY_CYCL_REG 0x32 +#define AMD_SPI_OPCODE_REG 0x45 +#define AMD_SPI_CMD_TRIGGER_REG 0x47 +#define AMD_SPI_TRIGGER_CMD BIT(7) +#define AMD_SPI_OPCODE_MASK 0xFF -#define AMD_SPI_ALT_CS_REG 0x1D -#define AMD_SPI_ALT_CS_MASK 0x3 +#define AMD_SPI_ALT_CS_REG 0x1D +#define AMD_SPI_ALT_CS_MASK GENMASK(1, 0) -#define AMD_SPI_FIFO_BASE 0x80 -#define AMD_SPI_TX_COUNT_REG 0x48 -#define AMD_SPI_RX_COUNT_REG 0x4B -#define AMD_SPI_STATUS_REG 0x4C +#define AMD_SPI_FIFO_BASE 0x80 +#define AMD_SPI_TX_COUNT_REG 0x48 +#define AMD_SPI_RX_COUNT_REG 0x4B +#define AMD_SPI_STATUS_REG 0x4C -#define AMD_SPI_FIFO_SIZE 70 -#define AMD_SPI_MEM_SIZE 200 +#define AMD_SPI_FIFO_SIZE 70 +#define AMD_SPI_MEM_SIZE 200 /* M_CMD OP codes for SPI */ -#define AMD_SPI_XFER_TX 1 -#define AMD_SPI_XFER_RX 2 +#define AMD_SPI_XFER_TX 1 +#define AMD_SPI_XFER_RX 2 struct amd_spi { void __iomem *io_remap_addr; unsigned long io_base_addr; u32 rom_addr; + const struct amd_spi_devtype_data *devtype_data; + struct spi_device *spi_dev; + struct spi_master *master; +}; + +struct amd_spi_devtype_data { + u8 version; + int (*exec_op)(struct amd_spi *amd_spi); + void (*set_op)(struct amd_spi *amd_spi, u8 cmd_opcode); }; static inline u8 amd_spi_readreg8(struct amd_spi *amd_spi, int idx) @@ -84,16 +99,26 @@ static void amd_spi_select_chip(struct amd_spi *amd_spi, u8 cs) amd_spi_setclear_reg8(amd_spi, AMD_SPI_ALT_CS_REG, cs, AMD_SPI_ALT_CS_MASK); } +static inline void amd_spi_clear_chip(struct amd_spi *amd_spi, u8 chip_select) +{ + amd_spi_writereg8(amd_spi, AMD_SPI_ALT_CS_REG, chip_select & ~AMD_SPI_ALT_CS_MASK); +} + static void amd_spi_clear_fifo_ptr(struct amd_spi *amd_spi) { amd_spi_setclear_reg32(amd_spi, AMD_SPI_CTRL0_REG, AMD_SPI_FIFO_CLEAR, AMD_SPI_FIFO_CLEAR); } -static void amd_spi_set_opcode(struct amd_spi *amd_spi, u8 cmd_opcode) +static void amd_spi_set_opcode_v1(struct amd_spi *amd_spi, u8 cmd_opcode) { amd_spi_setclear_reg32(amd_spi, AMD_SPI_CTRL0_REG, cmd_opcode, AMD_SPI_OPCODE_MASK); } +static void amd_spi_set_opcode_v2(struct amd_spi *amd_spi, u8 cmd_opcode) +{ + amd_spi_writereg8(amd_spi, AMD_SPI_OPCODE_REG, cmd_opcode); +} + static inline void amd_spi_set_rx_count(struct amd_spi *amd_spi, u8 rx_count) { amd_spi_setclear_reg8(amd_spi, AMD_SPI_RX_COUNT_REG, rx_count, 0xff); @@ -104,7 +129,7 @@ static inline void amd_spi_set_tx_count(struct amd_spi *amd_spi, u8 tx_count) amd_spi_setclear_reg8(amd_spi, AMD_SPI_TX_COUNT_REG, tx_count, 0xff); } -static int amd_spi_busy_wait(struct amd_spi *amd_spi) +static int amd_spi_busy_wait_v1(struct amd_spi *amd_spi) { u32 val; @@ -112,17 +137,39 @@ static int amd_spi_busy_wait(struct amd_spi *amd_spi) !(val & AMD_SPI_BUSY), 10, 100000); } -static int amd_spi_execute_opcode(struct amd_spi *amd_spi) +static int amd_spi_execute_opcode_v1(struct amd_spi *amd_spi) { - int ret = amd_spi_busy_wait(amd_spi); + int ret; + ret = amd_spi_busy_wait_v1(amd_spi); if (ret) return ret; - /* Set ExecuteOpCode bit in the CTRL0 register */ amd_spi_setclear_reg32(amd_spi, AMD_SPI_CTRL0_REG, AMD_SPI_EXEC_CMD, AMD_SPI_EXEC_CMD); - return amd_spi_busy_wait(amd_spi); + return amd_spi_busy_wait_v1(amd_spi); +} + +static int amd_spi_busy_wait_v2(struct amd_spi *amd_spi) +{ + u32 val; + + return readl_poll_timeout(amd_spi->io_remap_addr + AMD_SPI_STATUS_REG, val, + !(val & AMD_SPI_BUSY), 10, 1000); +} + +static int amd_spi_execute_opcode_v2(struct amd_spi *amd_spi) +{ + int ret; + + ret = amd_spi_busy_wait_v2(amd_spi); + if (ret) + return ret; + + amd_spi_setclear_reg8(amd_spi, AMD_SPI_CMD_TRIGGER_REG, AMD_SPI_TRIGGER_CMD, + AMD_SPI_TRIGGER_CMD); + + return amd_spi_busy_wait_v2(amd_spi); } static int amd_spi_master_setup(struct spi_device *spi) @@ -138,6 +185,7 @@ static int amd_spi_double_write(struct spi_master *mst, u8 *tx1_buf, u8 tx1_len, u8 tx2_len) { struct amd_spi *amd_spi = spi_master_get_devdata(mst); + const struct amd_spi_devtype_data *priv = amd_spi->devtype_data; int i, ret; if (tx1_len + tx2_len > AMD_SPI_FIFO_SIZE) @@ -146,7 +194,7 @@ static int amd_spi_double_write(struct spi_master *mst, u8 *tx1_buf, u8 tx1_len, amd_spi_clear_fifo_ptr(amd_spi); amd_spi_set_rx_count(amd_spi, 0); - amd_spi_set_opcode(amd_spi, tx1_buf[0]); + priv->set_op(amd_spi, tx1_buf[0]); tx1_len--; tx1_buf++; @@ -157,7 +205,7 @@ static int amd_spi_double_write(struct spi_master *mst, u8 *tx1_buf, u8 tx1_len, amd_spi_writereg8(amd_spi, (u8)(AMD_SPI_FIFO_BASE + tx1_len + i), tx2_buf[i]); amd_spi_set_tx_count(amd_spi, tx1_len + tx2_len); - ret = amd_spi_execute_opcode(amd_spi); + ret = priv->exec_op(amd_spi); return ret ? ret : tx1_len + 1 + tx2_len; } @@ -165,6 +213,7 @@ static int amd_spi_double_write(struct spi_master *mst, u8 *tx1_buf, u8 tx1_len, static int amd_spi_write_read(struct spi_master *mst, u8 *tx_buf, u8 tx_len, u8 *rx_buf, u8 rx_len) { struct amd_spi *amd_spi = spi_master_get_devdata(mst); + const struct amd_spi_devtype_data *priv = amd_spi->devtype_data; int i, ret; if (tx_len + rx_len > AMD_SPI_FIFO_SIZE) @@ -174,7 +223,7 @@ static int amd_spi_write_read(struct spi_master *mst, u8 *tx_buf, u8 tx_len, u8 if (tx_buf) { /* Take the first byte to be written and set as opcode */ - amd_spi_set_opcode(amd_spi, tx_buf[0]); + priv->set_op(amd_spi, tx_buf[0]); /* Set TX count as the number of bytes to be written less one (opcode byte) */ tx_len--; tx_buf++; @@ -191,7 +240,7 @@ static int amd_spi_write_read(struct spi_master *mst, u8 *tx_buf, u8 tx_len, u8 amd_spi_set_rx_count(amd_spi, rx_buf ? rx_len : 0); /* Trigger the transfer by executing the opcode */ - ret = amd_spi_execute_opcode(amd_spi); + ret = priv->exec_op(amd_spi); if (ret) return ret; @@ -274,6 +323,9 @@ static int amd_spi_master_transfer(struct spi_master *mst, struct spi_message *m msg->status = ret; spi_finalize_current_message(mst); + if (amd_spi->devtype_data->version) + amd_spi_clear_chip(amd_spi, msg->spi->chip_select); + return ret; } @@ -305,6 +357,12 @@ static int amd_spi_probe(struct platform_device *pdev) } dev_dbg(dev, "io_remap_address: %p\n", amd_spi->io_remap_addr); + amd_spi->devtype_data = device_get_match_data(dev); + if (!amd_spi->devtype_data) { + err = -ENODEV; + goto err_free_master; + } + /* Initialize the spi_master fields */ master->bus_num = 0; master->num_chipselect = 4; @@ -329,9 +387,23 @@ static int amd_spi_probe(struct platform_device *pdev) return err; } +static const struct amd_spi_devtype_data spi_v1 = { + .exec_op = amd_spi_execute_opcode_v1, + .set_op = amd_spi_set_opcode_v1, +}; + +static const struct amd_spi_devtype_data spi_v2 = { + .version = 1, + .exec_op = amd_spi_execute_opcode_v2, + .set_op = amd_spi_set_opcode_v2, +}; + #ifdef CONFIG_ACPI static const struct acpi_device_id spi_acpi_match[] = { - { "AMDI0061", 0 }, + { "AMDI0061", + .driver_data = (kernel_ulong_t)&spi_v1 }, + { "AMDI0062", + .driver_data = (kernel_ulong_t)&spi_v2 }, {}, }; MODULE_DEVICE_TABLE(acpi, spi_acpi_match); @@ -349,4 +421,5 @@ module_platform_driver(amd_spi_driver); MODULE_LICENSE("Dual BSD/GPL"); MODULE_AUTHOR("Sanjay Mehta "); +MODULE_AUTHOR("Nehal Bakulchandra Shah "); MODULE_DESCRIPTION("AMD SPI Master Controller Driver");