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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Aug 2021 20:15:33.7219 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e8b5550b-f649-44dd-e33d-08d969976cee X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT022.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4190 Precedence: bulk List-ID: X-Mailing-List: linux-hwmon@vger.kernel.org Some of the existing assumptions made do not scale properly to new silicon in upcoming changes. This commit should cause no functional changes to existing silicon. Signed-off-by: Mario Limonciello --- drivers/hwmon/k10temp.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/drivers/hwmon/k10temp.c b/drivers/hwmon/k10temp.c index f6b325b8463e..159dbad73d82 100644 --- a/drivers/hwmon/k10temp.c +++ b/drivers/hwmon/k10temp.c @@ -65,10 +65,11 @@ static DEFINE_MUTEX(nb_smu_ind_mutex); #define F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET 0xd8200c64 #define F15H_M60H_REPORTED_TEMP_CTRL_OFFSET 0xd8200ca4 -/* Common for Zen CPU families (Family 17h and 18h) */ -#define ZEN_REPORTED_TEMP_CTRL_OFFSET 0x00059800 +/* Common for Zen CPU families (Family 17h and 18h and 19h) */ +#define ZEN_REPORTED_TEMP_CTRL_BASE 0x00059800 -#define ZEN_CCD_TEMP(x) (0x00059954 + ((x) * 4)) +#define ZEN_CCD_TEMP(offset, x) (ZEN_REPORTED_TEMP_CTRL_BASE + \ + (offset) + ((x) * 4)) #define ZEN_CCD_TEMP_VALID BIT(11) #define ZEN_CCD_TEMP_MASK GENMASK(10, 0) @@ -103,6 +104,7 @@ struct k10temp_data { u32 temp_adjust_mask; u32 show_temp; bool is_zen; + u32 ccd_offset; }; #define TCTL_BIT 0 @@ -163,7 +165,7 @@ static void read_tempreg_nb_f15(struct pci_dev *pdev, u32 *regval) static void read_tempreg_nb_zen(struct pci_dev *pdev, u32 *regval) { amd_smn_read(amd_pci_dev_to_node_id(pdev), - ZEN_REPORTED_TEMP_CTRL_OFFSET, regval); + ZEN_REPORTED_TEMP_CTRL_BASE, regval); } static long get_raw_temp(struct k10temp_data *data) @@ -226,7 +228,8 @@ static int k10temp_read_temp(struct device *dev, u32 attr, int channel, break; case 2 ... 9: /* Tccd{1-8} */ amd_smn_read(amd_pci_dev_to_node_id(data->pdev), - ZEN_CCD_TEMP(channel - 2), ®val); + ZEN_CCD_TEMP(data->ccd_offset, channel - 2), + ®val); *val = (regval & ZEN_CCD_TEMP_MASK) * 125 - 49000; break; default: @@ -387,7 +390,7 @@ static void k10temp_get_ccd_support(struct pci_dev *pdev, for (i = 0; i < limit; i++) { amd_smn_read(amd_pci_dev_to_node_id(pdev), - ZEN_CCD_TEMP(i), ®val); + ZEN_CCD_TEMP(data->ccd_offset, i), ®val); if (regval & ZEN_CCD_TEMP_VALID) data->show_temp |= BIT(TCCD_BIT(i)); } @@ -433,12 +436,14 @@ static int k10temp_probe(struct pci_dev *pdev, const struct pci_device_id *id) case 0x8: /* Zen+ */ case 0x11: /* Zen APU */ case 0x18: /* Zen+ APU */ + data->ccd_offset = 0x154; k10temp_get_ccd_support(pdev, data, 4); break; case 0x31: /* Zen2 Threadripper */ case 0x60: /* Renoir */ case 0x68: /* Lucienne */ case 0x71: /* Zen2 */ + data->ccd_offset = 0x154; k10temp_get_ccd_support(pdev, data, 8); break; } @@ -451,6 +456,7 @@ static int k10temp_probe(struct pci_dev *pdev, const struct pci_device_id *id) case 0x0 ... 0x1: /* Zen3 SP3/TR */ case 0x21: /* Zen3 Ryzen Desktop */ case 0x50 ... 0x5f: /* Green Sardine */ + data->ccd_offset = 0x154; k10temp_get_ccd_support(pdev, data, 8); break; } From patchwork Fri Aug 27 20:15:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 12462867 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.0 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, UNWANTED_LANGUAGE_BODY,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6CCBAC43214 for ; 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Peter Anvin" , Jean Delvare , Bjorn Helgaas , Yazen Ghannam , David Bartley , "open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)" , "open list:PCI SUBSYSTEM" Subject: [PATCH v2 2/3] hwmon: (k10temp): Add support for yellow carp Date: Fri, 27 Aug 2021 15:15:26 -0500 Message-ID: <20210827201527.24454-3-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210827201527.24454-1-mario.limonciello@amd.com> References: <20210827201527.24454-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 2e3c8450-5ad5-42b0-3536-08d969976e5b X-MS-TrafficTypeDiagnostic: MN2PR12MB3311: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4303; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: dhoTPVE1qr3f4y6bNWXvi1HGsrbOKSz8qSwKdLzr84c101IBydSMGufvz7zOlQrQ+ewXEQt9FmkTrCYQSHk8NGnI78zWHONW7BBgyemu58IFYMITi57tqxnUb7vVqP0WrAVP5cmriovp1KZGLhu9R0dmaA5AFjxrZCaOBabIQWdkTYvQsXYS2yhE49ZVVKVn1MiX7n3E09P1a279P7dVlatJWRYZ62GPxatp3wT04L8EXsuvTDL4boCYf0DC7ewZc1Fby0Ug1/23gzMcYyir5xhJyy2eRtRsqKoBA6LtCeEsegoTZ9U6J+uwiBHRd3Ju4PdQVb/vTWd0UmDa8i8+vywsVcVL/5dH4r6nUkxlelFi2iQEdzh2HzEUvnY4YxtzfAO7vH6zOZlYAvgxeKoPhuQ+6TVSmiA1NABt2h4K302m5+Rr/v7p99ajvdA8iYzp7qMZAyicjv/PGO2QRibg9yEFD/087HCUyT5+La7BKYe2niMhxscQQSRYhx88uDG7gb6xDSL1VLerLL/HxofaL1hvAJKLGcSn0FKVy5vcBH25dMmqehXN0ZF3AQjOydeAf7Y1a7nVP4Ts6tUZWVePaUmtRxUBwgJr5zBuLcwg8X77OlYhbwEN5xXgK86Ex22jZaRbR9343wnj352H5fxtuJN5cs5x5tAcNCbf5YvXPExM/IkTXYCVxgz+MM6xmVbJfqnm/Mw2bYVxbWHZDuVgHxqVcI+ySXaD+3xyuRVuDBM= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(396003)(376002)(346002)(39860400002)(136003)(46966006)(36840700001)(7416002)(478600001)(44832011)(7696005)(4326008)(8936002)(5660300002)(316002)(54906003)(26005)(426003)(86362001)(2906002)(1076003)(2616005)(8676002)(186003)(70206006)(6916009)(82310400003)(83380400001)(36860700001)(356005)(82740400003)(81166007)(36756003)(16526019)(70586007)(336012)(47076005)(6666004)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Aug 2021 20:15:36.1045 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2e3c8450-5ad5-42b0-3536-08d969976e5b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT031.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB3311 Precedence: bulk List-ID: X-Mailing-List: linux-hwmon@vger.kernel.org Yellow carp matches same behavior as green sardine and other Zen3 products, but have different CCD offsets. Signed-off-by: Mario Limonciello Acked-by: Borislav Petkov --- arch/x86/kernel/amd_nb.c | 5 +++++ drivers/hwmon/k10temp.c | 5 +++++ include/linux/pci_ids.h | 1 + 3 files changed, 11 insertions(+) diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c index 23dda362dc0f..c92c9c774c0e 100644 --- a/arch/x86/kernel/amd_nb.c +++ b/arch/x86/kernel/amd_nb.c @@ -25,6 +25,8 @@ #define PCI_DEVICE_ID_AMD_17H_M60H_DF_F4 0x144c #define PCI_DEVICE_ID_AMD_17H_M70H_DF_F4 0x1444 #define PCI_DEVICE_ID_AMD_19H_DF_F4 0x1654 +#define PCI_DEVICE_ID_AMD_19H_M40H_ROOT 0x14b5 +#define PCI_DEVICE_ID_AMD_19H_M40H_DF_F4 0x167d #define PCI_DEVICE_ID_AMD_19H_M50H_DF_F4 0x166e /* Protect the PCI config register pairs used for SMN and DF indirect access. */ @@ -37,6 +39,7 @@ static const struct pci_device_id amd_root_ids[] = { { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_ROOT) }, { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M30H_ROOT) }, { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M60H_ROOT) }, + { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M40H_ROOT) }, {} }; @@ -58,6 +61,7 @@ static const struct pci_device_id amd_nb_misc_ids[] = { { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) }, { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F3) }, { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_DF_F3) }, + { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M40H_DF_F3) }, { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M50H_DF_F3) }, {} }; @@ -74,6 +78,7 @@ static const struct pci_device_id amd_nb_link_ids[] = { { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M60H_DF_F4) }, { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F4) }, { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_DF_F4) }, + { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M40H_DF_F4) }, { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M50H_DF_F4) }, { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CNB17H_F4) }, {} diff --git a/drivers/hwmon/k10temp.c b/drivers/hwmon/k10temp.c index 159dbad73d82..38bc35ac8135 100644 --- a/drivers/hwmon/k10temp.c +++ b/drivers/hwmon/k10temp.c @@ -459,6 +459,10 @@ static int k10temp_probe(struct pci_dev *pdev, const struct pci_device_id *id) data->ccd_offset = 0x154; k10temp_get_ccd_support(pdev, data, 8); break; + case 0x40 ... 0x4f: /* Yellow Carp */ + data->ccd_offset = 0x300; + k10temp_get_ccd_support(pdev, data, 8); + break; } } else { data->read_htcreg = read_htcreg_pci; @@ -499,6 +503,7 @@ static const struct pci_device_id k10temp_id_table[] = { { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M60H_DF_F3) }, { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F3) }, { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_DF_F3) }, + { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M40H_DF_F3) }, { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M50H_DF_F3) }, { PCI_VDEVICE(HYGON, PCI_DEVICE_ID_AMD_17H_DF_F3) }, {} diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h index 5356ccf1c275..e77a62fd0036 100644 --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h @@ -555,6 +555,7 @@ #define PCI_DEVICE_ID_AMD_17H_M60H_DF_F3 0x144b #define PCI_DEVICE_ID_AMD_17H_M70H_DF_F3 0x1443 #define PCI_DEVICE_ID_AMD_19H_DF_F3 0x1653 +#define PCI_DEVICE_ID_AMD_19H_M40H_DF_F3 0x167c #define PCI_DEVICE_ID_AMD_19H_M50H_DF_F3 0x166d #define PCI_DEVICE_ID_AMD_CNB17H_F3 0x1703 #define PCI_DEVICE_ID_AMD_LANCE 0x2000 From patchwork Fri Aug 27 20:15:27 2021 Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Aug 2021 20:15:38.8120 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a10b91f0-3554-44e1-300a-08d969976ff8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT031.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4171 Precedence: bulk List-ID: X-Mailing-List: linux-hwmon@vger.kernel.org Enabling Yellow Carp was initially not working "properly" because extra IDs were needed, but this wasn't obvious because fail values from `amd_smn_read` were ignored. Don't discard errors from any functions providing them, instead pass up to the caller. Signed-off-by: Mario Limonciello --- drivers/hwmon/k10temp.c | 87 ++++++++++++++++++++++++----------------- 1 file changed, 52 insertions(+), 35 deletions(-) diff --git a/drivers/hwmon/k10temp.c b/drivers/hwmon/k10temp.c index 38bc35ac8135..2edb49d39d22 100644 --- a/drivers/hwmon/k10temp.c +++ b/drivers/hwmon/k10temp.c @@ -98,8 +98,8 @@ static DEFINE_MUTEX(nb_smu_ind_mutex); struct k10temp_data { struct pci_dev *pdev; - void (*read_htcreg)(struct pci_dev *pdev, u32 *regval); - void (*read_tempreg)(struct pci_dev *pdev, u32 *regval); + int (*read_htcreg)(struct pci_dev *pdev, u32 *regval); + int (*read_tempreg)(struct pci_dev *pdev, u32 *regval); int temp_offset; u32 temp_adjust_mask; u32 show_temp; @@ -129,55 +129,65 @@ static const struct tctl_offset tctl_offset_table[] = { { 0x17, "AMD Ryzen Threadripper 29", 27000 }, /* 29{20,50,70,90}[W]X */ }; -static void read_htcreg_pci(struct pci_dev *pdev, u32 *regval) +static int read_htcreg_pci(struct pci_dev *pdev, u32 *regval) { - pci_read_config_dword(pdev, REG_HARDWARE_THERMAL_CONTROL, regval); + return pci_read_config_dword(pdev, REG_HARDWARE_THERMAL_CONTROL, regval); } -static void read_tempreg_pci(struct pci_dev *pdev, u32 *regval) +static int read_tempreg_pci(struct pci_dev *pdev, u32 *regval) { - pci_read_config_dword(pdev, REG_REPORTED_TEMPERATURE, regval); + return pci_read_config_dword(pdev, REG_REPORTED_TEMPERATURE, regval); } -static void amd_nb_index_read(struct pci_dev *pdev, unsigned int devfn, +static int amd_nb_index_read(struct pci_dev *pdev, unsigned int devfn, unsigned int base, int offset, u32 *val) { + int ret; + mutex_lock(&nb_smu_ind_mutex); - pci_bus_write_config_dword(pdev->bus, devfn, - base, offset); - pci_bus_read_config_dword(pdev->bus, devfn, - base + 4, val); + ret = pci_bus_write_config_dword(pdev->bus, devfn, + base, offset); + if (ret) + goto out; + ret = pci_bus_read_config_dword(pdev->bus, devfn, + base + 4, val); +out: mutex_unlock(&nb_smu_ind_mutex); + return ret; } -static void read_htcreg_nb_f15(struct pci_dev *pdev, u32 *regval) +static int read_htcreg_nb_f15(struct pci_dev *pdev, u32 *regval) { - amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8, - F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET, regval); + return amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8, + F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET, regval); } -static void read_tempreg_nb_f15(struct pci_dev *pdev, u32 *regval) +static int read_tempreg_nb_f15(struct pci_dev *pdev, u32 *regval) { - amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8, - F15H_M60H_REPORTED_TEMP_CTRL_OFFSET, regval); + return amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8, + F15H_M60H_REPORTED_TEMP_CTRL_OFFSET, regval); } -static void read_tempreg_nb_zen(struct pci_dev *pdev, u32 *regval) +static int read_tempreg_nb_zen(struct pci_dev *pdev, u32 *regval) { - amd_smn_read(amd_pci_dev_to_node_id(pdev), - ZEN_REPORTED_TEMP_CTRL_BASE, regval); + return amd_smn_read(amd_pci_dev_to_node_id(pdev), + ZEN_REPORTED_TEMP_CTRL_BASE, regval); } -static long get_raw_temp(struct k10temp_data *data) +static int get_raw_temp(struct k10temp_data *data, long *val) { u32 regval; - long temp; + int ret; - data->read_tempreg(data->pdev, ®val); - temp = (regval >> ZEN_CUR_TEMP_SHIFT) * 125; + ret = data->read_tempreg(data->pdev, ®val); + if (ret) + return ret; + *val = (regval >> ZEN_CUR_TEMP_SHIFT) * 125; if (regval & data->temp_adjust_mask) - temp -= 49000; - return temp; + *val -= 49000; + if (*val < 0) + return -EINVAL; + return 0; } static const char *k10temp_temp_label[] = { @@ -212,24 +222,27 @@ static int k10temp_read_temp(struct device *dev, u32 attr, int channel, { struct k10temp_data *data = dev_get_drvdata(dev); u32 regval; + int ret; switch (attr) { case hwmon_temp_input: switch (channel) { case 0: /* Tctl */ - *val = get_raw_temp(data); - if (*val < 0) - *val = 0; + ret = get_raw_temp(data, val); + if (ret) + return ret; break; case 1: /* Tdie */ - *val = get_raw_temp(data) - data->temp_offset; - if (*val < 0) - *val = 0; + ret = get_raw_temp(data, val) - data->temp_offset; + if (ret) + return ret; break; case 2 ... 9: /* Tccd{1-8} */ - amd_smn_read(amd_pci_dev_to_node_id(data->pdev), + ret = amd_smn_read(amd_pci_dev_to_node_id(data->pdev), ZEN_CCD_TEMP(data->ccd_offset, channel - 2), ®val); + if (ret) + return ret; *val = (regval & ZEN_CCD_TEMP_MASK) * 125 - 49000; break; default: @@ -240,11 +253,15 @@ static int k10temp_read_temp(struct device *dev, u32 attr, int channel, *val = 70 * 1000; break; case hwmon_temp_crit: - data->read_htcreg(data->pdev, ®val); + ret = data->read_htcreg(data->pdev, ®val); + if (ret) + return ret; *val = ((regval >> 16) & 0x7f) * 500 + 52000; break; case hwmon_temp_crit_hyst: - data->read_htcreg(data->pdev, ®val); + ret = data->read_htcreg(data->pdev, ®val); + if (ret) + return ret; *val = (((regval >> 16) & 0x7f) - ((regval >> 24) & 0xf)) * 500 + 52000; break;