From patchwork Sun Aug 29 15:47:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12464107 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2A7EDC43214 for ; Sun, 29 Aug 2021 15:48:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0C59E60FED for ; Sun, 29 Aug 2021 15:48:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235684AbhH2Psz (ORCPT ); Sun, 29 Aug 2021 11:48:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53146 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235642AbhH2Psy (ORCPT ); Sun, 29 Aug 2021 11:48:54 -0400 Received: from mail-lj1-x235.google.com (mail-lj1-x235.google.com [IPv6:2a00:1450:4864:20::235]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E0753C06175F for ; Sun, 29 Aug 2021 08:48:01 -0700 (PDT) Received: by mail-lj1-x235.google.com with SMTP id w4so21211412ljh.13 for ; Sun, 29 Aug 2021 08:48:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=inLqKYpa2FC3cgFT4WtB/EnDDjgqc5HnVORQi3svwOE=; b=F8ay6u/cSfUnNNdwiS+jLN3ZqiU1Vt8oW1KbB9/12Eh1M2l7M8JFC0G9UYbEIkeQGQ GTXgqxpPZYfeDPS2wbgh0kNkYts4z7S/xQMyntn6PXz7sxE421Ry5TeJ+2/3e1qwDYuM X3Sba1dek5IMManHoIPomr4EbRfitiY1/MAXbbn+0x2+Fl9/dfehNxIn3feJWkwSyuHY KENvz7iQPxQOfQXJu+o+fzznF75+NNwGA8uy+8j1uLxJHfrUl9o9jWzLoNEIdyMrW1LP rVqxWJfbRzT2qtQgdDapfiMxL5ekY+0CtBB/nbMa5bHwYtGA4VwWWOBKHDuj0Qx2PiGt 8PLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=inLqKYpa2FC3cgFT4WtB/EnDDjgqc5HnVORQi3svwOE=; b=P+CU5iRFi+PShVuZSGo6u58SKQ7sEfPm2jHNQVonHl2xipmQ7Dimtrgaxh5/i8rRp4 rimil0cEGWNmqPhnypdCr7fzL8A2mmn7snXs0mX0onkbnNZUAz30KgThcN8AAtnWat5e qqQHcuRTO9XNyHU0vxfdRNbf3mi8Kypof5+7BZ9A+HdAMSH35cKWYbhWo+glApemin/Y tVJf844Cla4+ko309i2glhS2lw65+1g0pDJ3vOASuZvwreBF8aXD23H2VXGS1VhD0WJT DP4xOe6j3XgPrWGyWOqW9EEX5W9rHuOSWVEI5OOwa/RfkvqRwEV3WtrL7PuqYrOykMdt 3DrA== X-Gm-Message-State: AOAM533fDr+GI+N5m1AnM3kw83X24PZSQNI89h0uZNShw4fPx2yh4g1E Hh3BeuFDHfh/yeFeGOg3DtJ35A== X-Google-Smtp-Source: ABdhPJz25zhv1EwE7h5kOWbKDjoJF/zD4TToDLyjp9wuFbb2cExt+RdUCStdkoXk01E9yDFSMYlXNA== X-Received: by 2002:a05:651c:144:: with SMTP id c4mr16480033ljd.223.1630252080200; Sun, 29 Aug 2021 08:48:00 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id y5sm1481243ljd.38.2021.08.29.08.47.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Aug 2021 08:47:59 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Stephen Boyd , Taniya Das , Jonathan Marek , Michael Turquette Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, Bryan O'Donoghue , Mark Brown , Ulf Hansson , linux-kernel@vger.kernel.org, Rob Herring Subject: [PATCH v7 1/8] dt-bindings: clock: qcom,dispcc-sm8x50: add mmcx power domain Date: Sun, 29 Aug 2021 18:47:50 +0300 Message-Id: <20210829154757.784699-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210829154757.784699-1-dmitry.baryshkov@linaro.org> References: <20210829154757.784699-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On sm8250 dispcc requires MMCX power domain to be powered up before clock controller's registers become available. For now sm8250 was using external regulator driven by the power domain to describe this relationship. Switch into specifying power-domain and required opp-state directly. Signed-off-by: Dmitry Baryshkov Reviewed-by: Bjorn Andersson Reviewed-by: Rob Herring --- .../bindings/clock/qcom,dispcc-sm8x50.yaml | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml index 6667261dc665..31497677e8de 100644 --- a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml @@ -56,6 +56,16 @@ properties: reg: maxItems: 1 + power-domains: + description: + A phandle and PM domain specifier for the MMCX power domain. + maxItems: 1 + + required-opps: + description: + A phandle to an OPP node describing required MMCX performance point. + maxItems: 1 + required: - compatible - reg @@ -70,6 +80,7 @@ additionalProperties: false examples: - | #include + #include clock-controller@af00000 { compatible = "qcom,sm8250-dispcc"; reg = <0x0af00000 0x10000>; @@ -90,5 +101,7 @@ examples: #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; + power-domains = <&rpmhpd SM8250_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; }; ... From patchwork Sun Aug 29 15:47:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12464111 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D8764C19F37 for ; Sun, 29 Aug 2021 15:48:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B03D560FE6 for ; Sun, 29 Aug 2021 15:48:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235720AbhH2Ps6 (ORCPT ); Sun, 29 Aug 2021 11:48:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53152 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235564AbhH2Psz (ORCPT ); Sun, 29 Aug 2021 11:48:55 -0400 Received: from mail-lj1-x235.google.com (mail-lj1-x235.google.com [IPv6:2a00:1450:4864:20::235]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A4B31C061796 for ; Sun, 29 Aug 2021 08:48:02 -0700 (PDT) Received: by mail-lj1-x235.google.com with SMTP id s3so21258009ljp.11 for ; Sun, 29 Aug 2021 08:48:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FTbSV1E56r1NVZnQXDLnD85O88p/XKd1hFPjXfdyNKM=; b=fUKbEOZOe8ciXUu+L1aPDtOfETIX4lcjQ4ye+RO8Tb0n1yBBGrGTWsfykF/igiM2ti JsntY4K3BnJ0JSV52cElEARTVg7hjXxeOm/ObhO+4voF5W8gZCVj5cAPpFviz2dXL5z2 ZkyHOsYV343oMOambqC74/BCeIHJ9tAJvvGvWYWW5JOEcPkbM+pVOGBdfeC+B3VAC8Nx qkH7BTiwbSGg2hoQbJnZJcDlc7MxGQXTguFaXElriA/Kjq0fmfAu3sp3VaYRHuShlgjJ McJntFk9Ecn3hcYI8GEbPTqTICpCH0JGAV/g04Xx3ANQFhFakicsFmRUMbjirUWIn5yU rzJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FTbSV1E56r1NVZnQXDLnD85O88p/XKd1hFPjXfdyNKM=; b=rT+Nn6BAOvWlyWf7Pis5ktKUhVLc2Skx7bc5WImz4/GMFPldsZxy+skJWMGoxzxOi4 IkV1NwHcehzc2TCM5im20Wy1abME+hJdwE+eLcDwIm2mlnwEy13RWqYkDMafrhnITgdY 4/a3+/B9eNZsUcFp9YI3mFPmxObdtjzjgp5p+w09CWo1kjQftnVOoSxD/73Ho6Eu/tHm UFSfTl/UQ/l+axVirtgsOgv2t+ifAUklaXKDNtCPTdybM3SDKZzuOi36JR7kv05KIDF8 MvDvjVGwbR5zmalyDmAfIwUfdA/xuB5ivu5BHoW32DpEa08lLM0Vbgqky9g6ROcxp3XC wyIg== X-Gm-Message-State: AOAM531ZahTm7rOcO2t4at9kKh/fmb7mRaRyKAtcxLZRYM3idMXixZl6 rkhipQjMlgAGMpSw1b+BxtK20g== X-Google-Smtp-Source: ABdhPJwu1w8Ez8V1SSEP1iN9iT0vYNZi4Mw24O1Bs5AWrkAvlJWFDrzy8Pzs0mcDOxQoHdV1ODa9ww== X-Received: by 2002:a2e:bb93:: with SMTP id y19mr16468601lje.79.1630252080977; Sun, 29 Aug 2021 08:48:00 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id y5sm1481243ljd.38.2021.08.29.08.48.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Aug 2021 08:48:00 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Stephen Boyd , Taniya Das , Jonathan Marek , Michael Turquette Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, Bryan O'Donoghue , Mark Brown , Ulf Hansson , linux-kernel@vger.kernel.org, Rob Herring Subject: [PATCH v7 2/8] dt-bindings: clock: qcom,videocc: add mmcx power domain Date: Sun, 29 Aug 2021 18:47:51 +0300 Message-Id: <20210829154757.784699-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210829154757.784699-1-dmitry.baryshkov@linaro.org> References: <20210829154757.784699-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On sm8250 videocc requires MMCX power domain to be powered up before clock controller's registers become available. For now sm8250 was using external regulator driven by the power domain to describe this relationship. Switch into specifying power-domain and required opp-state directly. Signed-off-by: Dmitry Baryshkov Reviewed-by: Bjorn Andersson Reviewed-by: Rob Herring --- .../devicetree/bindings/clock/qcom,videocc.yaml | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml index 567202942b88..5d7053503435 100644 --- a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml @@ -47,6 +47,16 @@ properties: reg: maxItems: 1 + power-domains: + description: + A phandle and PM domain specifier for the MMCX power domain. + maxItems: 1 + + required-opps: + description: + A phandle to an OPP node describing required MMCX performance point. + maxItems: 1 + required: - compatible - reg @@ -61,6 +71,7 @@ additionalProperties: false examples: - | #include + #include clock-controller@ab00000 { compatible = "qcom,sdm845-videocc"; reg = <0x0ab00000 0x10000>; @@ -69,5 +80,7 @@ examples: #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; + power-domains = <&rpmhpd SM8250_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; }; ... From patchwork Sun Aug 29 15:47:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12464109 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 25044C25AEB for ; Sun, 29 Aug 2021 15:48:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0789460FC0 for ; Sun, 29 Aug 2021 15:48:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235694AbhH2Ps5 (ORCPT ); Sun, 29 Aug 2021 11:48:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53164 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235679AbhH2Psz (ORCPT ); Sun, 29 Aug 2021 11:48:55 -0400 Received: from mail-lj1-x22d.google.com (mail-lj1-x22d.google.com [IPv6:2a00:1450:4864:20::22d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 41ECEC06175F for ; Sun, 29 Aug 2021 08:48:03 -0700 (PDT) Received: by mail-lj1-x22d.google.com with SMTP id i28so21259923ljm.7 for ; Sun, 29 Aug 2021 08:48:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uAcFEY+E0qmgNU+cIgtsjckvcJT9e5o7gZcnimCS7qE=; b=txsSBxfFz3uME9EGWLKsPisD83NoqkW3PVZXnetyTCer1e+GSgMWMqq7SAD4ZUJa8I TvwG1N0kBLFhSg7gEzUYf+eieOVTCRzMza6Uje55n4Zilr76DyeS/doFV/8xEa4xBZWw v0tNqrwaCfRBsg+/e1rmKntNVjm0iZEvyunpzFyVvJTmq0zn9d8FHzZ/C4ZBbhjVjmV1 /Hr8hi8gVwPM32KXdYL4yDYTwsOOVpDpUANtgfh+GzYh50EllusbX+yCyi3dw7Vc3Vsp F8B+TB84Mx0ulR7Az3eKnBf4L5SDD9T1fbyg44b9XKV1ucec2bvPktai9NMl+EkCpDj7 nJrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uAcFEY+E0qmgNU+cIgtsjckvcJT9e5o7gZcnimCS7qE=; b=ONMEGBdHcV9pIDFFlpoPIovqFKbJPp9UbQ/QBrub6sF4u4hRjBhQgxXIlWTaQFsoh6 NN3bJ97amteAJIRWtVHaB9GqN1UlU1bOLADD3mvsAzm1pLNW9h4iVuM1G7ZOgwBZOXYI Bj9INowDbZ2ojGkXmgBGPvYcDY5yO2DCeeI8vn4vUIXVLH8deKb6rtS5qdEBbUA/DXtY Euc940qw/pksKFxBNoisQ9cVOUkMO2u3itwnmI6qzymkkEPjV2HZHiQ4HL6TwhrG6KOk Rp1SnR19Wz7hFLqKhKPDjHf/FrWSm3UCLPFbFXcaNsnwctDm583W9hsbS0fCwDaQH5a7 Ppyw== X-Gm-Message-State: AOAM532O1VpYDJaJGIWeWujRi4Ev3YUHBvT8H7QwymSIa4UtQXR8mhal mACMoFXAWtB2Ee3mjObsUAiSLA== X-Google-Smtp-Source: ABdhPJxh6ttGvJTuKrUIAct+s3sIoQe21OrLpijFoCP5JmFHSJh2yRJsONxu3oyPpABJLDKFO5PnMw== X-Received: by 2002:a2e:a785:: with SMTP id c5mr16291427ljf.434.1630252081609; Sun, 29 Aug 2021 08:48:01 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id y5sm1481243ljd.38.2021.08.29.08.48.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Aug 2021 08:48:01 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Stephen Boyd , Taniya Das , Jonathan Marek , Michael Turquette Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, Bryan O'Donoghue , Mark Brown , Ulf Hansson , linux-kernel@vger.kernel.org Subject: [PATCH v7 3/8] clk: qcom: dispcc-sm8250: use runtime PM for the clock controller Date: Sun, 29 Aug 2021 18:47:52 +0300 Message-Id: <20210829154757.784699-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210829154757.784699-1-dmitry.baryshkov@linaro.org> References: <20210829154757.784699-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On sm8250 dispcc and videocc registers are powered up by the MMCX power domain. Use runtime PM calls to make sure that required power domain is powered on while we access clock controller's registers. Signed-off-by: Dmitry Baryshkov Reviewed-by: Bjorn Andersson --- drivers/clk/qcom/dispcc-sm8250.c | 27 +++++++++++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c index 601c7c0ba483..108dd1249b6a 100644 --- a/drivers/clk/qcom/dispcc-sm8250.c +++ b/drivers/clk/qcom/dispcc-sm8250.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include @@ -1226,13 +1227,31 @@ static const struct of_device_id disp_cc_sm8250_match_table[] = { }; MODULE_DEVICE_TABLE(of, disp_cc_sm8250_match_table); +static void disp_cc_sm8250_pm_runtime_disable(void *data) +{ + pm_runtime_disable(data); +} + static int disp_cc_sm8250_probe(struct platform_device *pdev) { struct regmap *regmap; + int ret; + + pm_runtime_enable(&pdev->dev); + + ret = devm_add_action_or_reset(&pdev->dev, disp_cc_sm8250_pm_runtime_disable, &pdev->dev); + if (ret) + return ret; + + ret = pm_runtime_resume_and_get(&pdev->dev); + if (ret) + return ret; regmap = qcom_cc_map(pdev, &disp_cc_sm8250_desc); - if (IS_ERR(regmap)) + if (IS_ERR(regmap)) { + pm_runtime_put(&pdev->dev); return PTR_ERR(regmap); + } /* note: trion == lucid, except for the prepare() op */ BUILD_BUG_ON(CLK_ALPHA_PLL_TYPE_TRION != CLK_ALPHA_PLL_TYPE_LUCID); @@ -1257,7 +1276,11 @@ static int disp_cc_sm8250_probe(struct platform_device *pdev) /* DISP_CC_XO_CLK always-on */ regmap_update_bits(regmap, 0x605c, BIT(0), BIT(0)); - return qcom_cc_really_probe(pdev, &disp_cc_sm8250_desc, regmap); + ret = qcom_cc_really_probe(pdev, &disp_cc_sm8250_desc, regmap); + + pm_runtime_put(&pdev->dev); + + return ret; } static struct platform_driver disp_cc_sm8250_driver = { From patchwork Sun Aug 29 15:47:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12464113 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DBDE3C25AEE for ; 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Sun, 29 Aug 2021 08:48:02 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id y5sm1481243ljd.38.2021.08.29.08.48.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Aug 2021 08:48:02 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Stephen Boyd , Taniya Das , Jonathan Marek , Michael Turquette Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, Bryan O'Donoghue , Mark Brown , Ulf Hansson , linux-kernel@vger.kernel.org Subject: [PATCH v7 4/8] clk: qcom: videocc-sm8250: use runtime PM for the clock controller Date: Sun, 29 Aug 2021 18:47:53 +0300 Message-Id: <20210829154757.784699-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210829154757.784699-1-dmitry.baryshkov@linaro.org> References: <20210829154757.784699-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On sm8250 dispcc and videocc registers are powered up by the MMCX power domain. Use runtime PM calls to make sure that required power domain is powered on while we access clock controller's registers. Signed-off-by: Dmitry Baryshkov Reviewed-by: Bjorn Andersson --- drivers/clk/qcom/videocc-sm8250.c | 27 +++++++++++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/videocc-sm8250.c b/drivers/clk/qcom/videocc-sm8250.c index 7b435a1c2c4b..8617454e4a77 100644 --- a/drivers/clk/qcom/videocc-sm8250.c +++ b/drivers/clk/qcom/videocc-sm8250.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include @@ -364,13 +365,31 @@ static const struct of_device_id video_cc_sm8250_match_table[] = { }; MODULE_DEVICE_TABLE(of, video_cc_sm8250_match_table); +static void video_cc_sm8250_pm_runtime_disable(void *data) +{ + pm_runtime_disable(data); +} + static int video_cc_sm8250_probe(struct platform_device *pdev) { struct regmap *regmap; + int ret; + + pm_runtime_enable(&pdev->dev); + + ret = devm_add_action_or_reset(&pdev->dev, video_cc_sm8250_pm_runtime_disable, &pdev->dev); + if (ret) + return ret; + + ret = pm_runtime_resume_and_get(&pdev->dev); + if (ret) + return ret; regmap = qcom_cc_map(pdev, &video_cc_sm8250_desc); - if (IS_ERR(regmap)) + if (IS_ERR(regmap)) { + pm_runtime_put(&pdev->dev); return PTR_ERR(regmap); + } clk_lucid_pll_configure(&video_pll0, regmap, &video_pll0_config); clk_lucid_pll_configure(&video_pll1, regmap, &video_pll1_config); @@ -379,7 +398,11 @@ static int video_cc_sm8250_probe(struct platform_device *pdev) regmap_update_bits(regmap, 0xe58, BIT(0), BIT(0)); regmap_update_bits(regmap, 0xeec, BIT(0), BIT(0)); - return qcom_cc_really_probe(pdev, &video_cc_sm8250_desc, regmap); + ret = qcom_cc_really_probe(pdev, &video_cc_sm8250_desc, regmap); + + pm_runtime_put(&pdev->dev); + + return ret; } static struct platform_driver video_cc_sm8250_driver = { From patchwork Sun Aug 29 15:47:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12464115 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2648FC25AE9 for ; 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Sun, 29 Aug 2021 08:48:03 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id y5sm1481243ljd.38.2021.08.29.08.48.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Aug 2021 08:48:02 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Stephen Boyd , Taniya Das , Jonathan Marek , Michael Turquette Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, Bryan O'Donoghue , Mark Brown , Ulf Hansson , linux-kernel@vger.kernel.org Subject: [PATCH v7 5/8] clk: qcom: gdsc: enable optional power domain support Date: Sun, 29 Aug 2021 18:47:54 +0300 Message-Id: <20210829154757.784699-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210829154757.784699-1-dmitry.baryshkov@linaro.org> References: <20210829154757.784699-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On sm8250 dispcc and videocc registers are powered up by the MMCX power domain. Currently we use a regulator to enable this domain on demand, however this has some consequences, as genpd code is not reentrant. Make gdsc code also use pm_runtime calls to ensure that registers are accessible during the gdsc_enable/gdsc_disable operations. Signed-off-by: Dmitry Baryshkov Reviewed-by: Bjorn Andersson --- drivers/clk/qcom/gdsc.c | 51 ++++++++++++++++++++++++++++++++++++++--- drivers/clk/qcom/gdsc.h | 2 ++ 2 files changed, 50 insertions(+), 3 deletions(-) diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c index 4ece326ea233..7e1dd8ccfa38 100644 --- a/drivers/clk/qcom/gdsc.c +++ b/drivers/clk/qcom/gdsc.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -50,6 +51,22 @@ enum gdsc_status { GDSC_ON }; +static int gdsc_pm_runtime_get(struct gdsc *sc) +{ + if (!sc->dev) + return 0; + + return pm_runtime_resume_and_get(sc->dev); +} + +static int gdsc_pm_runtime_put(struct gdsc *sc) +{ + if (!sc->dev) + return 0; + + return pm_runtime_put_sync(sc->dev); +} + /* Returns 1 if GDSC status is status, 0 if not, and < 0 on error */ static int gdsc_check_status(struct gdsc *sc, enum gdsc_status status) { @@ -232,9 +249,8 @@ static void gdsc_retain_ff_on(struct gdsc *sc) regmap_update_bits(sc->regmap, sc->gdscr, mask, mask); } -static int gdsc_enable(struct generic_pm_domain *domain) +static int _gdsc_enable(struct gdsc *sc) { - struct gdsc *sc = domain_to_gdsc(domain); int ret; if (sc->pwrsts == PWRSTS_ON) @@ -290,11 +306,22 @@ static int gdsc_enable(struct generic_pm_domain *domain) return 0; } -static int gdsc_disable(struct generic_pm_domain *domain) +static int gdsc_enable(struct generic_pm_domain *domain) { struct gdsc *sc = domain_to_gdsc(domain); int ret; + ret = gdsc_pm_runtime_get(sc); + if (ret) + return ret; + + return _gdsc_enable(sc); +} + +static int _gdsc_disable(struct gdsc *sc) +{ + int ret; + if (sc->pwrsts == PWRSTS_ON) return gdsc_assert_reset(sc); @@ -329,6 +356,18 @@ static int gdsc_disable(struct generic_pm_domain *domain) return 0; } +static int gdsc_disable(struct generic_pm_domain *domain) +{ + struct gdsc *sc = domain_to_gdsc(domain); + int ret; + + ret = _gdsc_disable(sc); + + gdsc_pm_runtime_put(sc); + + return ret; +} + static int gdsc_init(struct gdsc *sc) { u32 mask, val; @@ -443,6 +482,8 @@ int gdsc_register(struct gdsc_desc *desc, for (i = 0; i < num; i++) { if (!scs[i]) continue; + if (pm_runtime_enabled(dev)) + scs[i]->dev = dev; scs[i]->regmap = regmap; scs[i]->rcdev = rcdev; ret = gdsc_init(scs[i]); @@ -457,6 +498,8 @@ int gdsc_register(struct gdsc_desc *desc, continue; if (scs[i]->parent) pm_genpd_add_subdomain(scs[i]->parent, &scs[i]->pd); + else if (!IS_ERR_OR_NULL(dev->pm_domain)) + pm_genpd_add_subdomain(pd_to_genpd(dev->pm_domain), &scs[i]->pd); } return of_genpd_add_provider_onecell(dev->of_node, data); @@ -475,6 +518,8 @@ void gdsc_unregister(struct gdsc_desc *desc) continue; if (scs[i]->parent) pm_genpd_remove_subdomain(scs[i]->parent, &scs[i]->pd); + else if (!IS_ERR_OR_NULL(dev->pm_domain)) + pm_genpd_remove_subdomain(pd_to_genpd(dev->pm_domain), &scs[i]->pd); } of_genpd_del_provider(dev->of_node); } diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h index 5bb396b344d1..702d47a87af6 100644 --- a/drivers/clk/qcom/gdsc.h +++ b/drivers/clk/qcom/gdsc.h @@ -25,6 +25,7 @@ struct reset_controller_dev; * @resets: ids of resets associated with this gdsc * @reset_count: number of @resets * @rcdev: reset controller + * @dev: the device holding the GDSC, used for pm_runtime calls */ struct gdsc { struct generic_pm_domain pd; @@ -58,6 +59,7 @@ struct gdsc { const char *supply; struct regulator *rsupply; + struct device *dev; }; struct gdsc_desc { From patchwork Sun Aug 29 15:47:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12464117 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 356B5C43214 for ; Sun, 29 Aug 2021 15:48:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1B4C760F8F for ; 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Sun, 29 Aug 2021 08:48:03 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Stephen Boyd , Taniya Das , Jonathan Marek , Michael Turquette Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, Bryan O'Donoghue , Mark Brown , Ulf Hansson , linux-kernel@vger.kernel.org Subject: [PATCH v7 6/8] arm64: dts: qcom: sm8250: remove mmcx regulator Date: Sun, 29 Aug 2021 18:47:55 +0300 Message-Id: <20210829154757.784699-7-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210829154757.784699-1-dmitry.baryshkov@linaro.org> References: <20210829154757.784699-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Switch dispcc and videocc into using MMCX domain directly. Drop the now unused mmcx regulator. Signed-off-by: Dmitry Baryshkov Reviewed-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 4798368b02ef..0d35449fda02 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -273,13 +273,6 @@ memory@80000000 { reg = <0x0 0x80000000 0x0 0x0>; }; - mmcx_reg: mmcx-reg { - compatible = "regulator-fixed-domain"; - power-domains = <&rpmhpd SM8250_MMCX>; - required-opps = <&rpmhpd_opp_low_svs>; - regulator-name = "MMCX"; - }; - pmu { compatible = "arm,armv8-pmuv3"; interrupts = ; @@ -2451,7 +2444,8 @@ videocc: clock-controller@abf0000 { clocks = <&gcc GCC_VIDEO_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>; - mmcx-supply = <&mmcx_reg>; + power-domains = <&rpmhpd SM8250_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; clock-names = "iface", "bi_tcxo", "bi_tcxo_ao"; #clock-cells = <1>; #reset-cells = <1>; @@ -2720,7 +2714,8 @@ opp-358000000 { dispcc: clock-controller@af00000 { compatible = "qcom,sm8250-dispcc"; reg = <0 0x0af00000 0 0x10000>; - mmcx-supply = <&mmcx_reg>; + power-domains = <&rpmhpd SM8250_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&dsi0_phy 0>, <&dsi0_phy 1>, From patchwork Sun Aug 29 15:47:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12464119 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 775AEC43214 for ; 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Sun, 29 Aug 2021 08:48:04 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id y5sm1481243ljd.38.2021.08.29.08.48.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Aug 2021 08:48:04 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Stephen Boyd , Taniya Das , Jonathan Marek , Michael Turquette Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, Bryan O'Donoghue , Mark Brown , Ulf Hansson , linux-kernel@vger.kernel.org Subject: [PATCH v7 7/8] clk: qcom: dispcc-sm8250: stop using mmcx regulator Date: Sun, 29 Aug 2021 18:47:56 +0300 Message-Id: <20210829154757.784699-8-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210829154757.784699-1-dmitry.baryshkov@linaro.org> References: <20210829154757.784699-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Now as the common qcom clock controller code has been taught about power domains, stop mentioning mmcx supply as a way to power up the clock controller's gdsc. Signed-off-by: Dmitry Baryshkov Reviewed-by: Bjorn Andersson --- drivers/clk/qcom/dispcc-sm8250.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c index 108dd1249b6a..cf0bb12eb6e1 100644 --- a/drivers/clk/qcom/dispcc-sm8250.c +++ b/drivers/clk/qcom/dispcc-sm8250.c @@ -1129,7 +1129,6 @@ static struct gdsc mdss_gdsc = { }, .pwrsts = PWRSTS_OFF_ON, .flags = HW_CTRL, - .supply = "mmcx", }; static struct clk_regmap *disp_cc_sm8250_clocks[] = { From patchwork Sun Aug 29 15:47:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12464121 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D4110C00143 for ; Sun, 29 Aug 2021 15:48:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C08A861073 for ; Sun, 29 Aug 2021 15:48:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235777AbhH2PtG (ORCPT ); Sun, 29 Aug 2021 11:49:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53226 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235710AbhH2PtD (ORCPT ); Sun, 29 Aug 2021 11:49:03 -0400 Received: from mail-lj1-x22b.google.com (mail-lj1-x22b.google.com [IPv6:2a00:1450:4864:20::22b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 59A0CC061796 for ; Sun, 29 Aug 2021 08:48:07 -0700 (PDT) Received: by mail-lj1-x22b.google.com with SMTP id q21so21226742ljj.6 for ; Sun, 29 Aug 2021 08:48:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4wYSAh/xvV+vEiBG5k8GPtuGmF+0aSivWDvc36iPGZQ=; b=oFewvCdk4g9bOv+QIjNC4zmNCCVpJ4x6cB+yCEq8i+MCSbhoAxNogz25a12Fa2ern7 vSmqyT1gBDB8GsA1RXGMnoRls+STihl6OB+WdLz3pPPWXqvE02fx29faNqHZOAtRaihG aBzsLXRbMY+MKe1b7JYbV9xQF5V6xZPcTPLtpOjC263R9wFwAX9ZLl+iG3eemjAkGeS8 fm5qziQqNdfLWxMMihIO1uxn2q8zcXRy+aPkUkKSfHyTZUHIt+L2UOMA0v0qZVPLSkQI nq3KCRtTjwKfw3PiNR8gDEPbnOMbSMnhsvsM4Pk4ctsiidrjjgjdiW/9/kzeyXOOWiE3 naqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4wYSAh/xvV+vEiBG5k8GPtuGmF+0aSivWDvc36iPGZQ=; b=bGVJwFVrb5PF5VE6VW7KxtXzS9vhSU4qoMpPHLfz8P6SHaPDiZ1WsHX21t/2PKVM+o S/VsOjDADkZcZVN3JXF39uQpYLjEZDSba4pqehaka6IdnC0u027KjeoFLzcGdTjzK/qc aYavRSQdjpb/5JlSfIPFJNnHGn91kc3MOqmlSYxa+dL4rh2eeNND+H0btR2KsattKbWO S/Ms8OpoEVhVm32LgawSfcyNxFzPrdmitimC1N+9kcDdqi49KdC2VUzqKh1yMWd3e/A0 6x7FXAD0sUQBSpeexNb4UzFDJt7YYMrcVBaBFyxl/qMy2cc7JNHP6Q9zZvCIS/OWHGAj HHSw== X-Gm-Message-State: AOAM532OU41pKez8d/e5C9HLql2l7c+GXe8iKNFDJdHZRstsJLlX1DNl oyIpsbiojfsXHUShOrJrFuyQ5w== X-Google-Smtp-Source: ABdhPJxL8R3J3cKmcpKHszSldYyRqXI7vwDa9xFMUFMmsis2+4cgSK1YMVCfeLbNvBbhX3+2FDYC2Q== X-Received: by 2002:a05:651c:2c6:: with SMTP id f6mr16922455ljo.7.1630252085602; Sun, 29 Aug 2021 08:48:05 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id y5sm1481243ljd.38.2021.08.29.08.48.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Aug 2021 08:48:05 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Stephen Boyd , Taniya Das , Jonathan Marek , Michael Turquette Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, Bryan O'Donoghue , Mark Brown , Ulf Hansson , linux-kernel@vger.kernel.org Subject: [PATCH v7 8/8] clk: qcom: videocc-sm8250: stop using mmcx regulator Date: Sun, 29 Aug 2021 18:47:57 +0300 Message-Id: <20210829154757.784699-9-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210829154757.784699-1-dmitry.baryshkov@linaro.org> References: <20210829154757.784699-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Now as the common qcom clock controller code has been taught about power domains, stop mentioning mmcx supply as a way to power up the clock controller's gdscs. Signed-off-by: Dmitry Baryshkov Reviewed-by: Bjorn Andersson --- drivers/clk/qcom/videocc-sm8250.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/clk/qcom/videocc-sm8250.c b/drivers/clk/qcom/videocc-sm8250.c index 8617454e4a77..f28f2cb051d7 100644 --- a/drivers/clk/qcom/videocc-sm8250.c +++ b/drivers/clk/qcom/videocc-sm8250.c @@ -277,7 +277,6 @@ static struct gdsc mvs0c_gdsc = { }, .flags = 0, .pwrsts = PWRSTS_OFF_ON, - .supply = "mmcx", }; static struct gdsc mvs1c_gdsc = { @@ -287,7 +286,6 @@ static struct gdsc mvs1c_gdsc = { }, .flags = 0, .pwrsts = PWRSTS_OFF_ON, - .supply = "mmcx", }; static struct gdsc mvs0_gdsc = { @@ -297,7 +295,6 @@ static struct gdsc mvs0_gdsc = { }, .flags = HW_CTRL, .pwrsts = PWRSTS_OFF_ON, - .supply = "mmcx", }; static struct gdsc mvs1_gdsc = { @@ -307,7 +304,6 @@ static struct gdsc mvs1_gdsc = { }, .flags = HW_CTRL, .pwrsts = PWRSTS_OFF_ON, - .supply = "mmcx", }; static struct clk_regmap *video_cc_sm8250_clocks[] = {