From patchwork Mon Aug 30 16:22:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Siddiqui, Ayaz A" X-Patchwork-Id: 12465533 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5B40BC432BE for ; Mon, 30 Aug 2021 16:26:03 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 26B2F60ED6 for ; Mon, 30 Aug 2021 16:26:03 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 26B2F60ED6 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9B67A89CA0; Mon, 30 Aug 2021 16:26:02 +0000 (UTC) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0FCDC89CA0 for ; Mon, 30 Aug 2021 16:25:58 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10092"; a="279318021" X-IronPort-AV: E=Sophos;i="5.84,363,1620716400"; d="scan'208";a="279318021" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Aug 2021 09:25:58 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.84,363,1620716400"; d="scan'208";a="497802507" Received: from ayazahma-nuc8i7beh.iind.intel.com ([10.145.162.59]) by fmsmga008.fm.intel.com with ESMTP; 30 Aug 2021 09:25:57 -0700 From: Ayaz A Siddiqui To: intel-gfx@lists.freedesktop.org Cc: Ayaz A Siddiqui , CQ Tang Date: Mon, 30 Aug 2021 21:52:33 +0530 Message-Id: <20210830162240.3891502-2-ayaz.siddiqui@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210830162240.3891502-1-ayaz.siddiqui@intel.com> References: <20210830162240.3891502-1-ayaz.siddiqui@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH V3 1/8] drm/i915/gt: Add support of mocs propagation X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Now there are lots of Command and registers that require mocs index programming. So propagating mocs_index from mocs to gt so that it can be used directly without having platform-specific checks. Cc: CQ Tang Signed-off-by: Ayaz A Siddiqui Reviewed-by: Matt Roper --- drivers/gpu/drm/i915/gt/intel_gt_types.h | 4 ++++ drivers/gpu/drm/i915/gt/intel_mocs.c | 10 ++++++++++ 2 files changed, 14 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h index a81e21bf1bd1a..88601a2d2c229 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h @@ -192,6 +192,10 @@ struct intel_gt { unsigned long mslice_mask; } info; + + struct i915_mocs_index_gt { + u8 uc_index; + } mocs; }; enum intel_gt_scratch_field { diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c index 582c4423b95d6..10cc508c1a4f6 100644 --- a/drivers/gpu/drm/i915/gt/intel_mocs.c +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c @@ -22,6 +22,7 @@ struct drm_i915_mocs_table { unsigned int size; unsigned int n_entries; const struct drm_i915_mocs_entry *table; + u8 uc_index; }; /* Defines for the tables (XXX_MOCS_0 - XXX_MOCS_63) */ @@ -340,6 +341,8 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915, { unsigned int flags; + memset(table, 0, sizeof(struct drm_i915_mocs_table)); + if (IS_DG1(i915)) { table->size = ARRAY_SIZE(dg1_mocs_table); table->table = dg1_mocs_table; @@ -504,6 +507,12 @@ static u32 global_mocs_offset(void) return i915_mmio_reg_offset(GEN12_GLOBAL_MOCS(0)); } +static void set_mocs_index(struct intel_gt *gt, + struct drm_i915_mocs_table *table) +{ + gt->mocs.uc_index = table->uc_index; +} + void intel_mocs_init(struct intel_gt *gt) { struct drm_i915_mocs_table table; @@ -515,6 +524,7 @@ void intel_mocs_init(struct intel_gt *gt) flags = get_mocs_settings(gt->i915, &table); if (flags & HAS_GLOBAL_MOCS) __init_mocs_table(gt->uncore, &table, global_mocs_offset()); + set_mocs_index(gt, &table); } #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) From patchwork Mon Aug 30 16:22:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Siddiqui, Ayaz A" X-Patchwork-Id: 12465535 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BCC5DC432BE for ; Mon, 30 Aug 2021 16:26:06 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 85C0460ED6 for ; Mon, 30 Aug 2021 16:26:06 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 85C0460ED6 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0C18F89CAC; Mon, 30 Aug 2021 16:26:06 +0000 (UTC) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id E75B889CA2 for ; Mon, 30 Aug 2021 16:26:02 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10092"; a="279318032" X-IronPort-AV: E=Sophos;i="5.84,363,1620716400"; d="scan'208";a="279318032" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Aug 2021 09:26:02 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.84,363,1620716400"; d="scan'208";a="497802517" Received: from ayazahma-nuc8i7beh.iind.intel.com ([10.145.162.59]) by fmsmga008.fm.intel.com with ESMTP; 30 Aug 2021 09:25:58 -0700 From: Ayaz A Siddiqui To: intel-gfx@lists.freedesktop.org Cc: Srinivasan Shanmugam , Chris Wilson , Matt Roper , Ayaz A Siddiqui Date: Mon, 30 Aug 2021 21:52:34 +0530 Message-Id: <20210830162240.3891502-3-ayaz.siddiqui@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210830162240.3891502-1-ayaz.siddiqui@intel.com> References: <20210830162240.3891502-1-ayaz.siddiqui@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH V3 2/8] drm/i915/gt: Add support of mocs auxiliary registers programming X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Srinivasan Shanmugam Few registers need to be programmed with appropriate MOCS indexes for proper functioning. As of now, there are two categories of registers that need to be programmed, these are engine power domains register and engine state context register. A framework is being added to handle programming and verification of those registers. To add a register in the future we just need to add it in build_aux_regs(), the rest will be taken care of by the framework. V2: (Ayaz) Added CMD_CCTL in guc_mmio_regset_init(), so that this register can restored after engine reset. V3: (Ayaz) 1. Changed implementation to have a framework only. 2. Added register type for proper application. 3. Removed CMD_CCTL programming. Cc: Chris Wilson Cc: Matt Roper Signed-off-by: Srinivasan Shanmugam Signed-off-by: Ayaz A Siddiqui Reported-by: kernel test robot Reported-by: kernel test robot Reported-by: kernel test robot Reported-by: kernel test robot Reported-by: kernel test robot --- drivers/gpu/drm/i915/gt/intel_gt.c | 5 + drivers/gpu/drm/i915/gt/intel_mocs.c | 184 +++++++++++++++++++++ drivers/gpu/drm/i915/gt/intel_mocs.h | 5 + drivers/gpu/drm/i915/gt/selftest_mocs.c | 49 ++++++ drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 17 +- drivers/gpu/drm/i915/gt/uc/intel_guc_ads.h | 15 ++ 6 files changed, 263 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index 62d40c9866427..ccb257d5282f4 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -21,6 +21,7 @@ #include "intel_uncore.h" #include "intel_pm.h" #include "shmem_utils.h" +#include "intel_mocs.h" void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915) { @@ -530,6 +531,10 @@ static int __engines_record_defaults(struct intel_gt *gt) if (err) goto err_rq; + err = apply_mocs_aux_regs_ctx(rq); + if (err) + goto err_rq; + err = intel_renderstate_emit(&so, rq); if (err) goto err_rq; diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c index 10cc508c1a4f6..c52640523c218 100644 --- a/drivers/gpu/drm/i915/gt/intel_mocs.c +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c @@ -10,6 +10,8 @@ #include "intel_lrc_reg.h" #include "intel_mocs.h" #include "intel_ring.h" +#include "intel_gpu_commands.h" +#include "uc/intel_guc_ads.h" /* structures required */ struct drm_i915_mocs_entry { @@ -25,6 +27,28 @@ struct drm_i915_mocs_table { u8 uc_index; }; +enum register_type { + /* + * REG_GT: General register - Need to be re-plied after GT/GPU reset + * REG_ENGINE: Domain register - needs to be re-applied after + * engine reset + * REG_ENGINE_CONTEXT: Engine state context register - need to stored + * as part of Golden context. + */ + REG_GT = 0, + REG_ENGINE, + REG_ENGINE_CONTEXT +}; + +struct drm_i915_aux_table { + enum register_type type; + const char *name; + i915_reg_t offset; + u32 value; + u32 readmask; + struct drm_i915_aux_table *next; +}; + /* Defines for the tables (XXX_MOCS_0 - XXX_MOCS_63) */ #define _LE_CACHEABILITY(value) ((value) << 0) #define _LE_TGT_CACHE(value) ((value) << 2) @@ -336,6 +360,78 @@ static bool has_mocs(const struct drm_i915_private *i915) return !IS_DGFX(i915); } +static struct drm_i915_aux_table * +add_aux_reg(struct drm_i915_aux_table *aux, + enum register_type type, + const char *name, + i915_reg_t offset, + u32 value, + u32 read) +{ + struct drm_i915_aux_table *x; + + x = kmalloc(sizeof(*x), GFP_ATOMIC); + if (!x) { + DRM_ERROR("Failed to allocate aux reg '%s'\n", name); + return aux; + } + + x->type = type; + x->name = name; + x->offset = offset; + x->value = value; + x->readmask = read; + + x->next = aux; + return x; +} + +static const struct drm_i915_aux_table * +build_aux_regs(const struct intel_engine_cs *engine, + const struct drm_i915_mocs_table *mocs) +{ + struct drm_i915_aux_table *aux = NULL; + + if (GRAPHICS_VER(engine->i915) >= 12 && + !drm_WARN_ONCE(&engine->i915->drm, !mocs->uc_index, + "Platform that should have UC index defined and does not\n")) { + /* + * Add Auxiliary register which needs to be programmed with + * UC MOCS index. We need to call add_aux_reg() to add + * a entry in drm_i915_aux_table link list. + */ + } + return aux; +} + +static void +free_aux_regs(const struct drm_i915_aux_table *aux) +{ + while (aux) { + struct drm_i915_aux_table *next = aux->next; + + kfree(aux); + aux = next; + } +} + +static void apply_aux_regs_engine(struct intel_engine_cs *engine, + const struct drm_i915_aux_table *aux) +{ + u32 mmio_reg_offset; + + while (aux) { + if (aux->type == REG_ENGINE) { + mmio_reg_offset = i915_mmio_reg_offset(aux->offset); + intel_uncore_write_fw(engine->uncore, + _MMIO(engine->mmio_base + + mmio_reg_offset), + aux->value); + } + aux = aux->next; + } +} + static unsigned int get_mocs_settings(const struct drm_i915_private *i915, struct drm_i915_mocs_table *table) { @@ -347,10 +443,12 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915, table->size = ARRAY_SIZE(dg1_mocs_table); table->table = dg1_mocs_table; table->n_entries = GEN9_NUM_MOCS_ENTRIES; + table->uc_index = 1; } else if (GRAPHICS_VER(i915) >= 12) { table->size = ARRAY_SIZE(tgl_mocs_table); table->table = tgl_mocs_table; table->n_entries = GEN9_NUM_MOCS_ENTRIES; + table->uc_index = 3; } else if (GRAPHICS_VER(i915) == 11) { table->size = ARRAY_SIZE(icl_mocs_table); table->table = icl_mocs_table; @@ -395,6 +493,87 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915, return flags; } +int get_ctx_reg_count(const struct drm_i915_aux_table *aux) +{ + int count = 0; + + while (aux) { + if (aux->type == REG_ENGINE_CONTEXT) + count++; + aux = aux->next; + } + return count; +} + +void add_aux_mocs_guc_mmio_regset(struct temp_regset *regset, + struct intel_engine_cs *engine) +{ + const struct drm_i915_aux_table *aux; + struct drm_i915_mocs_table table; + int ret; + + ret = get_mocs_settings(engine->i915, &table); + if (!ret) + return; + + aux = build_aux_regs(engine, &table); + if (!aux) + return; + + while (aux) { + if (aux->type == REG_ENGINE) + GUC_MMIO_REG_ADD(regset, + _MMIO(engine->mmio_base + + i915_mmio_reg_offset(aux->offset)), + true); + aux = aux->next; + } + free_aux_regs(aux); +} + +int apply_mocs_aux_regs_ctx(struct i915_request *rq) +{ + const struct drm_i915_aux_table *aux; + struct drm_i915_mocs_table table; + u32 *cs; + int ret, count; + + ret = get_mocs_settings(rq->engine->i915, &table); + if (!ret) + return 0; + + aux = build_aux_regs(rq->engine, &table); + + count = get_ctx_reg_count(aux); + if (!count) + return 0; + ret = rq->engine->emit_flush(rq, EMIT_BARRIER); + if (ret) + return ret; + + cs = intel_ring_begin(rq, (count * 2 + 2)); + if (IS_ERR(cs)) + return PTR_ERR(cs); + + *cs++ = MI_LOAD_REGISTER_IMM(count); + while (aux) { + if (aux->type == REG_ENGINE_CONTEXT) { + *cs++ = i915_mmio_reg_offset(aux->offset); + *cs++ = aux->value; + } + aux = aux->next; + } + *cs++ = MI_NOOP; + + intel_ring_advance(rq, cs); + free_aux_regs(aux); + ret = rq->engine->emit_flush(rq, EMIT_BARRIER); + if (ret) + return ret; + + return 0; +} + /* * Get control_value from MOCS entry taking into account when it's not used: * I915_MOCS_PTE's value is returned in this case. @@ -484,6 +663,7 @@ static void init_l3cc_table(struct intel_engine_cs *engine, void intel_mocs_init_engine(struct intel_engine_cs *engine) { + const struct drm_i915_aux_table *aux; struct drm_i915_mocs_table table; unsigned int flags; @@ -500,6 +680,10 @@ void intel_mocs_init_engine(struct intel_engine_cs *engine) if (flags & HAS_RENDER_L3CC && engine->class == RENDER_CLASS) init_l3cc_table(engine, &table); + + aux = build_aux_regs(engine, &table); + apply_aux_regs_engine(engine, aux); + free_aux_regs(aux); } static u32 global_mocs_offset(void) diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.h b/drivers/gpu/drm/i915/gt/intel_mocs.h index d83274f5163bd..0f362a0acc3a3 100644 --- a/drivers/gpu/drm/i915/gt/intel_mocs.h +++ b/drivers/gpu/drm/i915/gt/intel_mocs.h @@ -33,8 +33,13 @@ struct intel_engine_cs; struct intel_gt; +struct i915_request; +struct temp_regset; void intel_mocs_init(struct intel_gt *gt); void intel_mocs_init_engine(struct intel_engine_cs *engine); +int apply_mocs_aux_regs_ctx(struct i915_request *rq); +void add_aux_mocs_guc_mmio_regset(struct temp_regset *regset, + struct intel_engine_cs *engine); #endif diff --git a/drivers/gpu/drm/i915/gt/selftest_mocs.c b/drivers/gpu/drm/i915/gt/selftest_mocs.c index 13d25bf2a94aa..2b0207dfbf21c 100644 --- a/drivers/gpu/drm/i915/gt/selftest_mocs.c +++ b/drivers/gpu/drm/i915/gt/selftest_mocs.c @@ -155,6 +155,47 @@ static int read_l3cc_table(struct i915_request *rq, return read_regs(rq, addr, (table->n_entries + 1) / 2, offset); } +static int read_aux_regs(struct i915_request *rq, + const struct drm_i915_aux_table *r, + u32 *offset) +{ + int err; + + while (r) { + err = read_regs(rq, + rq->engine->mmio_base + i915_mmio_reg_offset(r->offset), 1, + offset); + if (err) + return err; + + r = r->next; + } + + return 0; +} + +static int check_aux_regs(struct intel_engine_cs *engine, + const struct drm_i915_aux_table *r, + u32 **vaddr) +{ + while (r) { + u32 expect = r->value & r->readmask; + u32 masked_value = **vaddr & r->readmask; + + if (masked_value != expect) { + pr_err("%s: Invalid entry %s[%x]=0x%x, relevant bits were 0x%x vs expected 0x%x\n", + engine->name, r->name, + i915_mmio_reg_offset(r->offset), **vaddr, + masked_value, expect); + return -EINVAL; + } + ++*vaddr; + r = r->next; + } + + return 0; +} + static int check_mocs_table(struct intel_engine_cs *engine, const struct drm_i915_mocs_table *table, u32 **vaddr) @@ -216,6 +257,7 @@ static int check_mocs_engine(struct live_mocs *arg, struct intel_context *ce) { struct i915_vma *vma = arg->scratch; + const struct drm_i915_aux_table *aux; struct i915_request *rq; u32 offset; u32 *vaddr; @@ -223,6 +265,8 @@ static int check_mocs_engine(struct live_mocs *arg, memset32(arg->vaddr, STACK_MAGIC, PAGE_SIZE / sizeof(u32)); + aux = build_aux_regs(ce->engine, &arg->table); + rq = intel_context_create_request(ce); if (IS_ERR(rq)) return PTR_ERR(rq); @@ -239,6 +283,8 @@ static int check_mocs_engine(struct live_mocs *arg, err = read_mocs_table(rq, arg->mocs, &offset); if (!err && ce->engine->class == RENDER_CLASS) err = read_l3cc_table(rq, arg->l3cc, &offset); + if (!err) + err = read_aux_regs(rq, aux, &offset); offset -= i915_ggtt_offset(vma); GEM_BUG_ON(offset > PAGE_SIZE); @@ -252,10 +298,13 @@ static int check_mocs_engine(struct live_mocs *arg, err = check_mocs_table(ce->engine, arg->mocs, &vaddr); if (!err && ce->engine->class == RENDER_CLASS) err = check_l3cc_table(ce->engine, arg->l3cc, &vaddr); + if (!err) + err = check_aux_regs(ce->engine, aux, &vaddr); if (err) return err; GEM_BUG_ON(arg->vaddr + offset != vaddr); + free_aux_regs(aux); return 0; } diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c index 6926919bcac6b..be4cca49abced 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c @@ -12,6 +12,7 @@ #include "intel_guc_fwif.h" #include "intel_uc.h" #include "i915_drv.h" +#include "gt/intel_mocs.h" /* * The Additional Data Struct (ADS) has pointers for different buffers used by @@ -187,11 +188,6 @@ static void guc_mapping_table_init(struct intel_gt *gt, * inside the ADS. */ #define MAX_MMIO_REGS 128 /* Arbitrary size, increase as needed */ -struct temp_regset { - struct guc_mmio_reg *registers; - u32 used; - u32 size; -}; static int guc_mmio_reg_cmp(const void *a, const void *b) { @@ -201,8 +197,8 @@ static int guc_mmio_reg_cmp(const void *a, const void *b) return (int)ra->offset - (int)rb->offset; } -static void guc_mmio_reg_add(struct temp_regset *regset, - u32 offset, u32 flags) +void guc_mmio_reg_add(struct temp_regset *regset, + u32 offset, u32 flags) { u32 count = regset->used; struct guc_mmio_reg reg = { @@ -236,11 +232,6 @@ static void guc_mmio_reg_add(struct temp_regset *regset, } } -#define GUC_MMIO_REG_ADD(regset, reg, masked) \ - guc_mmio_reg_add(regset, \ - i915_mmio_reg_offset((reg)), \ - (masked) ? GUC_REGSET_MASKED : 0) - static void guc_mmio_regset_init(struct temp_regset *regset, struct intel_engine_cs *engine) { @@ -258,6 +249,8 @@ static void guc_mmio_regset_init(struct temp_regset *regset, for (i = 0, wa = wal->list; i < wal->count; i++, wa++) GUC_MMIO_REG_ADD(regset, wa->reg, wa->masked_reg); + add_aux_mocs_guc_mmio_regset(regset, engine); + /* Be extra paranoid and include all whitelist registers. */ for (i = 0; i < RING_MAX_NONPRIV_SLOTS; i++) GUC_MMIO_REG_ADD(regset, diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.h index 3d85051d57e45..75736c56fa187 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.h @@ -6,9 +6,24 @@ #ifndef _INTEL_GUC_ADS_H_ #define _INTEL_GUC_ADS_H_ +#include + +struct temp_regset { + struct guc_mmio_reg *registers; + u32 used; + u32 size; +}; + struct intel_guc; struct drm_printer; +void guc_mmio_reg_add(struct temp_regset *regset, + u32 offset, u32 flags); +#define GUC_MMIO_REG_ADD(regset, reg, masked) \ + guc_mmio_reg_add(regset, \ + i915_mmio_reg_offset((reg)), \ + (masked) ? GUC_REGSET_MASKED : 0) + int intel_guc_ads_create(struct intel_guc *guc); void intel_guc_ads_destroy(struct intel_guc *guc); void intel_guc_ads_init_late(struct intel_guc *guc); From patchwork Mon Aug 30 16:22:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Siddiqui, Ayaz A" X-Patchwork-Id: 12465537 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 48E26C4320A for ; Mon, 30 Aug 2021 16:26:07 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1B90E60ED6 for ; Mon, 30 Aug 2021 16:26:07 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 1B90E60ED6 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 36EB789CA2; Mon, 30 Aug 2021 16:26:06 +0000 (UTC) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id D100B89CA2 for ; Mon, 30 Aug 2021 16:26:03 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10092"; a="279318036" X-IronPort-AV: E=Sophos;i="5.84,363,1620716400"; d="scan'208";a="279318036" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Aug 2021 09:26:03 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.84,363,1620716400"; d="scan'208";a="497802540" Received: from ayazahma-nuc8i7beh.iind.intel.com ([10.145.162.59]) by fmsmga008.fm.intel.com with ESMTP; 30 Aug 2021 09:26:02 -0700 From: Ayaz A Siddiqui To: intel-gfx@lists.freedesktop.org Cc: Ayaz A Siddiqui , Matt Roper Date: Mon, 30 Aug 2021 21:52:35 +0530 Message-Id: <20210830162240.3891502-4-ayaz.siddiqui@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210830162240.3891502-1-ayaz.siddiqui@intel.com> References: <20210830162240.3891502-1-ayaz.siddiqui@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH V3 3/8] drm/i915/gt: Set CMD_CCTL to UC for Gen12 Onward X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Cache-control registers for Command Stream(CMD_CCTL) are used to set catchability for memory writes and reads outputted by Command Streamers on Gen12 onward platforms. These registers need to point un-cached(UC) MOCS index. Cc: Matt Roper Signed-off-by: Ayaz A Siddiqui --- drivers/gpu/drm/i915/gt/intel_mocs.c | 12 ++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 16 ++++++++++++++++ 2 files changed, 28 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c index c52640523c218..403bd48362b19 100644 --- a/drivers/gpu/drm/i915/gt/intel_mocs.c +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c @@ -386,6 +386,17 @@ add_aux_reg(struct drm_i915_aux_table *aux, return x; } +static struct drm_i915_aux_table * +add_cmd_cctl_override(struct drm_i915_aux_table *aux, u8 idx) +{ + return add_aux_reg(aux, + REG_ENGINE, + "CMD_CCTL", + RING_CMD_CCTL(0), + CMD_CCTL_MOCS_OVERRIDE(idx, idx), + CMD_CCTL_WRITE_OVERRIDE_MASK | CMD_CCTL_READ_OVERRIDE_MASK); +} + static const struct drm_i915_aux_table * build_aux_regs(const struct intel_engine_cs *engine, const struct drm_i915_mocs_table *mocs) @@ -400,6 +411,7 @@ build_aux_regs(const struct intel_engine_cs *engine, * UC MOCS index. We need to call add_aux_reg() to add * a entry in drm_i915_aux_table link list. */ + aux = add_cmd_cctl_override(aux, mocs->uc_index); } return aux; } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 8d4cf1e203ab7..df7a4550fb50f 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2551,6 +2551,22 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define RING_HWS_PGA(base) _MMIO((base) + 0x80) #define RING_ID(base) _MMIO((base) + 0x8c) #define RING_HWS_PGA_GEN6(base) _MMIO((base) + 0x2080) + +#define RING_CMD_CCTL(base) _MMIO((base) + 0xc4) +/* + * CMD_CCTL read/write fields take a MOCS value and _not_ a table index. + * The lsb of each can be considered a separate enabling bit for encryption. + * 6:0 == default MOCS value for reads => 6:1 == table index for reads. + * 13:7 == default MOCS value for writes => 13:8 == table index for writes. + * 15:14 == Reserved => 31:30 are set to 0. + */ +#define CMD_CCTL_WRITE_OVERRIDE_MASK REG_GENMASK(13, 7) +#define CMD_CCTL_READ_OVERRIDE_MASK REG_GENMASK(6, 0) +#define CMD_CCTL_MOCS_OVERRIDE(write, read) \ + _MASKED_FIELD(CMD_CCTL_WRITE_OVERRIDE_MASK | CMD_CCTL_READ_OVERRIDE_MASK, \ + REG_FIELD_PREP(CMD_CCTL_WRITE_OVERRIDE_MASK, (write) << 1) | \ + REG_FIELD_PREP(CMD_CCTL_READ_OVERRIDE_MASK, (read) << 1)) + #define RING_RESET_CTL(base) _MMIO((base) + 0xd0) #define RESET_CTL_CAT_ERROR REG_BIT(2) #define RESET_CTL_READY_TO_RESET REG_BIT(1) From patchwork Mon Aug 30 16:22:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Siddiqui, Ayaz A" X-Patchwork-Id: 12465545 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 54E5AC4320E for ; Mon, 30 Aug 2021 16:26:18 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 23A9460ED6 for ; Mon, 30 Aug 2021 16:26:18 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 23A9460ED6 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7955C89B3C; Mon, 30 Aug 2021 16:26:17 +0000 (UTC) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id BD94B89CAC for ; Mon, 30 Aug 2021 16:26:05 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10092"; a="279318042" X-IronPort-AV: E=Sophos;i="5.84,363,1620716400"; d="scan'208";a="279318042" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Aug 2021 09:26:05 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.84,363,1620716400"; d="scan'208";a="497802548" Received: from ayazahma-nuc8i7beh.iind.intel.com ([10.145.162.59]) by fmsmga008.fm.intel.com with ESMTP; 30 Aug 2021 09:26:03 -0700 From: Ayaz A Siddiqui To: intel-gfx@lists.freedesktop.org Cc: Apoorva Singh , Ayaz A Siddiqui Date: Mon, 30 Aug 2021 21:52:36 +0530 Message-Id: <20210830162240.3891502-5-ayaz.siddiqui@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210830162240.3891502-1-ayaz.siddiqui@intel.com> References: <20210830162240.3891502-1-ayaz.siddiqui@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH V3 4/8] drm/i915/gt: Set BLIT_CCTL reg to un-cached X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Apoorva Singh Blitter commands which do not have MOCS fields rely on cacheability of BlitterCacheControlRegister which was mapped to index 0 by default.Once we changed the MOCS value of index 0 to L3 WB, tests like gem_linear_blits started failing due to a change in cacheability from UC to WB. Program and place the BlitterCacheControlRegister in build_aux_regs(). Signed-off-by: Apoorva Singh Signed-off-by: Ayaz A Siddiqui --- drivers/gpu/drm/i915/gt/intel_mocs.c | 13 +++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 7 +++++++ 2 files changed, 20 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c index 403bd48362b19..82eafa8d22453 100644 --- a/drivers/gpu/drm/i915/gt/intel_mocs.c +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c @@ -386,6 +386,17 @@ add_aux_reg(struct drm_i915_aux_table *aux, return x; } +static struct drm_i915_aux_table * +add_blit_cctl_override(struct drm_i915_aux_table *aux, u8 idx) +{ + return add_aux_reg(aux, + REG_ENGINE_CONTEXT, + "BLIT_CCTL", + BLIT_CCTL(0), + BLIT_CCTL_MOCS(idx, idx), + 0); +} + static struct drm_i915_aux_table * add_cmd_cctl_override(struct drm_i915_aux_table *aux, u8 idx) { @@ -412,6 +423,8 @@ build_aux_regs(const struct intel_engine_cs *engine, * a entry in drm_i915_aux_table link list. */ aux = add_cmd_cctl_override(aux, mocs->uc_index); + if (engine->class == COPY_ENGINE_CLASS) + aux = add_blit_cctl_override(aux, mocs->uc_index); } return aux; } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index df7a4550fb50f..207e0ada179b2 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2567,6 +2567,13 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) REG_FIELD_PREP(CMD_CCTL_WRITE_OVERRIDE_MASK, (write) << 1) | \ REG_FIELD_PREP(CMD_CCTL_READ_OVERRIDE_MASK, (read) << 1)) +#define BLIT_CCTL(base) _MMIO((base) + 0x204) +#define BLIT_CCTL_DST_MOCS_MASK REG_GENMASK(14, 8) +#define BLIT_CCTL_SRC_MOCS_MASK REG_GENMASK(6, 0) +#define BLIT_CCTL_DST_MOCS_SHIFT 8 +#define BLIT_CCTL_MOCS(dst, src) \ + ((((dst) << 1) << BLIT_CCTL_DST_MOCS_SHIFT) | ((src) << 1)) + #define RING_RESET_CTL(base) _MMIO((base) + 0xd0) #define RESET_CTL_CAT_ERROR REG_BIT(2) #define RESET_CTL_READY_TO_RESET REG_BIT(1) From patchwork Mon Aug 30 16:22:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Siddiqui, Ayaz A" X-Patchwork-Id: 12465539 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3EAE5C432BE for ; Mon, 30 Aug 2021 16:26:12 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0F3B160ED6 for ; Mon, 30 Aug 2021 16:26:12 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 0F3B160ED6 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7787A89CB5; Mon, 30 Aug 2021 16:26:11 +0000 (UTC) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6F0BA89CAD for ; Mon, 30 Aug 2021 16:26:07 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10092"; a="279318048" X-IronPort-AV: E=Sophos;i="5.84,363,1620716400"; d="scan'208";a="279318048" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Aug 2021 09:26:07 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.84,363,1620716400"; d="scan'208";a="497802557" Received: from ayazahma-nuc8i7beh.iind.intel.com ([10.145.162.59]) by fmsmga008.fm.intel.com with ESMTP; 30 Aug 2021 09:26:05 -0700 From: Ayaz A Siddiqui To: intel-gfx@lists.freedesktop.org Cc: Ayaz A Siddiqui Date: Mon, 30 Aug 2021 21:52:37 +0530 Message-Id: <20210830162240.3891502-6-ayaz.siddiqui@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210830162240.3891502-1-ayaz.siddiqui@intel.com> References: <20210830162240.3891502-1-ayaz.siddiqui@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH V3 5/8] drm/i915/gt: Initialize unused MOCS entries with device specific values X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Historically we've initialized all undefined/reserved entries in a platform's MOCS table to the contents of table entry #1 (i.e., I915_MOCS_PTE). Going forward, we can't assume that table entry #1 will always contain suitable values to use for undefined/reserved table indices. We'll allow a platform-specific table index to be selected at table initialization time in these cases. This new mechanism to select L3 WB entry will be applicable for all the Gen12+ platforms except TGL and RKL. Since TGL and RLK are already in production so their mocs settings are intact to avoid ABI break. Signed-off-by: Ayaz A Siddiqui --- drivers/gpu/drm/i915/gt/intel_mocs.c | 41 +++++++++++++++------------- 1 file changed, 22 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c index 82eafa8d22453..a97cc08e5a395 100644 --- a/drivers/gpu/drm/i915/gt/intel_mocs.c +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c @@ -25,6 +25,7 @@ struct drm_i915_mocs_table { unsigned int n_entries; const struct drm_i915_mocs_entry *table; u8 uc_index; + u8 unused_entries_index; }; enum register_type { @@ -113,18 +114,25 @@ struct drm_i915_aux_table { * * Entries not part of the following tables are undefined as far as * userspace is concerned and shouldn't be relied upon. For Gen < 12 - * they will be initialized to PTE. Gen >= 12 onwards don't have a setting for - * PTE and will be initialized to an invalid value. + * they will be initialized to PTE. Gen >= 12 don't have a setting for + * PTE and those platforms except TGL/RKL will be initialized L3 WB to + * catch accidental use of reserved and unused mocs indexes. * * The last few entries are reserved by the hardware. For ICL+ they * should be initialized according to bspec and never used, for older * platforms they should never be written to. * - * NOTE: These tables are part of bspec and defined as part of hardware + * NOTE1: These tables are part of bspec and defined as part of hardware * interface for ICL+. For older platforms, they are part of kernel * ABI. It is expected that, for specific hardware platform, existing * entries will remain constant and the table will only be updated by * adding new entries, filling unused positions. + * + * NOTE2: For GEN >= 12 except TGL and RKL, reserved and unspecified MOCS + * indices have been set to L3 WB. These reserved entries should never + * be used, they may be changed to low performant variants with better + * coherency in the future if more entries are needed. + * For TGL/RKL, all the unspecified MOCS indexes are mapped to L3 UC. */ #define GEN9_MOCS_ENTRIES \ MOCS_ENTRY(I915_MOCS_UNCACHED, \ @@ -307,17 +315,9 @@ static const struct drm_i915_mocs_entry icl_mocs_table[] = { }; static const struct drm_i915_mocs_entry dg1_mocs_table[] = { - /* Error */ - MOCS_ENTRY(0, 0, L3_0_DIRECT), /* UC */ MOCS_ENTRY(1, 0, L3_1_UC), - - /* Reserved */ - MOCS_ENTRY(2, 0, L3_0_DIRECT), - MOCS_ENTRY(3, 0, L3_0_DIRECT), - MOCS_ENTRY(4, 0, L3_0_DIRECT), - /* WB - L3 */ MOCS_ENTRY(5, 0, L3_3_WB), /* WB - L3 50% */ @@ -469,6 +469,7 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915, table->table = dg1_mocs_table; table->n_entries = GEN9_NUM_MOCS_ENTRIES; table->uc_index = 1; + table->unused_entries_index = 5; } else if (GRAPHICS_VER(i915) >= 12) { table->size = ARRAY_SIZE(tgl_mocs_table); table->table = tgl_mocs_table; @@ -600,16 +601,17 @@ int apply_mocs_aux_regs_ctx(struct i915_request *rq) } /* - * Get control_value from MOCS entry taking into account when it's not used: - * I915_MOCS_PTE's value is returned in this case. + * Get control_value from MOCS entry taking into account when it's not used + * then if unused_entries_index is non-zero then its value will be returned + * otherwise I915_MOCS_PTE's value is returned in this case. */ static u32 get_entry_control(const struct drm_i915_mocs_table *table, unsigned int index) { if (index < table->size && table->table[index].used) return table->table[index].control_value; - - return table->table[I915_MOCS_PTE].control_value; + index = table->unused_entries_index ? : I915_MOCS_PTE; + return table->table[index].control_value; } #define for_each_mocs(mocs, t, i) \ @@ -650,16 +652,17 @@ static void init_mocs_table(struct intel_engine_cs *engine, } /* - * Get l3cc_value from MOCS entry taking into account when it's not used: - * I915_MOCS_PTE's value is returned in this case. + * Get l3cc_value from MOCS entry taking into account when it's not used + * then if unused_entries_index is not zero then its value will be returned + * otherwise I915_MOCS_PTE's value is returned in this case. */ static u16 get_entry_l3cc(const struct drm_i915_mocs_table *table, unsigned int index) { if (index < table->size && table->table[index].used) return table->table[index].l3cc_value; - - return table->table[I915_MOCS_PTE].l3cc_value; + index = table->unused_entries_index ? : I915_MOCS_PTE; + return table->table[index].l3cc_value; } static u32 l3cc_combine(u16 low, u16 high) From patchwork Mon Aug 30 16:22:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Siddiqui, Ayaz A" X-Patchwork-Id: 12465541 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E676DC4320A for ; Mon, 30 Aug 2021 16:26:12 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B662460ED6 for ; Mon, 30 Aug 2021 16:26:12 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org B662460ED6 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D14F289CB8; Mon, 30 Aug 2021 16:26:11 +0000 (UTC) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id A61E989CAD for ; Mon, 30 Aug 2021 16:26:10 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10092"; a="279318063" X-IronPort-AV: E=Sophos;i="5.84,363,1620716400"; d="scan'208";a="279318063" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Aug 2021 09:26:10 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.84,363,1620716400"; d="scan'208";a="497802567" Received: from ayazahma-nuc8i7beh.iind.intel.com ([10.145.162.59]) by fmsmga008.fm.intel.com with ESMTP; 30 Aug 2021 09:26:07 -0700 From: Ayaz A Siddiqui To: intel-gfx@lists.freedesktop.org Cc: Ayaz A Siddiqui , Chris P Wilson , Lucas De Marchi , Matt Roper Date: Mon, 30 Aug 2021 21:52:38 +0530 Message-Id: <20210830162240.3891502-7-ayaz.siddiqui@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210830162240.3891502-1-ayaz.siddiqui@intel.com> References: <20210830162240.3891502-1-ayaz.siddiqui@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH V3 6/8] drm/i95/adl: Define MOCS table for Alderlake X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" In order to program unused and reserved mocs entries to L3_WB, we need to create a separate mocs table for alderlake. This patch will also covers wa_1608975824. Cc: Chris P Wilson Cc: Lucas De Marchi Reviewed-by: Matt Roper Signed-off-by: Ayaz A Siddiqui --- drivers/gpu/drm/i915/gt/intel_mocs.c | 41 +++++++++++++++++++++++++++- 1 file changed, 40 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c index a97cc08e5a395..577a78dfedf99 100644 --- a/drivers/gpu/drm/i915/gt/intel_mocs.c +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c @@ -339,6 +339,39 @@ static const struct drm_i915_mocs_entry dg1_mocs_table[] = { MOCS_ENTRY(63, 0, L3_1_UC), }; +static const struct drm_i915_mocs_entry adl_mocs_table[] = { + /* wa_1608975824 */ + MOCS_ENTRY(0, + LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + + GEN11_MOCS_ENTRIES, + /* Implicitly enable L1 - HDC:L1 + L3 + LLC */ + MOCS_ENTRY(48, + LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + /* Implicitly enable L1 - HDC:L1 + L3 */ + MOCS_ENTRY(49, + LE_1_UC | LE_TC_1_LLC, + L3_3_WB), + /* Implicitly enable L1 - HDC:L1 + LLC */ + MOCS_ENTRY(50, + LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_1_UC), + /* Implicitly enable L1 - HDC:L1 */ + MOCS_ENTRY(51, + LE_1_UC | LE_TC_1_LLC, + L3_1_UC), + /* HW Special Case (CCS) */ + MOCS_ENTRY(60, + LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_1_UC), + /* HW Special Case (Displayable) */ + MOCS_ENTRY(61, + LE_1_UC | LE_TC_1_LLC, + L3_3_WB), +}; + enum { HAS_GLOBAL_MOCS = BIT(0), HAS_ENGINE_MOCS = BIT(1), @@ -464,7 +497,13 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915, memset(table, 0, sizeof(struct drm_i915_mocs_table)); - if (IS_DG1(i915)) { + if (IS_ALDERLAKE_S(i915) || IS_ALDERLAKE_P(i915)) { + table->size = ARRAY_SIZE(adl_mocs_table); + table->table = adl_mocs_table; + table->n_entries = GEN9_NUM_MOCS_ENTRIES; + table->uc_index = 3; + table->unused_entries_index = 2; + } else if (IS_DG1(i915)) { table->size = ARRAY_SIZE(dg1_mocs_table); table->table = dg1_mocs_table; table->n_entries = GEN9_NUM_MOCS_ENTRIES; From patchwork Mon Aug 30 16:22:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Siddiqui, Ayaz A" X-Patchwork-Id: 12465547 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BC34EC4320E for ; Mon, 30 Aug 2021 16:26:23 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8C82060ED6 for ; Mon, 30 Aug 2021 16:26:23 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 8C82060ED6 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 00A1589CE2; Mon, 30 Aug 2021 16:26:23 +0000 (UTC) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2870589CDD for ; Mon, 30 Aug 2021 16:26:12 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10092"; a="279318066" X-IronPort-AV: E=Sophos;i="5.84,363,1620716400"; d="scan'208";a="279318066" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Aug 2021 09:26:11 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.84,363,1620716400"; d="scan'208";a="497802572" Received: from ayazahma-nuc8i7beh.iind.intel.com ([10.145.162.59]) by fmsmga008.fm.intel.com with ESMTP; 30 Aug 2021 09:26:10 -0700 From: Ayaz A Siddiqui To: intel-gfx@lists.freedesktop.org Cc: Sreedhar Telukuntla , Ayaz A Siddiqui Date: Mon, 30 Aug 2021 21:52:39 +0530 Message-Id: <20210830162240.3891502-8-ayaz.siddiqui@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210830162240.3891502-1-ayaz.siddiqui@intel.com> References: <20210830162240.3891502-1-ayaz.siddiqui@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH V3 7/8] drm/i915/gt: Initialize L3CC table in mocs init X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Sreedhar Telukuntla Initialize the L3CC table as part of mocs initalization to program LNCFCMOCSx registers, so that the mocs settings are available for selection for subsequent memory transactions in driver load path. Signed-off-by: Sreedhar Telukuntla Signed-off-by: Ayaz A Siddiqui --- drivers/gpu/drm/i915/gt/intel_mocs.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c index 577a78dfedf99..405374f1d8ed2 100644 --- a/drivers/gpu/drm/i915/gt/intel_mocs.c +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c @@ -717,10 +717,9 @@ static u32 l3cc_combine(u16 low, u16 high) 0; \ i++) -static void init_l3cc_table(struct intel_engine_cs *engine, +static void init_l3cc_table(struct intel_uncore *uncore, const struct drm_i915_mocs_table *table) { - struct intel_uncore *uncore = engine->uncore; unsigned int i; u32 l3cc; @@ -746,7 +745,7 @@ void intel_mocs_init_engine(struct intel_engine_cs *engine) init_mocs_table(engine, &table); if (flags & HAS_RENDER_L3CC && engine->class == RENDER_CLASS) - init_l3cc_table(engine, &table); + init_l3cc_table(engine->uncore, &table); aux = build_aux_regs(engine, &table); apply_aux_regs_engine(engine, aux); @@ -776,6 +775,14 @@ void intel_mocs_init(struct intel_gt *gt) if (flags & HAS_GLOBAL_MOCS) __init_mocs_table(gt->uncore, &table, global_mocs_offset()); set_mocs_index(gt, &table); + + /* + * Initialize the L3CC table as part of mocs initalization to make + * sure the LNCFCMOCSx registers are programmed for the subsequent + * memory transactions including guc transactions + */ + if (flags & HAS_RENDER_L3CC) + init_l3cc_table(gt->uncore, &table); } #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) From patchwork Mon Aug 30 16:22:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Siddiqui, Ayaz A" X-Patchwork-Id: 12465543 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A61C5C432BE for ; Mon, 30 Aug 2021 16:26:17 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4FF5D604D7 for ; Mon, 30 Aug 2021 16:26:17 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 4FF5D604D7 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E1CC089B03; Mon, 30 Aug 2021 16:26:16 +0000 (UTC) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id A529489CDD for ; Mon, 30 Aug 2021 16:26:13 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10092"; a="279318071" X-IronPort-AV: E=Sophos;i="5.84,363,1620716400"; d="scan'208";a="279318071" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Aug 2021 09:26:13 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.84,363,1620716400"; d="scan'208";a="497802579" Received: from ayazahma-nuc8i7beh.iind.intel.com ([10.145.162.59]) by fmsmga008.fm.intel.com with ESMTP; 30 Aug 2021 09:26:12 -0700 From: Ayaz A Siddiqui To: intel-gfx@lists.freedesktop.org Cc: Ayaz A Siddiqui Date: Mon, 30 Aug 2021 21:52:40 +0530 Message-Id: <20210830162240.3891502-9-ayaz.siddiqui@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210830162240.3891502-1-ayaz.siddiqui@intel.com> References: <20210830162240.3891502-1-ayaz.siddiqui@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH V3 8/8] drm/i915/selftest: Remove Renderer class check for l3cc table read X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Some platform like XEHPSVD does not have Renderer engines. since read_l3cc_table() is guarded by renderer class due to that check of L3CC table was not being performed on those platforms. Signed-off-by: Ayaz A Siddiqui Reviewed-by: Matt Roper --- drivers/gpu/drm/i915/gt/selftest_mocs.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/selftest_mocs.c b/drivers/gpu/drm/i915/gt/selftest_mocs.c index 2b0207dfbf21c..05f5c57f82699 100644 --- a/drivers/gpu/drm/i915/gt/selftest_mocs.c +++ b/drivers/gpu/drm/i915/gt/selftest_mocs.c @@ -281,7 +281,7 @@ static int check_mocs_engine(struct live_mocs *arg, offset = i915_ggtt_offset(vma); if (!err) err = read_mocs_table(rq, arg->mocs, &offset); - if (!err && ce->engine->class == RENDER_CLASS) + if (!err) err = read_l3cc_table(rq, arg->l3cc, &offset); if (!err) err = read_aux_regs(rq, aux, &offset); @@ -296,7 +296,7 @@ static int check_mocs_engine(struct live_mocs *arg, vaddr = arg->vaddr; if (!err) err = check_mocs_table(ce->engine, arg->mocs, &vaddr); - if (!err && ce->engine->class == RENDER_CLASS) + if (!err) err = check_l3cc_table(ce->engine, arg->l3cc, &vaddr); if (!err) err = check_aux_regs(ce->engine, aux, &vaddr);