From patchwork Mon Aug 30 18:07:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mikhail Rudenko X-Patchwork-Id: 12465685 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.9 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0E64BC432BE for ; Mon, 30 Aug 2021 18:08:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E7088600CD for ; Mon, 30 Aug 2021 18:08:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238449AbhH3SJP (ORCPT ); Mon, 30 Aug 2021 14:09:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43990 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238442AbhH3SJL (ORCPT ); Mon, 30 Aug 2021 14:09:11 -0400 Received: from mail-lj1-x22f.google.com (mail-lj1-x22f.google.com [IPv6:2a00:1450:4864:20::22f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 413C2C06175F; Mon, 30 Aug 2021 11:08:17 -0700 (PDT) Received: by mail-lj1-x22f.google.com with SMTP id i28so27397677ljm.7; Mon, 30 Aug 2021 11:08:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ehFQwBA3BukYXlKRjKhYo7zYYZcV56jlrWBZsRudsVk=; b=Fifwl3XeLQJL4RlHoxrHI7pY51LOjaYOUgZNAL02Ng6vT2BzMjJGis80onUmGt7XGH WFP17IuJRfFI/ae3yl8IXnyYAgTY1ptRfs+oUNuI74JI57+XNHbikKMxCb+oo6zLk0RN 1k1XpzLXR9N31p4hJPDtXdFZSOXvAyE3xIzob7SbArBct3V/BpPRTw8US1/oW09rKUlS GT1zjShZlQDSO6L/Q/wiSHgLP40m8SWx6cH/AfUpcnLKG6KbW1zRnQzRcbr+rPix5cDF 0w6/hurDb6cZBNM8nknKOL6qwevmzvWgztnl4yT3f9eBK4ku/ogJRza8pGvtiwYtgH+3 arQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ehFQwBA3BukYXlKRjKhYo7zYYZcV56jlrWBZsRudsVk=; b=QvVT1UbxsShsW0awEI7n3tRqPoofZJQo8vg3jjENynpMvHOblX4V7r9HnLMb7bXgBz ninifr/+zlY4dumiItmtxIP9L4NPlxvfZ9lxWQmbeXNTWeyVHOtji2eRClL5AXx8D51s q/loQCHg1lnsYQQYtUCqeCUfKHZgTbOaNQr+ChWdfun4Z1BgzPAQsvQuRV+MmURGcQ0q VVSViyiHvdMlIS4XqTGv9d78pwQ82ko/90ElkCKhsFMzZwOqxYAaMpBHAOmsEgeV1nRd A3TbZx4taumgSzUUd1gJLWptJ4+OYCDT0yjzu3jHkEEI2g7ug0kjpy/uYzGz1IUOnK+n if9Q== X-Gm-Message-State: AOAM532KKjNir6SB1iS8PllR9TgD33aorFCU0cthfVoyY849+POpDydW h7I9ARjdA8iXHK+8uGhEt9U= X-Google-Smtp-Source: ABdhPJxxG8YG731ayRJQUndl/4IVw5XHoG6tIsVQhX87NC59tPsiXVaRZ5V/zbs4lREfOQ71p5+hyg== X-Received: by 2002:a05:651c:10a8:: with SMTP id k8mr21257633ljn.356.1630346895552; Mon, 30 Aug 2021 11:08:15 -0700 (PDT) Received: from localhost (37-145-211-218.broadband.corbina.ru. [37.145.211.218]) by smtp.gmail.com with ESMTPSA id l7sm1454952lfj.81.2021.08.30.11.08.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Aug 2021 11:08:15 -0700 (PDT) From: Mikhail Rudenko To: linux-phy@lists.infradead.org Cc: linux-media@vger.kernel.org, Mikhail Rudenko , Kishon Vijay Abraham I , Vinod Koul , Heiko Stuebner , linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 1/5] phy: phy-rockchip-dphy-rx0: refactor for tx1rx1 addition Date: Mon, 30 Aug 2021 21:07:50 +0300 Message-Id: <20210830180758.251390-2-mike.rudenko@gmail.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210830180758.251390-1-mike.rudenko@gmail.com> References: <20210830180758.251390-1-mike.rudenko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org In order to accommodate for rk3399 tx1rx1 addition, make enable/disable function calls indirect via function pointers in rk_dphy_drv_data. Also rename rk_dphy_write and rk_dphy_enable to avoid naming clashes. Signed-off-by: Mikhail Rudenko --- drivers/phy/rockchip/phy-rockchip-dphy-rx0.c | 38 +++++++++++++------- 1 file changed, 25 insertions(+), 13 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-dphy-rx0.c b/drivers/phy/rockchip/phy-rockchip-dphy-rx0.c index 4df9476ef2a9..72145cdfb036 100644 --- a/drivers/phy/rockchip/phy-rockchip-dphy-rx0.c +++ b/drivers/phy/rockchip/phy-rockchip-dphy-rx0.c @@ -138,12 +138,17 @@ static const struct dphy_reg rk3399_grf_dphy_regs[] = { [GRF_DPHY_RX0_TESTDOUT] = PHY_REG(RK3399_GRF_SOC_STATUS1, 8, 0), }; +struct rk_dphy; + struct rk_dphy_drv_data { const char * const *clks; unsigned int num_clks; const struct hsfreq_range *hsfreq_ranges; unsigned int num_hsfreq_ranges; const struct dphy_reg *regs; + + void (*enable)(struct rk_dphy *priv); + void (*disable)(struct rk_dphy *priv); }; struct rk_dphy { @@ -170,7 +175,7 @@ static inline void rk_dphy_write_grf(struct rk_dphy *priv, regmap_write(priv->grf, reg->offset, val); } -static void rk_dphy_write(struct rk_dphy *priv, u8 test_code, u8 test_data) +static void rk_dphy_write_mipi_rx(struct rk_dphy *priv, u8 test_code, u8 test_data) { rk_dphy_write_grf(priv, GRF_DPHY_RX0_TESTDIN, test_code); rk_dphy_write_grf(priv, GRF_DPHY_RX0_TESTEN, 1); @@ -186,7 +191,7 @@ static void rk_dphy_write(struct rk_dphy *priv, u8 test_code, u8 test_data) rk_dphy_write_grf(priv, GRF_DPHY_RX0_TESTCLK, 1); } -static void rk_dphy_enable(struct rk_dphy *priv) +static void rk_dphy_enable_rx(struct rk_dphy *priv) { rk_dphy_write_grf(priv, GRF_DPHY_RX0_FORCERXMODE, 0); rk_dphy_write_grf(priv, GRF_DPHY_RX0_FORCETXSTOPMODE, 0); @@ -206,22 +211,27 @@ static void rk_dphy_enable(struct rk_dphy *priv) usleep_range(100, 150); /* set clock lane */ - /* HS hsfreq_range & lane 0 settle bypass */ - rk_dphy_write(priv, CLOCK_LANE_HS_RX_CONTROL, 0); + /* HS hsfreq_range & lane 0 settle bypass */ + rk_dphy_write_mipi_rx(priv, CLOCK_LANE_HS_RX_CONTROL, 0); /* HS RX Control of lane0 */ - rk_dphy_write(priv, LANE0_HS_RX_CONTROL, priv->hsfreq << 1); + rk_dphy_write_mipi_rx(priv, LANE0_HS_RX_CONTROL, priv->hsfreq << 1); /* HS RX Control of lane1 */ - rk_dphy_write(priv, LANE1_HS_RX_CONTROL, priv->hsfreq << 1); + rk_dphy_write_mipi_rx(priv, LANE1_HS_RX_CONTROL, priv->hsfreq << 1); /* HS RX Control of lane2 */ - rk_dphy_write(priv, LANE2_HS_RX_CONTROL, priv->hsfreq << 1); + rk_dphy_write_mipi_rx(priv, LANE2_HS_RX_CONTROL, priv->hsfreq << 1); /* HS RX Control of lane3 */ - rk_dphy_write(priv, LANE3_HS_RX_CONTROL, priv->hsfreq << 1); + rk_dphy_write_mipi_rx(priv, LANE3_HS_RX_CONTROL, priv->hsfreq << 1); /* HS RX Data Lanes Settle State Time Control */ - rk_dphy_write(priv, LANES_THS_SETTLE_CONTROL, - THS_SETTLE_COUNTER_THRESHOLD); + rk_dphy_write_mipi_rx(priv, LANES_THS_SETTLE_CONTROL, + THS_SETTLE_COUNTER_THRESHOLD); /* Normal operation */ - rk_dphy_write(priv, 0x0, 0); + rk_dphy_write_mipi_rx(priv, 0x0, 0); +} + +static void rk_dphy_disable_rx(struct rk_dphy *priv) +{ + rk_dphy_write_grf(priv, GRF_DPHY_RX0_ENABLE, 0); } static int rk_dphy_configure(struct phy *phy, union phy_configure_opts *opts) @@ -266,7 +276,7 @@ static int rk_dphy_power_on(struct phy *phy) if (ret) return ret; - rk_dphy_enable(priv); + priv->drv_data->enable(priv); return 0; } @@ -275,7 +285,7 @@ static int rk_dphy_power_off(struct phy *phy) { struct rk_dphy *priv = phy_get_drvdata(phy); - rk_dphy_write_grf(priv, GRF_DPHY_RX0_ENABLE, 0); + priv->drv_data->disable(priv); clk_bulk_disable(priv->drv_data->num_clks, priv->clks); return 0; } @@ -310,6 +320,8 @@ static const struct rk_dphy_drv_data rk3399_mipidphy_drv_data = { .hsfreq_ranges = rk3399_mipidphy_hsfreq_ranges, .num_hsfreq_ranges = ARRAY_SIZE(rk3399_mipidphy_hsfreq_ranges), .regs = rk3399_grf_dphy_regs, + .enable = rk_dphy_enable_rx, + .disable = rk_dphy_disable_rx, }; static const struct of_device_id rk_dphy_dt_ids[] = { From patchwork Mon Aug 30 18:07:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mikhail Rudenko X-Patchwork-Id: 12465687 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.9 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7CD4FC432BE for ; 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[37.145.211.218]) by smtp.gmail.com with ESMTPSA id u11sm879448ljo.126.2021.08.30.11.08.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Aug 2021 11:08:16 -0700 (PDT) From: Mikhail Rudenko To: linux-phy@lists.infradead.org Cc: linux-media@vger.kernel.org, Mikhail Rudenko , Kishon Vijay Abraham I , Vinod Koul , Heiko Stuebner , linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 2/5] phy: phy-rockchip-dphy-rx0: add support for tx1rx1 in receive mode Date: Mon, 30 Aug 2021 21:07:51 +0300 Message-Id: <20210830180758.251390-3-mike.rudenko@gmail.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210830180758.251390-1-mike.rudenko@gmail.com> References: <20210830180758.251390-1-mike.rudenko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Implement RX mode of RK3399 TX1RX1 MIPI D-PHY. Unlike RX0 phy, it uses both mmio registers and grf for configuration. Add necessary register definitions, mmio register access functions, enable/disable functions, rk_dphy_drv_data instance and compatible string for tx1rx1. Probe function is adjusted accordingly. Additionally, individual init function is implemented, since, according to the comments in Rockchip BSP kernel, "According to the sequence of RK3399_TXRX_DPHY, the setting of isp0 mipi will affect txrx dphy in default state of grf_soc_con24." Signed-off-by: Mikhail Rudenko --- drivers/phy/rockchip/phy-rockchip-dphy-rx0.c | 193 +++++++++++++++++-- 1 file changed, 172 insertions(+), 21 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-dphy-rx0.c b/drivers/phy/rockchip/phy-rockchip-dphy-rx0.c index 72145cdfb036..3ce307b49e51 100644 --- a/drivers/phy/rockchip/phy-rockchip-dphy-rx0.c +++ b/drivers/phy/rockchip/phy-rockchip-dphy-rx0.c @@ -34,6 +34,12 @@ #define RK3399_GRF_SOC_CON24 0x6260 #define RK3399_GRF_SOC_CON25 0x6264 #define RK3399_GRF_SOC_STATUS1 0xe2a4 +#define RK3399_GRF_IO_VSEL 0x0900 + +#define RK3399_PHY_TEST_CTRL0 0xb4 +#define RK3399_PHY_TEST_CTRL1 0xb8 +#define RK3399_PHY_SHUTDOWNZ 0xa0 +#define RK3399_PHY_RSTZ 0xa0 #define CLOCK_LANE_HS_RX_CONTROL 0x34 #define LANE0_HS_RX_CONTROL 0x44 @@ -43,6 +49,11 @@ #define LANES_THS_SETTLE_CONTROL 0x75 #define THS_SETTLE_COUNTER_THRESHOLD 0x04 +#define PHY_TESTEN_ADDR (0x1 << 16) +#define PHY_TESTEN_DATA (0x0 << 16) +#define PHY_TESTCLK (0x1 << 1) +#define PHY_TESTCLR (0x1 << 0) + struct hsfreq_range { u16 range_h; u8 cfg_bit; @@ -61,12 +72,6 @@ static const struct hsfreq_range rk3399_mipidphy_hsfreq_ranges[] = { { 1399, 0x1c }, { 1449, 0x2c }, { 1500, 0x3c } }; -static const char * const rk3399_mipidphy_clks[] = { - "dphy-ref", - "dphy-cfg", - "grf", -}; - enum dphy_reg_id { GRF_DPHY_RX0_TURNDISABLE = 0, GRF_DPHY_RX0_FORCERXMODE, @@ -99,6 +104,14 @@ enum dphy_reg_id { /* below is for rk3399 only */ GRF_DPHY_RX0_CLK_INV_SEL, GRF_DPHY_RX1_CLK_INV_SEL, + GRF_DPHY_TX1RX1_SRC_SEL, +}; + +enum txrx_reg_id { + TXRX_PHY_TEST_CTRL0 = 0, + TXRX_PHY_TEST_CTRL1, + TXRX_PHY_SHUTDOWNZ, + TXRX_PHY_RSTZ, }; struct dphy_reg { @@ -127,7 +140,7 @@ static const struct dphy_reg rk3399_grf_dphy_regs[] = { [GRF_DPHY_TX1RX1_FORCETXSTOPMODE] = PHY_REG(RK3399_GRF_SOC_CON23, 4, 8), [GRF_DPHY_TX1RX1_TURNDISABLE] = PHY_REG(RK3399_GRF_SOC_CON23, 4, 12), [GRF_DPHY_TX1RX1_TURNREQUEST] = PHY_REG(RK3399_GRF_SOC_CON24, 4, 0), - [GRF_DPHY_RX1_SRC_SEL] = PHY_REG(RK3399_GRF_SOC_CON24, 1, 4), + [GRF_DPHY_TX1RX1_SRC_SEL] = PHY_REG(RK3399_GRF_SOC_CON24, 1, 4), [GRF_DPHY_TX1RX1_BASEDIR] = PHY_REG(RK3399_GRF_SOC_CON24, 1, 5), [GRF_DPHY_TX1RX1_ENABLECLK] = PHY_REG(RK3399_GRF_SOC_CON24, 1, 6), [GRF_DPHY_TX1RX1_MASTERSLAVEZ] = PHY_REG(RK3399_GRF_SOC_CON24, 1, 7), @@ -136,6 +149,21 @@ static const struct dphy_reg rk3399_grf_dphy_regs[] = { [GRF_DPHY_RX0_TESTCLK] = PHY_REG(RK3399_GRF_SOC_CON25, 1, 9), [GRF_DPHY_RX0_TESTCLR] = PHY_REG(RK3399_GRF_SOC_CON25, 1, 10), [GRF_DPHY_RX0_TESTDOUT] = PHY_REG(RK3399_GRF_SOC_STATUS1, 8, 0), + [GRF_DVP_V18SEL] = PHY_REG(RK3399_GRF_IO_VSEL, 1, 1), +}; + +struct txrx_reg { + u32 offset; +}; + +#define TXRX_REG(_offset) \ + { .offset = _offset, } + +static const struct txrx_reg rk3399_txrx_regs[] = { + [TXRX_PHY_TEST_CTRL0] = TXRX_REG(RK3399_PHY_TEST_CTRL0), + [TXRX_PHY_TEST_CTRL1] = TXRX_REG(RK3399_PHY_TEST_CTRL1), + [TXRX_PHY_SHUTDOWNZ] = TXRX_REG(RK3399_PHY_SHUTDOWNZ), + [TXRX_PHY_RSTZ] = TXRX_REG(RK3399_PHY_RSTZ), }; struct rk_dphy; @@ -146,15 +174,18 @@ struct rk_dphy_drv_data { const struct hsfreq_range *hsfreq_ranges; unsigned int num_hsfreq_ranges; const struct dphy_reg *regs; + const struct txrx_reg *txrx_regs; void (*enable)(struct rk_dphy *priv); void (*disable)(struct rk_dphy *priv); + void (*individual_init)(struct rk_dphy *priv); }; struct rk_dphy { struct device *dev; struct regmap *grf; struct clk_bulk_data *clks; + void __iomem *txrx_base_addr; const struct rk_dphy_drv_data *drv_data; struct phy_configure_opts_mipi_dphy config; @@ -234,6 +265,74 @@ static void rk_dphy_disable_rx(struct rk_dphy *priv) rk_dphy_write_grf(priv, GRF_DPHY_RX0_ENABLE, 0); } +static inline void rk_dphy_write_tx1rx1(struct rk_dphy *priv, + int index, u32 value) +{ + const struct txrx_reg *reg = &priv->drv_data->txrx_regs[index]; + + if (reg->offset) + writel(value, priv->txrx_base_addr + reg->offset); +} + +static void rk_dphy_write_mipi_tx1rx1(struct rk_dphy *priv, unsigned char addr, + unsigned char data) +{ + /* + * TESTEN =1,TESTDIN=addr + * TESTCLK=0 + * TESTEN =0,TESTDIN=data + * TESTCLK=1 + */ + rk_dphy_write_tx1rx1(priv, TXRX_PHY_TEST_CTRL1, PHY_TESTEN_ADDR | addr); + rk_dphy_write_tx1rx1(priv, TXRX_PHY_TEST_CTRL0, 0x00); + rk_dphy_write_tx1rx1(priv, TXRX_PHY_TEST_CTRL1, PHY_TESTEN_DATA | data); + rk_dphy_write_tx1rx1(priv, TXRX_PHY_TEST_CTRL0, 0x02); +} + +static void rk_dphy_enable_txrx(struct rk_dphy *priv) +{ + rk_dphy_write_tx1rx1(priv, TXRX_PHY_TEST_CTRL0, PHY_TESTCLR | PHY_TESTCLK); + usleep_range(100, 150); + + rk_dphy_write_grf(priv, GRF_DPHY_TX1RX1_MASTERSLAVEZ, 0); + rk_dphy_write_grf(priv, GRF_DPHY_TX1RX1_BASEDIR, 1); + + rk_dphy_write_grf(priv, GRF_DPHY_TX1RX1_FORCERXMODE, 0); + rk_dphy_write_grf(priv, GRF_DPHY_TX1RX1_FORCETXSTOPMODE, 0); + rk_dphy_write_grf(priv, GRF_DPHY_TX1RX1_TURNREQUEST, 0); + rk_dphy_write_grf(priv, GRF_DPHY_TX1RX1_TURNDISABLE, 0xf); + usleep_range(100, 150); + + rk_dphy_write_tx1rx1(priv, TXRX_PHY_TEST_CTRL0, PHY_TESTCLK); + usleep_range(100, 150); + + rk_dphy_write_mipi_tx1rx1(priv, CLOCK_LANE_HS_RX_CONTROL, 0); + rk_dphy_write_mipi_tx1rx1(priv, LANE0_HS_RX_CONTROL, priv->hsfreq << 1); + rk_dphy_write_mipi_tx1rx1(priv, LANE1_HS_RX_CONTROL, 0); + rk_dphy_write_mipi_tx1rx1(priv, LANE2_HS_RX_CONTROL, 0); + rk_dphy_write_mipi_tx1rx1(priv, LANE3_HS_RX_CONTROL, 0); + + rk_dphy_write_grf(priv, GRF_DPHY_TX1RX1_ENABLE, GENMASK(priv->config.lanes - 1, 0)); + usleep_range(100, 150); +} + +static void rk_dphy_disable_txrx(struct rk_dphy *priv) +{ + rk_dphy_write_grf(priv, GRF_DPHY_TX1RX1_ENABLE, 0); +} + +static void rk3399_mipidphy_individual_init(struct rk_dphy *priv) +{ + /* + * According to the sequence of RK3399_TXRX_DPHY, the setting of isp0 mipi + * will affect txrx dphy in default state of grf_soc_con24. + */ + rk_dphy_write_grf(priv, GRF_DPHY_TX1RX1_SRC_SEL, 0); + rk_dphy_write_grf(priv, GRF_DPHY_TX1RX1_MASTERSLAVEZ, 0); + rk_dphy_write_grf(priv, GRF_DPHY_TX1RX1_BASEDIR, 0); + rk_dphy_write_grf(priv, GRF_DVP_V18SEL, 0x1); +} + static int rk_dphy_configure(struct phy *phy, union phy_configure_opts *opts) { struct rk_dphy *priv = phy_get_drvdata(phy); @@ -314,20 +413,50 @@ static const struct phy_ops rk_dphy_ops = { .owner = THIS_MODULE, }; -static const struct rk_dphy_drv_data rk3399_mipidphy_drv_data = { - .clks = rk3399_mipidphy_clks, - .num_clks = ARRAY_SIZE(rk3399_mipidphy_clks), +static const char * const rk3399_mipidphy_rx_clks[] = { + "dphy-ref", + "dphy-cfg", + "grf", +}; + +static const char * const rk3399_mipidphy_txrx_clks[] = { + "dphy-ref", + "dphy-cfg", + "grf", + "dsi", +}; + +static const struct rk_dphy_drv_data rk3399_mipidphy_rx_drv_data = { + .clks = rk3399_mipidphy_rx_clks, + .num_clks = ARRAY_SIZE(rk3399_mipidphy_rx_clks), .hsfreq_ranges = rk3399_mipidphy_hsfreq_ranges, .num_hsfreq_ranges = ARRAY_SIZE(rk3399_mipidphy_hsfreq_ranges), .regs = rk3399_grf_dphy_regs, .enable = rk_dphy_enable_rx, .disable = rk_dphy_disable_rx, + .individual_init = rk3399_mipidphy_individual_init, +}; + +static const struct rk_dphy_drv_data rk3399_mipidphy_txrx_drv_data = { + .clks = rk3399_mipidphy_txrx_clks, + .num_clks = ARRAY_SIZE(rk3399_mipidphy_txrx_clks), + .hsfreq_ranges = rk3399_mipidphy_hsfreq_ranges, + .num_hsfreq_ranges = ARRAY_SIZE(rk3399_mipidphy_hsfreq_ranges), + .regs = rk3399_grf_dphy_regs, + .txrx_regs = rk3399_txrx_regs, + .enable = rk_dphy_enable_txrx, + .disable = rk_dphy_disable_txrx, + .individual_init = rk3399_mipidphy_individual_init, }; static const struct of_device_id rk_dphy_dt_ids[] = { { .compatible = "rockchip,rk3399-mipi-dphy-rx0", - .data = &rk3399_mipidphy_drv_data, + .data = &rk3399_mipidphy_rx_drv_data, + }, + { + .compatible = "rockchip,rk3399-mipi-dphy-tx1rx1", + .data = &rk3399_mipidphy_txrx_drv_data, }, {} }; @@ -345,26 +474,42 @@ static int rk_dphy_probe(struct platform_device *pdev) unsigned int i; int ret; - if (!dev->parent || !dev->parent->of_node) - return -ENODEV; - priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); if (!priv) return -ENOMEM; priv->dev = dev; - priv->grf = syscon_node_to_regmap(dev->parent->of_node); - if (IS_ERR(priv->grf)) { - dev_err(dev, "Can't find GRF syscon\n"); - return -ENODEV; - } - of_id = of_match_device(rk_dphy_dt_ids, dev); if (!of_id) return -EINVAL; drv_data = of_id->data; priv->drv_data = drv_data; + + if (!drv_data->txrx_regs) { + if (!dev->parent || !dev->parent->of_node) + return -ENODEV; + + priv->grf = syscon_node_to_regmap(dev->parent->of_node); + if (IS_ERR(priv->grf)) { + dev_err(dev, "Can't find GRF syscon\n"); + return -ENODEV; + } + } else { + priv->grf = syscon_regmap_lookup_by_phandle(dev->of_node, + "rockchip,grf"); + if (IS_ERR(priv->grf)) { + dev_err(dev, "Can't find GRF syscon\n"); + return -ENODEV; + } + + priv->txrx_base_addr = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->txrx_base_addr)) { + dev_err(dev, "Failed to ioremap resource\n"); + return PTR_ERR(priv->txrx_base_addr); + } + } + priv->clks = devm_kcalloc(&pdev->dev, drv_data->num_clks, sizeof(*priv->clks), GFP_KERNEL); if (!priv->clks) @@ -383,8 +528,14 @@ static int rk_dphy_probe(struct platform_device *pdev) phy_set_drvdata(phy, priv); phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + if (IS_ERR(phy_provider)) { + dev_err(dev, "failed to register phy provider\n"); + return PTR_ERR(phy_provider); + } - return PTR_ERR_OR_ZERO(phy_provider); + drv_data->individual_init(priv); + + return 0; } static struct platform_driver rk_dphy_driver = { From patchwork Mon Aug 30 18:07:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mikhail Rudenko X-Patchwork-Id: 12465693 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AA838C4320A for ; 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[37.145.211.218]) by smtp.gmail.com with ESMTPSA id j1sm1108503lja.108.2021.08.30.11.08.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Aug 2021 11:08:20 -0700 (PDT) From: Mikhail Rudenko To: linux-phy@lists.infradead.org Cc: linux-media@vger.kernel.org, Mikhail Rudenko , Kishon Vijay Abraham I , Vinod Koul , Heiko Stuebner , Ezequiel Garcia , Tiezhu Yang , linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 3/5] phy: rename phy-rockchip-dphy-rx0 to phy-rockchip-dphy-rx Date: Mon, 30 Aug 2021 21:07:52 +0300 Message-Id: <20210830180758.251390-4-mike.rudenko@gmail.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210830180758.251390-1-mike.rudenko@gmail.com> References: <20210830180758.251390-1-mike.rudenko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Since the driver now supports both rx0 and tx1rx1 phys, rename module and Kconfig option to phy-rockchip-dphy-rx and PHY_ROCKCHIP_DPHY_RX respectively. Signed-off-by: Mikhail Rudenko --- drivers/phy/rockchip/Kconfig | 8 ++++---- drivers/phy/rockchip/Makefile | 2 +- .../{phy-rockchip-dphy-rx0.c => phy-rockchip-dphy-rx.c} | 0 3 files changed, 5 insertions(+), 5 deletions(-) rename drivers/phy/rockchip/{phy-rockchip-dphy-rx0.c => phy-rockchip-dphy-rx.c} (100%) diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig index e812adad7242..6096ca9a07f9 100644 --- a/drivers/phy/rockchip/Kconfig +++ b/drivers/phy/rockchip/Kconfig @@ -9,17 +9,17 @@ config PHY_ROCKCHIP_DP help Enable this to support the Rockchip Display Port PHY. -config PHY_ROCKCHIP_DPHY_RX0 +config PHY_ROCKCHIP_DPHY_RX tristate "Rockchip MIPI Synopsys DPHY RX0 driver" depends on ARCH_ROCKCHIP || COMPILE_TEST select GENERIC_PHY_MIPI_DPHY select GENERIC_PHY help - Enable this to support the Rockchip MIPI Synopsys DPHY RX0 - associated to the Rockchip ISP module present in RK3399 SoCs. + Enable this to support the Rockchip MIPI Synopsys DPHY RX + associated to the Rockchip ISP modules present in RK3399 SoCs. To compile this driver as a module, choose M here: the module - will be called phy-rockchip-dphy-rx0. + will be called phy-rockchip-dphy-rx. config PHY_ROCKCHIP_EMMC tristate "Rockchip EMMC PHY Driver" diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile index f0eec212b2aa..2d28526808a6 100644 --- a/drivers/phy/rockchip/Makefile +++ b/drivers/phy/rockchip/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_PHY_ROCKCHIP_DP) += phy-rockchip-dp.o -obj-$(CONFIG_PHY_ROCKCHIP_DPHY_RX0) += phy-rockchip-dphy-rx0.o +obj-$(CONFIG_PHY_ROCKCHIP_DPHY_RX) += phy-rockchip-dphy-rx.o obj-$(CONFIG_PHY_ROCKCHIP_EMMC) += phy-rockchip-emmc.o obj-$(CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY) += phy-rockchip-inno-csidphy.o obj-$(CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY) += phy-rockchip-inno-dsidphy.o diff --git a/drivers/phy/rockchip/phy-rockchip-dphy-rx0.c b/drivers/phy/rockchip/phy-rockchip-dphy-rx.c similarity index 100% rename from drivers/phy/rockchip/phy-rockchip-dphy-rx0.c rename to drivers/phy/rockchip/phy-rockchip-dphy-rx.c From patchwork Mon Aug 30 18:07:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mikhail Rudenko X-Patchwork-Id: 12465689 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9904AC43216 for ; Mon, 30 Aug 2021 18:08:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 830A960F5B for ; Mon, 30 Aug 2021 18:08:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238481AbhH3SJV (ORCPT ); Mon, 30 Aug 2021 14:09:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44036 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238465AbhH3SJS (ORCPT ); Mon, 30 Aug 2021 14:09:18 -0400 Received: from mail-lj1-x22d.google.com (mail-lj1-x22d.google.com [IPv6:2a00:1450:4864:20::22d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2F4F2C061575; Mon, 30 Aug 2021 11:08:23 -0700 (PDT) Received: by mail-lj1-x22d.google.com with SMTP id y6so27440430lje.2; Mon, 30 Aug 2021 11:08:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hcseY+qtZ/IjcQloLwbPBGPptbdvikn0Z2Vb6xHjpXM=; b=Oq20zOGsyCYBDgFP6zD7gX08ZhhMJg4shGSTNPVd+klto7tShSkvOrWZXv1rLRGgp2 odCHyScPnBCNe5c+hN9zjOvmLgreyOiwG4gxrANcVJfQKtpIyzQ3ugzDfAOiuZcmd00u q1DQI+y1WAozv8XlPsvvqW8Lbb+SsuyqMMtDZZ/7pZYJXCJw6tco/FdmAWiS5XPobwJT UTlvLdX761tVjtYZqeobEcsORFTsCWF8/uBKUeR1dxO2/7277FwFECAkpsCN8tzDMEpK xTuaqZiHR2xuZCxudjYAn9k5jb7oY6o9fV8RCjVclWqv1fgKw9cw6S5sDxZUfOYw9OJ4 9gbw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hcseY+qtZ/IjcQloLwbPBGPptbdvikn0Z2Vb6xHjpXM=; b=jvUqjkKbvsqU6zz/CWTaVaJideKZTJsb79iERDnJWAKShAS6EjhglG2J01W2pOr3al 40BmOAopOzGhQLkBsK3XXNLx8f3NhqOWP0KQHwxU0bIEfxMnqDyymyRWQuYwOY9Vj5Wc v80BIXrM7vufSvc8dR2Kh4BVOza8oYffAg9jqSgHD3Y94Pb33P3cACLhAhgP2DJTdeC8 8oHmQsjeCNVRrESCQRbb2L6JSiZ6/P3Jx8nVyfObCYkuEutekCgGwVTfiW1mnYFhvsi2 ppAkbWMw3RVfXUAH8RTOziMdGHIa7+VPcWNkpkHOePjSrqeFS7qOnsxN6Wz2Bw+Ghxr0 csBA== X-Gm-Message-State: AOAM531Ov2ioIUkYLVs/N5H/XAeCvILVUf9oGp8gIa8dA6XcG/mL8w+1 cPS3+jPxvJIIXIDu2fDQjXA= X-Google-Smtp-Source: ABdhPJxphrh25Yv1GBTQg44hFGXBbULWXm9T/wKn3URGjgqT6xhOA4a0OBIPF3N3K4r2YReRITwA3g== X-Received: by 2002:a2e:9852:: with SMTP id e18mr21208915ljj.173.1630346901454; Mon, 30 Aug 2021 11:08:21 -0700 (PDT) Received: from localhost (37-145-211-218.broadband.corbina.ru. [37.145.211.218]) by smtp.gmail.com with ESMTPSA id r13sm1862328ljh.61.2021.08.30.11.08.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Aug 2021 11:08:21 -0700 (PDT) From: Mikhail Rudenko To: linux-phy@lists.infradead.org Cc: linux-media@vger.kernel.org, Mikhail Rudenko , Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Heiko Stuebner , Helen Koike , Ezequiel Garcia , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 4/5] dt-bindings: phy: phy-rockchip-dphy-rx0: add support for tx1rx1 phy Date: Mon, 30 Aug 2021 21:07:53 +0300 Message-Id: <20210830180758.251390-5-mike.rudenko@gmail.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210830180758.251390-1-mike.rudenko@gmail.com> References: <20210830180758.251390-1-mike.rudenko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org RK3399 TX1RX1 D-PHY is not a child of GRF and uses reg, thus add corresponding properties conditionally. It also requires DSI clock to operate, so check for it. Since we now support both rx0 and tx1rx1, rename the schema to rockchip-mipi-dphy-rx.yaml. Signed-off-by: Mikhail Rudenko --- ...hy-rx0.yaml => rockchip-mipi-dphy-rx.yaml} | 39 +++++++++++++++++-- 1 file changed, 35 insertions(+), 4 deletions(-) rename Documentation/devicetree/bindings/phy/{rockchip-mipi-dphy-rx0.yaml => rockchip-mipi-dphy-rx.yaml} (65%) diff --git a/Documentation/devicetree/bindings/phy/rockchip-mipi-dphy-rx0.yaml b/Documentation/devicetree/bindings/phy/rockchip-mipi-dphy-rx.yaml similarity index 65% rename from Documentation/devicetree/bindings/phy/rockchip-mipi-dphy-rx0.yaml rename to Documentation/devicetree/bindings/phy/rockchip-mipi-dphy-rx.yaml index 7d888d358823..f42319448fc9 100644 --- a/Documentation/devicetree/bindings/phy/rockchip-mipi-dphy-rx0.yaml +++ b/Documentation/devicetree/bindings/phy/rockchip-mipi-dphy-rx.yaml @@ -1,10 +1,10 @@ # SPDX-License-Identifier: (GPL-2.0+ OR MIT) %YAML 1.2 --- -$id: http://devicetree.org/schemas/phy/rockchip-mipi-dphy-rx0.yaml# +$id: http://devicetree.org/schemas/phy/rockchip-mipi-dphy-rx.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Rockchip SoC MIPI RX0 D-PHY Device Tree Bindings +title: Rockchip SoC MIPI RX0/TX1RX1 D-PHY Device Tree Bindings maintainers: - Helen Koike @@ -16,19 +16,28 @@ description: | properties: compatible: - const: rockchip,rk3399-mipi-dphy-rx0 + enum: + - rockchip,rk3399-mipi-dphy-rx0 + - rockchip,rk3399-mipi-dphy-tx1rx1 + + reg: + maxItems: 1 clocks: + minItems: 3 items: - description: MIPI D-PHY ref clock - - description: MIPI D-PHY RX0 cfg clock + - description: MIPI D-PHY RX0/TX1RX1 cfg clock - description: Video in/out general register file clock + - description: MIPI D-PHY DSI clock clock-names: + minItems: 3 items: - const: dphy-ref - const: dphy-cfg - const: grf + - const: dsi '#phy-cells': const: 0 @@ -37,6 +46,12 @@ properties: description: Video in/out power domain. maxItems: 1 + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + The phandle of the syscon node for the general register file + (GRF), required for TX1RX1 MIPI D-PHY on RK3399. + required: - compatible - clocks @@ -44,6 +59,22 @@ required: - '#phy-cells' - power-domains +if: + properties: + compatible: + contains: + const: rockchip,rk3399-mipi-dphy-tx1rx1 +then: + required: + - reg + - rockchip,grf + + properties: + clocks: + minItems: 4 + clock-names: + minItems: 4 + additionalProperties: false examples: From patchwork Mon Aug 30 18:07:54 2021 Content-Type: text/plain; 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[37.145.211.218]) by smtp.gmail.com with ESMTPSA id q189sm1859345ljb.68.2021.08.30.11.08.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Aug 2021 11:08:23 -0700 (PDT) From: Mikhail Rudenko To: linux-phy@lists.infradead.org Cc: linux-media@vger.kernel.org, Mikhail Rudenko , Rob Herring , Heiko Stuebner , Johan Jonker , Marc Zyngier , Helen Koike , Elaine Zhang , Shunqian Zheng , Robin Murphy , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 5/5] arm64: dts: rockchip: add mipi-dphy-tx1rx1 for rk3399 Date: Mon, 30 Aug 2021 21:07:54 +0300 Message-Id: <20210830180758.251390-6-mike.rudenko@gmail.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210830180758.251390-1-mike.rudenko@gmail.com> References: <20210830180758.251390-1-mike.rudenko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add DT node for RX mode of RK3399 TX1RX1 D-PHY. Signed-off-by: Mikhail Rudenko --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 3871c7fd83b0..2e4513275a87 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1902,6 +1902,21 @@ mipi1_in_vopl: endpoint@1 { }; }; + mipi_dphy_tx1rx1: mipi-dphy-tx1rx1@ff968000 { + compatible = "rockchip,rk3399-mipi-dphy-tx1rx1"; + reg = <0x0 0xff968000 0x0 0x8000>; + clocks = <&cru SCLK_MIPIDPHY_REF>, + <&cru SCLK_DPHY_TX1RX1_CFG>, + <&cru PCLK_VIO_GRF>, + <&cru PCLK_MIPI_DSI1>; + clock-names = "dphy-ref", "dphy-cfg", + "grf", "dsi"; + rockchip,grf = <&grf>; + power-domains = <&power RK3399_PD_VIO>; + #phy-cells = <0>; + status = "disabled"; + }; + edp: edp@ff970000 { compatible = "rockchip,rk3399-edp"; reg = <0x0 0xff970000 0x0 0x8000>;