From patchwork Sun Aug 5 17:30:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: John David Anglin X-Patchwork-Id: 10556191 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 415C4157D for ; Sun, 5 Aug 2018 17:30:34 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2DA44296A6 for ; Sun, 5 Aug 2018 17:30:34 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 22071296A7; Sun, 5 Aug 2018 17:30:34 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI,T_TVD_MIME_EPI,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7FD75296AE for ; Sun, 5 Aug 2018 17:30:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726362AbeHETfu (ORCPT ); Sun, 5 Aug 2018 15:35:50 -0400 Received: from belmont80srvr.owm.bell.net ([184.150.200.80]:36712 "EHLO mtlfep02.bell.net" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726243AbeHETft (ORCPT ); Sun, 5 Aug 2018 15:35:49 -0400 Received: from bell.net mtlfep02 184.150.200.30 by mtlfep02.bell.net with ESMTP id <20180805173031.FFAS26486.mtlfep02.bell.net@mtlspm01.bell.net> for ; Sun, 5 Aug 2018 13:30:31 -0400 Received: from [192.168.2.49] (really [70.53.62.189]) by mtlspm01.bell.net with ESMTP id <20180805173031.GKVL28394.mtlspm01.bell.net@[192.168.2.49]>; Sun, 5 Aug 2018 13:30:31 -0400 To: linux-parisc Cc: Helge Deller , James Bottomley From: John David Anglin Subject: [PATCH] parisc: Define mb() and add memory barriers to assembler unlock sequences Message-ID: Date: Sun, 5 Aug 2018 13:30:31 -0400 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 MIME-Version: 1.0 Content-Language: en-US X-Cloudmark-Analysis: v=2.2 cv=XaJm9Mx5 c=1 sm=0 tr=0 a=VCUqJnZSONuD0ISaPFNHjQ==:17 a=dapMudl6Dx4A:10 a=r77TgQKjGQsHNAKrUKIA:9 a=rVej1LWLAAAA:20 a=cH6R9-kdAAAA:8 a=FBHGMhGWAAAA:8 a=KKImMeOA8UfYesNMhnAA:9 a=QEXdDO2ut3YA:10 a=5oUhZmIK8UPkVLQt3tYA:9 a=ichUEFZdvV4A:10 a=wOv8yIheiOqzjp_GPQAA:9 a=9gvnlMMaQFpL9xblJ6ne:22 Sender: linux-parisc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-parisc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP For years I thought all parisc machines executed loads and stores in order.  However, Jeff Law recently indicated on gcc-patches that this is not correct.  There are various degrees of out-of-order execution all the way back to the PA7xxx processor series (hit-under-miss).  The PA8xxx series has full out-of-order execution for both integer operations, and loads and stores. This is described in the following article: http://web.archive.org/web/20040214092531/http://www.cpus.hp.com/technical_references/advperf.shtml For this reason, we need to define mb() and to insert a memory barrier before the store unlocking spinlocks.  This ensures that all memory accesses are complete prior to unlocking.  The ldcw instruction performs the same function on entry. Signed-off-by: John David Anglin diff --git a/arch/parisc/kernel/entry.S b/arch/parisc/kernel/entry.S index e95207c0565e..13b783ba5b0a 100644 --- a/arch/parisc/kernel/entry.S +++ b/arch/parisc/kernel/entry.S @@ -481,8 +481,10 @@ /* Release pa_tlb_lock lock without reloading lock address. */ .macro tlb_unlock0 spc,tmp #ifdef CONFIG_SMP - or,COND(=) %r0,\spc,%r0 + cmpib,COND(=),n 0,\spc,1f + sync stw \spc,0(\tmp) +1: #endif .endm diff --git a/arch/parisc/kernel/pacache.S b/arch/parisc/kernel/pacache.S index 22e6374ece44..b2bc244dca1a 100644 --- a/arch/parisc/kernel/pacache.S +++ b/arch/parisc/kernel/pacache.S @@ -352,6 +352,7 @@ ENDPROC_CFI(flush_data_cache_local) .macro tlb_unlock la,flags,tmp #ifdef CONFIG_SMP + sync ldi 1,\tmp stw \tmp,0(\la) mtsm \flags diff --git a/arch/parisc/kernel/syscall.S b/arch/parisc/kernel/syscall.S index e775f80ae28c..4886a6db42e9 100644 --- a/arch/parisc/kernel/syscall.S +++ b/arch/parisc/kernel/syscall.S @@ -633,6 +633,7 @@ cas_action: sub,<> %r28, %r25, %r0 2: stw,ma %r24, 0(%r26) /* Free lock */ + sync stw,ma %r20, 0(%sr2,%r20) #if ENABLE_LWS_DEBUG /* Clear thread register indicator */ @@ -647,6 +648,7 @@ cas_action: 3: /* Error occurred on load or store */ /* Free lock */ + sync stw %r20, 0(%sr2,%r20) #if ENABLE_LWS_DEBUG stw %r0, 4(%sr2,%r20) @@ -848,6 +850,7 @@ cas2_action: cas2_end: /* Free lock */ + sync stw,ma %r20, 0(%sr2,%r20) /* Enable interrupts */ ssm PSW_SM_I, %r0 @@ -858,6 +861,7 @@ cas2_end: 22: /* Error occurred on load or store */ /* Free lock */ + sync stw %r20, 0(%sr2,%r20) ssm PSW_SM_I, %r0 ldo 1(%r0),%r28 --- /dev/null 2018-08-04 12:32:49.880000000 -0400 +++ arch/parisc/include/asm/barrier.h 2018-08-04 13:10:48.843495530 -0400 @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __ASM_BARRIER_H +#define __ASM_BARRIER_H + +#ifndef __ASSEMBLY__ + +/* The synchronize caches instruction executes as a nop on systems in + which all memory references are performed in order. */ +#define synchronize_caches() __asm__ __volatile__ ("sync" : : : "memory") + +#if defined(CONFIG_SMP) +#define mb() do { synchronize_caches(); } while (0) +#define rmb() mb() +#define wmb() mb() +#define dma_rmb() mb() +#define dma_wmb() mb() +#else +#define mb() barrier() +#define rmb() barrier() +#define wmb() barrier() +#define dma_rmb() barrier() +#define dma_wmb() barrier() +#endif + +#define __smp_mb() mb() +#define __smp_rmb() mb() +#define __smp_wmb() mb() + +#include + +#endif /* !__ASSEMBLY__ */ +#endif /* __ASM_BARRIER_H */