From patchwork Mon Sep 6 07:15:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?TmFuY3kgTGluICjmnpfmrKPonqIp?= X-Patchwork-Id: 12476419 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2E5E8C433F5 for ; Mon, 6 Sep 2021 07:19:18 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E25946054E for ; Mon, 6 Sep 2021 07:19:17 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org E25946054E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=gYkHtFVvejekpEZH4L0dVbN+bwhlSuS/N6bFOllRwCo=; b=dP+8fBbO7GxytM 63C7PfQnfsbUhBAOI2a03SyEfzey5n9qcOTTUQEtAGdAL4vj5i5vG/cpWwMBw8y3p/09Du6Lu6gLB TdoH7wCsaI1H5MZDrJ7IRJUf4DEICvoZAI27hRz13iscevx8YnxuWV6WdWmDXVfhncdYhSNON41u5 6sAQJn0rBxVpa3BdBm7qJLl06VRqa9aEORphJcRbh53VcSLwGzxixT12CEjImHSlJtovJrFx6Go3X VTF/ERhYsh/myPWfJQonqGkg5QfWBmgKX/sNlcxHg8DuyvzJ3TDo4+Cnxd1Ck+mTkOXseu8P76gMe 9oJ4dIZToGbXbEPTuHwA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mN8rC-00HXVZ-T1; Mon, 06 Sep 2021 07:15:55 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mN8r3-00HXOw-T0; Mon, 06 Sep 2021 07:15:47 +0000 X-UUID: 2d227f09d66b4f38a660497017e51750-20210906 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=9Tvgdc6LzRAXassBC0jY2qEAwCUHrP5oDDfs3h7aBzo=; b=C1Xkc6lK6NR5CLe1q/jVM9euziXgF+7SOVAu0Yt2V1AGXxYSFjlWGlLmNSmRKd/m3skPbTySEIuYRPvB6ROFnYcfNU3Gb9mND2yFjB+Mq5S6qpAGGabIk1Wdg80Umcq5pmSguKFw8btpCVz4xDfIKWcgSWYo6BF6+S254R93dmo=; X-UUID: 2d227f09d66b4f38a660497017e51750-20210906 Received: from mtkcas67.mediatek.inc [(172.29.193.45)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 978782631; Mon, 06 Sep 2021 00:15:43 -0700 Received: from MTKMBS07N2.mediatek.inc (172.21.101.141) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 6 Sep 2021 00:15:42 -0700 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 6 Sep 2021 15:15:40 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 6 Sep 2021 15:15:40 +0800 From: Nancy.Lin To: CK Hu CC: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Matthias Brugger , "jason-jh . lin" , "Nancy . Lin" , Yongqiang Niu , , , , , , , Subject: [PATCH v5 01/16] dt-bindings: mediatek: add vdosys1 RDMA definition for mt8195 Date: Mon, 6 Sep 2021 15:15:24 +0800 Message-ID: <20210906071539.12953-2-nancy.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210906071539.12953-1-nancy.lin@mediatek.com> References: <20210906071539.12953-1-nancy.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210906_001545_993182_7A873E1E X-CRM114-Status: GOOD ( 14.73 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add vdosys1 RDMA definition. Signed-off-by: Nancy.Lin --- .../display/mediatek/mediatek,mdp-rdma.yaml | 77 +++++++++++++++++++ 1 file changed, 77 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml new file mode 100644 index 000000000000..3610093848e1 --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,mdp-rdma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: mediatek display MDP RDMA + +maintainers: + - CK Hu + +description: | + The mediatek display MDP RDMA stands for Read Direct Memory Access. + It provides real time data to the back-end panel driver, such as DSI, + DPI and DP_INTF. + It contains one line buffer to store the sufficient pixel data. + RDMA device node must be siblings to the central MMSYS_CONFIG node. + For a description of the MMSYS_CONFIG binding, see + Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml for details. + +properties: + compatible: + oneOf: + - items: + - const: mediatek,mt8195-vdo1-rdma + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + power-domains: + description: A phandle and PM domain specifier as defined by bindings of + the power controller specified by phandle. See + Documentation/devicetree/bindings/power/power-domain.yaml for details. + + clocks: + items: + - description: RDMA Clock + + iommus: + description: + This property should point to the respective IOMMU block with master port as argument, + see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details. + + mediatek,gce-client-reg: + description: + The register of display function block to be set by gce. There are 4 arguments, + such as gce node, subsys id, offset and register size. The subsys id that is + mapping to the register of display function blocks is defined in the gce header + include/include/dt-bindings/gce/-gce.h of each chips. + $ref: /schemas/types.yaml#/definitions/phandle-array + maxItems: 1 + +required: + - compatible + - reg + - power-domains + - clocks + - iommus + +additionalProperties: false + +examples: + - | + + vdo1_rdma0: vdo1_rdma@1c104000 { + compatible = "mediatek,mt8195-vdo1-rdma"; + reg = <0 0x1c104000 0 0x1000>; + interrupts = ; + clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x4000 0x1000>; + }; + From patchwork Mon Sep 6 07:15:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?TmFuY3kgTGluICjmnpfmrKPonqIp?= X-Patchwork-Id: 12476417 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4AEF9C433F5 for ; Mon, 6 Sep 2021 07:19:09 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 17D8160F43 for ; Mon, 6 Sep 2021 07:19:09 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 17D8160F43 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=u4d6wRTlNUJyR2dpLkw/fx25WaDOBfwki0R2PR9Myak=; b=dtpepUwIAgdu4G 1+Io4WBWGD9Sra+akT0NkZZIDoP7PGqRv0HIkTZCE+Xbc1OvAQ+/cHSjgGAZPYELYX5c2VELZ0LCo obAmHRE60BZtqw9Zgp6XhuW8Kwg6MQMuSJPO2exdqwiQtZWnn+tcg5K4JlSjbT/2Er5M6Tj9DrqHK K6L4A9MTkwWx1+eQOCNoB+TgHFnwHmAO1sjhCnahbHgbP5ISIX7f7FqxNznpZbpuFNPdOXeMJBuvp h0zhyhnqAkq6qGq2C/bro3jmEYEkBM6RhJfcFHFfD/gT/KnbGanyMSm4++KB4fuP9PZd5nmSWJm7l BufrBPB3F6YRqmioOqHw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mN8si-00HYI4-QJ; Mon, 06 Sep 2021 07:17:29 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mN8r5-00HXOw-N6; Mon, 06 Sep 2021 07:15:49 +0000 X-UUID: 35e2e406aa024d60b3dbfbd1f02eb439-20210906 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=RG8MNrooymgofOFSX4mISTCPYgvW852sUNq76/gdBe0=; b=g/KMvfLjIFzicd/PkBJoGKmJUVHXIPz9oOxySfMM7mSHYlzqdGmBoNfG+hDkCdidHSAnN6DTRBCR8Y2NnT3eBUy5SwKJB36fboRvlerMY3XDmqHFBQsYjDXsSzP3GciMpTxfPSQZaC2u+sYa4v2tLQadRUW3GAAmVNTCMgw1AOU=; X-UUID: 35e2e406aa024d60b3dbfbd1f02eb439-20210906 Received: from mtkcas67.mediatek.inc [(172.29.193.45)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1713708043; Mon, 06 Sep 2021 00:15:43 -0700 Received: from MTKMBS07N2.mediatek.inc (172.21.101.141) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 6 Sep 2021 00:15:42 -0700 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 6 Sep 2021 15:15:40 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 6 Sep 2021 15:15:40 +0800 From: Nancy.Lin To: CK Hu CC: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Matthias Brugger , "jason-jh . lin" , "Nancy . Lin" , Yongqiang Niu , , , , , , , Subject: [PATCH v5 02/16] dt-bindings: mediatek: add vdosys1 MERGE property for mt8195 Date: Mon, 6 Sep 2021 15:15:25 +0800 Message-ID: <20210906071539.12953-3-nancy.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210906071539.12953-1-nancy.lin@mediatek.com> References: <20210906071539.12953-1-nancy.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210906_001547_797777_36C0F71C X-CRM114-Status: UNSURE ( 9.36 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org MT8195 vdosys1 merge1 to merge4 have HW mute function. Add MERGE additional mute property description. Signed-off-by: Nancy.Lin --- .../devicetree/bindings/display/mediatek/mediatek,merge.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml index b15c6e17b421..5be3715ddc56 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml @@ -52,6 +52,9 @@ properties: ultra and preulra command to SMI to speed up the data rate. type: boolean + mediatek,merge-mute: + description: Support mute function. Mute the content of merge output. + type: boolean mediatek,gce-client-reg: description: From patchwork Mon Sep 6 07:15:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?TmFuY3kgTGluICjmnpfmrKPonqIp?= X-Patchwork-Id: 12476449 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7A737C433EF for ; Mon, 6 Sep 2021 07:24:39 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4505760724 for ; Mon, 6 Sep 2021 07:24:39 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 4505760724 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=HF7O1On+3gG8NkRmZSQCIoQxkggrm1CqkbHR2HEuU60=; b=gK41fnyyHL/iwN CVOmzEt4bEbdt717vexxcEN01oL3btizo2D8sBVq633MXCEeMZlGDDOx+3YJ366UL4oPIetSQsPvM cDBKHbhboSnXJNoQyKbtxoTdFmUDQvKEb3yievVH+/VQ7b72RX7AiHIjXjHwYFlhpGbHkcxfWf4lg eG642di7PepHxsK0otxbVnIH12GMPc9iikjfNUPGpv9oLbJZQgr+Ci2KiUK3EZZHFuUH3cX3qcYsk BPzpIGPX5lZzBQUkbAoMmrlkKDbYQAD4exaoYpKlXP9C7GKdWZ0vYd+XOUJvKjIsfj4+DXTattQ2A EMDxTZ7Zhj/rNf/cLX8A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mN8x3-00HaWf-5N; Mon, 06 Sep 2021 07:21:58 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mN8rA-00HXPX-9e; Mon, 06 Sep 2021 07:15:54 +0000 X-UUID: c1f95456fa984810ae850c04bbf4db31-20210906 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=CzdzTbRSdVSPeYr8HGtssRWSXl2lsUzo6pdIA6adn6w=; b=MUZ2XqGTxNomW8JGlFUJWkhJWg+sak4LeSHGfh8Rh+/OvR4kjNfzMOR7VgoOODYEI21uh74ELtEwENyB0fECD0UTH6hIOgTyiIHYB7wX8NY78ElPkD8a9VExonnkhy0lHeDULVUzjMIrq00Sf+r66SHcunZzhN7bqcYCJh6hj8s=; X-UUID: c1f95456fa984810ae850c04bbf4db31-20210906 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1198697006; Mon, 06 Sep 2021 00:15:43 -0700 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 6 Sep 2021 00:15:42 -0700 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 6 Sep 2021 15:15:40 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 6 Sep 2021 15:15:41 +0800 From: Nancy.Lin To: CK Hu CC: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Matthias Brugger , "jason-jh . lin" , "Nancy . Lin" , Yongqiang Niu , , , , , , , Subject: [PATCH v5 03/16] dt-bindings: mediatek: add ethdr definition for mt8195 Date: Mon, 6 Sep 2021 15:15:26 +0800 Message-ID: <20210906071539.12953-4-nancy.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210906071539.12953-1-nancy.lin@mediatek.com> References: <20210906071539.12953-1-nancy.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210906_001552_382395_CF4D1D19 X-CRM114-Status: GOOD ( 15.05 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add vdosys1 ETHDR definition. Signed-off-by: Nancy.Lin --- .../display/mediatek/mediatek,ethdr.yaml | 144 ++++++++++++++++++ 1 file changed, 144 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml new file mode 100644 index 000000000000..64d5349cdf8f --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml @@ -0,0 +1,144 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,ethdr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: mediatek ethdr Device Tree Bindings + +maintainers: + - CK Hu + - Nancy.Lin + +description: | + ETHDR is designed for HDR video and graphics conversion in the external display path. + It handles multiple HDR input types and performs tone mapping, color space/color + format conversion, and then combine different layers, output the required HDR or + SDR signal to the subsequent display path. This engine is composed of two video + frontends, two graphic frontends, one video backend and a mixer. + +properties: + compatible: + items: + - const: mediatek,mt8195-disp-ethdr + reg: + maxItems: 7 + reg-names: + items: + - const: mixer + - const: vdo_fe0 + - const: vdo_fe1 + - const: gfx_fe0 + - const: gfx_fe1 + - const: vdo_be + - const: adl_ds + interrupts: + minItems: 1 + iommus: + description: The compatible property is DMA function blocks. + Should point to the respective IOMMU block with master port as argument, + see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for + details. + minItems: 1 + maxItems: 2 + clocks: + items: + - description: mixer clock + - description: video frontend 0 clock + - description: video frontend 1 clock + - description: graphic frontend 0 clock + - description: graphic frontend 1 clock + - description: video backend clock + - description: autodownload and menuload clock + - description: video frontend 0 async clock + - description: video frontend 1 async clock + - description: graphic frontend 0 async clock + - description: graphic frontend 1 async clock + - description: video backend async clock + - description: ethdr top clock + clock-names: + items: + - const: mixer + - const: vdo_fe0 + - const: vdo_fe1 + - const: gfx_fe0 + - const: gfx_fe1 + - const: vdo_be + - const: adl_ds + - const: vdo_fe0_async + - const: vdo_fe1_async + - const: gfx_fe0_async + - const: gfx_fe1_async + - const: vdo_be_async + - const: ethdr_top + power-domains: + maxItems: 1 + resets: + maxItems: 5 + mediatek,gce-client-reg: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: The register of display function block to be set by gce. + There are 4 arguments in this property, gce node, subsys id, offset and + register size. The subsys id is defined in the gce header of each chips + include/include/dt-bindings/gce/-gce.h, mapping to the register of + display function block. + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + +additionalProperties: false + +examples: + - | + + disp_ethdr@1c114000 { + compatible = "mediatek,mt8195-disp-ethdr"; + reg = <0 0x1c114000 0 0x1000>, + <0 0x1c115000 0 0x1000>, + <0 0x1c117000 0 0x1000>, + <0 0x1c119000 0 0x1000>, + <0 0x1c11A000 0 0x1000>, + <0 0x1c11B000 0 0x1000>, + <0 0x1c11C000 0 0x1000>; + reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1", + "vdo_be", "adl_ds"; + mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x4000 0x1000>, + <&gce1 SUBSYS_1c11XXXX 0x5000 0x1000>, + <&gce1 SUBSYS_1c11XXXX 0x7000 0x1000>, + <&gce1 SUBSYS_1c11XXXX 0x9000 0x1000>, + <&gce1 SUBSYS_1c11XXXX 0xA000 0x1000>, + <&gce1 SUBSYS_1c11XXXX 0xB000 0x1000>, + <&gce1 SUBSYS_1c11XXXX 0xC000 0x1000>; + clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>, + <&vdosys1 CLK_VDO1_HDR_VDO_FE0>, + <&vdosys1 CLK_VDO1_HDR_VDO_FE1>, + <&vdosys1 CLK_VDO1_HDR_GFX_FE0>, + <&vdosys1 CLK_VDO1_HDR_GFX_FE1>, + <&vdosys1 CLK_VDO1_HDR_VDO_BE>, + <&vdosys1 CLK_VDO1_26M_SLOW>, + <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>, + <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>, + <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>, + <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>, + <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>, + <&topckgen CLK_TOP_ETHDR_SEL>; + clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1", + "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async", + "gfx_fe0_async", "gfx_fe1_async","vdo_be_async", + "ethdr_top"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>, + <&iommu_vpp M4U_PORT_L3_HDR_ADL>; + interrupts = ; /* disp mixer */ + resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>, + <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>, + <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>, + <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>, + <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>; + }; + +... From patchwork Mon Sep 6 07:15:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?TmFuY3kgTGluICjmnpfmrKPonqIp?= X-Patchwork-Id: 12476413 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DD74FC433EF for ; Mon, 6 Sep 2021 07:18:37 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A75476054E for ; Mon, 6 Sep 2021 07:18:37 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org A75476054E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=7v9OdbHWYJQfwNLgJF3Z/0f9wDwMgBpP6ocWBYQKUJ8=; b=ATVxaM4vbigRPc sHU/ChcTCCQAWbEDZzfONAu2zwI4JDf4TZGV8cRe36ElXCwdGt0nfvxOkeXnvV6uKx+9dLHA+9Tlq ZUsbUdwPMEtwKqm0hncbf46PiCAHyuAlLBGITDK3fwmTnhs6G59CjKtLDmxseUci1iQC5j6G96Aly gB31wv+ixPpzXsdcBDwwQZbz/xotcXf8epp36VWFZ4Y/naWvcPD9n4yUj7RdE5D5/Gg6g2d2hg5KV nq+TtN5CobJ9V7KLb0Q42Ga9ZDgr4S0YzwTnYfnSwM6AYlMr89qgRhAx4CvZzizD3GbWjg4JJ8Av5 5kfrsFqdEfR7XHOYkOEQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mN8rl-00HXnk-Od; Mon, 06 Sep 2021 07:16:29 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mN8r4-00HXPX-02; Mon, 06 Sep 2021 07:15:49 +0000 X-UUID: 42d02745ccd24e6b8638e5259f0d945f-20210906 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=WU6Qw8JhsqsDf5kyJ/ZjIjq/RAJ2Kdea5Ltf9U6bIIs=; b=BogeBtXQ1riz6y7TkqrA+ZGuCWYAkbutCq1TKWJECWZLuW6m861MqRNU1ymxH/bItnPDDHFYp0Hbzt2WGZjabb15QwhYA6NDa6LHeJxZLztscHkhi5CPmw1ANC1X4NtncFh6YPkn7+WATgsgzmZeGMDIbCNz2n4ZMIvYCXz2jrI=; X-UUID: 42d02745ccd24e6b8638e5259f0d945f-20210906 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1879645313; Mon, 06 Sep 2021 00:15:43 -0700 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 6 Sep 2021 00:15:42 -0700 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 6 Sep 2021 15:15:41 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 6 Sep 2021 15:15:41 +0800 From: Nancy.Lin To: CK Hu CC: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Matthias Brugger , "jason-jh . lin" , "Nancy . Lin" , Yongqiang Niu , , , , , , , Subject: [PATCH v5 04/16] dt-bindings: reset: mt8195: add vdosys1 reset control bit Date: Mon, 6 Sep 2021 15:15:27 +0800 Message-ID: <20210906071539.12953-5-nancy.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210906071539.12953-1-nancy.lin@mediatek.com> References: <20210906071539.12953-1-nancy.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210906_001546_097515_F05A0348 X-CRM114-Status: UNSURE ( 8.95 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add vdosys1 reset control bit for MT8195 platform. Signed-off-by: Nancy.Lin --- include/dt-bindings/reset/mt8195-resets.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/include/dt-bindings/reset/mt8195-resets.h b/include/dt-bindings/reset/mt8195-resets.h index a26bccc8b957..eaaa882c09bd 100644 --- a/include/dt-bindings/reset/mt8195-resets.h +++ b/include/dt-bindings/reset/mt8195-resets.h @@ -26,4 +26,16 @@ #define MT8195_TOPRGU_SW_RST_NUM 16 +/* VDOSYS1 */ +#define MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC 25 +#define MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC 26 +#define MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC 27 +#define MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC 28 +#define MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC 29 +#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC 51 +#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC 52 +#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC 53 +#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC 54 +#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC 55 + #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */ From patchwork Mon Sep 6 07:15:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?TmFuY3kgTGluICjmnpfmrKPonqIp?= X-Patchwork-Id: 12476431 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AE2F5C433EF for ; Mon, 6 Sep 2021 07:22:58 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7875360724 for ; Mon, 6 Sep 2021 07:22:58 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 7875360724 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=BVK3BT0HITAq6YsJTnaD4gHlkc0aNsM3jYzhUDpwYxk=; b=hLUpREjSjutueq yHEOfSfmU4WNhdLrcbQbNqYbbb7nYhsyXiH1gKwvr4GYDLeRSsEyxewF0Gc2TjA31uTnft+BH0PpB +8g2nt0zhwj4eFDUX5KwYDq0sFlQe4Bwb1RnFncijYONCb8myl1q50sa1amAtEyTDrJdf3/Jxz2qv NDbq/1ncT7XkYNJ4OY4sXEWNYD+c5xXrG9PPLaUQ/WkjLjwQX0QuiMUMgOGInZgbq6UnLjxdDcfe/ MAboGdbelhr7Uz4EmOjzUjZbA4UyBh/l+uo5wiMIA9k6BNeeLGVfayDgtkgPOciBtXZNdJ9X+Kaeb 7Q5kyAO6EVWGvxyc0YNQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mN8vP-00HZjP-0Y; Mon, 06 Sep 2021 07:20:15 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mN8r8-00HXPS-1C; Mon, 06 Sep 2021 07:15:53 +0000 X-UUID: bd5f1389027b47e589aa4f013b564266-20210906 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=F9cYmP6qWegEieoanL8lAKgAtxsddsRbgP/ydTffYL4=; b=Ix9f6a69fwkVht8VsIJ3kHuJvvuoiIGjUnG55/7hHHTCtfzcbbHy5WUotfpD7r9YYPq2Z4u2JlNnoJzXc0yu/Uw3X4oUaspK2kEtIDEq6J725+Uz7wAfzisbrk9NbcQtu9Oie5/c5TOkjrMD5YwpmkUi0pOav1KAFx6kxYmEoqM=; X-UUID: bd5f1389027b47e589aa4f013b564266-20210906 Received: from mtkcas67.mediatek.inc [(172.29.193.45)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 288284604; Mon, 06 Sep 2021 00:15:44 -0700 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 6 Sep 2021 00:15:43 -0700 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 6 Sep 2021 15:15:41 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 6 Sep 2021 15:15:41 +0800 From: Nancy.Lin To: CK Hu CC: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Matthias Brugger , "jason-jh . lin" , "Nancy . Lin" , Yongqiang Niu , , , , , , , Subject: [PATCH v5 05/16] arm64: dts: mt8195: add display node for vdosys1 Date: Mon, 6 Sep 2021 15:15:28 +0800 Message-ID: <20210906071539.12953-6-nancy.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210906071539.12953-1-nancy.lin@mediatek.com> References: <20210906071539.12953-1-nancy.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210906_001550_165572_633E48A2 X-CRM114-Status: GOOD ( 10.40 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add display node for vdosys1. Signed-off-by: Nancy.Lin --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 221 +++++++++++++++++++++++ 1 file changed, 221 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 4064a92e28a5..6ea6d0c6d840 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -10,6 +10,7 @@ #include #include #include +#include / { compatible = "mediatek,mt8195"; @@ -20,6 +21,21 @@ aliases { gce0 = &gce0; gce1 = &gce1; + mutex0 = &mutex; + mutex1 = &mutex1; + merge1 = &merge1; + merge2 = &merge2; + merge3 = &merge3; + merge4 = &merge4; + merge5 = &merge5; + vdo1_rdma0 = &vdo1_rdma0; + vdo1_rdma1 = &vdo1_rdma1; + vdo1_rdma2 = &vdo1_rdma2; + vdo1_rdma3 = &vdo1_rdma3; + vdo1_rdma4 = &vdo1_rdma4; + vdo1_rdma5 = &vdo1_rdma5; + vdo1_rdma6 = &vdo1_rdma6; + vdo1_rdma7 = &vdo1_rdma7; }; clocks { @@ -1272,7 +1288,212 @@ vdosys1: syscon@1c100000 { compatible = "mediatek,mt8195-vdosys1", "syscon"; reg = <0 0x1c100000 0 0x1000>; + mboxes = <&gce1 1 CMDQ_THR_PRIO_4>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x0000 0x1000>; #clock-cells = <1>; + #reset-cells = <1>; + }; + + mutex1: disp_mutex0@1c101000 { + compatible = "mediatek,mt8195-disp-mutex"; + reg = <0 0x1c101000 0 0x1000>; + reg-names = "vdo1_mutex"; + interrupts = ; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + clocks = <&vdosys1 CLK_VDO1_DISP_MUTEX>; + clock-names = "vdo1_mutex"; + mediatek,gce-events = ; + }; + + vdo1_rdma0: vdo1_rdma@1c104000 { + compatible = "mediatek,mt8195-vdo1-rdma"; + reg = <0 0x1c104000 0 0x1000>; + interrupts = ; + clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x4000 0x1000>; + }; + + vdo1_rdma1: vdo1_rdma@1c105000 { + compatible = "mediatek,mt8195-vdo1-rdma"; + reg = <0 0x1c105000 0 0x1000>; + interrupts = ; + clocks = <&vdosys1 CLK_VDO1_MDP_RDMA1>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA1>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x5000 0x1000>; + }; + + vdo1_rdma2: vdo1_rdma@1c106000 { + compatible = "mediatek,mt8195-vdo1-rdma"; + reg = <0 0x1c106000 0 0x1000>; + interrupts = ; + clocks = <&vdosys1 CLK_VDO1_MDP_RDMA2>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA2>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x6000 0x1000>; + }; + + vdo1_rdma3: vdo1_rdma@1c107000 { + compatible = "mediatek,mt8195-vdo1-rdma"; + reg = <0 0x1c107000 0 0x1000>; + interrupts = ; + clocks = <&vdosys1 CLK_VDO1_MDP_RDMA3>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA3>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x7000 0x1000>; + }; + + vdo1_rdma4: vdo1_rdma@1c108000 { + compatible = "mediatek,mt8195-vdo1-rdma"; + reg = <0 0x1c108000 0 0x1000>; + interrupts = ; + clocks = <&vdosys1 CLK_VDO1_MDP_RDMA4>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA4>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x8000 0x1000>; + }; + + vdo1_rdma5: vdo1_rdma@1c109000 { + compatible = "mediatek,mt8195-vdo1-rdma"; + reg = <0 0x1c109000 0 0x1000>; + interrupts = ; + clocks = <&vdosys1 CLK_VDO1_MDP_RDMA5>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA5>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x9000 0x1000>; + }; + + vdo1_rdma6: vdo1_rdma@1c10a000 { + compatible = "mediatek,mt8195-vdo1-rdma"; + reg = <0 0x1c10a000 0 0x1000>; + interrupts = ; + clocks = <&vdosys1 CLK_VDO1_MDP_RDMA6>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA6>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xa000 0x1000>; + }; + + vdo1_rdma7: vdo1_rdma@1c10b000 { + compatible = "mediatek,mt8195-vdo1-rdma"; + reg = <0 0x1c10b000 0 0x1000>; + interrupts = ; + clocks = <&vdosys1 CLK_VDO1_MDP_RDMA7>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA7>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xb000 0x1000>; + }; + + merge1: disp_vpp_merge@1c10c000 { + compatible = "mediatek,mt8195-disp-merge"; + reg = <0 0x1c10c000 0 0x1000>; + interrupts = ; + clocks = <&vdosys1 CLK_VDO1_VPP_MERGE0>, + <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>; + clock-names = "merge","merge_async"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xc000 0x1000>; + mediatek,merge-mute = <1>; + resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC>; + }; + + merge2: disp_vpp_merge@1c10d000 { + compatible = "mediatek,mt8195-disp-merge"; + reg = <0 0x1c10d000 0 0x1000>; + interrupts = ; + clocks = <&vdosys1 CLK_VDO1_VPP_MERGE1>, + <&vdosys1 CLK_VDO1_MERGE1_DL_ASYNC>; + clock-names = "merge","merge_async"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xd000 0x1000>; + mediatek,merge-mute = <1>; + resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC>; + }; + + merge3: disp_vpp_merge@1c10e000 { + compatible = "mediatek,mt8195-disp-merge"; + reg = <0 0x1c10e000 0 0x1000>; + interrupts = ; + clocks = <&vdosys1 CLK_VDO1_VPP_MERGE2>, + <&vdosys1 CLK_VDO1_MERGE2_DL_ASYNC>; + clock-names = "merge","merge_async"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xe000 0x1000>; + mediatek,merge-mute = <1>; + resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC>; + }; + + merge4: disp_vpp_merge@1c10f000 { + compatible = "mediatek,mt8195-disp-merge"; + reg = <0 0x1c10f000 0 0x1000>; + interrupts = ; + clocks = <&vdosys1 CLK_VDO1_VPP_MERGE3>, + <&vdosys1 CLK_VDO1_MERGE3_DL_ASYNC>; + clock-names = "merge","merge_async"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xf000 0x1000>; + mediatek,merge-mute = <1>; + resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC>; + }; + + merge5: disp_vpp_merge5@1c110000 { + compatible = "mediatek,mt8195-disp-merge"; + reg = <0 0x1c110000 0 0x1000>; + interrupts = ; + clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>, + <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>; + clock-names = "merge","merge_async"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x0000 0x1000>; + mediatek,merge-fifo-en = <1>; + resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>; + }; + + disp_ethdr@1c114000 { + compatible = "mediatek,mt8195-disp-ethdr"; + reg = <0 0x1c114000 0 0x1000>, + <0 0x1c115000 0 0x1000>, + <0 0x1c117000 0 0x1000>, + <0 0x1c119000 0 0x1000>, + <0 0x1c11A000 0 0x1000>, + <0 0x1c11B000 0 0x1000>, + <0 0x1c11C000 0 0x1000>; + reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1", + "vdo_be", "adl_ds"; + mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x4000 0x1000>, + <&gce1 SUBSYS_1c11XXXX 0x5000 0x1000>, + <&gce1 SUBSYS_1c11XXXX 0x7000 0x1000>, + <&gce1 SUBSYS_1c11XXXX 0x9000 0x1000>, + <&gce1 SUBSYS_1c11XXXX 0xA000 0x1000>, + <&gce1 SUBSYS_1c11XXXX 0xB000 0x1000>, + <&gce1 SUBSYS_1c11XXXX 0xC000 0x1000>; + clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>, + <&vdosys1 CLK_VDO1_HDR_VDO_FE0>, + <&vdosys1 CLK_VDO1_HDR_VDO_FE1>, + <&vdosys1 CLK_VDO1_HDR_GFX_FE0>, + <&vdosys1 CLK_VDO1_HDR_GFX_FE1>, + <&vdosys1 CLK_VDO1_HDR_VDO_BE>, + <&vdosys1 CLK_VDO1_26M_SLOW>, + <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>, + <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>, + <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>, + <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>, + <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>, + <&topckgen CLK_TOP_ETHDR_SEL>; + clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1", + "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async", + "gfx_fe0_async", "gfx_fe1_async","vdo_be_async", + "ethdr_top"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>, + <&iommu_vpp M4U_PORT_L3_HDR_ADL>; + interrupts = ; /* disp mixer */ + resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>, + <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>, + <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>, + <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>, + <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>; }; }; From patchwork Mon Sep 6 07:15:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?TmFuY3kgTGluICjmnpfmrKPonqIp?= X-Patchwork-Id: 12476425 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, UPPERCASE_50_75,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 069B4C433EF for ; Mon, 6 Sep 2021 07:20:03 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C48B16054E for ; Mon, 6 Sep 2021 07:20:02 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org C48B16054E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=fNYdIfnZQZIWkbvVbbM6RJOAhMR0hvC2fW8U2rMGb5M=; b=lxr2n0czxme1c/ C/5WV4yPUmX1eqXo/oK4icOLqBZJKFiTe6GpXnk4PTUkQuVstcX06Hmso++rN9xDipWnwFm0rwj1N yVFhyzCyutImQPrxjbAfsjVuy18SY/qIj+/RMOXJbyF9yfM9xxIlNFhXsXmmeJK3YMOFEZIgS0E/X ZwaD+FpdzjL6YcS/SW7od5pKyogbtUy6fuE2mVF4AyIVDC8e6Iu2K0/h7yNA+zywZxOhANJT8neKW +Q/OmL41BmIh2zik/hbfhmVN3Z0ewoNcm4DlqadENjaWLpTWmHTuQuwm6b+ByvXeMwTVAuNqUP3V0 1oXmIHGdXnAciHeUD8PA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mN8sL-00HY7U-PG; Mon, 06 Sep 2021 07:17:05 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mN8r5-00HXPS-TT; Mon, 06 Sep 2021 07:15:49 +0000 X-UUID: 23d3c73acf1f4e64a5255de06bbffad5-20210906 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=Ggbcot565kbb9R4pktLZmDuivO9g4EFK2Mpwo/xFBuQ=; b=gE2SjJTl54QddFnOErhK4zA+lwjt9jshGY9klxxW6lciBk5ppA1NtFuWP8nFTmNJyUUGXl7WmIX2OJjESlWkQ4/pRk698BOAajLBMtY9G5diGdRrMlqSd9axYprXdTtEZyN3HRnw3eYiVXXrCH7eMnL4foh1ejcUndGXyyoPZX4=; X-UUID: 23d3c73acf1f4e64a5255de06bbffad5-20210906 Received: from mtkcas67.mediatek.inc [(172.29.193.45)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 605522735; Mon, 06 Sep 2021 00:15:44 -0700 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 6 Sep 2021 00:15:44 -0700 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 6 Sep 2021 15:15:41 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 6 Sep 2021 15:15:41 +0800 From: Nancy.Lin To: CK Hu CC: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Matthias Brugger , "jason-jh . lin" , "Nancy . Lin" , Yongqiang Niu , , , , , , , Subject: [PATCH v5 06/16] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1 Date: Mon, 6 Sep 2021 15:15:29 +0800 Message-ID: <20210906071539.12953-7-nancy.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210906071539.12953-1-nancy.lin@mediatek.com> References: <20210906071539.12953-1-nancy.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210906_001548_013167_37A1B70E X-CRM114-Status: GOOD ( 12.42 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add mt8195 vdosys1 clock driver name and routing table to the driver data of mtk-mmsys. Signed-off-by: Nancy.Lin --- drivers/soc/mediatek/mt8195-mmsys.h | 136 +++++++++++++++++++++++++ drivers/soc/mediatek/mtk-mmsys.c | 10 ++ include/linux/soc/mediatek/mtk-mmsys.h | 2 + 3 files changed, 148 insertions(+) diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h index 0c97a5f016c1..f19ec72c1243 100644 --- a/drivers/soc/mediatek/mt8195-mmsys.h +++ b/drivers/soc/mediatek/mt8195-mmsys.h @@ -59,6 +59,70 @@ #define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 << 16) #define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE (3 << 16) +#define MT8195_VDO1_VPP_MERGE0_P0_SEL_IN 0xf04 +#define MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0 (1 << 0) + +#define MT8195_VDO1_VPP_MERGE0_P1_SEL_IN 0xf08 +#define MT8195_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1 (1 << 0) + +#define MT8195_VDO1_DISP_DPI1_SEL_IN 0xf10 +#define MT8195_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT (0 << 0) + +#define MT8195_VDO1_DISP_DP_INTF0_SEL_IN 0xf14 +#define MT8195_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT (0 << 0) + +#define MT8195_VDO1_MERGE4_SOUT_SEL 0xf18 +#define MT8195_MERGE4_SOUT_TO_DPI1_SEL (2 << 0) +#define MT8195_MERGE4_SOUT_TO_DP_INTF0_SEL (3 << 0) + +#define MT8195_VDO1_MIXER_IN1_SEL_IN 0xf24 +#define MT8195_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT (1 << 0) + +#define MT8195_VDO1_MIXER_IN2_SEL_IN 0xf28 +#define MT8195_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT (1 << 0) + +#define MT8195_VDO1_MIXER_IN3_SEL_IN 0xf2c +#define MT8195_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT (1 << 0) + +#define MT8195_VDO1_MIXER_IN4_SEL_IN 0xf30 +#define MT8195_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT (1 << 0) + +#define MT8195_VDO1_MIXER_OUT_SOUT_SEL 0xf34 +#define MT8195_MIXER_SOUT_TO_MERGE4_ASYNC_SEL (1 << 0) + +#define MT8195_VDO1_VPP_MERGE1_P0_SEL_IN 0xf3c +#define MT8195_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2 (1 << 0) + +#define MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL 0xf40 +#define MT8195_SOUT_TO_MIXER_IN1_SEL (1 << 0) + +#define MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL 0xf44 +#define MT8195_SOUT_TO_MIXER_IN2_SEL (1 << 0) + +#define MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL 0xf48 +#define MT8195_SOUT_TO_MIXER_IN3_SEL (1 << 0) + +#define MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL 0xf4c +#define MT8195_SOUT_TO_MIXER_IN4_SEL (1 << 0) + +#define MT8195_VDO1_MERGE4_ASYNC_SEL_IN 0xf50 +#define MT8195_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT (1 << 0) + +#define MT8195_VDO1_MIXER_IN1_SOUT_SEL 0xf58 +#define MT8195_MIXER_IN1_SOUT_TO_DISP_MIXER (0 << 0) + +#define MT8195_VDO1_MIXER_IN2_SOUT_SEL 0xf5c +#define MT8195_MIXER_IN2_SOUT_TO_DISP_MIXER (0 << 0) + +#define MT8195_VDO1_MIXER_IN3_SOUT_SEL 0xf60 +#define MT8195_MIXER_IN3_SOUT_TO_DISP_MIXER (0 << 0) + +#define MT8195_VDO1_MIXER_IN4_SOUT_SEL 0xf64 +#define MT8195_MIXER_IN4_SOUT_TO_DISP_MIXER (0 << 0) + +#define MT8195_VDO1_MIXER_SOUT_SEL_IN 0xf68 +#define MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER (0 << 0) + static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = { { DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, @@ -108,6 +172,78 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = { DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0, MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_DP_INTF0, MT8195_SOUT_VPP_MERGE_TO_DP_INTF0 + }, { + DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5, + MT8195_VDO1_VPP_MERGE0_P0_SEL_IN, GENMASK(0, 0), + MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0 + }, { + DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5, + MT8195_VDO1_VPP_MERGE0_P1_SEL_IN, GENMASK(0, 0), + MT8195_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1 + }, { + DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5, + MT8195_VDO1_VPP_MERGE1_P0_SEL_IN, GENMASK(0, 0), + MT8195_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2 + }, { + DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5, + MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL, GENMASK(1, 0), + MT8195_SOUT_TO_MIXER_IN1_SEL + }, { + DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5, + MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL, GENMASK(1, 0), + MT8195_SOUT_TO_MIXER_IN2_SEL + }, { + DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5, + MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL, GENMASK(1, 0), + MT8195_SOUT_TO_MIXER_IN3_SEL + }, { + DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5, + MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL, GENMASK(1, 0), + MT8195_SOUT_TO_MIXER_IN4_SEL + }, { + DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5, + MT8195_VDO1_MIXER_OUT_SOUT_SEL, GENMASK(0, 0), + MT8195_MIXER_SOUT_TO_MERGE4_ASYNC_SEL + }, { + DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5, + MT8195_VDO1_MIXER_IN1_SEL_IN, GENMASK(0, 0), + MT8195_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT + }, { + DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5, + MT8195_VDO1_MIXER_IN2_SEL_IN, GENMASK(0, 0), + MT8195_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT + }, { + DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5, + MT8195_VDO1_MIXER_IN3_SEL_IN, GENMASK(0, 0), + MT8195_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT + }, { + DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5, + MT8195_VDO1_MIXER_IN4_SEL_IN, GENMASK(0, 0), + MT8195_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT + }, { + DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5, + MT8195_VDO1_MIXER_SOUT_SEL_IN, GENMASK(2, 0), + MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER + }, { + DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5, + MT8195_VDO1_MERGE4_ASYNC_SEL_IN, GENMASK(2, 0), + MT8195_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT + }, { + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1, + MT8195_VDO1_DISP_DPI1_SEL_IN, GENMASK(1, 0), + MT8195_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT + }, { + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1, + MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0), + MT8195_MERGE4_SOUT_TO_DPI1_SEL + }, { + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1, + MT8195_VDO1_DISP_DP_INTF0_SEL_IN, GENMASK(1, 0), + MT8195_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT + }, { + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1, + MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0), + MT8195_MERGE4_SOUT_TO_DP_INTF0_SEL } }; diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index 1c60650c7adb..5ad2cc796f5b 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -68,6 +68,12 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = { .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table), }; +static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = { + .clk_driver = "clk-mt8195-vdo1", + .routes = mmsys_mt8195_routing_table, + .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table), +}; + struct mtk_mmsys { void __iomem *regs; const struct mtk_mmsys_driver_data *data; @@ -251,6 +257,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = { .compatible = "mediatek,mt8195-vdosys0", .data = &mt8195_vdosys0_driver_data, }, + { + .compatible = "mediatek,mt8195-vdosys1", + .data = &mt8195_vdosys1_driver_data, + }, { } }; diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index 6d6ece48b61e..619392221a52 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -18,6 +18,7 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_COLOR1, DDP_COMPONENT_DITHER, DDP_COMPONENT_DP_INTF0, + DDP_COMPONENT_DP_INTF1, DDP_COMPONENT_DPI0, DDP_COMPONENT_DPI1, DDP_COMPONENT_DSC0, @@ -38,6 +39,7 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_OVL_2L1, + DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_OVL1, DDP_COMPONENT_PWM0, DDP_COMPONENT_PWM1, From patchwork Mon Sep 6 07:15:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?TmFuY3kgTGluICjmnpfmrKPonqIp?= X-Patchwork-Id: 12476423 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A1B0BC433F5 for ; Mon, 6 Sep 2021 07:19:42 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 66E8D6054E for ; Mon, 6 Sep 2021 07:19:42 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 66E8D6054E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=sj/uzuFzXhodWMMmx5cblvl4O+JGlc8SWHnH/ExOnMY=; b=XBUgV1oXoysZlN 4FhmrF6pBQ+tt+AVdVOqQGg6N+rfZmCofxEun7lyE3kCQyq0n4gLREAli7WueNY2cyCRM1XHgvEMG 4QsUGMKwZbkR949EELITZlS5Z0JprTOF1n1dUN2eIJpDAYge52m34LvVE62Zlx7wLib1sQmfhDudm 5qtWNbq2uY0WhI6QvcY02fSIS/rHRCQy/OhobFxzI13UxJocs9cbiOKVsuerg244qUW93Ti9hZrdO bQqBI88+fVuaDRtHZlymPrNM0Ou0QwXy+sl9SKTXcYqrCh8ubrwyKce/aUg4qcJ5uUYrS3zxYi7Lo QqDuzE3Wg3wuT2xlYccw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mN8tB-00HYV3-GY; Mon, 06 Sep 2021 07:17:58 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mN8r7-00HXPX-7C; Mon, 06 Sep 2021 07:15:52 +0000 X-UUID: a981c388125443a7a4a62a51825b7dc5-20210906 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=VzGklr9bLNMh60yhecFbMOdUlkxwe4uwiP7Lo0AZ/Yc=; b=E/YP+ShQ9DfDxMfj9vMtyBVngI2WMUbtiPbim163qPRR3B9I+rZJMkXH8G8Ng8J9F7whWE0Q2MUW07HZPHD0AbOU7JX/Gt0j3gOuKtJBGTfk2r/CY+F6H+kIcyoXBJX3geGC0zM4s1UjNSH3h1DsCkwuXPOXTyNoxJWVcSzNDwc=; X-UUID: a981c388125443a7a4a62a51825b7dc5-20210906 Received: from mtkcas67.mediatek.inc [(172.29.193.45)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 529712755; Mon, 06 Sep 2021 00:15:43 -0700 Received: from MTKMBS07N2.mediatek.inc (172.21.101.141) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 6 Sep 2021 00:15:43 -0700 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 6 Sep 2021 15:15:41 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 6 Sep 2021 15:15:41 +0800 From: Nancy.Lin To: CK Hu CC: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Matthias Brugger , "jason-jh . lin" , "Nancy . Lin" , Yongqiang Niu , , , , , , , Subject: [PATCH v5 07/16] soc: mediatek: add mtk-mmsys config API for mt8195 vdosys1 Date: Mon, 6 Sep 2021 15:15:30 +0800 Message-ID: <20210906071539.12953-8-nancy.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210906071539.12953-1-nancy.lin@mediatek.com> References: <20210906071539.12953-1-nancy.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210906_001549_308101_BC5C3CEE X-CRM114-Status: GOOD ( 18.73 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add mmsys config API. The config API is used for config mmsys reg. Some mmsys regs need to be setting according to the HW engine binding to the mmsys simultaneously. Signed-off-by: Nancy.Lin --- drivers/soc/mediatek/mt8195-mmsys.h | 62 ++++++++++++++++++++++++++ drivers/soc/mediatek/mtk-mmsys.c | 33 ++++++++++++++ drivers/soc/mediatek/mtk-mmsys.h | 10 +++++ include/linux/soc/mediatek/mtk-mmsys.h | 16 +++++++ 4 files changed, 121 insertions(+) diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h index f19ec72c1243..648baaec112b 100644 --- a/drivers/soc/mediatek/mt8195-mmsys.h +++ b/drivers/soc/mediatek/mt8195-mmsys.h @@ -123,6 +123,21 @@ #define MT8195_VDO1_MIXER_SOUT_SEL_IN 0xf68 #define MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER (0 << 0) +#define MT8195_VDO1_MERGE0_ASYNC_CFG_WD 0xe30 +#define MT8195_VDO1_MERGE1_ASYNC_CFG_WD 0xe40 +#define MT8195_VDO1_MERGE2_ASYNC_CFG_WD 0xe50 +#define MT8195_VDO1_MERGE3_ASYNC_CFG_WD 0xe60 +#define MT8195_VDO1_HDRBE_ASYNC_CFG_WD 0xe70 +#define MT8195_VDO1_HDR_TOP_CFG 0xd00 +#define MT8195_VDO1_MIXER_IN1_ALPHA 0xd30 +#define MT8195_VDO1_MIXER_IN2_ALPHA 0xd34 +#define MT8195_VDO1_MIXER_IN3_ALPHA 0xd38 +#define MT8195_VDO1_MIXER_IN4_ALPHA 0xd3c +#define MT8195_VDO1_MIXER_IN1_PAD 0xd40 +#define MT8195_VDO1_MIXER_IN2_PAD 0xd44 +#define MT8195_VDO1_MIXER_IN3_PAD 0xd48 +#define MT8195_VDO1_MIXER_IN4_PAD 0xd4c + static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = { { DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, @@ -247,4 +262,51 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = { } }; +/* + * mtk_mmsys_config table is used for config mmsys reg in runtime. + * MMSYS_CONFIG_MERGE_ASYNC_WIDTH: config merge async width + * MMSYS_CONFIG_MERGE_ASYNC_HEIGHT: config merge async height + * MMSYS_CONFIG_HDR_BE_ASYNC_WIDTH: config hdr_be async width + * MMSYS_CONFIG_HDR_BE_ASYNC_HEIGHT: config hdr_be async height + * MMSYS_CONFIG_MIXER_IN_ALPHA_ODD: config mixer odd channel 9bit alpha value + * MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN: config mixer even channel 9bit alpha value + * MMSYS_CONFIG_MIXER_IN_CH_SWAP: config mixer input RGB channel swap + * MMSYS_CONFIG_HDR_ALPHA_SEL: config alpha source + * MMSYS_CONFIG_MIXER_IN_MODE: config mixer pad mode(bypass/even extend mode) + * MMSYS_CONFIG_MIXER_IN_BIWIDTH: config mixer pad width. formula: width / 2 - 1 + */ +static const struct mtk_mmsys_config mmsys_mt8195_config_table[] = { + { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 0, MT8195_VDO1_MERGE0_ASYNC_CFG_WD, GENMASK(13, 0), 0}, + { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 0, MT8195_VDO1_MERGE0_ASYNC_CFG_WD, GENMASK(29, 16), 16}, + { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 1, MT8195_VDO1_MERGE1_ASYNC_CFG_WD, GENMASK(13, 0), 0}, + { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 1, MT8195_VDO1_MERGE1_ASYNC_CFG_WD, GENMASK(29, 16), 16}, + { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 2, MT8195_VDO1_MERGE2_ASYNC_CFG_WD, GENMASK(13, 0), 0}, + { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 2, MT8195_VDO1_MERGE2_ASYNC_CFG_WD, GENMASK(29, 16), 16}, + { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 3, MT8195_VDO1_MERGE3_ASYNC_CFG_WD, GENMASK(13, 0), 0}, + { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 3, MT8195_VDO1_MERGE3_ASYNC_CFG_WD, GENMASK(29, 16), 16}, + { MMSYS_CONFIG_HDR_BE_ASYNC_WIDTH, 0, MT8195_VDO1_HDRBE_ASYNC_CFG_WD, GENMASK(13, 0), 0}, + { MMSYS_CONFIG_HDR_BE_ASYNC_HEIGHT, 0, MT8195_VDO1_HDRBE_ASYNC_CFG_WD, GENMASK(29, 16), 16}, + { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 1, MT8195_VDO1_MIXER_IN1_ALPHA, GENMASK(8, 0), 0}, + { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 1, MT8195_VDO1_MIXER_IN1_ALPHA, GENMASK(24, 16), 16}, + { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 2, MT8195_VDO1_MIXER_IN2_ALPHA, GENMASK(8, 0), 0}, + { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 2, MT8195_VDO1_MIXER_IN2_ALPHA, GENMASK(24, 16), 16}, + { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 3, MT8195_VDO1_MIXER_IN3_ALPHA, GENMASK(8, 0), 0}, + { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 3, MT8195_VDO1_MIXER_IN3_ALPHA, GENMASK(24, 16), 16}, + { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 4, MT8195_VDO1_MIXER_IN4_ALPHA, GENMASK(8, 0), 0}, + { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 4, MT8195_VDO1_MIXER_IN4_ALPHA, GENMASK(24, 16), 16}, + { MMSYS_CONFIG_MIXER_IN_CH_SWAP, 4, MT8195_VDO1_MIXER_IN4_PAD, GENMASK(4, 4), 4}, + { MMSYS_CONFIG_HDR_ALPHA_SEL, 1, MT8195_VDO1_HDR_TOP_CFG, GENMASK(20, 20), 20}, + { MMSYS_CONFIG_HDR_ALPHA_SEL, 2, MT8195_VDO1_HDR_TOP_CFG, GENMASK(21, 21), 21}, + { MMSYS_CONFIG_HDR_ALPHA_SEL, 3, MT8195_VDO1_HDR_TOP_CFG, GENMASK(22, 22), 22}, + { MMSYS_CONFIG_HDR_ALPHA_SEL, 4, MT8195_VDO1_HDR_TOP_CFG, GENMASK(23, 23), 23}, + { MMSYS_CONFIG_MIXER_IN_MODE, 1, MT8195_VDO1_MIXER_IN1_PAD, GENMASK(1, 0), 0}, + { MMSYS_CONFIG_MIXER_IN_MODE, 2, MT8195_VDO1_MIXER_IN2_PAD, GENMASK(1, 0), 0}, + { MMSYS_CONFIG_MIXER_IN_MODE, 3, MT8195_VDO1_MIXER_IN3_PAD, GENMASK(1, 0), 0}, + { MMSYS_CONFIG_MIXER_IN_MODE, 4, MT8195_VDO1_MIXER_IN4_PAD, GENMASK(1, 0), 0}, + { MMSYS_CONFIG_MIXER_IN_BIWIDTH, 1, MT8195_VDO1_MIXER_IN1_PAD, GENMASK(31, 16), 16}, + { MMSYS_CONFIG_MIXER_IN_BIWIDTH, 2, MT8195_VDO1_MIXER_IN2_PAD, GENMASK(31, 16), 16}, + { MMSYS_CONFIG_MIXER_IN_BIWIDTH, 3, MT8195_VDO1_MIXER_IN3_PAD, GENMASK(31, 16), 16}, + { MMSYS_CONFIG_MIXER_IN_BIWIDTH, 4, MT8195_VDO1_MIXER_IN4_PAD, GENMASK(31, 16), 16}, +}; + #endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */ diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index 5ad2cc796f5b..3a38b8269c71 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -72,6 +72,8 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = { .clk_driver = "clk-mt8195-vdo1", .routes = mmsys_mt8195_routing_table, .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table), + .config = mmsys_mt8195_config_table, + .num_configs = ARRAY_SIZE(mmsys_mt8195_config_table), }; struct mtk_mmsys { @@ -171,6 +173,37 @@ static const struct reset_control_ops mtk_mmsys_reset_ops = { .reset = mtk_mmsys_reset, }; +void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config, + u32 id, u32 val) +{ + struct mtk_mmsys *mmsys = dev_get_drvdata(dev); + const struct mtk_mmsys_config *mmsys_config = mmsys->data->config; + u32 reg_val; + u32 mask; + u32 offset; + int i; + + if (!mmsys->data->num_configs) + return; + + for (i = 0; i < mmsys->data->num_configs; i++) + if (config == mmsys_config[i].config && id == mmsys_config[i].id) + break; + + if (i == mmsys->data->num_configs) + return; + + offset = mmsys_config[i].addr; + mask = mmsys_config[i].mask; + reg_val = val << mmsys_config[i].shift; + + u32 tmp = readl(mmsys->regs + offset); + + tmp = (tmp & ~mask) | reg_val; + writel(tmp, mmsys->regs + offset); +} +EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_config); + static int mtk_mmsys_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h index 3bd50ca70eda..8c6b57f19edb 100644 --- a/drivers/soc/mediatek/mtk-mmsys.h +++ b/drivers/soc/mediatek/mtk-mmsys.h @@ -88,10 +88,20 @@ struct mtk_mmsys_routes { u32 val; }; +struct mtk_mmsys_config { + enum mtk_mmsys_config_type config; + u32 id; + u32 addr; + u32 mask; + u32 shift; +}; + struct mtk_mmsys_driver_data { const char *clk_driver; const struct mtk_mmsys_routes *routes; const unsigned int num_routes; + const struct mtk_mmsys_config *config; + const unsigned int num_configs; }; /* diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index 619392221a52..ef2a6d9a834b 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -53,6 +53,19 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_ID_MAX, }; +enum mtk_mmsys_config_type { + MMSYS_CONFIG_MERGE_ASYNC_WIDTH, + MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, + MMSYS_CONFIG_HDR_BE_ASYNC_WIDTH, + MMSYS_CONFIG_HDR_BE_ASYNC_HEIGHT, + MMSYS_CONFIG_HDR_ALPHA_SEL, + MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, + MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, + MMSYS_CONFIG_MIXER_IN_CH_SWAP, + MMSYS_CONFIG_MIXER_IN_MODE, + MMSYS_CONFIG_MIXER_IN_BIWIDTH, +}; + void mtk_mmsys_ddp_connect(struct device *dev, enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next); @@ -61,4 +74,7 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next); +void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config, + u32 id, u32 val); + #endif /* __MTK_MMSYS_H */ From patchwork Mon Sep 6 07:15:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?TmFuY3kgTGluICjmnpfmrKPonqIp?= X-Patchwork-Id: 12476447 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5AE54C433EF for ; Mon, 6 Sep 2021 07:24:17 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2283960724 for ; Mon, 6 Sep 2021 07:24:17 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 2283960724 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=wlSqnuzJr/lbJfWvTbnxEaKCSTvPyI/Me2lZLjQKhWE=; b=AjJmQ7LQd8NUK/ +rowS4SG2QtULWw4D4c1Sh3vLSQLOJfme0GTjg2HCxgdXhEk1qQY4hM3J3FrtFB9J9LeG6NMxt3r6 dH+6nZ6+7XTRTcOJacEuQNtpJiWhFNq+Zj+BZpBAmxgimLHR/EIm5N+zV92tLVm9V3GKcs03ro2qT ugVbN/LotHCF8jSnDlckYk/kDQONzGYBR4RwCccloDsmyqpFy4GgVkZXpp5TBB4MWrsYBiToAIb2Z pFCyqI8xXFEZU0E/eWwJMzzzwmniE8HSVYHfYZ4gQvAgUc6S5YQLet44oeyghbwJjh/nQaABckCZn y8iu5NvZZOJTgjS8JZXA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mN8wD-00Ha64-OI; Mon, 06 Sep 2021 07:21:06 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mN8rA-00HXOw-HS; Mon, 06 Sep 2021 07:15:54 +0000 X-UUID: ee3c4af0b916456fa24a875a0222ceb6-20210906 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=miEK0jYm+n3GR+S01MjGizGrMPC4vtpMG8mDm/gh3YQ=; b=av+OtEN75AHWQNZaPiyXJam/+Q1yWpnPBjt4h68aY/RJMkiuZ5RQYW3N1DPwX/5W21P8Xpvt5JBvipEvBTwg6DDNZrcgpbuB3k6iGEd2ZmvVDDAaK71bkeWKijptHRHqwzI/Bg+Aa68ZdK82CkqwYd2++twaXON2FegNiCJA6Rk=; X-UUID: ee3c4af0b916456fa24a875a0222ceb6-20210906 Received: from mtkcas68.mediatek.inc [(172.29.94.19)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 549954634; Mon, 06 Sep 2021 00:15:46 -0700 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 6 Sep 2021 00:15:44 -0700 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 6 Sep 2021 15:15:41 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 6 Sep 2021 15:15:41 +0800 From: Nancy.Lin To: CK Hu CC: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Matthias Brugger , "jason-jh . lin" , "Nancy . Lin" , Yongqiang Niu , , , , , , , Subject: [PATCH v5 08/16] soc: mediatek: add cmdq support of mtk-mmsys config API for mt8195 vdosys1 Date: Mon, 6 Sep 2021 15:15:31 +0800 Message-ID: <20210906071539.12953-9-nancy.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210906071539.12953-1-nancy.lin@mediatek.com> References: <20210906071539.12953-1-nancy.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210906_001552_659059_7D4AD777 X-CRM114-Status: GOOD ( 18.83 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add cmdq support for mtk-mmsys config API. The mmsys config register settings need to take effect with the other HW settings(like OVL_ADAPTOR...) at the same vblanking time. If we use CPU to write the mmsys reg, we can't guarantee all the settings can be written in the same vblanking time. Cmdq is used for this purpose. We prepare all the related HW settings in one cmdq packet. The first command in the packet is "wait stream done", and then following with all the HW settings. After the cmdq packet is flush to GCE HW. The GCE waits for the "stream done event" to coming and then starts flushing all the HW settings. This can guarantee all the settings flush in the same vblanking. Signed-off-by: Nancy.Lin --- drivers/soc/mediatek/mtk-mmsys.c | 28 +++++++++++++++++++++----- include/linux/soc/mediatek/mtk-mmsys.h | 6 +++++- 2 files changed, 28 insertions(+), 6 deletions(-) diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index 3a38b8269c71..060065501b8a 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -81,6 +81,7 @@ struct mtk_mmsys { const struct mtk_mmsys_driver_data *data; spinlock_t lock; /* protects mmsys_sw_rst_b reg */ struct reset_controller_dev rcdev; + struct cmdq_client_reg cmdq_base; }; void mtk_mmsys_ddp_connect(struct device *dev, @@ -174,7 +175,7 @@ static const struct reset_control_ops mtk_mmsys_reset_ops = { }; void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config, - u32 id, u32 val) + u32 id, u32 val, struct cmdq_pkt *cmdq_pkt) { struct mtk_mmsys *mmsys = dev_get_drvdata(dev); const struct mtk_mmsys_config *mmsys_config = mmsys->data->config; @@ -197,10 +198,20 @@ void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config, mask = mmsys_config[i].mask; reg_val = val << mmsys_config[i].shift; - u32 tmp = readl(mmsys->regs + offset); - - tmp = (tmp & ~mask) | reg_val; - writel(tmp, mmsys->regs + offset); +#if IS_REACHABLE(CONFIG_MTK_CMDQ) + if (cmdq_pkt && mmsys->cmdq_base.size) { + cmdq_pkt_write_mask(cmdq_pkt, mmsys->cmdq_base.subsys, + mmsys->cmdq_base.offset + offset, reg_val, + mask); + } else { +#endif + u32 tmp = readl(mmsys->regs + offset); + + tmp = (tmp & ~mask) | reg_val; + writel(tmp, mmsys->regs + offset); +#if IS_REACHABLE(CONFIG_MTK_CMDQ) + } +#endif } EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_config); @@ -236,6 +247,13 @@ static int mtk_mmsys_probe(struct platform_device *pdev) } mmsys->data = of_device_get_match_data(&pdev->dev); + +#if IS_REACHABLE(CONFIG_MTK_CMDQ) + ret = cmdq_dev_get_client_reg(dev, &mmsys->cmdq_base, 0); + if (ret) + dev_dbg(dev, "No mediatek,gce-client-reg!\n"); +#endif + platform_set_drvdata(pdev, mmsys); clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver, diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index ef2a6d9a834b..9705d242849a 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -6,6 +6,10 @@ #ifndef __MTK_MMSYS_H #define __MTK_MMSYS_H +#include +#include +#include + enum mtk_ddp_comp_id; struct device; @@ -75,6 +79,6 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, enum mtk_ddp_comp_id next); void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config, - u32 id, u32 val); + u32 id, u32 val, struct cmdq_pkt *cmdq_pkt); #endif /* __MTK_MMSYS_H */ From patchwork Mon Sep 6 07:15:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?TmFuY3kgTGluICjmnpfmrKPonqIp?= X-Patchwork-Id: 12476415 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E53E5C433F5 for ; Mon, 6 Sep 2021 07:18:40 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B26276054E for ; Mon, 6 Sep 2021 07:18:40 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org B26276054E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=9iVr8aL27NIV8LGJ4lnBHIJXpBUgO8Jbzhefe//y0Sc=; b=yGs0qV1jwsACle bBtHCkfpwCi0x68UOEsaqU2cq4cQMbSXcsOwDkqVlra62k2FHIoIvxegVm88/4pA3rSo8HC+3unAA XIq1RBQSRFub1oFYu1FNq7N/DJsv0crcBwsjFjRWnf4SZVC6fFqqmF96GcDrCFywEB1LfZHBciV7F 19dQbbYlVk/EytdyymEZuHCfrR8O1rlRbfCcAZKCkV4lzEVkPmOlqjytIZaGQ922/yGVFxrSCK1zT h3tYWyNeDyahaFceWnorQVsWInsL+IaZTyhxdv/dyUN6qY9coSWh+zaJGPKTp6Kq0dA0dM7g/SBMx rMFDxGEOn3FZujnQ/rQg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mN8s5-00HXxo-5i; Mon, 06 Sep 2021 07:16:49 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mN8r4-00HXQI-KZ; Mon, 06 Sep 2021 07:15:49 +0000 X-UUID: 97be35d627f54b308a5656607f3a200b-20210906 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=E3RIERgbqhr/xm5/6xxvQ2vVrPEQ1U6WTl6h7HDLUBY=; b=QW8Wq+yFd0tNwXDhhSZMovkvgs0kkM1A++rJcDw1/h3yB72YMUnnqoW0sljHazs6tY//c5EwGsK7PlANsYUYSBlQLcLFLDUkkHkJUXKjg7gIRWLBzV9RAxMhmV+miuapGx2ng4hBVRcmFgM/dJCSf5137o/A9QW8uNwwDhZObPU=; X-UUID: 97be35d627f54b308a5656607f3a200b-20210906 Received: from mtkcas68.mediatek.inc [(172.29.94.19)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 132380084; Mon, 06 Sep 2021 00:15:45 -0700 Received: from MTKMBS07N2.mediatek.inc (172.21.101.141) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 6 Sep 2021 00:15:43 -0700 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 6 Sep 2021 15:15:41 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 6 Sep 2021 15:15:42 +0800 From: Nancy.Lin To: CK Hu CC: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Matthias Brugger , "jason-jh . lin" , "Nancy . Lin" , Yongqiang Niu , , , , , , , Subject: [PATCH v5 09/16] soc: mediatek: mmsys: modify reset controller for MT8195 vdosys1 Date: Mon, 6 Sep 2021 15:15:32 +0800 Message-ID: <20210906071539.12953-10-nancy.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210906071539.12953-1-nancy.lin@mediatek.com> References: <20210906071539.12953-1-nancy.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210906_001546_729600_8ED13E65 X-CRM114-Status: GOOD ( 14.05 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org MT8195 vdosys1 has more than 32 reset bits and a different reset base than other chips. Modify mmsys for support 64 bit and different reset base. Signed-off-by: Nancy.Lin --- drivers/soc/mediatek/mt8195-mmsys.h | 1 + drivers/soc/mediatek/mtk-mmsys.c | 15 ++++++++++++--- drivers/soc/mediatek/mtk-mmsys.h | 1 + 3 files changed, 14 insertions(+), 3 deletions(-) diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h index 648baaec112b..f67801c42fd9 100644 --- a/drivers/soc/mediatek/mt8195-mmsys.h +++ b/drivers/soc/mediatek/mt8195-mmsys.h @@ -123,6 +123,7 @@ #define MT8195_VDO1_MIXER_SOUT_SEL_IN 0xf68 #define MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER (0 << 0) +#define MT8195_VDO1_SW0_RST_B 0x1d0 #define MT8195_VDO1_MERGE0_ASYNC_CFG_WD 0xe30 #define MT8195_VDO1_MERGE1_ASYNC_CFG_WD 0xe40 #define MT8195_VDO1_MERGE2_ASYNC_CFG_WD 0xe50 diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index 060065501b8a..97cb26339ef6 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -18,6 +18,8 @@ #include "mt8365-mmsys.h" #include "mt8195-mmsys.h" +#define MMSYS_SW_RESET_PER_REG 32 + static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { .clk_driver = "clk-mt2701-mm", .routes = mmsys_default_routing_table, @@ -48,12 +50,14 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { .clk_driver = "clk-mt8173-mm", .routes = mmsys_default_routing_table, .num_routes = ARRAY_SIZE(mmsys_default_routing_table), + .sw_reset_start = MMSYS_SW0_RST_B, }; static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { .clk_driver = "clk-mt8183-mm", .routes = mmsys_mt8183_routing_table, .num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table), + .sw_reset_start = MMSYS_SW0_RST_B, }; static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = { @@ -74,6 +78,7 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = { .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table), .config = mmsys_mt8195_config_table, .num_configs = ARRAY_SIZE(mmsys_mt8195_config_table), + .sw_reset_start = MT8195_VDO1_SW0_RST_B, }; struct mtk_mmsys { @@ -126,19 +131,23 @@ static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned l { struct mtk_mmsys *mmsys = container_of(rcdev, struct mtk_mmsys, rcdev); unsigned long flags; + u32 offset; u32 reg; int i; + offset = (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32); + id = id % MMSYS_SW_RESET_PER_REG; + spin_lock_irqsave(&mmsys->lock, flags); - reg = readl_relaxed(mmsys->regs + MMSYS_SW0_RST_B); + reg = readl_relaxed(mmsys->regs + mmsys->data->sw_reset_start + offset); if (assert) reg &= ~BIT(id); else reg |= BIT(id); - writel_relaxed(reg, mmsys->regs + MMSYS_SW0_RST_B); + writel_relaxed(reg, mmsys->regs + mmsys->data->sw_reset_start + offset); spin_unlock_irqrestore(&mmsys->lock, flags); @@ -237,7 +246,7 @@ static int mtk_mmsys_probe(struct platform_device *pdev) spin_lock_init(&mmsys->lock); mmsys->rcdev.owner = THIS_MODULE; - mmsys->rcdev.nr_resets = 32; + mmsys->rcdev.nr_resets = 64; mmsys->rcdev.ops = &mtk_mmsys_reset_ops; mmsys->rcdev.of_node = pdev->dev.of_node; ret = devm_reset_controller_register(&pdev->dev, &mmsys->rcdev); diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h index 8c6b57f19edb..f7f65d7adbf7 100644 --- a/drivers/soc/mediatek/mtk-mmsys.h +++ b/drivers/soc/mediatek/mtk-mmsys.h @@ -102,6 +102,7 @@ struct mtk_mmsys_driver_data { const unsigned int num_routes; const struct mtk_mmsys_config *config; const unsigned int num_configs; + u32 sw_reset_start; }; /* From patchwork Mon Sep 6 07:15:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?TmFuY3kgTGluICjmnpfmrKPonqIp?= X-Patchwork-Id: 12476453 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, UPPERCASE_50_75,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0CD01C433EF for ; Mon, 6 Sep 2021 07:26:23 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C4FC460E8B for ; Mon, 6 Sep 2021 07:26:22 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org C4FC460E8B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=z1RRbd/tp/ateQc1B1lrS+1iDRWxlseb/7kA4kkRzNI=; b=SIsn1xNLpgJTS5 J5O/KwOEQpaJqrxCSTb5wwxSIZ9wVupY2J7gHQWKoQSVkAEB0xBCuu57hlTVkdeLaLEWruLz5C9Ka E6aPyYKtFUL8/VkIj43Wl0/FLvikfe/PXGOkzy650iVo8oj7wFB4TaqCJyyR/BSt+xVW7GRzSu0C6 0mytpycS8vcPixQUtUHV9GvlHDdbtMjTke6Li0uo5annq1iYx8xCgECx7x5kbw+xcY/UalN/4k4DX OorqWZxhdE7LuqmaI4rOI4H1I4ttWg1MVz64Elm/bzEFGZgfEPx7yErUjk+GFWjDjFpOfQbNWtR7M ZUMNHZDNSkGEMTprKrfw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mN8yd-00008H-EO; Mon, 06 Sep 2021 07:23:36 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mN8rC-00HXPX-Lk; Mon, 06 Sep 2021 07:15:57 +0000 X-UUID: 235200fe73f64b4fad0e7f761bb7d9d2-20210906 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=Dqs8scmQVahYrsNL7yT7wJaai6xyOp9T3oRAcN+jXh4=; b=KuqTol0QEfsp+BGSACw1ui61HTE56FKeUHgrCLHN/8ThQjUq1aLiSdIiM08vc8/WIqSTjGykI6ttl582ipFRMtao7gXz2upukf7jWyLNaLaQumZh0xmbJz5eU3+xjISh+mRg+TUwA992VthTZeTNmT7uuSRDDjmFDaw3YOV2tmI=; X-UUID: 235200fe73f64b4fad0e7f761bb7d9d2-20210906 Received: from mtkcas68.mediatek.inc [(172.29.94.19)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1750569642; Mon, 06 Sep 2021 00:15:46 -0700 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 6 Sep 2021 00:15:45 -0700 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 6 Sep 2021 15:15:42 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 6 Sep 2021 15:15:42 +0800 From: Nancy.Lin To: CK Hu CC: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Matthias Brugger , "jason-jh . lin" , "Nancy . Lin" , Yongqiang Niu , , , , , , , Subject: [PATCH v5 10/16] soc: mediatek: add mtk-mutex support for mt8195 vdosys1 Date: Mon, 6 Sep 2021 15:15:33 +0800 Message-ID: <20210906071539.12953-11-nancy.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210906071539.12953-1-nancy.lin@mediatek.com> References: <20210906071539.12953-1-nancy.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210906_001554_774983_29511A4B X-CRM114-Status: UNSURE ( 9.14 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add mtk-mutex support for mt8195 vdosys1. The vdosys1 path component contains ovl_adaptor, merge5, and dp_intf1. Ovl_adaptor is composed of several sub-elements, so change it to support multi-bit control. Signed-off-by: Nancy.Lin --- drivers/soc/mediatek/mtk-mutex.c | 270 ++++++++++++++++++------------- 1 file changed, 162 insertions(+), 108 deletions(-) diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c index c177156ee2fa..588e378d1855 100644 --- a/drivers/soc/mediatek/mtk-mutex.c +++ b/drivers/soc/mediatek/mtk-mutex.c @@ -29,101 +29,130 @@ #define INT_MUTEX BIT(1) -#define MT8167_MUTEX_MOD_DISP_PWM 1 -#define MT8167_MUTEX_MOD_DISP_OVL0 6 -#define MT8167_MUTEX_MOD_DISP_OVL1 7 -#define MT8167_MUTEX_MOD_DISP_RDMA0 8 -#define MT8167_MUTEX_MOD_DISP_RDMA1 9 -#define MT8167_MUTEX_MOD_DISP_WDMA0 10 -#define MT8167_MUTEX_MOD_DISP_CCORR 11 -#define MT8167_MUTEX_MOD_DISP_COLOR 12 -#define MT8167_MUTEX_MOD_DISP_AAL 13 -#define MT8167_MUTEX_MOD_DISP_GAMMA 14 -#define MT8167_MUTEX_MOD_DISP_DITHER 15 -#define MT8167_MUTEX_MOD_DISP_UFOE 16 - -#define MT8183_MUTEX_MOD_DISP_RDMA0 0 -#define MT8183_MUTEX_MOD_DISP_RDMA1 1 -#define MT8183_MUTEX_MOD_DISP_OVL0 9 -#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10 -#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11 -#define MT8183_MUTEX_MOD_DISP_WDMA0 12 -#define MT8183_MUTEX_MOD_DISP_COLOR0 13 -#define MT8183_MUTEX_MOD_DISP_CCORR0 14 -#define MT8183_MUTEX_MOD_DISP_AAL0 15 -#define MT8183_MUTEX_MOD_DISP_GAMMA0 16 -#define MT8183_MUTEX_MOD_DISP_DITHER0 17 - -#define MT8173_MUTEX_MOD_DISP_OVL0 11 -#define MT8173_MUTEX_MOD_DISP_OVL1 12 -#define MT8173_MUTEX_MOD_DISP_RDMA0 13 -#define MT8173_MUTEX_MOD_DISP_RDMA1 14 -#define MT8173_MUTEX_MOD_DISP_RDMA2 15 -#define MT8173_MUTEX_MOD_DISP_WDMA0 16 -#define MT8173_MUTEX_MOD_DISP_WDMA1 17 -#define MT8173_MUTEX_MOD_DISP_COLOR0 18 -#define MT8173_MUTEX_MOD_DISP_COLOR1 19 -#define MT8173_MUTEX_MOD_DISP_AAL 20 -#define MT8173_MUTEX_MOD_DISP_GAMMA 21 -#define MT8173_MUTEX_MOD_DISP_UFOE 22 -#define MT8173_MUTEX_MOD_DISP_PWM0 23 -#define MT8173_MUTEX_MOD_DISP_PWM1 24 -#define MT8173_MUTEX_MOD_DISP_OD 25 - -#define MT8195_MUTEX_MOD_DISP_OVL0 0 -#define MT8195_MUTEX_MOD_DISP_WDMA0 1 -#define MT8195_MUTEX_MOD_DISP_RDMA0 2 -#define MT8195_MUTEX_MOD_DISP_COLOR0 3 -#define MT8195_MUTEX_MOD_DISP_CCORR0 4 -#define MT8195_MUTEX_MOD_DISP_AAL0 5 -#define MT8195_MUTEX_MOD_DISP_GAMMA0 6 -#define MT8195_MUTEX_MOD_DISP_DITHER0 7 -#define MT8195_MUTEX_MOD_DISP_DSI0 8 -#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 9 -#define MT8195_MUTEX_MOD_DISP_OVL1 10 -#define MT8195_MUTEX_MOD_DISP_WDMA1 11 -#define MT8195_MUTEX_MOD_DISP_RDMA1 12 -#define MT8195_MUTEX_MOD_DISP_COLOR1 13 -#define MT8195_MUTEX_MOD_DISP_CCORR1 14 -#define MT8195_MUTEX_MOD_DISP_AAL1 15 -#define MT8195_MUTEX_MOD_DISP_GAMMA1 16 -#define MT8195_MUTEX_MOD_DISP_DITHER1 17 -#define MT8195_MUTEX_MOD_DISP_DSI1 18 -#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE1 19 -#define MT8195_MUTEX_MOD_DISP_VPP_MERGE 20 -#define MT8195_MUTEX_MOD_DISP_DP_INTF0 21 -#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY0 22 -#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY1 23 -#define MT8195_MUTEX_MOD_DISP_VDO1_DL_RELAY2 24 -#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY3 25 -#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY4 26 -#define MT8195_MUTEX_MOD_DISP_PWM0 27 -#define MT8195_MUTEX_MOD_DISP_PWM1 28 - -#define MT2712_MUTEX_MOD_DISP_PWM2 10 -#define MT2712_MUTEX_MOD_DISP_OVL0 11 -#define MT2712_MUTEX_MOD_DISP_OVL1 12 -#define MT2712_MUTEX_MOD_DISP_RDMA0 13 -#define MT2712_MUTEX_MOD_DISP_RDMA1 14 -#define MT2712_MUTEX_MOD_DISP_RDMA2 15 -#define MT2712_MUTEX_MOD_DISP_WDMA0 16 -#define MT2712_MUTEX_MOD_DISP_WDMA1 17 -#define MT2712_MUTEX_MOD_DISP_COLOR0 18 -#define MT2712_MUTEX_MOD_DISP_COLOR1 19 -#define MT2712_MUTEX_MOD_DISP_AAL0 20 -#define MT2712_MUTEX_MOD_DISP_UFOE 22 -#define MT2712_MUTEX_MOD_DISP_PWM0 23 -#define MT2712_MUTEX_MOD_DISP_PWM1 24 -#define MT2712_MUTEX_MOD_DISP_OD0 25 -#define MT2712_MUTEX_MOD2_DISP_AAL1 33 -#define MT2712_MUTEX_MOD2_DISP_OD1 34 - -#define MT2701_MUTEX_MOD_DISP_OVL 3 -#define MT2701_MUTEX_MOD_DISP_WDMA 6 -#define MT2701_MUTEX_MOD_DISP_COLOR 7 -#define MT2701_MUTEX_MOD_DISP_BLS 9 -#define MT2701_MUTEX_MOD_DISP_RDMA0 10 -#define MT2701_MUTEX_MOD_DISP_RDMA1 12 +#define MT8167_MUTEX_MOD_DISP_PWM BIT(1) +#define MT8167_MUTEX_MOD_DISP_OVL0 BIT(6) +#define MT8167_MUTEX_MOD_DISP_OVL1 BIT(7) +#define MT8167_MUTEX_MOD_DISP_RDMA0 BIT(8) +#define MT8167_MUTEX_MOD_DISP_RDMA1 BIT(9) +#define MT8167_MUTEX_MOD_DISP_WDMA0 BIT(10) +#define MT8167_MUTEX_MOD_DISP_CCORR BIT(11) +#define MT8167_MUTEX_MOD_DISP_COLOR BIT(12) +#define MT8167_MUTEX_MOD_DISP_AAL BIT(13) +#define MT8167_MUTEX_MOD_DISP_GAMMA BIT(14) +#define MT8167_MUTEX_MOD_DISP_DITHER BIT(15) +#define MT8167_MUTEX_MOD_DISP_UFOE BIT(16) + +#define MT8183_MUTEX_MOD_DISP_RDMA0 BIT(0) +#define MT8183_MUTEX_MOD_DISP_RDMA1 BIT(1) +#define MT8183_MUTEX_MOD_DISP_OVL0 BIT(9) +#define MT8183_MUTEX_MOD_DISP_OVL0_2L BIT(10) +#define MT8183_MUTEX_MOD_DISP_OVL1_2L BIT(11) +#define MT8183_MUTEX_MOD_DISP_WDMA0 BIT(12) +#define MT8183_MUTEX_MOD_DISP_COLOR0 BIT(13) +#define MT8183_MUTEX_MOD_DISP_CCORR0 BIT(14) +#define MT8183_MUTEX_MOD_DISP_AAL0 BIT(15) +#define MT8183_MUTEX_MOD_DISP_GAMMA0 BIT(16) +#define MT8183_MUTEX_MOD_DISP_DITHER0 BIT(17) + +#define MT8173_MUTEX_MOD_DISP_OVL0 BIT(11) +#define MT8173_MUTEX_MOD_DISP_OVL1 BIT(12) +#define MT8173_MUTEX_MOD_DISP_RDMA0 BIT(13) +#define MT8173_MUTEX_MOD_DISP_RDMA1 BIT(14) +#define MT8173_MUTEX_MOD_DISP_RDMA2 BIT(15) +#define MT8173_MUTEX_MOD_DISP_WDMA0 BIT(16) +#define MT8173_MUTEX_MOD_DISP_WDMA1 BIT(17) +#define MT8173_MUTEX_MOD_DISP_COLOR0 BIT(18) +#define MT8173_MUTEX_MOD_DISP_COLOR1 BIT(19) +#define MT8173_MUTEX_MOD_DISP_AAL BIT(20) +#define MT8173_MUTEX_MOD_DISP_GAMMA BIT(21) +#define MT8173_MUTEX_MOD_DISP_UFOE BIT(22) +#define MT8173_MUTEX_MOD_DISP_PWM0 BIT(23) +#define MT8173_MUTEX_MOD_DISP_PWM1 BIT(24) +#define MT8173_MUTEX_MOD_DISP_OD BIT(25) + +#define MT8195_MUTEX_MOD_DISP_OVL0 BIT(0) +#define MT8195_MUTEX_MOD_DISP_WDMA0 BIT(1) +#define MT8195_MUTEX_MOD_DISP_RDMA0 BIT(2) +#define MT8195_MUTEX_MOD_DISP_COLOR0 BIT(3) +#define MT8195_MUTEX_MOD_DISP_CCORR0 BIT(4) +#define MT8195_MUTEX_MOD_DISP_AAL0 BIT(5) +#define MT8195_MUTEX_MOD_DISP_GAMMA0 BIT(6) +#define MT8195_MUTEX_MOD_DISP_DITHER0 BIT(7) +#define MT8195_MUTEX_MOD_DISP_DSI0 BIT(8) +#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 BIT(9) +#define MT8195_MUTEX_MOD_DISP_OVL1 BIT(10) +#define MT8195_MUTEX_MOD_DISP_WDMA1 BIT(11) +#define MT8195_MUTEX_MOD_DISP_RDMA1 BIT(12) +#define MT8195_MUTEX_MOD_DISP_COLOR1 BIT(13) +#define MT8195_MUTEX_MOD_DISP_CCORR1 BIT(14) +#define MT8195_MUTEX_MOD_DISP_AAL1 BIT(15) +#define MT8195_MUTEX_MOD_DISP_GAMMA1 BIT(16) +#define MT8195_MUTEX_MOD_DISP_DITHER1 BIT(17) +#define MT8195_MUTEX_MOD_DISP_DSI1 BIT(18) +#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE1 BIT(19) +#define MT8195_MUTEX_MOD_DISP_VPP_MERGE BIT(20) +#define MT8195_MUTEX_MOD_DISP_DP_INTF0 BIT(21) +#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY0 BIT(22) +#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY1 BIT(23) +#define MT8195_MUTEX_MOD_DISP_VDO1_DL_RELAY2 BIT(24) +#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY3 BIT(25) +#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY4 BIT(26) +#define MT8195_MUTEX_MOD_DISP_PWM0 BIT(27) +#define MT8195_MUTEX_MOD_DISP_PWM1 BIT(28) + +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA0 BIT(0) +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA1 BIT(1) +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA2 BIT(2) +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA3 BIT(3) +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA4 BIT(4) +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA5 BIT(5) +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA6 BIT(6) +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA7 BIT(7) +#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE0 BIT(8) +#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE1 BIT(9) +#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE2 BIT(10) +#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE3 BIT(11) +#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE4 BIT(12) +#define MT8195_MUTEX_MOD_DISP1_VPP2_DL_RELAY BIT(13) +#define MT8195_MUTEX_MOD_DISP1_VPP3_DL_RELAY BIT(14) +#define MT8195_MUTEX_MOD_DISP1_VDO0_DSC_DL_ASYNC BIT(15) +#define MT8195_MUTEX_MOD_DISP1_VDO0_MERGE_DL_ASYNC BIT(16) +#define MT8195_MUTEX_MOD_DISP1_VDO1_OUT_DL_RELAY BIT(17) +#define MT8195_MUTEX_MOD_DISP1_DISP_MIXER BIT(18) +#define MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE0 BIT(19) +#define MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE1 BIT(20) +#define MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE0 BIT(21) +#define MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE1 BIT(22) +#define MT8195_MUTEX_MOD_DISP1_HDR_VDO_BE0 BIT(23) +#define MT8195_MUTEX_MOD_DISP1_HDR_MLOAD BIT(24) +#define MT8195_MUTEX_MOD_DISP1_DPI0 BIT(25) +#define MT8195_MUTEX_MOD_DISP1_DPI1 BIT(26) +#define MT8195_MUTEX_MOD_DISP1_DP_INTF0 BIT(27) + +#define MT2712_MUTEX_MOD_DISP_PWM2 BIT(10) +#define MT2712_MUTEX_MOD_DISP_OVL0 BIT(11) +#define MT2712_MUTEX_MOD_DISP_OVL1 BIT(12) +#define MT2712_MUTEX_MOD_DISP_RDMA0 BIT(13) +#define MT2712_MUTEX_MOD_DISP_RDMA1 BIT(14) +#define MT2712_MUTEX_MOD_DISP_RDMA2 BIT(15) +#define MT2712_MUTEX_MOD_DISP_WDMA0 BIT(16) +#define MT2712_MUTEX_MOD_DISP_WDMA1 BIT(17) +#define MT2712_MUTEX_MOD_DISP_COLOR0 BIT(18) +#define MT2712_MUTEX_MOD_DISP_COLOR1 BIT(19) +#define MT2712_MUTEX_MOD_DISP_AAL0 BIT(20) +#define MT2712_MUTEX_MOD_DISP_UFOE BIT(22) +#define MT2712_MUTEX_MOD_DISP_PWM0 BIT(23) +#define MT2712_MUTEX_MOD_DISP_PWM1 BIT(24) +#define MT2712_MUTEX_MOD_DISP_OD0 BIT(25) +#define MT2712_MUTEX_MOD2_DISP_AAL1 BIT(33) +#define MT2712_MUTEX_MOD2_DISP_OD1 BIT(34) + +#define MT2701_MUTEX_MOD_DISP_OVL BIT(3) +#define MT2701_MUTEX_MOD_DISP_WDMA BIT(6) +#define MT2701_MUTEX_MOD_DISP_COLOR BIT(7) +#define MT2701_MUTEX_MOD_DISP_BLS BIT(9) +#define MT2701_MUTEX_MOD_DISP_RDMA0 BIT(10) +#define MT2701_MUTEX_MOD_DISP_RDMA1 BIT(12) #define MT2712_MUTEX_SOF_SINGLE_MODE 0 #define MT2712_MUTEX_SOF_DSI0 1 @@ -174,7 +203,7 @@ enum mtk_mutex_sof_id { }; struct mtk_mutex_data { - const unsigned int *mutex_mod; + const unsigned long *mutex_mod; const unsigned int *mutex_sof; const unsigned int mutex_mod_reg; const unsigned int mutex_sof_reg; @@ -189,7 +218,7 @@ struct mtk_mutex_ctx { const struct mtk_mutex_data *data; }; -static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = { +static const unsigned long mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_BLS] = MT2701_MUTEX_MOD_DISP_BLS, [DDP_COMPONENT_COLOR0] = MT2701_MUTEX_MOD_DISP_COLOR, [DDP_COMPONENT_OVL0] = MT2701_MUTEX_MOD_DISP_OVL, @@ -198,7 +227,7 @@ static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_WDMA0] = MT2701_MUTEX_MOD_DISP_WDMA, }; -static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = { +static const unsigned long mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_AAL0] = MT2712_MUTEX_MOD_DISP_AAL0, [DDP_COMPONENT_AAL1] = MT2712_MUTEX_MOD2_DISP_AAL1, [DDP_COMPONENT_COLOR0] = MT2712_MUTEX_MOD_DISP_COLOR0, @@ -218,7 +247,7 @@ static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_WDMA1] = MT2712_MUTEX_MOD_DISP_WDMA1, }; -static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = { +static const unsigned long mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_AAL0] = MT8167_MUTEX_MOD_DISP_AAL, [DDP_COMPONENT_CCORR] = MT8167_MUTEX_MOD_DISP_CCORR, [DDP_COMPONENT_COLOR0] = MT8167_MUTEX_MOD_DISP_COLOR, @@ -233,7 +262,7 @@ static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_WDMA0] = MT8167_MUTEX_MOD_DISP_WDMA0, }; -static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = { +static const unsigned long mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_AAL0] = MT8173_MUTEX_MOD_DISP_AAL, [DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0, [DDP_COMPONENT_COLOR1] = MT8173_MUTEX_MOD_DISP_COLOR1, @@ -251,7 +280,7 @@ static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1, }; -static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { +static const unsigned long mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0, [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0, [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0, @@ -265,7 +294,7 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, }; -static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = { +static const unsigned long mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0, [DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0, [DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0, @@ -279,6 +308,27 @@ static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0, [DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0, [DDP_COMPONENT_DP_INTF0] = MT8195_MUTEX_MOD_DISP_DP_INTF0, + [DDP_COMPONENT_OVL_ADAPTOR] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA0 | + MT8195_MUTEX_MOD_DISP1_MDP_RDMA1 | + MT8195_MUTEX_MOD_DISP1_MDP_RDMA2 | + MT8195_MUTEX_MOD_DISP1_MDP_RDMA3 | + MT8195_MUTEX_MOD_DISP1_MDP_RDMA4 | + MT8195_MUTEX_MOD_DISP1_MDP_RDMA5 | + MT8195_MUTEX_MOD_DISP1_MDP_RDMA6 | + MT8195_MUTEX_MOD_DISP1_MDP_RDMA7 | + MT8195_MUTEX_MOD_DISP1_VPP_MERGE0 | + MT8195_MUTEX_MOD_DISP1_VPP_MERGE1 | + MT8195_MUTEX_MOD_DISP1_VPP_MERGE2 | + MT8195_MUTEX_MOD_DISP1_VPP_MERGE3 | + MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE0 | + MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE1 | + MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE0 | + MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE1 | + MT8195_MUTEX_MOD_DISP1_HDR_VDO_BE0 | + MT8195_MUTEX_MOD_DISP1_HDR_MLOAD | + MT8195_MUTEX_MOD_DISP1_DISP_MIXER, + [DDP_COMPONENT_MERGE5] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE4, + [DDP_COMPONENT_DP_INTF1] = MT8195_MUTEX_MOD_DISP1_DP_INTF0, }; static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = { @@ -436,17 +486,20 @@ void mtk_mutex_add_comp(struct mtk_mutex *mutex, case DDP_COMPONENT_DP_INTF0: sof_id = MUTEX_SOF_DP_INTF0; break; + case DDP_COMPONENT_DP_INTF1: + sof_id = MUTEX_SOF_DP_INTF1; + break; default: - if (mtx->data->mutex_mod[id] < 32) { + if (mtx->data->mutex_mod[id] <= BIT(31)) { offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg, mutex->id); reg = readl_relaxed(mtx->regs + offset); - reg |= 1 << mtx->data->mutex_mod[id]; + reg |= mtx->data->mutex_mod[id]; writel_relaxed(reg, mtx->regs + offset); } else { offset = DISP_REG_MUTEX_MOD2(mutex->id); reg = readl_relaxed(mtx->regs + offset); - reg |= 1 << (mtx->data->mutex_mod[id] - 32); + reg |= (mtx->data->mutex_mod[id] >> 32); writel_relaxed(reg, mtx->regs + offset); } return; @@ -476,22 +529,23 @@ void mtk_mutex_remove_comp(struct mtk_mutex *mutex, case DDP_COMPONENT_DPI0: case DDP_COMPONENT_DPI1: case DDP_COMPONENT_DP_INTF0: + case DDP_COMPONENT_DP_INTF1: writel_relaxed(MUTEX_SOF_SINGLE_MODE, mtx->regs + DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, mutex->id)); break; default: - if (mtx->data->mutex_mod[id] < 32) { + if (mtx->data->mutex_mod[id] <= BIT(31)) { offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg, mutex->id); reg = readl_relaxed(mtx->regs + offset); - reg &= ~(1 << mtx->data->mutex_mod[id]); + reg &= ~(mtx->data->mutex_mod[id]); writel_relaxed(reg, mtx->regs + offset); } else { offset = DISP_REG_MUTEX_MOD2(mutex->id); reg = readl_relaxed(mtx->regs + offset); - reg &= ~(1 << (mtx->data->mutex_mod[id] - 32)); + reg &= ~(mtx->data->mutex_mod[id] >> 32); writel_relaxed(reg, mtx->regs + offset); } break; From patchwork Mon Sep 6 07:15:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?TmFuY3kgTGluICjmnpfmrKPonqIp?= X-Patchwork-Id: 12476451 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 458EDC433F5 for ; Mon, 6 Sep 2021 07:25:45 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0BFE560724 for ; Mon, 6 Sep 2021 07:25:45 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 0BFE560724 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=89XMJd21VS9GJMvDzzz+apu90RueblW3JsMUbU8hA3o=; b=p3mRCT8z3xhNER IGX+oXOTMvkRawp/uE4QzgpSDt1VkQVw+d5nMs2KS7/8bUMGpKGPhOhEzzVVtAPvWjPkX/Z6ZWYVe QYCmQle5T50x78DNSXvr2Fs20BMlysoPPlf8FQo0WcGVHl04jn1jASU6w5BrEXAGfQ6IFvekTGS7E kab5o9P3Md6mujNav945xEEkqvjNXqFE1DWJG5ugiOFEsKYee1zGbXbP5B1TXaMHhVYDVrLbEfMD2 QF5Hn/rYFVWGkJeTQE73z1/cgBMyLVEuB2Sa6caTEJjF7jw2EAa/jlT/PtPzafadnnLoZ4FE9xHxL /ZkvIpqeQ9rXkKxDBbVg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mN8xk-00Hap5-Ud; Mon, 06 Sep 2021 07:22:42 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mN8rC-00HXOw-Fx; Mon, 06 Sep 2021 07:15:57 +0000 X-UUID: b7e2bb93b0c5492fa882dfa8b4f36541-20210906 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=/smzeZWKT1X39PCbLapAqWAHJ/Wto2wjSw+ZpusdaLw=; b=mb2H31If7iwuVhmF6CmpS6FpguzdfzGGUAIT6yUX7tWDgo6SJCGdJBcepk+CqFOLFReZfa/Q8CSfaipYH5eKp3QoQSS5a+Jfu+CNdtio9/sZthOjc42lDwkexnd6uZqwht9WRjAA3Puvq52Tk2swLUaWl8iQBP8bSwdw9iNIG/w=; X-UUID: b7e2bb93b0c5492fa882dfa8b4f36541-20210906 Received: from mtkcas68.mediatek.inc [(172.29.94.19)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1602467048; Mon, 06 Sep 2021 00:15:46 -0700 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 6 Sep 2021 00:15:45 -0700 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 6 Sep 2021 15:15:42 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 6 Sep 2021 15:15:42 +0800 From: Nancy.Lin To: CK Hu CC: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Matthias Brugger , "jason-jh . lin" , "Nancy . Lin" , Yongqiang Niu , , , , , , , Subject: [PATCH v5 11/16] drm/mediatek: add display MDP RDMA support for MT8195 Date: Mon, 6 Sep 2021 15:15:34 +0800 Message-ID: <20210906071539.12953-12-nancy.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210906071539.12953-1-nancy.lin@mediatek.com> References: <20210906071539.12953-1-nancy.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210906_001554_616625_4BF9B4EF X-CRM114-Status: GOOD ( 20.18 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add MDP_RDMA driver for MT8195. MDP_RDMA is the DMA engine of the ovl_adaptor component. Signed-off-by: Nancy.Lin --- drivers/gpu/drm/mediatek/Makefile | 3 +- drivers/gpu/drm/mediatek/mtk_disp_drv.h | 7 + drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 301 ++++++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_mdp_rdma.h | 37 +++ 4 files changed, 347 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.c create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.h diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile index a38e88e82d12..6e604a933ed0 100644 --- a/drivers/gpu/drm/mediatek/Makefile +++ b/drivers/gpu/drm/mediatek/Makefile @@ -13,7 +13,8 @@ mediatek-drm-y := mtk_disp_aal.o \ mtk_drm_gem.o \ mtk_drm_plane.o \ mtk_dsi.o \ - mtk_dpi.o + mtk_dpi.o \ + mtk_mdp_rdma.o obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h index a33b13fe2b6e..b3a372cab0bd 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -8,6 +8,7 @@ #include #include "mtk_drm_plane.h" +#include "mtk_mdp_rdma.h" int mtk_aal_clk_enable(struct device *dev); void mtk_aal_clk_disable(struct device *dev); @@ -106,4 +107,10 @@ void mtk_rdma_enable_vblank(struct device *dev, void *vblank_cb_data); void mtk_rdma_disable_vblank(struct device *dev); +int mtk_mdp_rdma_clk_enable(struct device *dev); +void mtk_mdp_rdma_clk_disable(struct device *dev); +void mtk_mdp_rdma_start(struct device *dev, struct cmdq_pkt *cmdq_pkt); +void mtk_mdp_rdma_stop(struct device *dev, struct cmdq_pkt *cmdq_pkt); +void mtk_mdp_rdma_config(struct device *dev, struct mtk_mdp_rdma_cfg *cfg, + struct cmdq_pkt *cmdq_pkt); #endif diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c new file mode 100644 index 000000000000..052434d960b9 --- /dev/null +++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c @@ -0,0 +1,301 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021 MediaTek Inc. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "mtk_drm_drv.h" +#include "mtk_disp_drv.h" +#include "mtk_mdp_rdma.h" + +#define MDP_RDMA_EN 0x000 + #define FLD_ROT_ENABLE BIT(0) + +#define MDP_RDMA_RESET 0x008 + +#define MDP_RDMA_CON 0x020 + #define FLD_OUTPUT_10B BIT(5) + #define FLD_SIMPLE_MODE BIT(4) + +#define MDP_RDMA_GMCIF_CON 0x028 + #define FLD_COMMAND_DIV BIT(0) + #define FLD_EXT_PREULTRA_EN BIT(3) + #define FLD_RD_REQ_TYPE GENMASK(7, 4) + #define VAL_RD_REQ_TYPE_BURST_8_ACCESS 7 + #define FLD_ULTRA_EN GENMASK(13, 12) + #define VAL_ULTRA_EN_ENABLE 1 + #define FLD_PRE_ULTRA_EN GENMASK(17, 16) + #define VAL_PRE_ULTRA_EN_ENABLE 1 + #define FLD_EXT_ULTRA_EN BIT(18) + +#define MDP_RDMA_SRC_CON 0x030 + #define FLD_OUTPUT_ARGB BIT(25) + #define FLD_BIT_NUMBER GENMASK(19, 18) + #define FLD_UNIFORM_CONFIG BIT(17) + #define FLD_SWAP BIT(14) + #define FLD_SRC_FORMAT GENMASK(3, 0) + +#define MDP_RDMA_COMP_CON 0x038 + #define FLD_AFBC_EN BIT(22) + #define FLD_AFBC_YUV_TRANSFORM BIT(21) + #define FLD_UFBDC_EN BIT(12) + +#define MDP_RDMA_MF_BKGD_SIZE_IN_BYTE 0x060 + #define FLD_MF_BKGD_WB GENMASK(22, 0) + +#define MDP_RDMA_MF_SRC_SIZE 0x070 + #define FLD_MF_SRC_H GENMASK(30, 16) + #define FLD_MF_SRC_W GENMASK(14, 0) + +#define MDP_RDMA_MF_CLIP_SIZE 0x078 + #define FLD_MF_CLIP_H GENMASK(30, 16) + #define FLD_MF_CLIP_W GENMASK(14, 0) + +#define MDP_RDMA_TARGET_LINE 0x0a0 + #define FLD_LINE_THRESHOLD GENMASK(31, 17) + #define FLD_TARGET_LINE_EN BIT(16) + +#define MDP_RDMA_SRC_OFFSET_0 0x118 + #define FLD_SRC_OFFSET_0 GENMASK(31, 0) + +#define MDP_RDMA_TRANSFORM_0 0x200 + #define FLD_INT_MATRIX_SEL GENMASK(27, 23) + #define FLD_TRANS_EN BIT(16) + +#define MDP_RDMA_SRC_BASE_0 0xf00 + #define FLD_SRC_BASE_0 GENMASK(31, 0) + +#define RDMA_INPUT_SWAP BIT(14) +#define RDMA_INPUT_10BIT BIT(18) + +enum rdma_format { + RDMA_INPUT_FORMAT_RGB565 = 0, + RDMA_INPUT_FORMAT_RGB888 = 1, + RDMA_INPUT_FORMAT_RGBA8888 = 2, + RDMA_INPUT_FORMAT_ARGB8888 = 3, + RDMA_INPUT_FORMAT_UYVY = 4, + RDMA_INPUT_FORMAT_YUY2 = 5, + RDMA_INPUT_FORMAT_Y8 = 7, + RDMA_INPUT_FORMAT_YV12 = 8, + RDMA_INPUT_FORMAT_UYVY_3PL = 9, + RDMA_INPUT_FORMAT_NV12 = 12, + RDMA_INPUT_FORMAT_UYVY_2PL = 13, + RDMA_INPUT_FORMAT_Y410 = 14 +}; + +struct mtk_mdp_rdma { + void __iomem *regs; + struct clk *clk; + struct cmdq_client_reg cmdq_reg; +}; + +static unsigned int rdma_fmt_convert(unsigned int fmt) +{ + switch (fmt) { + default: + case DRM_FORMAT_RGB565: + return RDMA_INPUT_FORMAT_RGB565; + case DRM_FORMAT_BGR565: + return RDMA_INPUT_FORMAT_RGB565 | RDMA_INPUT_SWAP; + case DRM_FORMAT_RGB888: + return RDMA_INPUT_FORMAT_RGB888; + case DRM_FORMAT_BGR888: + return RDMA_INPUT_FORMAT_RGB888 | RDMA_INPUT_SWAP; + case DRM_FORMAT_RGBX8888: + case DRM_FORMAT_RGBA8888: + return RDMA_INPUT_FORMAT_ARGB8888; + case DRM_FORMAT_BGRX8888: + case DRM_FORMAT_BGRA8888: + return RDMA_INPUT_FORMAT_ARGB8888 | RDMA_INPUT_SWAP; + case DRM_FORMAT_XRGB8888: + case DRM_FORMAT_ARGB8888: + return RDMA_INPUT_FORMAT_RGBA8888; + case DRM_FORMAT_XBGR8888: + case DRM_FORMAT_ABGR8888: + return RDMA_INPUT_FORMAT_RGBA8888 | RDMA_INPUT_SWAP; + case DRM_FORMAT_ABGR2101010: + return RDMA_INPUT_FORMAT_RGBA8888 | RDMA_INPUT_SWAP | + RDMA_INPUT_10BIT; + case DRM_FORMAT_ARGB2101010: + return RDMA_INPUT_FORMAT_RGBA8888 | RDMA_INPUT_10BIT; + case DRM_FORMAT_RGBA1010102: + return RDMA_INPUT_FORMAT_ARGB8888 | RDMA_INPUT_SWAP | + RDMA_INPUT_10BIT; + case DRM_FORMAT_BGRA1010102: + return RDMA_INPUT_FORMAT_ARGB8888 | RDMA_INPUT_10BIT; + case DRM_FORMAT_UYVY: + return RDMA_INPUT_FORMAT_UYVY; + case DRM_FORMAT_YUYV: + return RDMA_INPUT_FORMAT_YUY2; + } +} + +static void mtk_mdp_rdma_fifo_config(struct device *dev, struct cmdq_pkt *cmdq_pkt) +{ + struct mtk_mdp_rdma *priv = dev_get_drvdata(dev); + + mtk_ddp_write_mask(cmdq_pkt, FLD_EXT_ULTRA_EN | VAL_PRE_ULTRA_EN_ENABLE << 16 | + VAL_ULTRA_EN_ENABLE << 12 | VAL_RD_REQ_TYPE_BURST_8_ACCESS << 4 | + FLD_EXT_PREULTRA_EN | FLD_COMMAND_DIV, &priv->cmdq_reg, + priv->regs, MDP_RDMA_GMCIF_CON, FLD_EXT_ULTRA_EN | + FLD_PRE_ULTRA_EN | FLD_ULTRA_EN | FLD_RD_REQ_TYPE | + FLD_EXT_PREULTRA_EN | FLD_COMMAND_DIV); +} + +void mtk_mdp_rdma_start(struct device *dev, struct cmdq_pkt *cmdq_pkt) +{ + struct mtk_mdp_rdma *priv = dev_get_drvdata(dev); + + mtk_ddp_write_mask(cmdq_pkt, FLD_ROT_ENABLE, &priv->cmdq_reg, + priv->regs, MDP_RDMA_EN, FLD_ROT_ENABLE); +} + +void mtk_mdp_rdma_stop(struct device *dev, struct cmdq_pkt *cmdq_pkt) +{ + struct mtk_mdp_rdma *priv = dev_get_drvdata(dev); + + mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg, + priv->regs, MDP_RDMA_EN, FLD_ROT_ENABLE); + mtk_ddp_write(cmdq_pkt, 1, &priv->cmdq_reg, priv->regs, MDP_RDMA_RESET); + mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, MDP_RDMA_RESET); +} + +void mtk_mdp_rdma_config(struct device *dev, struct mtk_mdp_rdma_cfg *cfg, + struct cmdq_pkt *cmdq_pkt) +{ + struct mtk_mdp_rdma *priv = dev_get_drvdata(dev); + const struct drm_format_info *fmt_info = drm_format_info(cfg->fmt); + unsigned int src_pitch_y = cfg->pitch; + unsigned int bpp_y = fmt_info->cpp[0] * 8; + unsigned int offset_y = 0; + + mtk_mdp_rdma_fifo_config(dev, cmdq_pkt); + + mtk_ddp_write_mask(cmdq_pkt, FLD_UNIFORM_CONFIG, &priv->cmdq_reg, priv->regs, + MDP_RDMA_SRC_CON, FLD_UNIFORM_CONFIG); + mtk_ddp_write_mask(cmdq_pkt, rdma_fmt_convert(cfg->fmt), &priv->cmdq_reg, priv->regs, + MDP_RDMA_SRC_CON, FLD_SWAP | FLD_SRC_FORMAT | FLD_BIT_NUMBER); + + if (!cfg->csc_enable && fmt_info->has_alpha) + mtk_ddp_write_mask(cmdq_pkt, FLD_OUTPUT_ARGB, &priv->cmdq_reg, + priv->regs, MDP_RDMA_SRC_CON, FLD_OUTPUT_ARGB); + else + mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, + MDP_RDMA_SRC_CON, FLD_OUTPUT_ARGB); + + mtk_ddp_write_mask(cmdq_pkt, cfg->addr0, &priv->cmdq_reg, priv->regs, + MDP_RDMA_SRC_BASE_0, FLD_SRC_BASE_0); + + mtk_ddp_write_mask(cmdq_pkt, src_pitch_y, &priv->cmdq_reg, priv->regs, + MDP_RDMA_MF_BKGD_SIZE_IN_BYTE, FLD_MF_BKGD_WB); + + mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, MDP_RDMA_COMP_CON, + FLD_AFBC_YUV_TRANSFORM | FLD_UFBDC_EN | FLD_AFBC_EN); + mtk_ddp_write_mask(cmdq_pkt, FLD_OUTPUT_10B, &priv->cmdq_reg, priv->regs, + MDP_RDMA_CON, FLD_OUTPUT_10B); + mtk_ddp_write_mask(cmdq_pkt, FLD_SIMPLE_MODE, &priv->cmdq_reg, priv->regs, + MDP_RDMA_CON, FLD_SIMPLE_MODE); + mtk_ddp_write_mask(cmdq_pkt, cfg->csc_enable << 16, &priv->cmdq_reg, priv->regs, + MDP_RDMA_TRANSFORM_0, FLD_TRANS_EN); + mtk_ddp_write_mask(cmdq_pkt, cfg->profile << 23, &priv->cmdq_reg, priv->regs, + MDP_RDMA_TRANSFORM_0, FLD_INT_MATRIX_SEL); + + offset_y = (cfg->x_left * bpp_y >> 3) + cfg->y_top * src_pitch_y; + + mtk_ddp_write_mask(cmdq_pkt, offset_y, &priv->cmdq_reg, priv->regs, + MDP_RDMA_SRC_OFFSET_0, FLD_SRC_OFFSET_0); + mtk_ddp_write_mask(cmdq_pkt, cfg->width, &priv->cmdq_reg, priv->regs, + MDP_RDMA_MF_SRC_SIZE, FLD_MF_SRC_W); + mtk_ddp_write_mask(cmdq_pkt, cfg->height << 16, &priv->cmdq_reg, priv->regs, + MDP_RDMA_MF_SRC_SIZE, FLD_MF_SRC_H); + mtk_ddp_write_mask(cmdq_pkt, cfg->width, &priv->cmdq_reg, priv->regs, + MDP_RDMA_MF_CLIP_SIZE, FLD_MF_CLIP_W); + mtk_ddp_write_mask(cmdq_pkt, cfg->height << 16, &priv->cmdq_reg, priv->regs, + MDP_RDMA_MF_CLIP_SIZE, FLD_MF_CLIP_H); + mtk_ddp_write_mask(cmdq_pkt, cfg->height << 17, &priv->cmdq_reg, priv->regs, + MDP_RDMA_TARGET_LINE, FLD_LINE_THRESHOLD); + mtk_ddp_write_mask(cmdq_pkt, FLD_TARGET_LINE_EN, &priv->cmdq_reg, priv->regs, + MDP_RDMA_TARGET_LINE, FLD_TARGET_LINE_EN); +} + +int mtk_mdp_rdma_clk_enable(struct device *dev) +{ + struct mtk_mdp_rdma *rdma = dev_get_drvdata(dev); + + pm_runtime_get_sync(dev); + clk_prepare_enable(rdma->clk); + return 0; +} + +void mtk_mdp_rdma_clk_disable(struct device *dev) +{ + struct mtk_mdp_rdma *rdma = dev_get_drvdata(dev); + + clk_disable_unprepare(rdma->clk); + pm_runtime_put(dev); +} + +static int mtk_mdp_rdma_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct resource *res; + struct mtk_mdp_rdma *priv; + int ret = 0; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + priv->regs = devm_ioremap_resource(dev, res); + if (IS_ERR(priv->regs)) { + dev_err(dev, "failed to ioremap rdma\n"); + return PTR_ERR(priv->regs); + } + + priv->clk = devm_clk_get(dev, NULL); + if (IS_ERR(priv->clk)) { + dev_err(dev, "failed to get rdma clk\n"); + return PTR_ERR(priv->clk); + } + +#if IS_REACHABLE(CONFIG_MTK_CMDQ) + ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0); + if (ret) + dev_dbg(dev, "get mediatek,gce-client-reg fail!\n"); +#endif + platform_set_drvdata(pdev, priv); + + pm_runtime_enable(dev); + return ret; +} + +static int mtk_mdp_rdma_remove(struct platform_device *pdev) +{ + pm_runtime_disable(&pdev->dev); + return 0; +} + +static const struct of_device_id mtk_mdp_rdma_driver_dt_match[] = { + { .compatible = "mediatek,mt8195-vdo1-rdma", }, + {}, +}; +MODULE_DEVICE_TABLE(of, mtk_mdp_rdma_driver_dt_match); + +struct platform_driver mtk_mdp_rdma_driver = { + .probe = mtk_mdp_rdma_probe, + .remove = mtk_mdp_rdma_remove, + .driver = { + .name = "mediatek-mdp-rdma", + .owner = THIS_MODULE, + .of_match_table = mtk_mdp_rdma_driver_dt_match, + }, +}; +module_platform_driver(mtk_mdp_rdma_driver); diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h new file mode 100644 index 000000000000..df8e28f0e3a4 --- /dev/null +++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021 MediaTek Inc. + */ + +#ifndef __MTK_MDP_RDMA_H__ +#define __MTK_MDP_RDMA_H__ + +enum mtk_mdp_rdma_profile { + RDMA_CSC_RGB_TO_JPEG = 0, + RDMA_CSC_RGB_TO_FULL709 = 1, + RDMA_CSC_RGB_TO_BT601 = 2, + RDMA_CSC_RGB_TO_BT709 = 3, + RDMA_CSC_JPEG_TO_RGB = 4, + RDMA_CSC_FULL709_TO_RGB = 5, + RDMA_CSC_BT601_TO_RGB = 6, + RDMA_CSC_BT709_TO_RGB = 7, + RDMA_CSC_JPEG_TO_BT601 = 8, + RDMA_CSC_JPEG_TO_BT709 = 9, + RDMA_CSC_BT601_TO_JPEG = 10, + RDMA_CSC_BT709_TO_BT601 = 11, + RDMA_CSC_BT601_TO_BT709 = 12 +}; + +struct mtk_mdp_rdma_cfg { + enum mtk_mdp_rdma_profile profile; + unsigned int pitch; + unsigned int addr0; + unsigned int width; + unsigned int height; + unsigned int x_left; + unsigned int y_top; + bool csc_enable; + int fmt; +}; + +#endif // __MTK_MDP_RDMA_H__ From patchwork Mon Sep 6 07:15:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?TmFuY3kgTGluICjmnpfmrKPonqIp?= X-Patchwork-Id: 12476427 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B5283C433F5 for ; Mon, 6 Sep 2021 07:20:18 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 827AC6054E for ; Mon, 6 Sep 2021 07:20:18 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 827AC6054E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=rxyqob/E0OIU5wIfvkiOZrVicTeV92b10inSBHkJt6s=; b=wL+8cHYrTh1HEw uN0I7+FH4Vm/IM0OeKjlVd3jw6jdSnoZSKBDLqWF3Aq8Idk9f+21ATRPWdtCNOb4T6mnVU9sL94FU Sbg9WSDJUBZSu5rmCcSTX0t94MHU2F3SRZl490fkU0PdI6eSFjbBG6t5LwPnlnJY5ezInJ+/aLRAP mLy6FfgoeSR13moy79HNFgEVpVK3BVF1HqWLwnJiorxiXVo+T9+MfsIR5gMkPg510Q7OiR2gdgrbM oiYAuhKk0BE3Y0D3NH1OEokyEd41393nwhwdxkH7lpSk7NpviYyZmRhkzaS4GFAbVc1MzuLtrxZIJ q/oCtZg68zqlIt44FXbQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mN8tr-00HYra-FK; Mon, 06 Sep 2021 07:18:40 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mN8r7-00HXQI-K3; Mon, 06 Sep 2021 07:15:52 +0000 X-UUID: 413ac1230b24459085a647ded908a77f-20210906 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=+lPsc8iW8nKfDGEDFdPbGD0W7ZHX4VliJTMXWOhf5F4=; b=Tq5TCs9UgR3WbNQC0pL51RotMo3xRJP4Ys1IoGZRtclOTj+f2rUVH/KFjoMmeGf5SwbIH986mCG1UT0CC+XWOZqnbvvNjLHOA5hk+JYsSYIaa+XFWYCUT6qVc1JhWDXlIE6Hy+ISvqqyc5BBm7nA5Z+Je4/FmGKkbjFpy9cs+t8=; X-UUID: 413ac1230b24459085a647ded908a77f-20210906 Received: from mtkcas68.mediatek.inc [(172.29.94.19)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1534636450; Mon, 06 Sep 2021 00:15:45 -0700 Received: from MTKMBS07N2.mediatek.inc (172.21.101.141) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 6 Sep 2021 00:15:44 -0700 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 6 Sep 2021 15:15:42 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 6 Sep 2021 15:15:42 +0800 From: Nancy.Lin To: CK Hu CC: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Matthias Brugger , "jason-jh . lin" , "Nancy . Lin" , Yongqiang Niu , , , , , , , Subject: [PATCH v5 12/16] drm/mediatek: add display merge api support for MT8195 Date: Mon, 6 Sep 2021 15:15:35 +0800 Message-ID: <20210906071539.12953-13-nancy.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210906071539.12953-1-nancy.lin@mediatek.com> References: <20210906071539.12953-1-nancy.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210906_001549_756090_658DC696 X-CRM114-Status: GOOD ( 16.01 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add merge new API. 1. Vdosys1 merge1~merge4 support HW mute function, so add unmute API. 2. Add merge new advance config API. The original merge API is mtk_ddp_comp_funcs function prototype. The API interface parameters cannot be modified, so add a new config API for extension. 3. Add merge enable/disable API for cmdq support. The ovl_adaptor merges are configured with each drm plane update. Need to enable/disable merge with cmdq making sure all the settings taken effect in the same vblank. Signed-off-by: Nancy.Lin --- drivers/gpu/drm/mediatek/mtk_disp_drv.h | 6 ++ drivers/gpu/drm/mediatek/mtk_disp_merge.c | 74 ++++++++++++++++++++--- 2 files changed, 70 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h index b3a372cab0bd..2446ad0a4977 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -63,6 +63,12 @@ void mtk_merge_config(struct device *dev, unsigned int width, unsigned int bpc, struct cmdq_pkt *cmdq_pkt); void mtk_merge_start(struct device *dev); void mtk_merge_stop(struct device *dev); +void mtk_merge_advance_config(struct device *dev, unsigned int l_w, unsigned int r_w, + unsigned int h, unsigned int vrefresh, unsigned int bpc, + struct cmdq_pkt *cmdq_pkt); +void mtk_merge_unmute(struct device *dev, struct cmdq_pkt *cmdq_pkt); +void mtk_merge_enable(struct device *dev, struct cmdq_pkt *cmdq_pkt); +void mtk_merge_disable(struct device *dev, struct cmdq_pkt *cmdq_pkt); void mtk_ovl_bgclr_in_on(struct device *dev); void mtk_ovl_bgclr_in_off(struct device *dev); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/mediatek/mtk_disp_merge.c index b05e1df79c3d..41bff6d3a8da 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_merge.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c @@ -17,6 +17,7 @@ #define DISP_REG_MERGE_CTRL 0x000 #define MERGE_EN 1 #define DISP_REG_MERGE_CFG_0 0x010 +#define DISP_REG_MERGE_CFG_1 0x014 #define DISP_REG_MERGE_CFG_4 0x020 #define DISP_REG_MERGE_CFG_10 0x038 /* no swap */ @@ -25,9 +26,12 @@ #define DISP_REG_MERGE_CFG_12 0x040 #define CFG_10_10_1PI_2PO_BUF_MODE 6 #define CFG_10_10_2PI_2PO_BUF_MODE 8 +#define CFG_11_10_1PI_2PO_MERGE 18 #define FLD_CFG_MERGE_MODE GENMASK(4, 0) #define DISP_REG_MERGE_CFG_24 0x070 #define DISP_REG_MERGE_CFG_25 0x074 +#define DISP_REG_MERGE_CFG_26 0x078 +#define DISP_REG_MERGE_CFG_27 0x07c #define DISP_REG_MERGE_CFG_36 0x0a0 #define ULTRA_EN BIT(0) #define PREULTRA_EN BIT(4) @@ -54,26 +58,52 @@ #define FLD_PREULTRA_TH_LOW GENMASK(15, 0) #define FLD_PREULTRA_TH_HIGH GENMASK(31, 16) +#define DISP_REG_MERGE_MUTE_0 0xf00 + struct mtk_disp_merge { void __iomem *regs; struct clk *clk; struct clk *async_clk; struct cmdq_client_reg cmdq_reg; bool fifo_en; + bool mute_support; }; void mtk_merge_start(struct device *dev) +{ + mtk_merge_enable(dev, NULL); +} + +void mtk_merge_stop(struct device *dev) { struct mtk_disp_merge *priv = dev_get_drvdata(dev); - writel(MERGE_EN, priv->regs + DISP_REG_MERGE_CTRL); + mtk_merge_disable(dev, NULL); } -void mtk_merge_stop(struct device *dev) +void mtk_merge_enable(struct device *dev, struct cmdq_pkt *cmdq_pkt) +{ + struct mtk_disp_merge *priv = dev_get_drvdata(dev); + + mtk_ddp_write(cmdq_pkt, 1, &priv->cmdq_reg, priv->regs, + DISP_REG_MERGE_CTRL); +} + +void mtk_merge_disable(struct device *dev, struct cmdq_pkt *cmdq_pkt) { struct mtk_disp_merge *priv = dev_get_drvdata(dev); - writel(0x0, priv->regs + DISP_REG_MERGE_CTRL); + mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, + DISP_REG_MERGE_CTRL); +} + +void mtk_merge_unmute(struct device *dev, struct cmdq_pkt *cmdq_pkt) +{ + struct mtk_disp_merge *priv = dev_get_drvdata(dev); + + if (priv->mute_support) + mtk_ddp_write(cmdq_pkt, 0x0, &priv->cmdq_reg, priv->regs, + DISP_REG_MERGE_MUTE_0); } static void mtk_merge_fifo_setting(struct mtk_disp_merge *priv, @@ -98,12 +128,19 @@ static void mtk_merge_fifo_setting(struct mtk_disp_merge *priv, void mtk_merge_config(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt) +{ + mtk_merge_advance_config(dev, w, 0, h, vrefresh, bpc, cmdq_pkt); +} + +void mtk_merge_advance_config(struct device *dev, unsigned int l_w, unsigned int r_w, + unsigned int h, unsigned int vrefresh, unsigned int bpc, + struct cmdq_pkt *cmdq_pkt) { struct mtk_disp_merge *priv = dev_get_drvdata(dev); unsigned int mode = CFG_10_10_1PI_2PO_BUF_MODE; - if (!h || !w) { - dev_err(dev, "%s: input width(%d) or height(%d) is invalid\n", __func__, w, h); + if (!h || !l_w) { + dev_err(dev, "%s: input width(%d) or height(%d) is invalid\n", __func__, l_w, h); return; } @@ -112,14 +149,29 @@ void mtk_merge_config(struct device *dev, unsigned int w, mode = CFG_10_10_2PI_2PO_BUF_MODE; } - mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, + if (r_w) + mode = CFG_11_10_1PI_2PO_MERGE; + + mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_0); - mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, + mtk_ddp_write(cmdq_pkt, h << 16 | r_w, &priv->cmdq_reg, priv->regs, + DISP_REG_MERGE_CFG_1); + mtk_ddp_write(cmdq_pkt, h << 16 | (l_w + r_w), &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_4); - mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, + mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_24); - mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, - DISP_REG_MERGE_CFG_25); + if (r_w) + mtk_ddp_write(cmdq_pkt, h << 16 | r_w, &priv->cmdq_reg, priv->regs, + DISP_REG_MERGE_CFG_25); + else + mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg, priv->regs, + DISP_REG_MERGE_CFG_25); + + mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg, priv->regs, + DISP_REG_MERGE_CFG_26); + mtk_ddp_write(cmdq_pkt, h << 16 | r_w, &priv->cmdq_reg, priv->regs, + DISP_REG_MERGE_CFG_27); + mtk_ddp_write_mask(cmdq_pkt, SWAP_MODE, &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_10, FLD_SWAP_MODE); mtk_ddp_write_mask(cmdq_pkt, mode, &priv->cmdq_reg, priv->regs, @@ -205,6 +257,8 @@ static int mtk_disp_merge_probe(struct platform_device *pdev) priv->fifo_en = of_property_read_bool(dev->of_node, "mediatek,merge-fifo-en"); + priv->mute_support = of_property_read_bool(dev->of_node, + "mediatek,merge-mute"); platform_set_drvdata(pdev, priv); ret = component_add(dev, &mtk_disp_merge_component_ops); From patchwork Mon Sep 6 07:15:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?TmFuY3kgTGluICjmnpfmrKPonqIp?= X-Patchwork-Id: 12476463 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 642AFC433F5 for ; Mon, 6 Sep 2021 07:31:17 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 246B2606A5 for ; Mon, 6 Sep 2021 07:31:17 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 246B2606A5 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=aTKiwtCBhXo26stzeTtX1v6xF+svcQZzZ+Zjp6D+aog=; b=1pZ/cs5ipkvV8q yqrG6V3woee6fSoPa4Wbk4mJqSSVl8Hz7luGowf3CKRSJzF13MAX2vHclIrg/khmEmw9ETJso4sXq uv1ygDDdTfeBN31Bd1+9MlrTPm50etVNjWiNOYudpf45QdtXp+Rt/MEgPYbFxf5kEVZpGBHbsDw9/ NfcdTtjHgMfhuErx8FklHelpSzNpnLyrcO72Jlg/COVQx0cMSC8q1m6Gpmrs82VfrY7ejS/5LvSv4 xDtp0115H14bHKZE4xNnRQ04w4NqqbgpCGKsOXRegw17629JjyxgwaX9Nz5OlgSMndgA3pZUU4zWh mOL77WYrdJxfNKGHnt8Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mN93s-0002NY-Rk; Mon, 06 Sep 2021 07:29:02 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mN90q-0001CI-M2; Mon, 06 Sep 2021 07:25:56 +0000 X-UUID: 34a228674b4442e1b7fc8ec1df5c9b7d-20210906 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=6lM5hCPW/HJnC4GjT58C2B9xCKz+Su7mYNEza+CnWMk=; b=DVdEeUHDidW0bUqGrxUFHJh5WBmd4zrwDspRvuqV2VWnWpzzDGKTl4XOGxVCLKzmhuU5DudYdAGuSAR117hlOfO6r4dhVrZW6PiZbQvD7fxN7wYX77yrRwlmimVdJblZsjZw55EFzBG23oENSrmVdhCOAjqhDSkzF+UAYWwoWAA=; X-UUID: 34a228674b4442e1b7fc8ec1df5c9b7d-20210906 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 2066652430; Mon, 06 Sep 2021 00:25:47 -0700 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 6 Sep 2021 00:15:46 -0700 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 6 Sep 2021 15:15:42 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 6 Sep 2021 15:15:42 +0800 From: Nancy.Lin To: CK Hu CC: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Matthias Brugger , "jason-jh . lin" , "Nancy . Lin" , Yongqiang Niu , , , , , , , Subject: [PATCH v5 13/16] drm/mediatek: add ETHDR support for MT8195 Date: Mon, 6 Sep 2021 15:15:36 +0800 Message-ID: <20210906071539.12953-14-nancy.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210906071539.12953-1-nancy.lin@mediatek.com> References: <20210906071539.12953-1-nancy.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210906_002552_910127_905B22D0 X-CRM114-Status: GOOD ( 19.66 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org ETHDR is a part of ovl_adaptor. ETHDR is designed for HDR video and graphics conversion in the external display path. It handles multiple HDR input types and performs tone mapping, color space/color format conversion, and then combine different layers, output the required HDR or SDR signal to the subsequent display path. Signed-off-by: Nancy.Lin --- drivers/gpu/drm/mediatek/Makefile | 1 + drivers/gpu/drm/mediatek/mtk_ethdr.c | 424 +++++++++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_ethdr.h | 25 ++ 3 files changed, 450 insertions(+) create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.c create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.h diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile index 6e604a933ed0..fb158a1e7f06 100644 --- a/drivers/gpu/drm/mediatek/Makefile +++ b/drivers/gpu/drm/mediatek/Makefile @@ -14,6 +14,7 @@ mediatek-drm-y := mtk_disp_aal.o \ mtk_drm_plane.o \ mtk_dsi.o \ mtk_dpi.o \ + mtk_ethdr.o \ mtk_mdp_rdma.o obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediatek/mtk_ethdr.c new file mode 100644 index 000000000000..c93c881c5a36 --- /dev/null +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c @@ -0,0 +1,424 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021 MediaTek Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mtk_drm_crtc.h" +#include "mtk_drm_ddp_comp.h" +#include "mtk_drm_drv.h" +#include "mtk_ethdr.h" + +#define MIX_INTEN 0x4 + #define MIX_FME_CPL_INTEN BIT(1) +#define MIX_INTSTA 0x8 +#define MIX_EN 0xc +#define MIX_RST 0x14 +#define MIX_ROI_SIZE 0x18 +#define MIX_DATAPATH_CON 0x1c + #define OUTPUT_NO_RND BIT(3) + #define SOURCE_RGB_SEL BIT(7) + #define BACKGROUND_RELAY (4 << 9) +#define MIX_ROI_BGCLR 0x20 + #define BGCLR_BLACK 0xff000000 +#define MIX_SRC_CON 0x24 + #define MIX_SRC_L0_EN BIT(0) +#define MIX_L_SRC_CON(n) (0x28 + 0x18 * (n)) + #define NON_PREMULTI_SOURCE (2 << 12) +#define MIX_L_SRC_SIZE(n) (0x30 + 0x18 * (n)) +#define MIX_L_SRC_OFFSET(n) (0x34 + 0x18 * (n)) +#define MIX_FUNC_DCM0 0x120 +#define MIX_FUNC_DCM1 0x124 + #define MIX_FUNC_DCM_ENABLE 0xffffffff + +#define HDR_VDO_FE_0804_HDR_DM_FE 0x804 + #define HDR_VDO_FE_0804_BYPASS_ALL 0xfd +#define HDR_GFX_FE_0204_GFX_HDR_FE 0x204 + #define HDR_GFX_FE_0204_BYPASS_ALL 0xfd +#define HDR_VDO_BE_0204_VDO_DM_BE 0x204 + #define HDR_VDO_BE_0204_BYPASS_ALL 0x7e + +#define MIXER_INx_MODE_BYPASS 0 +#define MIXER_INx_MODE_EVEN_EXTEND 1 +#define MIXER_INx_MODE_ODD_EXTEND 2 +#define DEFAULT_9BIT_ALPHA 0x100 +#define MIXER_ALPHA_AEN BIT(8) +#define MIXER_ALPHA 0xff +#define ETHDR_CLK_NUM 13 + +enum mtk_ethdr_comp_id { + ETHDR_MIXER, + ETHDR_VDO_FE0, + ETHDR_VDO_FE1, + ETHDR_GFX_FE0, + ETHDR_GFX_FE1, + ETHDR_VDO_BE, + ETHDR_ADL_DS, + ETHDR_ID_MAX +}; + +struct mtk_ethdr_comp { + struct device *dev; + void __iomem *regs; + struct cmdq_client_reg cmdq_base; +}; + +struct mtk_ethdr { + struct mtk_ethdr_comp ethdr_comp[ETHDR_ID_MAX]; + struct clk_bulk_data ethdr_clk[ETHDR_CLK_NUM]; + struct device *ovl_adaptor_dev; + struct device *mmsys_dev; + spinlock_t lock; /* protects vblank_cb and vblank_cb_data */ + void (*vblank_cb)(void *data); + void *vblank_cb_data; + int irq; +}; + +static const char * const ethdr_comp_str[] = { + "ETHDR_MIXER", + "ETHDR_VDO_FE0", + "ETHDR_VDO_FE1", + "ETHDR_GFX_FE0", + "ETHDR_GFX_FE1", + "ETHDR_VDO_BE", + "ETHDR_ADL_DS", + "ETHDR_ID_MAX" +}; + +static const char * const ethdr_clk_str[] = { + "ethdr_top", + "mixer", + "vdo_fe0", + "vdo_fe1", + "gfx_fe0", + "gfx_fe1", + "vdo_be", + "adl_ds", + "vdo_fe0_async", + "vdo_fe1_async", + "gfx_fe0_async", + "gfx_fe1_async", + "vdo_be_async", +}; + +void mtk_ethdr_enable_vblank(struct device *dev, + void (*vblank_cb)(void *), + void *vblank_cb_data) +{ + struct mtk_ethdr *priv = dev_get_drvdata(dev); + unsigned long flags; + + spin_lock_irqsave(&priv->lock, flags); + priv->vblank_cb = vblank_cb; + priv->vblank_cb_data = vblank_cb_data; + spin_unlock_irqrestore(&priv->lock, flags); + + writel(MIX_FME_CPL_INTEN, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTEN); +} + +void mtk_ethdr_disable_vblank(struct device *dev) +{ + struct mtk_ethdr *priv = dev_get_drvdata(dev); + unsigned long flags; + + spin_lock_irqsave(&priv->lock, flags); + priv->vblank_cb = NULL; + priv->vblank_cb_data = NULL; + spin_unlock_irqrestore(&priv->lock, flags); + + writel(0x0, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTEN); +} + +static irqreturn_t mtk_ethdr_irq_handler(int irq, void *dev_id) +{ + struct mtk_ethdr *priv = dev_id; + unsigned long flags; + + writel(0x0, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTSTA); + + spin_lock_irqsave(&priv->lock, flags); + if (!priv->vblank_cb) { + spin_unlock_irqrestore(&priv->lock, flags); + return IRQ_NONE; + } + + priv->vblank_cb(priv->vblank_cb_data); + spin_unlock_irqrestore(&priv->lock, flags); + + return IRQ_HANDLED; +} + +void mtk_ethdr_layer_config(struct device *dev, unsigned int idx, + struct mtk_plane_state *state, + struct cmdq_pkt *cmdq_pkt) +{ + struct mtk_ethdr *priv = dev_get_drvdata(dev); + struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER]; + struct mtk_plane_pending_state *pending = &state->pending; + unsigned int offset = (pending->y << 16) | pending->x; + unsigned int mixer_pad_mode = MIXER_INx_MODE_BYPASS; + unsigned int alpha_con = 0; + unsigned int fmt = 0; + bool x_offset_odd = false; + + dev_dbg(dev, "%s+ idx:%d", __func__, idx); + + if (idx >= 4) + return; + + if (!pending->enable) { + mtk_ddp_write(cmdq_pkt, 0, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(idx)); + mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_MODE, + idx + 1, MIXER_INx_MODE_BYPASS, cmdq_pkt); + mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_BIWIDTH, + idx + 1, 0, cmdq_pkt); + return; + } + + if (pending->x % 2) { + x_offset_odd = true; + mixer_pad_mode = MIXER_INx_MODE_EVEN_EXTEND; + } + mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_MODE, + idx + 1, mixer_pad_mode, cmdq_pkt); + mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_BIWIDTH, + idx + 1, pending->width / 2 - 1, cmdq_pkt); + + if (state->base.fb && state->base.fb->format->has_alpha) { + alpha_con = MIXER_ALPHA_AEN | MIXER_ALPHA; + mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_HDR_ALPHA_SEL, + idx + 1, 0, cmdq_pkt); + } else { + mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_HDR_ALPHA_SEL, + idx + 1, 1, cmdq_pkt); + } + mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, idx + 1, + DEFAULT_9BIT_ALPHA, cmdq_pkt); + mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, idx + 1, + DEFAULT_9BIT_ALPHA, cmdq_pkt); + + mtk_ddp_write(cmdq_pkt, (pending->height << 16) | pending->width, &mixer->cmdq_base, + mixer->regs, MIX_L_SRC_SIZE(idx)); + mtk_ddp_write(cmdq_pkt, (x_offset_odd << 31) | offset, &mixer->cmdq_base, + mixer->regs, MIX_L_SRC_OFFSET(idx)); + mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_CON(idx), + 0x1ff); + mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer->cmdq_base, mixer->regs, MIX_SRC_CON, + BIT(idx)); +} + +void mtk_ethdr_config(struct device *dev, unsigned int w, + unsigned int h, unsigned int vrefresh, + unsigned int bpc, struct cmdq_pkt *cmdq_pkt) +{ + struct mtk_ethdr *priv = dev_get_drvdata(dev); + struct mtk_ethdr_comp *vdo_fe0 = &priv->ethdr_comp[ETHDR_VDO_FE0]; + struct mtk_ethdr_comp *vdo_fe1 = &priv->ethdr_comp[ETHDR_VDO_FE1]; + struct mtk_ethdr_comp *gfx_fe0 = &priv->ethdr_comp[ETHDR_GFX_FE0]; + struct mtk_ethdr_comp *gfx_fe1 = &priv->ethdr_comp[ETHDR_GFX_FE1]; + struct mtk_ethdr_comp *vdo_be = &priv->ethdr_comp[ETHDR_VDO_BE]; + struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER]; + + dev_dbg(dev, "%s-w:%d, h:%d\n", __func__, w, h); + + mtk_ddp_write(cmdq_pkt, HDR_VDO_FE_0804_BYPASS_ALL, &vdo_fe0->cmdq_base, + vdo_fe0->regs, HDR_VDO_FE_0804_HDR_DM_FE); + + mtk_ddp_write(cmdq_pkt, HDR_VDO_FE_0804_BYPASS_ALL, &vdo_fe1->cmdq_base, + vdo_fe1->regs, HDR_VDO_FE_0804_HDR_DM_FE); + + mtk_ddp_write(cmdq_pkt, HDR_GFX_FE_0204_BYPASS_ALL, &gfx_fe0->cmdq_base, + gfx_fe0->regs, HDR_GFX_FE_0204_GFX_HDR_FE); + + mtk_ddp_write(cmdq_pkt, HDR_GFX_FE_0204_BYPASS_ALL, &gfx_fe1->cmdq_base, + gfx_fe1->regs, HDR_GFX_FE_0204_GFX_HDR_FE); + + mtk_ddp_write(cmdq_pkt, HDR_VDO_BE_0204_BYPASS_ALL, &vdo_be->cmdq_base, + vdo_be->regs, HDR_VDO_BE_0204_VDO_DM_BE); + + mtk_ddp_write(cmdq_pkt, MIX_FUNC_DCM_ENABLE, &mixer->cmdq_base, mixer->regs, MIX_FUNC_DCM0); + mtk_ddp_write(cmdq_pkt, MIX_FUNC_DCM_ENABLE, &mixer->cmdq_base, mixer->regs, MIX_FUNC_DCM1); + mtk_ddp_write(cmdq_pkt, (h << 16 | w), &mixer->cmdq_base, mixer->regs, MIX_ROI_SIZE); + mtk_ddp_write(cmdq_pkt, BGCLR_BLACK, &mixer->cmdq_base, mixer->regs, MIX_ROI_BGCLR); + mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs, + MIX_L_SRC_CON(0)); + mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs, + MIX_L_SRC_CON(1)); + mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs, + MIX_L_SRC_CON(2)); + mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs, + MIX_L_SRC_CON(3)); + mtk_ddp_write(cmdq_pkt, 0x0, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(0)); + mtk_ddp_write(cmdq_pkt, OUTPUT_NO_RND | SOURCE_RGB_SEL | BACKGROUND_RELAY, + &mixer->cmdq_base, mixer->regs, MIX_DATAPATH_CON); + mtk_ddp_write_mask(cmdq_pkt, MIX_SRC_L0_EN, &mixer->cmdq_base, mixer->regs, + MIX_SRC_CON, MIX_SRC_L0_EN); + + mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_HDR_BE_ASYNC_WIDTH, 0, + w / 2, cmdq_pkt); + mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_HDR_BE_ASYNC_HEIGHT, 0, + h, cmdq_pkt); + mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_CH_SWAP, 4, 0, cmdq_pkt); +} + +void mtk_ethdr_start(struct device *dev) +{ + struct mtk_ethdr *priv = dev_get_drvdata(dev); + struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER]; + + writel(1, mixer->regs + MIX_EN); +} + +void mtk_ethdr_stop(struct device *dev) +{ + struct mtk_ethdr *priv = dev_get_drvdata(dev); + struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER]; + + writel(0, mixer->regs + MIX_EN); + writel(1, mixer->regs + MIX_RST); + reset_control_reset(devm_reset_control_array_get(dev, true, true)); + writel(0, mixer->regs + MIX_RST); +} + +int mtk_ethdr_clk_enable(struct device *dev) +{ + int ret; + struct mtk_ethdr *priv = dev_get_drvdata(dev); + + ret = clk_bulk_prepare_enable(ETHDR_CLK_NUM, priv->ethdr_clk); + if (ret) + dev_err(dev, + "ethdr_clk prepare enable failed\n"); + return ret; +} + +void mtk_ethdr_clk_disable(struct device *dev) +{ + struct mtk_ethdr *priv = dev_get_drvdata(dev); + + clk_bulk_disable_unprepare(ETHDR_CLK_NUM, priv->ethdr_clk); +} + +static int mtk_ethdr_bind(struct device *dev, struct device *master, + void *data) +{ + struct mtk_ethdr *priv = dev_get_drvdata(dev); + struct platform_device *ovl_adaptor; + struct drm_device *drm_dev = data; + struct mtk_drm_private *drm_private = drm_dev->dev_private; + + priv->mmsys_dev = drm_private->mmsys_dev; + + /* Bring up ovl adaptor rdma and merge */ + ovl_adaptor = platform_device_register_data(dev, "mediatek-disp-ovl-adaptor", + PLATFORM_DEVID_NONE, (void *)priv->mmsys_dev, + sizeof(*priv->mmsys_dev)); + if (IS_ERR(ovl_adaptor)) + return PTR_ERR(ovl_adaptor); + + priv->ovl_adaptor_dev = &ovl_adaptor->dev; + + return 0; +} + +static void mtk_ethdr_unbind(struct device *dev, struct device *master, void *data) +{ +} + +static const struct component_ops mtk_ethdr_component_ops = { + .bind = mtk_ethdr_bind, + .unbind = mtk_ethdr_unbind, +}; + +static int mtk_ethdr_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct mtk_ethdr *priv; + int ret; + int i; + + dev_info(dev, "%s+\n", __func__); + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + for (i = 0; i < ETHDR_ID_MAX; i++) { + priv->ethdr_comp[i].dev = dev; + priv->ethdr_comp[i].regs = of_iomap(dev->of_node, i); +#if IS_REACHABLE(CONFIG_MTK_CMDQ) + ret = cmdq_dev_get_client_reg(dev, + &priv->ethdr_comp[i].cmdq_base, i); + if (ret) + dev_dbg(dev, "get mediatek,gce-client-reg fail!\n"); +#endif + dev_info(dev, "[DRM]regs:0x%x, node:%s\n", + priv->ethdr_comp[i].regs, ethdr_comp_str[i]); + } + + for (i = 0; i < ETHDR_CLK_NUM; i++) + priv->ethdr_clk[i].id = ethdr_clk_str[i]; + ret = devm_clk_bulk_get_optional(dev, ETHDR_CLK_NUM, priv->ethdr_clk); + if (ret) + return ret; + + priv->irq = platform_get_irq(pdev, 0); + if (priv->irq < 0) + priv->irq = 0; + + if (priv->irq) { + ret = devm_request_irq(dev, priv->irq, mtk_ethdr_irq_handler, + IRQF_TRIGGER_NONE, dev_name(dev), priv); + if (ret < 0) { + dev_err(dev, "Failed to request irq %d: %d\n", priv->irq, ret); + return ret; + } + } + + spin_lock_init(&priv->lock); + platform_set_drvdata(pdev, priv); + + ret = component_add(dev, &mtk_ethdr_component_ops); + if (ret) + dev_notice(dev, "Failed to add component: %d\n", ret); + + dev_info(dev, "%s-\n", __func__); + pm_runtime_enable(dev); + + return ret; +} + +static int mtk_ethdr_remove(struct platform_device *pdev) +{ + component_del(&pdev->dev, &mtk_ethdr_component_ops); + pm_runtime_disable(&pdev->dev); + return 0; +} + +static const struct of_device_id mtk_ethdr_driver_dt_match[] = { + { .compatible = "mediatek,mt8195-disp-ethdr"}, + {}, +}; + +MODULE_DEVICE_TABLE(of, mtk_ethdr_driver_dt_match); + +struct platform_driver mtk_ethdr_driver = { + .probe = mtk_ethdr_probe, + .remove = mtk_ethdr_remove, + .driver = { + .name = "mediatek-disp-ethdr", + .owner = THIS_MODULE, + .of_match_table = mtk_ethdr_driver_dt_match, + }, +}; +module_platform_driver(mtk_ethdr_driver); diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.h b/drivers/gpu/drm/mediatek/mtk_ethdr.h new file mode 100644 index 000000000000..84eb9bf2ede0 --- /dev/null +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021 MediaTek Inc. + */ + +#ifndef __MTK_ETHDR_H__ +#define __MTK_ETHDR_H__ + +#include + +void mtk_ethdr_start(struct device *dev); +void mtk_ethdr_stop(struct device *dev); +int mtk_ethdr_clk_enable(struct device *dev); +void mtk_ethdr_clk_disable(struct device *dev); +void mtk_ethdr_config(struct device *dev, unsigned int w, + unsigned int h, unsigned int vrefresh, + unsigned int bpc, struct cmdq_pkt *cmdq_pkt); +void mtk_ethdr_layer_config(struct device *dev, unsigned int idx, + struct mtk_plane_state *state, + struct cmdq_pkt *cmdq_pkt); +void mtk_ethdr_enable_vblank(struct device *dev, void (*vblank_cb)(void *), + void *vblank_cb_data); +void mtk_ethdr_disable_vblank(struct device *dev); +#endif + From patchwork Mon Sep 6 07:15:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?TmFuY3kgTGluICjmnpfmrKPonqIp?= X-Patchwork-Id: 12476461 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2333CC433F5 for ; Mon, 6 Sep 2021 07:30:21 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D50FE60E8B for ; Mon, 6 Sep 2021 07:30:20 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org D50FE60E8B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ihU8BMY3DMw3JZQPo5uB8RNRCJ0VixvRxjOFQPjO0ts=; b=ClqfrKYuXd6edP 13jl3WJ6MGQz1ZZCrWAMIPjPpz8crvdknSUr9dsreJl+uRiUtEk2ME3NZroyK5PbzfoKtd5Rb5eZm KETuCdCdfc1LWrF3vnJxXblZeYjpGFP0vrYP0s+xJWVIdRGr1cM4Um3a0qzqqtr66vC4Ga9lDOp2p 66IvTTf3AsKGV1v9XBYL8RitnTzL4Hn/eA7Wxq3s0STyGkysrJTsl5TdGx3QzN346gk8I9NnXA0SJ VV6pBCFLNREFGdY5opA3jcgtfAy1qCAd5BsUM2qY8xyiPYr7phRGBQQz7LCYoBuYTx9VXl70wB29A U+1HuGwE1woto9PLDyxw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mN92V-0001qu-Su; Mon, 06 Sep 2021 07:27:37 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mN90n-0001BE-Gl; Mon, 06 Sep 2021 07:25:52 +0000 X-UUID: b5356c1639a34c8b9cc7b58c0e3840f0-20210906 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=rELAU/l/tHv/hoF1X0yoNkdbPx5h5xXPILthyVqkzB0=; b=O6HE+odLdPDrg3x4IHLTsykAx3BL8yGtqgHYVAMP4hLRFc6ct4ao5YjLbMaC/kQwX3esUdicedzBUotvoC+/18rYrbCAxWIIJTnwr6hMl5GrdMTIEJwa8rc3eor4KPek1gJ/kHA21d5svyaeNyUSIzAUSxrq5zx3dzsK2QcMsGA=; X-UUID: b5356c1639a34c8b9cc7b58c0e3840f0-20210906 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 132508750; Mon, 06 Sep 2021 00:25:47 -0700 Received: from MTKMBS07N2.mediatek.inc (172.21.101.141) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 6 Sep 2021 00:15:45 -0700 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 6 Sep 2021 15:15:42 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 6 Sep 2021 15:15:42 +0800 From: Nancy.Lin To: CK Hu CC: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Matthias Brugger , "jason-jh . lin" , "Nancy . Lin" , Yongqiang Niu , , , , , , , Subject: [PATCH v5 14/16] drm/mediatek: add ovl_adaptor support for MT8195 Date: Mon, 6 Sep 2021 15:15:37 +0800 Message-ID: <20210906071539.12953-15-nancy.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210906071539.12953-1-nancy.lin@mediatek.com> References: <20210906071539.12953-1-nancy.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210906_002549_706720_9E325D9C X-CRM114-Status: GOOD ( 20.67 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add ovl_adaptor driver for MT8195. Ovl_adaptor is an encapsulated module and designed for simplified DRM control flow. This module is composed of 8 RDMAs, 4 MERGEs and an ETHDR. Two RDMAs merge into one layer, so this module support 4 layers. Signed-off-by: Nancy.Lin --- drivers/gpu/drm/mediatek/Makefile | 1 + drivers/gpu/drm/mediatek/mtk_disp_drv.h | 16 + .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 408 ++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 + 4 files changed, 426 insertions(+) create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile index fb158a1e7f06..3abd27d7c91d 100644 --- a/drivers/gpu/drm/mediatek/Makefile +++ b/drivers/gpu/drm/mediatek/Makefile @@ -6,6 +6,7 @@ mediatek-drm-y := mtk_disp_aal.o \ mtk_disp_gamma.o \ mtk_disp_merge.o \ mtk_disp_ovl.o \ + mtk_disp_ovl_adaptor.o \ mtk_disp_rdma.o \ mtk_drm_crtc.o \ mtk_drm_ddp_comp.o \ diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h index 2446ad0a4977..6a4f4c42aedb 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -113,6 +113,22 @@ void mtk_rdma_enable_vblank(struct device *dev, void *vblank_cb_data); void mtk_rdma_disable_vblank(struct device *dev); +int mtk_ovl_adaptor_clk_enable(struct device *dev); +void mtk_ovl_adaptor_clk_disable(struct device *dev); +void mtk_ovl_adaptor_config(struct device *dev, unsigned int w, + unsigned int h, unsigned int vrefresh, + unsigned int bpc, struct cmdq_pkt *cmdq_pkt); +void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx, + struct mtk_plane_state *state, + struct cmdq_pkt *cmdq_pkt); +void mtk_ovl_adaptor_enable_vblank(struct device *dev, + void (*vblank_cb)(void *), + void *vblank_cb_data); +void mtk_ovl_adaptor_disable_vblank(struct device *dev); +void mtk_ovl_adaptor_start(struct device *dev); +void mtk_ovl_adaptor_stop(struct device *dev); +unsigned int mtk_ovl_adaptor_layer_nr(struct device *dev); + int mtk_mdp_rdma_clk_enable(struct device *dev); void mtk_mdp_rdma_clk_disable(struct device *dev); void mtk_mdp_rdma_start(struct device *dev, struct cmdq_pkt *cmdq_pkt); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c new file mode 100644 index 000000000000..068682c6fe07 --- /dev/null +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c @@ -0,0 +1,408 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021 MediaTek Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mtk_drm_drv.h" +#include "mtk_drm_crtc.h" +#include "mtk_drm_ddp_comp.h" +#include "mtk_disp_drv.h" +#include "mtk_ethdr.h" + +#define MTK_OVL_ADAPTOR_RDMA_MAX_WIDTH 1920 +#define MTK_OVL_ADAPTOR_LAYER_NUM 4 + +enum mtk_ovl_adaptor_comp_type { + OVL_ADAPTOR_TYPE_RDMA = 0, + OVL_ADAPTOR_TYPE_MERGE, + OVL_ADAPTOR_TYPE_NUM, +}; + +enum mtk_ovl_adaptor_comp_id { + OVL_ADAPTOR_MDP_RDMA0, + OVL_ADAPTOR_MDP_RDMA1, + OVL_ADAPTOR_MDP_RDMA2, + OVL_ADAPTOR_MDP_RDMA3, + OVL_ADAPTOR_MDP_RDMA4, + OVL_ADAPTOR_MDP_RDMA5, + OVL_ADAPTOR_MDP_RDMA6, + OVL_ADAPTOR_MDP_RDMA7, + OVL_ADAPTOR_MERGE0, + OVL_ADAPTOR_MERGE1, + OVL_ADAPTOR_MERGE2, + OVL_ADAPTOR_MERGE3, + OVL_ADAPTOR_ID_MAX +}; + +struct ovl_adaptor_comp_match { + enum mtk_ovl_adaptor_comp_type type; + int alias_id; +}; + +struct mtk_disp_ovl_adaptor { + struct device *ovl_adaptor_comp[OVL_ADAPTOR_ID_MAX]; + struct device *mmsys_dev; +}; + +static const char * const ovl_adaptor_comp_str[] = { + "OVL_ADAPTOR_MDP_RDMA0", + "OVL_ADAPTOR_MDP_RDMA1", + "OVL_ADAPTOR_MDP_RDMA2", + "OVL_ADAPTOR_MDP_RDMA3", + "OVL_ADAPTOR_MDP_RDMA4", + "OVL_ADAPTOR_MDP_RDMA5", + "OVL_ADAPTOR_MDP_RDMA6", + "OVL_ADAPTOR_MDP_RDMA7", + "OVL_ADAPTOR_MERGE0", + "OVL_ADAPTOR_MERGE1", + "OVL_ADAPTOR_MERGE2", + "OVL_ADAPTOR_MERGE3", + "OVL_ADAPTOR_ID_MAX" +}; + +static const char * const private_comp_stem[OVL_ADAPTOR_TYPE_NUM] = { + [OVL_ADAPTOR_TYPE_RDMA] = "vdo1_rdma", + [OVL_ADAPTOR_TYPE_MERGE] = "merge", +}; + +static const struct ovl_adaptor_comp_match comp_matches[OVL_ADAPTOR_ID_MAX] = { + [OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_RDMA, 0 }, + [OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_RDMA, 1 }, + [OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_RDMA, 2 }, + [OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_RDMA, 3 }, + [OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_RDMA, 4 }, + [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_RDMA, 5 }, + [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_RDMA, 6 }, + [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_RDMA, 7 }, + [OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, 1 }, + [OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, 2 }, + [OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, 3 }, + [OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE, 4 }, +}; + +static struct device *get_ovl_adaptor(struct device *parent) +{ + return device_find_child_by_name(parent, "mediatek-disp-ovl-adaptor"); +} + +void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx, + struct mtk_plane_state *state, + struct cmdq_pkt *cmdq_pkt) +{ + struct device *ovl_adaptor_dev = get_ovl_adaptor(dev); + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(ovl_adaptor_dev); + struct mtk_plane_pending_state *pending = &state->pending; + struct mtk_mdp_rdma_cfg rdma_config = {0}; + struct device *rdma_l; + struct device *rdma_r; + struct device *merge; + const struct drm_format_info *fmt_info = drm_format_info(pending->format); + bool use_dual_pipe = false; + unsigned int l_w = 0; + unsigned int r_w = 0; + + dev_dbg(dev, "%s+ idx:%d, enable:%d, fmt:0x%x\n", __func__, idx, + pending->enable, pending->format); + dev_dbg(dev, "addr 0x%lx, fb w:%d, {%d,%d,%d,%d}\n", + pending->addr, (pending->pitch / fmt_info->cpp[0]), + pending->x, pending->y, pending->width, pending->height); + + rdma_l = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx]; + rdma_r = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx + 1]; + merge = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + idx]; + + if (!pending->enable) { + mtk_merge_disable(merge, cmdq_pkt); + mtk_mdp_rdma_stop(rdma_l, cmdq_pkt); + mtk_mdp_rdma_stop(rdma_r, cmdq_pkt); + mtk_ethdr_layer_config(dev, idx, state, cmdq_pkt); + return; + } + + /* ETHDR is in 1T2P domain, width needs to be 2 pixels align */ + pending->width = ALIGN_DOWN(pending->width, 2); + + if (pending->width > MTK_OVL_ADAPTOR_RDMA_MAX_WIDTH) + use_dual_pipe = true; + + if (use_dual_pipe) { + l_w = (pending->width / 2) + ((pending->width / 2) % 2); + r_w = pending->width - l_w; + } else { + l_w = pending->width; + } + mtk_merge_advance_config(merge, l_w, r_w, pending->height, 0, 0, cmdq_pkt); + mtk_mmsys_ddp_config(ovl_adaptor->mmsys_dev, MMSYS_CONFIG_MERGE_ASYNC_WIDTH, + idx, pending->width / 2, cmdq_pkt); + mtk_mmsys_ddp_config(ovl_adaptor->mmsys_dev, MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, + idx, pending->height, cmdq_pkt); + + rdma_config.csc_enable = fmt_info->is_yuv ? true : false; + rdma_config.profile = RDMA_CSC_FULL709_TO_RGB; + rdma_config.width = l_w; + rdma_config.height = pending->height; + rdma_config.addr0 = pending->addr; + rdma_config.pitch = pending->pitch; + rdma_config.fmt = pending->format; + mtk_mdp_rdma_config(rdma_l, &rdma_config, cmdq_pkt); + + if (use_dual_pipe) { + rdma_config.x_left = l_w; + rdma_config.width = r_w; + mtk_mdp_rdma_config(rdma_r, &rdma_config, cmdq_pkt); + } + + mtk_merge_enable(merge, cmdq_pkt); + mtk_merge_unmute(merge, cmdq_pkt); + + mtk_mdp_rdma_start(rdma_l, cmdq_pkt); + if (use_dual_pipe) + mtk_mdp_rdma_start(rdma_r, cmdq_pkt); + else + mtk_mdp_rdma_stop(rdma_r, cmdq_pkt); + + mtk_ethdr_layer_config(dev, idx, state, cmdq_pkt); +} + +void mtk_ovl_adaptor_config(struct device *dev, unsigned int w, + unsigned int h, unsigned int vrefresh, + unsigned int bpc, struct cmdq_pkt *cmdq_pkt) +{ + mtk_ethdr_config(dev, w, h, vrefresh, bpc, cmdq_pkt); +} + +void mtk_ovl_adaptor_start(struct device *dev) +{ + mtk_ethdr_start(dev); +} + +void mtk_ovl_adaptor_stop(struct device *dev) +{ + struct device *ovl_adaptor_dev = get_ovl_adaptor(dev); + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(ovl_adaptor_dev); + struct device *rdma_l; + struct device *rdma_r; + struct device *merge; + u32 i; + + for (i = 0; i < MTK_OVL_ADAPTOR_LAYER_NUM; i++) { + rdma_l = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * i]; + rdma_r = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * i + 1]; + merge = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + i]; + + mtk_mdp_rdma_stop(rdma_l, NULL); + mtk_mdp_rdma_stop(rdma_r, NULL); + mtk_merge_stop(merge); + } + + mtk_ethdr_stop(dev); +} + +int mtk_ovl_adaptor_clk_enable(struct device *dev) +{ + struct device *ovl_adaptor_dev = get_ovl_adaptor(dev); + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(ovl_adaptor_dev); + struct device *comp; + int ret; + int i; + + for (i = OVL_ADAPTOR_MDP_RDMA0; i < OVL_ADAPTOR_ID_MAX; i++) { + comp = ovl_adaptor->ovl_adaptor_comp[i]; + + if (i < OVL_ADAPTOR_MERGE0) + ret = mtk_mdp_rdma_clk_enable(comp); + else + ret = mtk_merge_clk_enable(comp); + if (ret) { + dev_err(dev, + "Failed to enable clock %d, err %d-%s\n", + i, ret, ovl_adaptor_comp_str[i]); + goto clk_err; + } + } + + mtk_ethdr_clk_enable(dev); + return ret; + +clk_err: + while (--i >= 0) { + comp = ovl_adaptor->ovl_adaptor_comp[i]; + if (i < OVL_ADAPTOR_MERGE0) + mtk_mdp_rdma_clk_disable(comp); + else + mtk_merge_clk_disable(comp); + } + return ret; +} + +void mtk_ovl_adaptor_clk_disable(struct device *dev) +{ + struct device *ovl_adaptor_dev = get_ovl_adaptor(dev); + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(ovl_adaptor_dev); + struct device *comp; + int i; + + for (i = OVL_ADAPTOR_MDP_RDMA0; i < OVL_ADAPTOR_ID_MAX; i++) { + comp = ovl_adaptor->ovl_adaptor_comp[i]; + + if (i < OVL_ADAPTOR_MERGE0) + mtk_mdp_rdma_clk_disable(comp); + else + mtk_merge_clk_disable(comp); + } + mtk_ethdr_clk_disable(dev); +} + +unsigned int mtk_ovl_adaptor_layer_nr(struct device *dev) +{ + return MTK_OVL_ADAPTOR_LAYER_NUM; +} + +void mtk_ovl_adaptor_enable_vblank(struct device *dev, void (*vblank_cb)(void *), + void *vblank_cb_data) +{ + mtk_ethdr_enable_vblank(dev, vblank_cb, vblank_cb_data); +} + +void mtk_ovl_adaptor_disable_vblank(struct device *dev) +{ + mtk_ethdr_disable_vblank(dev); +} + +static int ovl_adaptor_comp_get_id(struct device *dev, struct device_node *node, + enum mtk_ovl_adaptor_comp_type type) +{ + int alias_id = of_alias_get_id(node, private_comp_stem[type]); + int ret; + int i; + + for (i = 0; i < ARRAY_SIZE(comp_matches); i++) + if (comp_matches[i].type == type && + comp_matches[i].alias_id == alias_id) + return i; + + dev_err(dev, "Failed to get id. type: %d, alias: %d\n", type, alias_id); + return -EINVAL; +} + +static const struct of_device_id mtk_ovl_adaptor_comp_dt_ids[] = { + { + .compatible = "mediatek,mt8195-vdo1-rdma", + .data = (void *)OVL_ADAPTOR_TYPE_RDMA, + }, { + .compatible = "mediatek,mt8195-disp-merge", + .data = (void *)OVL_ADAPTOR_TYPE_MERGE, + }, + {}, +}; + +static int ovl_adaptor_comp_init(struct device *dev) +{ + struct mtk_disp_ovl_adaptor *priv = dev_get_drvdata(dev); + struct device_node *node, *parent; + struct platform_device *comp_pdev; + int i, ret; + + parent = dev->parent->of_node->parent; + + for_each_child_of_node(parent, node) { + const struct of_device_id *of_id; + enum mtk_ovl_adaptor_comp_type type; + int id; + + of_id = of_match_node(mtk_ovl_adaptor_comp_dt_ids, node); + if (!of_id) + continue; + + if (!of_device_is_available(node)) { + dev_info(dev, "Skipping disabled component %pOF\n", + node); + continue; + } + + type = (enum mtk_ovl_adaptor_comp_type)of_id->data; + id = ovl_adaptor_comp_get_id(dev, node, type); + if (id < 0) { + dev_warn(dev, "Skipping unknown component %pOF\n", + node); + continue; + } + + comp_pdev = of_find_device_by_node(node); + if (!comp_pdev) { + dev_warn(dev, "can't find platform device of node:%s\n", + node->name); + return -ENODEV; + } + priv->ovl_adaptor_comp[id] = &comp_pdev->dev; + + dev_info(dev, "[DRM]dev:%s, node:%s\n", dev_name(priv->ovl_adaptor_comp[id]), + ovl_adaptor_comp_str[id]); + } + + return 0; +} + +static const struct of_device_id ovl_adaptor_driver_dt_match[] = { + { .compatible = "mediatek,mt8195-disp-ethdr"}, + {}, +}; +MODULE_DEVICE_TABLE(of, mtk_disp_ovl_adaptor_driver_dt_match); + +static int mtk_disp_ovl_adaptor_probe(struct platform_device *pdev) +{ + struct mtk_disp_ovl_adaptor *priv; + struct device *dev = &pdev->dev; + struct device_node *phandle = dev->parent->of_node; + const struct of_device_id *of_id; + int ret; + int i; + + dev_info(dev, "%s+\n", __func__); + + of_id = of_match_node(ovl_adaptor_driver_dt_match, phandle); + if (!of_id) + return -ENODEV; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->mmsys_dev = pdev->dev.platform_data; + + platform_set_drvdata(pdev, priv); + + ret = ovl_adaptor_comp_init(dev); + if (ret) { + dev_notice(dev, "ovl_adaptor comp init fail\n"); + return ret; + } + + dev_info(dev, "%s-\n", __func__); + return ret; +} + +static int mtk_disp_ovl_adaptor_remove(struct platform_device *pdev) +{ + return 0; +} + +struct platform_driver mtk_disp_ovl_adaptor_driver = { + .probe = mtk_disp_ovl_adaptor_probe, + .remove = mtk_disp_ovl_adaptor_remove, + .driver = { + .name = "mediatek-disp-ovl-adaptor", + .owner = THIS_MODULE, + }, +}; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h index a58cebd01d35..1ad9f7edfcc7 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h @@ -51,6 +51,7 @@ extern struct platform_driver mtk_disp_ccorr_driver; extern struct platform_driver mtk_disp_color_driver; extern struct platform_driver mtk_disp_gamma_driver; extern struct platform_driver mtk_disp_merge_driver; +extern struct platform_driver mtk_disp_ovl_adaptor_driver; extern struct platform_driver mtk_disp_ovl_driver; extern struct platform_driver mtk_disp_rdma_driver; extern struct platform_driver mtk_dpi_driver; From patchwork Mon Sep 6 07:15:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?TmFuY3kgTGluICjmnpfmrKPonqIp?= X-Patchwork-Id: 12476465 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.3 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, UNWANTED_LANGUAGE_BODY,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7CAD5C433EF for ; Mon, 6 Sep 2021 07:32:53 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4436E60E8B for ; Mon, 6 Sep 2021 07:32:53 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 4436E60E8B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=JjSI8no246pXEeH76ZDSBOt0Q2j9/GEuw8+9OyfickQ=; b=r6DA7Bu5U8FCpY CH8eaLxJMKXAgQBsFalENsd3wUxCQ1gcRUOqq/f9oUtlmBG6PogrZQSTKIJi/m1sLxaP1qnHVNDx5 Nlt1mR2XStg+4kXszknym3xniYTye78LEL4BCWYOvvWCKCNPSwCDg75L5XLXhZT+QOFBXbY25Lq57 aR2sKoLHxbL7HUaOXBtPhOjQ4EIJEGAOZO02wDsqjGxM2zgbbEiWjREv2rRE3H5vj7mWQr3wuzrgA MkDnQafpfRTdZB2rAbrgcXg2UN+72sV3LsU1Esc9/nzKQN/xZcktvwqUr6rRo87kkF4ZSwgRJgFRh mGO8gqm/QosK+R4CCejg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mN95G-0002yc-8g; Mon, 06 Sep 2021 07:30:27 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mN90q-0001CU-JP; Mon, 06 Sep 2021 07:25:56 +0000 X-UUID: 90f90626cc414567b59bb10686ad14d9-20210906 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=KF/aZkSy04JHxezpx8owLUS1KOITuHUugGkebz+IQS4=; b=iUNxsAQeXZFFoHShJkIpntqdWZVZ3GDe/5zNmREJfl0oJZRBb+Hq2ry42TQg8fNCMMbM9P8DZyFnaB/+3ygiXRAdeemi81WXdO6L0Bdf9i0ZbW1V56hHPlI/+LO8fOGKMJsxT7hPqJNo3nLRBd5wAYouPagLCzpoU8WpA0biYdg=; X-UUID: 90f90626cc414567b59bb10686ad14d9-20210906 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 73707539; Mon, 06 Sep 2021 00:25:47 -0700 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 6 Sep 2021 00:15:46 -0700 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 6 Sep 2021 15:15:42 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 6 Sep 2021 15:15:43 +0800 From: Nancy.Lin To: CK Hu CC: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Matthias Brugger , "jason-jh . lin" , "Nancy . Lin" , Yongqiang Niu , , , , , , , Subject: [PATCH v5 15/16] drm/mediatek: modify mediatek-drm for mt8195 multi mmsys support Date: Mon, 6 Sep 2021 15:15:38 +0800 Message-ID: <20210906071539.12953-16-nancy.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210906071539.12953-1-nancy.lin@mediatek.com> References: <20210906071539.12953-1-nancy.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210906_002552_764184_6F4A3F80 X-CRM114-Status: GOOD ( 20.92 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org MT8195 have two mmsys. Modify drm for MT8195 multi-mmsys support. The two mmsys (vdosys0 and vdosys1) will bring up two drm drivers, only one drm driver register as the drm device. Each drm driver binds its own component. The first bind drm driver will allocate the drm device, and the last bind drm driver registers the drm device to drm core. Each crtc path is created with the corresponding drm driver data. Signed-off-by: Nancy.Lin --- drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 25 +- drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 3 +- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 360 +++++++++++++++++++----- drivers/gpu/drm/mediatek/mtk_drm_drv.h | 8 +- 4 files changed, 320 insertions(+), 76 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c index 474efb844249..68cb15c38c3f 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c @@ -737,21 +737,28 @@ static int mtk_drm_crtc_init_comp_planes(struct drm_device *drm_dev, } int mtk_drm_crtc_create(struct drm_device *drm_dev, - const enum mtk_ddp_comp_id *path, unsigned int path_len) + const enum mtk_ddp_comp_id *path, unsigned int path_len, + int priv_data_index) { struct mtk_drm_private *priv = drm_dev->dev_private; struct device *dev = drm_dev->dev; struct mtk_drm_crtc *mtk_crtc; unsigned int num_comp_planes = 0; - int pipe = priv->num_pipes; int ret; int i; bool has_ctm = false; uint gamma_lut_size = 0; + struct drm_crtc *tmp; + int crtc_i = 0; if (!path) return 0; + priv = priv->all_drm_private[priv_data_index]; + + drm_for_each_crtc(tmp, drm_dev) + crtc_i++; + for (i = 0; i < path_len; i++) { enum mtk_ddp_comp_id comp_id = path[i]; struct device_node *node; @@ -760,7 +767,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev, if (!node) { dev_info(dev, "Not creating crtc %d because component %d is disabled or missing\n", - pipe, comp_id); + crtc_i, comp_id); return 0; } } @@ -816,25 +823,25 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev, for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { ret = mtk_drm_crtc_init_comp_planes(drm_dev, mtk_crtc, i, - pipe); + crtc_i); if (ret) return ret; } - ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, pipe); + ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, crtc_i); if (ret < 0) return ret; if (gamma_lut_size) drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size); drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size); - priv->num_pipes++; mutex_init(&mtk_crtc->hw_lock); #if IS_REACHABLE(CONFIG_MTK_CMDQ) + i = (priv->data->mmsys_dev_num > 1) ? 0 : drm_crtc_index(&mtk_crtc->base); + mtk_crtc->cmdq_client = - cmdq_mbox_create(mtk_crtc->mmsys_dev, - drm_crtc_index(&mtk_crtc->base)); + cmdq_mbox_create(mtk_crtc->mmsys_dev, i); if (IS_ERR(mtk_crtc->cmdq_client)) { dev_dbg(dev, "mtk_crtc %d failed to create mailbox client, writing register by CPU now\n", drm_crtc_index(&mtk_crtc->base)); @@ -844,7 +851,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev, if (mtk_crtc->cmdq_client) { ret = of_property_read_u32_index(priv->mutex_node, "mediatek,gce-events", - drm_crtc_index(&mtk_crtc->base), + i, &mtk_crtc->cmdq_event); if (ret) { dev_dbg(dev, "mtk_crtc %d failed to get mediatek,gce-events property\n", diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h index cb9a36c48d4f..a57eb12d7c05 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h @@ -17,7 +17,8 @@ void mtk_drm_crtc_commit(struct drm_crtc *crtc); int mtk_drm_crtc_create(struct drm_device *drm_dev, const enum mtk_ddp_comp_id *path, - unsigned int path_len); + unsigned int path_len, + int priv_data_index); int mtk_drm_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane, struct mtk_plane_state *state); void mtk_drm_crtc_async_update(struct drm_crtc *crtc, struct drm_plane *plane, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index ae8df7ecc872..782c791b368e 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -166,6 +166,8 @@ static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { .ext_path = mt2701_mtk_ddp_ext, .ext_len = ARRAY_SIZE(mt2701_mtk_ddp_ext), .shadow_register = true, + .mmsys_id = 0, + .mmsys_dev_num = 1, }; static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = { @@ -174,6 +176,8 @@ static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = { .ext_path = mt7623_mtk_ddp_ext, .ext_len = ARRAY_SIZE(mt7623_mtk_ddp_ext), .shadow_register = true, + .mmsys_id = 0, + .mmsys_dev_num = 1, }; static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { @@ -183,6 +187,8 @@ static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { .ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext), .third_path = mt2712_mtk_ddp_third, .third_len = ARRAY_SIZE(mt2712_mtk_ddp_third), + .mmsys_id = 0, + .mmsys_dev_num = 1, }; static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { @@ -190,6 +196,8 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { .main_len = ARRAY_SIZE(mt8173_mtk_ddp_main), .ext_path = mt8173_mtk_ddp_ext, .ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext), + .mmsys_id = 0, + .mmsys_dev_num = 1, }; static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { @@ -197,32 +205,219 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { .main_len = ARRAY_SIZE(mt8183_mtk_ddp_main), .ext_path = mt8183_mtk_ddp_ext, .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext), + .mmsys_id = 0, + .mmsys_dev_num = 1, }; static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = { .main_path = mt8195_mtk_ddp_main, .main_len = ARRAY_SIZE(mt8195_mtk_ddp_main), + .mmsys_id = 0, + .mmsys_dev_num = 2, }; +static const struct of_device_id mtk_drm_of_ids[] = { + { .compatible = "mediatek,mt2701-mmsys", + .data = &mt2701_mmsys_driver_data}, + { .compatible = "mediatek,mt7623-mmsys", + .data = &mt7623_mmsys_driver_data}, + { .compatible = "mediatek,mt2712-mmsys", + .data = &mt2712_mmsys_driver_data}, + { .compatible = "mediatek,mt8173-mmsys", + .data = &mt8173_mmsys_driver_data}, + { .compatible = "mediatek,mt8183-mmsys", + .data = &mt8183_mmsys_driver_data}, + { .compatible = "mediatek,mt8195-vdosys0", + .data = &mt8195_vdosys0_driver_data}, + { .compatible = "mediatek,mt8195-vdosys1", + .data = &mt8195_vdosys1_driver_data}, + { } +}; +MODULE_DEVICE_TABLE(of, mtk_drm_of_ids); + +static int mtk_drm_match(struct device *dev, void *data) +{ + if (!strncmp(dev_name(dev), "mediatek-drm", sizeof("mediatek-drm") - 1)) + return true; + return false; +} + +static int mtk_drm_get_drm_priv(struct device *dev, + struct mtk_drm_private **all_drm_priv, + int num) +{ + struct mtk_drm_private *drm_priv = dev_get_drvdata(dev); + struct device_node *phandle = dev->parent->of_node; + const struct of_device_id *of_id; + struct device_node *node; + int cnt = 0; + struct device *drm_dev; + + for_each_child_of_node(phandle->parent, node) { + struct platform_device *pdev; + + of_id = of_match_node(mtk_drm_of_ids, node); + if (!of_id) + continue; + + pdev = of_find_device_by_node(node); + if (!pdev) + continue; + + drm_dev = device_find_child(&pdev->dev, NULL, mtk_drm_match); + if (!drm_dev || !dev_get_drvdata(drm_dev)) + continue; + + all_drm_priv[cnt++] = dev_get_drvdata(drm_dev); + if (cnt == num) + break; + } + + return 0; +} + +static bool mtk_drm_check_last_drm_bind(struct device *dev) +{ + struct mtk_drm_private *drm_priv = dev_get_drvdata(dev); + struct mtk_drm_private *all_drm_priv[MAX_CRTC]; + int cnt = 0; + int i; + + mtk_drm_get_drm_priv(dev, all_drm_priv, drm_priv->data->mmsys_dev_num); + + for (i = 0; i < MAX_CRTC; i++) + if (all_drm_priv[i] && all_drm_priv[i]->mtk_drm_bound) + cnt++; + + return (drm_priv->data->mmsys_dev_num == cnt); +} + +static bool mtk_drm_find_drm_dev(struct device *dev, struct drm_device **drm) +{ + struct device_node *phandle = dev->parent->of_node; + struct mtk_drm_private *drm_priv = dev_get_drvdata(dev); + struct mtk_drm_private *all_drm_priv[MAX_CRTC]; + int i; + + if (!drm_priv->data->mmsys_dev_num) + return false; + + mtk_drm_get_drm_priv(dev, all_drm_priv, drm_priv->data->mmsys_dev_num); + + for (i = 0; i < MAX_CRTC; i++) { + if (all_drm_priv[i] && all_drm_priv[i]->mtk_drm_bound) { + *drm = all_drm_priv[i]->drm; + return true; + } + } + + return false; +} + +static int mtk_drm_setup_all_drm_private(struct device *dev) +{ + struct mtk_drm_private *drm_priv = dev_get_drvdata(dev); + struct mtk_drm_private *all_drm_priv[MAX_CRTC]; + int mmsys_dev_num = drm_priv->data->mmsys_dev_num; + int i; + int j; + + mtk_drm_get_drm_priv(dev, all_drm_priv, mmsys_dev_num); + + for (i = 0; i < mmsys_dev_num; i++) + for (j = 0; j < mmsys_dev_num; j++) + all_drm_priv[j]->all_drm_private[i] = all_drm_priv[i]; + + return 0; +} + +static bool mtk_drm_find_mmsys_comp(struct mtk_drm_private *private, int comp_id) +{ + const struct mtk_mmsys_driver_data *drv_data = private->data; + int ret = false; + int i; + + if (drv_data->mmsys_dev_num == 1) + return true; + + if (drv_data->main_path) { + for (i = 0; i < drv_data->main_len; i++) + if (drv_data->main_path[i] == comp_id) + ret |= true; + + if (i == drv_data->main_len) + ret |= false; + } + + if (drv_data->ext_path) { + for (i = 0; i < drv_data->ext_len; i++) + if (drv_data->ext_path[i] == comp_id) + ret |= true; + + if (i == drv_data->ext_len) + ret |= false; + } + + if (drv_data->third_path) { + for (i = 0; i < drv_data->third_len; i++) + if (drv_data->third_path[i] == comp_id) + ret |= true; + + if (i == drv_data->third_len) + ret |= false; + } + + return ret; +} + +static int mtk_drm_check_mutex_dev(struct mtk_drm_private *private) +{ + struct platform_device *pdev; + struct mtk_drm_private *priv_i; + int ret; + int i; + + for (i = 0; i < private->data->mmsys_dev_num; i++) { + priv_i = private->all_drm_private[i]; + + pdev = of_find_device_by_node(priv_i->mutex_node); + if (!pdev) { + dev_err(priv_i->dev, "Waiting for disp-mutex device %pOF\n", + priv_i->mutex_node); + ret = -EPROBE_DEFER; + goto err_put_mutex; + } + priv_i->mutex_dev = &pdev->dev; + } + + return 0; + +err_put_mutex: + for (i = 0; i < private->data->mmsys_dev_num; i++) { + priv_i = private->all_drm_private[i]; + of_node_put(priv_i->mutex_node); + } + + return ret; +} + static int mtk_drm_kms_init(struct drm_device *drm) { struct mtk_drm_private *private = drm->dev_private; + struct mtk_drm_private *priv_n; struct platform_device *pdev; - struct device_node *np; + struct device_node *np = NULL; struct device *dma_dev; int ret; + int i; + int j; if (!iommu_present(&platform_bus_type)) return -EPROBE_DEFER; - pdev = of_find_device_by_node(private->mutex_node); - if (!pdev) { - dev_err(drm->dev, "Waiting for disp-mutex device %pOF\n", - private->mutex_node); - of_node_put(private->mutex_node); - return -EPROBE_DEFER; - } - private->mutex_dev = &pdev->dev; + ret = mtk_drm_check_mutex_dev(private); + if (ret) + return ret; ret = drmm_mode_config_init(drm); if (ret) @@ -241,33 +436,57 @@ static int mtk_drm_kms_init(struct drm_device *drm) drm->mode_config.funcs = &mtk_drm_mode_config_funcs; drm->mode_config.helper_private = &mtk_drm_mode_config_helpers; - ret = component_bind_all(drm->dev, drm); - if (ret) - goto put_mutex_dev; + for (i = 0; i < private->data->mmsys_dev_num; i++) { + drm->dev_private = private->all_drm_private[i]; + ret = component_bind_all(private->all_drm_private[i]->dev, drm); + if (ret) + goto put_mutex_dev; + } /* * We currently support two fixed data streams, each optional, * and each statically assigned to a crtc: * OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0 ... */ - ret = mtk_drm_crtc_create(drm, private->data->main_path, - private->data->main_len); - if (ret < 0) - goto err_component_unbind; - /* ... and OVL1 -> COLOR1 -> GAMMA -> RDMA1 -> DPI0. */ - ret = mtk_drm_crtc_create(drm, private->data->ext_path, - private->data->ext_len); - if (ret < 0) - goto err_component_unbind; - - ret = mtk_drm_crtc_create(drm, private->data->third_path, - private->data->third_len); - if (ret < 0) - goto err_component_unbind; + for (i = 0; i < MAX_CRTC; i++) { + for (j = 0; j < private->data->mmsys_dev_num; j++) { + priv_n = private->all_drm_private[j]; + + if (i == 0 && priv_n->data->main_len) { + ret = mtk_drm_crtc_create(drm, priv_n->data->main_path, + priv_n->data->main_len, j); + if (ret) + goto err_component_unbind; + + if (!np) + np = priv_n->comp_node[priv_n->data->main_path[0]]; + + continue; + } else if (i == 1 && priv_n->data->ext_len) { + ret = mtk_drm_crtc_create(drm, priv_n->data->ext_path, + priv_n->data->ext_len, j); + if (ret) + goto err_component_unbind; + + if (!np) + np = priv_n->comp_node[priv_n->data->ext_path[0]]; + + continue; + } else if (i == 2 && priv_n->data->third_len) { + ret = mtk_drm_crtc_create(drm, priv_n->data->third_path, + priv_n->data->third_len, j); + if (ret) + goto err_component_unbind; + + if (!np) + np = priv_n->comp_node[priv_n->data->third_path[0]]; + + continue; + } + } + } /* Use OVL device for all DMA memory allocations */ - np = private->comp_node[private->data->main_path[0]] ?: - private->comp_node[private->data->ext_path[0]]; pdev = of_find_device_by_node(np); if (!pdev) { ret = -ENODEV; @@ -276,7 +495,8 @@ static int mtk_drm_kms_init(struct drm_device *drm) } dma_dev = &pdev->dev; - private->dma_dev = dma_dev; + for (i = 0; i < private->data->mmsys_dev_num; i++) + private->all_drm_private[i]->dma_dev = dma_dev; /* * Configure the DMA segment size to make sure we get contiguous IOVA @@ -304,9 +524,12 @@ static int mtk_drm_kms_init(struct drm_device *drm) return 0; err_component_unbind: - component_unbind_all(drm->dev, drm); + for (i = 0; i < private->data->mmsys_dev_num; i++) + component_unbind_all(private->all_drm_private[i]->dev, drm); put_mutex_dev: - put_device(private->mutex_dev); + for (i = 0; i < private->data->mmsys_dev_num; i++) + put_device(private->all_drm_private[i]->mutex_dev); + return ret; } @@ -371,12 +594,21 @@ static int mtk_drm_bind(struct device *dev) struct drm_device *drm; int ret; - drm = drm_dev_alloc(&mtk_drm_driver, dev); - if (IS_ERR(drm)) - return PTR_ERR(drm); + if (!mtk_drm_find_drm_dev(dev, &drm)) { + drm = drm_dev_alloc(&mtk_drm_driver, dev); + if (IS_ERR(drm)) + return PTR_ERR(drm); + drm->dev_private = private; + } - drm->dev_private = private; + private->dev = dev; private->drm = drm; + private->mtk_drm_bound = true; + + if (!mtk_drm_check_last_drm_bind(dev)) + return 0; + + mtk_drm_setup_all_drm_private(dev); ret = mtk_drm_kms_init(drm); if (ret < 0) @@ -401,10 +633,13 @@ static void mtk_drm_unbind(struct device *dev) { struct mtk_drm_private *private = dev_get_drvdata(dev); - drm_dev_unregister(private->drm); - mtk_drm_kms_deinit(private->drm); - drm_dev_put(private->drm); - private->num_pipes = 0; + /* for multi mmsys dev, unregister drm dev in mmsys master */ + if (private->data->mmsys_id == 0) { + drm_dev_unregister(private->drm); + mtk_drm_kms_deinit(private->drm); + drm_dev_put(private->drm); + } + private->mtk_drm_bound = false; private->drm = NULL; } @@ -487,50 +722,40 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { { } }; -static const struct of_device_id mtk_drm_of_ids[] = { - { .compatible = "mediatek,mt2701-mmsys", - .data = &mt2701_mmsys_driver_data}, - { .compatible = "mediatek,mt7623-mmsys", - .data = &mt7623_mmsys_driver_data}, - { .compatible = "mediatek,mt2712-mmsys", - .data = &mt2712_mmsys_driver_data}, - { .compatible = "mediatek,mt8173-mmsys", - .data = &mt8173_mmsys_driver_data}, - { .compatible = "mediatek,mt8183-mmsys", - .data = &mt8183_mmsys_driver_data}, - {.compatible = "mediatek,mt8195-vdosys0", - .data = &mt8195_vdosys0_driver_data}, - { } -}; -MODULE_DEVICE_TABLE(of, mtk_drm_of_ids); - static int mtk_drm_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct device_node *phandle = dev->parent->of_node; const struct of_device_id *of_id; + const struct mtk_mmsys_driver_data *drv_data; struct mtk_drm_private *private; struct device_node *node; struct component_match *match = NULL; int ret; int i; + of_id = of_match_node(mtk_drm_of_ids, phandle); + if (!of_id) + return -ENODEV; + + drv_data = of_id->data; private = devm_kzalloc(dev, sizeof(*private), GFP_KERNEL); if (!private) return -ENOMEM; + private->all_drm_private = devm_kmalloc_array(dev, drv_data->mmsys_dev_num, + sizeof(*private->all_drm_private), + GFP_KERNEL); + if (!private->all_drm_private) + return -ENOMEM; + + private->data = drv_data; private->mmsys_dev = dev->parent; if (!private->mmsys_dev) { dev_err(dev, "Failed to get MMSYS device\n"); return -ENODEV; } - of_id = of_match_node(mtk_drm_of_ids, phandle); - if (!of_id) - return -ENODEV; - - private->data = of_id->data; - /* Iterate over sibling DISP function blocks */ for_each_child_of_node(phandle->parent, node) { const struct of_device_id *of_id; @@ -550,7 +775,13 @@ static int mtk_drm_probe(struct platform_device *pdev) comp_type = (enum mtk_ddp_comp_type)of_id->data; if (comp_type == MTK_DISP_MUTEX) { - private->mutex_node = of_node_get(node); + int id; + + id = of_alias_get_id(node, "mutex"); + if (id < 0 || id == drv_data->mmsys_id) { + private->mutex_node = of_node_get(node); + dev_dbg(dev, "get mutex for mmsys %d", drv_data->mmsys_id); + } continue; } @@ -561,6 +792,9 @@ static int mtk_drm_probe(struct platform_device *pdev) continue; } + if (!mtk_drm_find_mmsys_comp(private, comp_id)) + continue; + private->comp_node[comp_id] = of_node_get(node); /* diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h index 1ad9f7edfcc7..b87ba900c8e2 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h @@ -29,14 +29,15 @@ struct mtk_mmsys_driver_data { unsigned int third_len; bool shadow_register; + unsigned int mmsys_id; + unsigned int mmsys_dev_num; }; struct mtk_drm_private { struct drm_device *drm; struct device *dma_dev; - - unsigned int num_pipes; - + bool mtk_drm_bound; + struct device *dev; struct device_node *mutex_node; struct device *mutex_dev; struct device *mmsys_dev; @@ -44,6 +45,7 @@ struct mtk_drm_private { struct mtk_ddp_comp ddp_comp[DDP_COMPONENT_ID_MAX]; const struct mtk_mmsys_driver_data *data; struct drm_atomic_state *suspend_state; + struct mtk_drm_private **all_drm_private; }; extern struct platform_driver mtk_disp_aal_driver; From patchwork Mon Sep 6 07:15:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?TmFuY3kgTGluICjmnpfmrKPonqIp?= X-Patchwork-Id: 12476421 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2CF8EC433F5 for ; Mon, 6 Sep 2021 07:19:31 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id EEF2260F6E for ; Mon, 6 Sep 2021 07:19:30 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org EEF2260F6E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=y9v1IQl7H43CVjf5oaw21cGpuhfOQq0hRB6p/HQykvQ=; b=XNRL6zWfWLbbr9 519scL8vxk9N5BLM3e6S1MX5a8lNeG83nXKxOftWvIfcozCyEwRdGa/wVR+rftrRDFffS7GD5pWRi 6kiwwXk5D2DHfDlptRkSaMaojcfTE65v8lOrCGH/Ppz5P99C+fp52nTAb47fA+/DppTZ6TssIsYjI 0lCc0GiDRfn9vRR8jsqrykL/KP1I1k4ZLaP9NO+DuAut/aUxY8g3gujqZq6POV0m24dSPWbxUpOMK sNjLS2Jgl633fHPrp0LLNhpgOhqSomZxtGi1RVCZcrUw8HkqD2D/TH3X/vMgIm7awmyp0hFq5W2Kl t2YLZBOFYex2uKC6ENew==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mN8rQ-00HXcZ-NU; Mon, 06 Sep 2021 07:16:08 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mN8r3-00HXPS-VG; Mon, 06 Sep 2021 07:15:47 +0000 X-UUID: cf174173c2a440b4895ea5db0aac0bef-20210906 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=rsX9wlZWUaBplWUQd+QEk0rUvlGFmS2Qxja0Zt/BV50=; b=S1UMFR5uaQYrRwHrc4bik2VZ5or5bKGbIp9gsBwmpv+gN+MH4dN/Y5Dn4FrrC/0LviJF7/OFhxTmNdLsrRuZ2DXRN/jTHv1pq101rDgxYNBPoAAEaH3C3JGWSRuZXNnG9oM0xqsFVyyXKigUfaRr9JKMJtskOB+hyy/vZYrFVO4=; X-UUID: cf174173c2a440b4895ea5db0aac0bef-20210906 Received: from mtkcas68.mediatek.inc [(172.29.94.19)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 961457511; Mon, 06 Sep 2021 00:15:45 -0700 Received: from MTKMBS07N2.mediatek.inc (172.21.101.141) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 6 Sep 2021 00:15:44 -0700 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 6 Sep 2021 15:15:42 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 6 Sep 2021 15:15:43 +0800 From: Nancy.Lin To: CK Hu CC: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Matthias Brugger , "jason-jh . lin" , "Nancy . Lin" , Yongqiang Niu , , , , , , , Subject: [PATCH v5 16/16] drm/mediatek: add mediatek-drm of vdosys1 support for MT8195 Date: Mon, 6 Sep 2021 15:15:39 +0800 Message-ID: <20210906071539.12953-17-nancy.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210906071539.12953-1-nancy.lin@mediatek.com> References: <20210906071539.12953-1-nancy.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210906_001546_060668_57E9B291 X-CRM114-Status: GOOD ( 14.24 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add driver data of mt8195 vdosys1 to mediatek-drm and the sub driver. Signed-off-by: Nancy.Lin --- drivers/gpu/drm/mediatek/mtk_disp_merge.c | 4 ++++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 15 +++++++++++++++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 17 +++++++++++++++++ 4 files changed, 37 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/mediatek/mtk_disp_merge.c index 41bff6d3a8da..13c788f67ced 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_merge.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include "mtk_drm_ddp_comp.h" @@ -79,6 +80,9 @@ void mtk_merge_stop(struct device *dev) struct mtk_disp_merge *priv = dev_get_drvdata(dev); mtk_merge_disable(dev, NULL); + + if (priv->async_clk) + device_reset_optional(dev); } void mtk_merge_enable(struct device *dev, struct cmdq_pkt *cmdq_pkt) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 2885fe83162a..900f9c9f61f3 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -345,6 +345,18 @@ static const struct mtk_ddp_comp_funcs ddp_ufoe = { .start = mtk_ufoe_start, }; +static const struct mtk_ddp_comp_funcs ddp_ovl_adaptor = { + .clk_enable = mtk_ovl_adaptor_clk_enable, + .clk_disable = mtk_ovl_adaptor_clk_disable, + .config = mtk_ovl_adaptor_config, + .start = mtk_ovl_adaptor_start, + .stop = mtk_ovl_adaptor_stop, + .layer_nr = mtk_ovl_adaptor_layer_nr, + .layer_config = mtk_ovl_adaptor_layer_config, + .enable_vblank = mtk_ovl_adaptor_enable_vblank, + .disable_vblank = mtk_ovl_adaptor_disable_vblank, +}; + static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = { [MTK_DISP_AAL] = "aal", [MTK_DISP_BLS] = "bls", @@ -358,6 +370,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = { [MTK_DISP_OD] = "od", [MTK_DISP_OVL] = "ovl", [MTK_DISP_OVL_2L] = "ovl-2l", + [MTK_DISP_OVL_ADAPTOR] = "ovl_adaptor", [MTK_DISP_PWM] = "pwm", [MTK_DISP_RDMA] = "rdma", [MTK_DISP_UFOE] = "ufoe", @@ -401,6 +414,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl }, [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl }, [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl }, + [DDP_COMPONENT_OVL_ADAPTOR] = { MTK_DISP_OVL_ADAPTOR, 0, &ddp_ovl_adaptor }, [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL }, [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL }, [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL }, @@ -529,6 +543,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp, type == MTK_DISP_MERGE || type == MTK_DISP_OVL || type == MTK_DISP_OVL_2L || + type == MTK_DISP_OVL_ADAPTOR || type == MTK_DISP_PWM || type == MTK_DISP_RDMA || type == MTK_DPI || diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index b42a47c06956..a8e5e770ce2f 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -30,6 +30,7 @@ enum mtk_ddp_comp_type { MTK_DISP_OD, MTK_DISP_OVL, MTK_DISP_OVL_2L, + MTK_DISP_OVL_ADAPTOR, MTK_DISP_PWM, MTK_DISP_RDMA, MTK_DISP_UFOE, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index 782c791b368e..e831175a66f3 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -160,6 +160,12 @@ static const enum mtk_ddp_comp_id mt8195_mtk_ddp_main[] = { DDP_COMPONENT_DP_INTF0, }; +static const enum mtk_ddp_comp_id mt8195_mtk_ddp_ext[] = { + DDP_COMPONENT_OVL_ADAPTOR, + DDP_COMPONENT_MERGE5, + DDP_COMPONENT_DP_INTF1, +}; + static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { .main_path = mt2701_mtk_ddp_main, .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main), @@ -216,6 +222,13 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = { .mmsys_dev_num = 2, }; +static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = { + .ext_path = mt8195_mtk_ddp_ext, + .ext_len = ARRAY_SIZE(mt8195_mtk_ddp_ext), + .mmsys_id = 1, + .mmsys_dev_num = 2, +}; + static const struct of_device_id mtk_drm_of_ids[] = { { .compatible = "mediatek,mt2701-mmsys", .data = &mt2701_mmsys_driver_data}, @@ -691,6 +704,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { .data = (void *)MTK_DISP_OVL }, { .compatible = "mediatek,mt8183-disp-ovl-2l", .data = (void *)MTK_DISP_OVL_2L }, + { .compatible = "mediatek,mt8195-disp-ethdr", + .data = (void *)MTK_DISP_OVL_ADAPTOR }, { .compatible = "mediatek,mt2701-disp-pwm", .data = (void *)MTK_DISP_BLS }, { .compatible = "mediatek,mt8173-disp-pwm", @@ -809,6 +824,7 @@ static int mtk_drm_probe(struct platform_device *pdev) comp_type == MTK_DISP_MERGE || comp_type == MTK_DISP_OVL || comp_type == MTK_DISP_OVL_2L || + comp_type == MTK_DISP_OVL_ADAPTOR || comp_type == MTK_DISP_RDMA || comp_type == MTK_DPI || comp_type == MTK_DSI) { @@ -909,6 +925,7 @@ static struct platform_driver * const mtk_drm_drivers[] = { &mtk_disp_color_driver, &mtk_disp_gamma_driver, &mtk_disp_merge_driver, + &mtk_disp_ovl_adaptor_driver, &mtk_disp_ovl_driver, &mtk_disp_rdma_driver, &mtk_dpi_driver,