From patchwork Wed Sep 8 08:23:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12480587 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 605E3C433EF for ; Wed, 8 Sep 2021 08:26:52 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2D4A960ED8 for ; Wed, 8 Sep 2021 08:26:52 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 2D4A960ED8 Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=bpoZ26fzoBLyRETIK9f83t3RaJv+nhRgkbS9rB+xMLk=; b=xB6MCFxf3O3Ulc qzv9Y8nXUPWl/Mz7vY9UxOrot7aofyaZLjnlGVqs6mBZ+Od0hc5xPNCnTqeMkc61p1RqhQX4txAMO h4r2dmU7egI13S/lKI55Hivk+FfV1y/qzmKeUMpTH4LejSpwyv3RxOYHXflqG2iUSdlCZ1Sg6Nlls n5JtuEGhvTP054+SJqmYLfk0aSgZycufNtNbKmxLNl73X5Zo9m7SDKeDCoBkwbGC97/wik7n1W3+l jYmcdZp5MA/fQkoOU9hFsBgB35Ax9aJOaMX5i3kvncc+y6eOVIORIv0lkTfqok4ocPrcV5EfpuV+K UL2RtnC6SHiAp1WXXgow==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mNssz-00696T-WD; Wed, 08 Sep 2021 08:24:50 +0000 Received: from esa.microchip.iphmx.com ([68.232.153.233]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mNssl-006948-2q for linux-arm-kernel@lists.infradead.org; Wed, 08 Sep 2021 08:24:36 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1631089474; x=1662625474; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=BXf+FHnpR4fs4FVTvZ+v1Xc+qNyyi3KSxfT/XPNM5OY=; b=dQQGKA8OORkIdwQFbIex1y6vurt6tByKK//Z0hmbPr8BDD2gAL+kqnS9 wi4I3NJdjSZa8rwYg+2znRSmCuFRxCRiicG3myHs07njQD+fxOsSVZb4G nP3/5lITbo79Yi/I4DMNbq/TrKCVDAYsPtWIVgorYYe9F0TIVI+wCUOo9 ytg0RabxB1TSF/YX3LuRRdNGCGjgzyETvT4Gk954ms4lnPTqbZoqKZLEz dX5IIUtsQgk74bq9cTc2JP39n1Lkg3Tdo+v9DIwGEi4M9Ru0M7Hz1kiBv LRfzi92P7WfqI9lr3cF/Jl9nkL67MIjavV6unHJzWus1k08edRHPjA87a Q==; IronPort-SDR: jpBvov4PZ1S5fLl1Azf7gojmJ3Ykyg1BR7maJa/wGdsU1UZORud/K2Bh9xhSVOV9uljzjAcYft HrYJ6HsP9WKo5o/Ldwft00WgbFdVt7cl/g7QqbWGcDY+nyfLEy/AMf8MG9j5zreswwfF8sRw6L C2DJm4t8jBxWfHjUTjYbOND3CSKR772hq/susIKOhWp+5qF0EFma6Ek3o1zNjqWRswWhKmaPqX 8stWkJjIVhTo04Otzm/cg2hvicYQySOxryBh9BH8gwm5tRY8QeenfrTBUSdyTPIs1YrTIriidl eYVuWnpXSB3wy/knpaeOQhE8 X-IronPort-AV: E=Sophos;i="5.85,277,1624345200"; d="scan'208";a="143286314" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 08 Sep 2021 01:24:32 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Wed, 8 Sep 2021 01:24:32 -0700 Received: from m18063-ThinkPad-T460p.mchp-main.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Wed, 8 Sep 2021 01:24:29 -0700 From: Claudiu Beznea To: , , CC: , , , Claudiu Beznea Subject: [PATCH v2 1/2] dt-bindings: microchip,eic: add bindings Date: Wed, 8 Sep 2021 11:23:49 +0300 Message-ID: <20210908082350.106948-2-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210908082350.106948-1-claudiu.beznea@microchip.com> References: <20210908082350.106948-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210908_012435_178134_8FBBB57F X-CRM114-Status: GOOD ( 13.48 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add DT bindings for Microchip External Interrupt Controller. Signed-off-by: Claudiu Beznea --- .../interrupt-controller/microchip,eic.yaml | 73 +++++++++++++++++++ 1 file changed, 73 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/microchip,eic.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/microchip,eic.yaml b/Documentation/devicetree/bindings/interrupt-controller/microchip,eic.yaml new file mode 100644 index 000000000000..917a35e97b7a --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/microchip,eic.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/microchip,eic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip External Interrupt Controller + +maintainers: + - Claudiu Beznea + +description: + This interrupt controller is found in Microchip SoCs (SAMA7G5) and provides + support for handling up to 2 external interrupt lines. + +properties: + compatible: + enum: + - microchip,sama7g5-eic + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + description: + The first cell is the input IRQ number (between 0 and 1), the second cell + is the trigger type as defined in interrupt.txt present in this directory. + + interrupts: + description: | + Contains the GIC SPI IRQs mapped to the external interrupt lines. They + should be specified sequentially from output 0 to output 1. + minItems: 2 + maxItems: 2 + + clocks: + maxItems: 1 + + clock-names: + const: pclk + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + - interrupts + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + + eic: interrupt-controller@e1628000 { + compatible = "microchip,sama7g5-eic"; + reg = <0xe1628000 0x100>; + interrupt-parent = <&gic>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = , + ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 37>; + clock-names = "pclk"; + }; + +... From patchwork Wed Sep 8 08:23:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12480589 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 27992C433EF for ; Wed, 8 Sep 2021 08:27:04 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E3AF361165 for ; Wed, 8 Sep 2021 08:27:03 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org E3AF361165 Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=M0ihJLspGlNdUTAg9cvKH/utgWpIB3tWMcPaSfDtoJk=; b=KH2m6GrOWFgo4Y TYqLKoqpLIEAcbCnumFXhKY9xRcOvZClgXbO/WsEx/+ov2hVJI0UC9w4015elTAROpNBZXJfNxN/u IT+5I6569yMXh8/BF7de9OrGHor6CTRb59FZ1lo2wUhTDXnX+91dkEnVEO0T87o8EuJx29umYu96J PYH4HwKpP7AY+JVGJwXni9achWFz872W5SPMmrR4AuYy3Zvp/tC1UaTuNdaikUBfhHM3/d2P6vDE3 611BZ8Wv9j+nVUXOKWb/nr2/gC4iouZM8MXsuGnVPYm+CQN1zn+AtkDFareH4X4adaW2VBWVmD47H emQltTrAKWA3GqMQz60Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mNstA-00697Z-Jx; Wed, 08 Sep 2021 08:25:00 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mNssn-00694e-H4 for linux-arm-kernel@lists.infradead.org; Wed, 08 Sep 2021 08:24:39 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1631089477; x=1662625477; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=CL803+H9r0bBc0YlUYvi4inAUp/+fZDOIeBm6G27KQo=; b=IxEmLRHBHqPUuDUn0jQ1oMjv6xob9A+KYphrcITbhsgLpiHyHwUlV54r MkPIzoKQEQzs1Er7dNGloaBzdqRLCK0J9C7qqU0SkY4VfzSDDU/UsW4sV D+bReUv7CC11gXTx/Mfw4FdQ3q8c+IQxTx+Y7TeQNEkeSPHILphuZ0XUf I9yMZfIshyRdySIFk7dlFzorkQuaJgdqEIGmjvmtJEgbD7s4pJ0vSoQXI 127ltUvdsLRmeaTr1N6Ifc9LaQHUqJnBbDvooAcbHIJrX5hqs6Fjw4HTB zE+2lB3YS1L49//trkaSFIoK+jOkWs7D76jxRqo9Ug3oBMdRjugxlIKWO g==; IronPort-SDR: a1bywzcGqjsrX3ClZGU4HRFnGAWO4s1g1I0eUQwo6S7Lc2qtYm/sv9jVEwl4dGWc5LrHpCqnOM g1IBRQua/oWlDId1CtV0wfZNHAcOQJXtjQ2AKWrnLML9jC1jjOAPilSdDUTxYcBnTJu3J+U3gi FGtXDLaJODDdMAvSa+IyJ+tPEmGYYUpaMOuhlfQDpVNejNiTg62Ghh3rE7T8QBPmFb7fyQ0plY F8qLuFHqcZ/uY2AmhRy6wS5sZVOHERO/aeIDPQaPemlpRKUpsYwKxUmzSSniE5nIW0x2BtRruM ZTI9n3wSFPJZIiUG6gfg6pdQ X-IronPort-AV: E=Sophos;i="5.85,277,1624345200"; d="scan'208";a="128593945" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 08 Sep 2021 01:24:35 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Wed, 8 Sep 2021 01:24:35 -0700 Received: from m18063-ThinkPad-T460p.mchp-main.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Wed, 8 Sep 2021 01:24:33 -0700 From: Claudiu Beznea To: , , CC: , , , Claudiu Beznea Subject: [PATCH v2 2/2] irqchip/mchp-eic: add support Date: Wed, 8 Sep 2021 11:23:50 +0300 Message-ID: <20210908082350.106948-3-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210908082350.106948-1-claudiu.beznea@microchip.com> References: <20210908082350.106948-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210908_012437_685344_F2F65541 X-CRM114-Status: GOOD ( 27.31 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add support for Microchip External Interrupt Controller. The controller supports 2 external interrupt lines. For every external input there is a connection to GIC. The interrupt controllers contains only 4 registers: - EIC_GFCS (read only): which indicates that glitch filter configuration is ready (not addressed in this implementation) - EIC_SCFG0R, EIC_SCFG1R (read, write): allows per interrupt specific settings: enable, polarity/edge settings, glitch filter settings - EIC_WPMR, EIC_WPSR: enables write protection mode specific settings (which are architecture specific) for the controller and are not addressed in this implementation Signed-off-by: Claudiu Beznea --- MAINTAINERS | 6 + drivers/irqchip/Kconfig | 8 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-mchp-eic.c | 314 +++++++++++++++++++++++++++++++++ 4 files changed, 329 insertions(+) create mode 100644 drivers/irqchip/irq-mchp-eic.c diff --git a/MAINTAINERS b/MAINTAINERS index c9467d2839f5..7e20a840b7dc 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12149,6 +12149,12 @@ L: linux-crypto@vger.kernel.org S: Maintained F: drivers/crypto/atmel-ecc.* +MICROCHIP EIC DRIVER +M: Claudiu Beznea +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +S: Supported +F: drivers/irqchip/irq-mchp-eic.c + MICROCHIP I2C DRIVER M: Codrin Ciubotariu L: linux-i2c@vger.kernel.org diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 4d5924e9f766..450c7b8ab30f 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -601,4 +601,12 @@ config APPLE_AIC Support for the Apple Interrupt Controller found on Apple Silicon SoCs, such as the M1. +config MCHP_EIC + bool "Microchip External Interrupt Controller" + depends on ARCH_AT91 || COMPILE_TEST + select IRQ_DOMAIN + select IRQ_DOMAIN_HIERARCHY + help + Support for Microchip External Interrupt Controller. + endmenu diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index f88cbf36a9d2..c1f611cbfbf8 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -116,3 +116,4 @@ obj-$(CONFIG_MACH_REALTEK_RTL) += irq-realtek-rtl.o obj-$(CONFIG_WPCM450_AIC) += irq-wpcm450-aic.o obj-$(CONFIG_IRQ_IDT3243X) += irq-idt3243x.o obj-$(CONFIG_APPLE_AIC) += irq-apple-aic.o +obj-$(CONFIG_MCHP_EIC) += irq-mchp-eic.o diff --git a/drivers/irqchip/irq-mchp-eic.c b/drivers/irqchip/irq-mchp-eic.c new file mode 100644 index 000000000000..ab24a464b929 --- /dev/null +++ b/drivers/irqchip/irq-mchp-eic.c @@ -0,0 +1,314 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Microchip External Interrupt Controller driver + * + * Copyright (C) 2021 Microchip Technology Inc. and its subsidiaries + * + * Author: Claudiu Beznea + */ +#include +#include +#include +#include +#include +#include + +#include + +#define MCHP_EIC_GFCS (0x0) +#define MCHP_EIC_SCFG(x) (0x4 + (x) * 0x4) +#define MCHP_EIC_SCFG_EN BIT(16) +#define MCHP_EIC_SCFG_LVL BIT(9) +#define MCHP_EIC_SCFG_POL BIT(8) + +#define MCHP_EIC_NIRQ (2) + +/* + * struct mchp_eic - EIC private data structure + * @base: base address + * @dev: eic device + * @clk: peripheral clock + * @domain: irq domain + * @irqs: irqs b/w eic and gic + * @scfg: backup for scfg registers (necessary for backup and self-refresh mode) + * @wakeup_source: wakeup source mask + */ +struct mchp_eic { + void __iomem *base; + struct device *dev; + struct clk *clk; + struct irq_domain *domain; + u32 irqs[MCHP_EIC_NIRQ]; + u32 scfg[MCHP_EIC_NIRQ]; + u32 wakeup_source; +}; + +static void mchp_eic_irq_mask(struct irq_data *d) +{ + struct mchp_eic *eic = irq_data_get_irq_chip_data(d); + unsigned int tmp; + + tmp = readl_relaxed(eic->base + MCHP_EIC_SCFG(d->hwirq)); + tmp &= ~MCHP_EIC_SCFG_EN; + writel_relaxed(tmp, eic->base + MCHP_EIC_SCFG(d->hwirq)); + + irq_chip_mask_parent(d); +} + +static void mchp_eic_irq_unmask(struct irq_data *d) +{ + struct mchp_eic *eic = irq_data_get_irq_chip_data(d); + unsigned int tmp; + + tmp = readl_relaxed(eic->base + MCHP_EIC_SCFG(d->hwirq)); + tmp |= MCHP_EIC_SCFG_EN; + writel_relaxed(tmp, eic->base + MCHP_EIC_SCFG(d->hwirq)); + + irq_chip_unmask_parent(d); +} + +static int mchp_eic_irq_set_type(struct irq_data *d, unsigned int type) +{ + struct mchp_eic *eic = irq_data_get_irq_chip_data(d); + unsigned int parent_irq_type; + unsigned int tmp; + + tmp = readl_relaxed(eic->base + MCHP_EIC_SCFG(d->hwirq)); + tmp &= ~(MCHP_EIC_SCFG_POL | MCHP_EIC_SCFG_LVL); + switch (type) { + case IRQ_TYPE_LEVEL_HIGH: + tmp |= MCHP_EIC_SCFG_POL | MCHP_EIC_SCFG_LVL; + parent_irq_type = IRQ_TYPE_LEVEL_HIGH; + break; + case IRQ_TYPE_LEVEL_LOW: + tmp |= MCHP_EIC_SCFG_LVL; + parent_irq_type = IRQ_TYPE_LEVEL_HIGH; + break; + case IRQ_TYPE_EDGE_RISING: + parent_irq_type = IRQ_TYPE_EDGE_RISING; + break; + case IRQ_TYPE_EDGE_FALLING: + tmp |= MCHP_EIC_SCFG_POL; + parent_irq_type = IRQ_TYPE_EDGE_RISING; + break; + default: + return -EINVAL; + } + + writel_relaxed(tmp, eic->base + MCHP_EIC_SCFG(d->hwirq)); + + return irq_chip_set_type_parent(d, parent_irq_type); +} + +static int mchp_eic_irq_set_wake(struct irq_data *d, unsigned int on) +{ + struct mchp_eic *eic = irq_data_get_irq_chip_data(d); + + irq_set_irq_wake(eic->irqs[d->hwirq], on); + if (on) + eic->wakeup_source |= BIT(d->hwirq); + else + eic->wakeup_source &= ~BIT(d->hwirq); + + return 0; +} + +static struct irq_chip mchp_eic_chip = { + .name = "eic", + .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SET_TYPE_MASKED, + .irq_mask = mchp_eic_irq_mask, + .irq_unmask = mchp_eic_irq_unmask, + .irq_set_type = mchp_eic_irq_set_type, + .irq_ack = irq_chip_ack_parent, + .irq_eoi = irq_chip_eoi_parent, + .irq_retrigger = irq_chip_retrigger_hierarchy, + .irq_set_wake = mchp_eic_irq_set_wake, +}; + +static int mchp_eic_domain_translate(struct irq_domain *d, + struct irq_fwspec *fwspec, + unsigned long *hwirq, + unsigned int *type) +{ + if (!is_of_node(fwspec->fwnode)) + return -EINVAL; + + if (fwspec->param_count != 2 || fwspec->param[0] >= MCHP_EIC_NIRQ) + return -EINVAL; + + *hwirq = fwspec->param[0]; + *type = fwspec->param[1]; + + return 0; +} + +static int mchp_eic_domain_alloc(struct irq_domain *domain, unsigned int virq, + unsigned int nr_irqs, void *data) +{ + struct mchp_eic *eic = domain->host_data; + struct irq_fwspec *fwspec = data; + struct irq_fwspec parent_fwspec; + irq_hw_number_t hwirq; + unsigned int type; + int ret; + + if (WARN_ON(nr_irqs != 1)) + return -EINVAL; + + ret = mchp_eic_domain_translate(domain, fwspec, &hwirq, &type); + if (ret) + return ret; + + switch (type) { + case IRQ_TYPE_EDGE_RISING: + case IRQ_TYPE_LEVEL_HIGH: + break; + case IRQ_TYPE_EDGE_FALLING: + type = IRQ_TYPE_EDGE_RISING; + break; + case IRQ_TYPE_LEVEL_LOW: + type = IRQ_TYPE_LEVEL_HIGH; + break; + default: + return -EINVAL; + } + + irq_domain_set_hwirq_and_chip(domain, virq, hwirq, &mchp_eic_chip, eic); + + parent_fwspec.fwnode = domain->parent->fwnode; + parent_fwspec.param_count = 3; + parent_fwspec.param[0] = GIC_SPI; + parent_fwspec.param[1] = eic->irqs[hwirq]; + parent_fwspec.param[2] = type; + + return irq_domain_alloc_irqs_parent(domain, virq, 1, &parent_fwspec); +} + +static const struct irq_domain_ops mchp_eic_domain_ops = { + .translate = mchp_eic_domain_translate, + .alloc = mchp_eic_domain_alloc, + .free = irq_domain_free_irqs_common, +}; + +static int mchp_eic_probe(struct platform_device *pdev) +{ + struct irq_domain *parent_domain = NULL; + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct device_node *gic_node; + struct mchp_eic *eic; + int ret, i; + + eic = devm_kzalloc(dev, sizeof(*eic), GFP_KERNEL); + if (!eic) + return -ENOMEM; + + eic->base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); + if (IS_ERR(eic->base)) + return PTR_ERR(eic->base); + + gic_node = of_irq_find_parent(np); + if (gic_node) + parent_domain = irq_find_host(gic_node); + of_node_put(gic_node); + if (!parent_domain) + return -ENODEV; + + eic->clk = devm_clk_get(dev, NULL); + if (IS_ERR(eic->clk)) + return PTR_ERR(eic->clk); + + ret = clk_prepare_enable(eic->clk); + if (ret) + return ret; + + for (i = 0; i < MCHP_EIC_NIRQ; i++) { + struct of_phandle_args irq; + + /* Disable it, if any. */ + writel_relaxed(0UL, eic->base + MCHP_EIC_SCFG(i)); + + ret = of_irq_parse_one(np, i, &irq); + if (ret) + goto clk_unprepare; + + if (WARN_ON(irq.args_count != 3)) { + ret = -EINVAL; + goto clk_unprepare; + } + + eic->irqs[i] = irq.args[1]; + } + + eic->domain = irq_domain_add_hierarchy(parent_domain, 0, MCHP_EIC_NIRQ, + np, &mchp_eic_domain_ops, eic); + if (!eic->domain) { + ret = dev_err_probe(dev, -ENOMEM, "Failed to add domain\n"); + goto clk_unprepare; + } + + eic->dev = dev; + platform_set_drvdata(pdev, eic); + + dev_info(dev, "EIC registered, nr_irqs %u\n", MCHP_EIC_NIRQ); + + return 0; + +clk_unprepare: + clk_disable_unprepare(eic->clk); + return ret; +} + +static int __maybe_unused mchp_eic_suspend(struct device *dev) +{ + struct mchp_eic *eic = dev_get_drvdata(dev); + unsigned int hwirq; + + for (hwirq = 0; hwirq < MCHP_EIC_NIRQ; hwirq++) + eic->scfg[hwirq] = readl_relaxed(eic->base + + MCHP_EIC_SCFG(hwirq)); + + if (!eic->wakeup_source) + clk_disable_unprepare(eic->clk); + + return 0; +} + +static int __maybe_unused mchp_eic_resume(struct device *dev) +{ + struct mchp_eic *eic = dev_get_drvdata(dev); + unsigned int hwirq; + + if (!eic->wakeup_source) + clk_prepare_enable(eic->clk); + + for (hwirq = 0; hwirq < MCHP_EIC_NIRQ; hwirq++) + writel_relaxed(eic->scfg[hwirq], eic->base + + MCHP_EIC_SCFG(hwirq)); + + return 0; +} + +static const struct dev_pm_ops mchp_eic_pm_ops = { + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mchp_eic_suspend, mchp_eic_resume) +}; + +static const struct of_device_id mchp_eic_dt_ids[] = { + { .compatible = "microchip,sama7g5-eic", }, + { }, +}; +MODULE_DEVICE_TABLE(of, mchp_eic_dt_ids); + +static struct platform_driver mchp_eic_device_driver = { + .probe = mchp_eic_probe, + .driver = { + .name = "mchp-eic", + .of_match_table = of_match_ptr(mchp_eic_dt_ids), + .pm = pm_ptr(&mchp_eic_pm_ops), + }, +}; +builtin_platform_driver(mchp_eic_device_driver); + +MODULE_DESCRIPTION("Microchip External Interrupt Controller"); +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Claudiu Beznea ");