From patchwork Sat Sep 11 23:26:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luca Weiss X-Patchwork-Id: 12486639 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7AA9CC433F5 for ; Sat, 11 Sep 2021 23:28:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 549D8611AD for ; Sat, 11 Sep 2021 23:28:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234385AbhIKX3T (ORCPT ); Sat, 11 Sep 2021 19:29:19 -0400 Received: from mail.z3ntu.xyz ([128.199.32.197]:56426 "EHLO mail.z3ntu.xyz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231534AbhIKX3S (ORCPT ); Sat, 11 Sep 2021 19:29:18 -0400 Received: from localhost.localdomain (ip-213-127-63-121.ip.prioritytelecom.net [213.127.63.121]) by mail.z3ntu.xyz (Postfix) with ESMTPSA id 6F69CCAEE3; Sat, 11 Sep 2021 23:28:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=z3ntu.xyz; s=z3ntu; t=1631402884; bh=Ktxuspf8zLP6lR/lYt9+9Mxagdfs83zP+MehmPTG1CM=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=Mg/PB8NJU6g5JRVRr5OmWTStLoW1tS4SMr+HVnNlhzitKABZlldHUs90EZncgonj0 aXLcONAs3R2hdDImEZnvNB62ctUF1vzEbUC60OfuG2W7ywiUsBN5pee1y6yiQyimY2 EDFU34Qe0PWAJynUWyiWCENOFIhI81f0N3wkvECc= From: Luca Weiss To: linux-arm-msm@vger.kernel.org Cc: ~postmarketos/upstreaming@lists.sr.ht, bartosz.dudziak@snejp.pl, Luca Weiss , Bjorn Andersson , Andy Gross , Linus Walleij , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/8] pinctrl: qcom: msm8226: fill in more functions Date: Sun, 12 Sep 2021 01:26:55 +0200 Message-Id: <20210911232707.259615-2-luca@z3ntu.xyz> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210911232707.259615-1-luca@z3ntu.xyz> References: <20210911232707.259615-1-luca@z3ntu.xyz> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the functions for QUP4 (spi, uart, uim & i2c), sdc3 and audio_pcm as derived from the downstream gpiomux configuration. Also sort the functions alphabetically, while we're at it. Signed-off-by: Luca Weiss Reviewed-by: Bjorn Andersson --- drivers/pinctrl/qcom/pinctrl-msm8226.c | 74 ++++++++++++++++++-------- 1 file changed, 52 insertions(+), 22 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-msm8226.c b/drivers/pinctrl/qcom/pinctrl-msm8226.c index 98779e62e951..fca0645e8008 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8226.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8226.c @@ -338,26 +338,32 @@ static const unsigned int sdc2_data_pins[] = { 122 }; * the pingroup table below. */ enum msm8226_functions { - MSM_MUX_gpio, - MSM_MUX_cci_i2c0, + MSM_MUX_audio_pcm, MSM_MUX_blsp_i2c1, MSM_MUX_blsp_i2c2, MSM_MUX_blsp_i2c3, + MSM_MUX_blsp_i2c4, MSM_MUX_blsp_i2c5, MSM_MUX_blsp_spi1, MSM_MUX_blsp_spi2, MSM_MUX_blsp_spi3, + MSM_MUX_blsp_spi4, MSM_MUX_blsp_spi5, MSM_MUX_blsp_uart1, MSM_MUX_blsp_uart2, MSM_MUX_blsp_uart3, + MSM_MUX_blsp_uart4, MSM_MUX_blsp_uart5, MSM_MUX_blsp_uim1, MSM_MUX_blsp_uim2, MSM_MUX_blsp_uim3, + MSM_MUX_blsp_uim4, MSM_MUX_blsp_uim5, MSM_MUX_cam_mclk0, MSM_MUX_cam_mclk1, + MSM_MUX_cci_i2c0, + MSM_MUX_gpio, + MSM_MUX_sdc3, MSM_MUX_wlan, MSM_MUX_NA, }; @@ -382,6 +388,10 @@ static const char * const gpio_groups[] = { "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", }; +static const char * const audio_pcm_groups[] = { + "gpio63", "gpio64", "gpio65", "gpio66" +}; + static const char * const blsp_uart1_groups[] = { "gpio0", "gpio1", "gpio2", "gpio3" }; @@ -412,6 +422,16 @@ static const char * const blsp_spi3_groups[] = { "gpio8", "gpio9", "gpio10", "gpio11" }; +static const char * const blsp_uart4_groups[] = { + "gpio12", "gpio13", "gpio14", "gpio15" +}; + +static const char * const blsp_uim4_groups[] = { "gpio12", "gpio13" }; +static const char * const blsp_i2c4_groups[] = { "gpio14", "gpio15" }; +static const char * const blsp_spi4_groups[] = { + "gpio12", "gpio13", "gpio14", "gpio15" +}; + static const char * const blsp_uart5_groups[] = { "gpio16", "gpio17", "gpio18", "gpio19" }; @@ -427,31 +447,41 @@ static const char * const cci_i2c0_groups[] = { "gpio29", "gpio30" }; static const char * const cam_mclk0_groups[] = { "gpio26" }; static const char * const cam_mclk1_groups[] = { "gpio27" }; +static const char * const sdc3_groups[] = { + "gpio39", "gpio40", "gpio41", "gpio42", "gpio43", "gpio44" +}; + static const char * const wlan_groups[] = { "gpio40", "gpio41", "gpio42", "gpio43", "gpio44" }; static const struct msm_function msm8226_functions[] = { - FUNCTION(gpio), - FUNCTION(cci_i2c0), - FUNCTION(blsp_uim1), - FUNCTION(blsp_uim2), - FUNCTION(blsp_uim3), - FUNCTION(blsp_uim5), + FUNCTION(audio_pcm), FUNCTION(blsp_i2c1), FUNCTION(blsp_i2c2), FUNCTION(blsp_i2c3), + FUNCTION(blsp_i2c4), FUNCTION(blsp_i2c5), FUNCTION(blsp_spi1), FUNCTION(blsp_spi2), FUNCTION(blsp_spi3), + FUNCTION(blsp_spi4), FUNCTION(blsp_spi5), FUNCTION(blsp_uart1), FUNCTION(blsp_uart2), FUNCTION(blsp_uart3), + FUNCTION(blsp_uart4), FUNCTION(blsp_uart5), + FUNCTION(blsp_uim1), + FUNCTION(blsp_uim2), + FUNCTION(blsp_uim3), + FUNCTION(blsp_uim4), + FUNCTION(blsp_uim5), FUNCTION(cam_mclk0), FUNCTION(cam_mclk1), + FUNCTION(cci_i2c0), + FUNCTION(gpio), + FUNCTION(sdc3), FUNCTION(wlan), }; @@ -468,10 +498,10 @@ static const struct msm_pingroup msm8226_groups[] = { PINGROUP(9, blsp_spi3, blsp_uart3, blsp_uim3, NA, NA, NA, NA), PINGROUP(10, blsp_spi3, blsp_uart3, blsp_i2c3, NA, NA, NA, NA), PINGROUP(11, blsp_spi3, blsp_uart3, blsp_i2c3, NA, NA, NA, NA), - PINGROUP(12, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(13, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(14, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(15, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(12, blsp_spi4, blsp_uart4, blsp_uim4, NA, NA, NA, NA), + PINGROUP(13, blsp_spi4, blsp_uart4, blsp_uim4, NA, NA, NA, NA), + PINGROUP(14, blsp_spi4, blsp_uart4, blsp_i2c4, NA, NA, NA, NA), + PINGROUP(15, blsp_spi4, blsp_uart4, blsp_i2c4, NA, NA, NA, NA), PINGROUP(16, blsp_spi5, blsp_uart5, blsp_uim5, NA, NA, NA, NA), PINGROUP(17, blsp_spi5, blsp_uart5, blsp_uim5, NA, NA, NA, NA), PINGROUP(18, blsp_spi5, blsp_uart5, blsp_i2c5, NA, NA, NA, NA), @@ -495,12 +525,12 @@ static const struct msm_pingroup msm8226_groups[] = { PINGROUP(36, NA, NA, NA, NA, NA, NA, NA), PINGROUP(37, NA, NA, NA, NA, NA, NA, NA), PINGROUP(38, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(39, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(40, wlan, NA, NA, NA, NA, NA, NA), - PINGROUP(41, wlan, NA, NA, NA, NA, NA, NA), - PINGROUP(42, wlan, NA, NA, NA, NA, NA, NA), - PINGROUP(43, wlan, NA, NA, NA, NA, NA, NA), - PINGROUP(44, wlan, NA, NA, NA, NA, NA, NA), + PINGROUP(39, NA, sdc3, NA, NA, NA, NA, NA), + PINGROUP(40, wlan, sdc3, NA, NA, NA, NA, NA), + PINGROUP(41, wlan, sdc3, NA, NA, NA, NA, NA), + PINGROUP(42, wlan, sdc3, NA, NA, NA, NA, NA), + PINGROUP(43, wlan, sdc3, NA, NA, NA, NA, NA), + PINGROUP(44, wlan, sdc3, NA, NA, NA, NA, NA), PINGROUP(45, NA, NA, NA, NA, NA, NA, NA), PINGROUP(46, NA, NA, NA, NA, NA, NA, NA), PINGROUP(47, NA, NA, NA, NA, NA, NA, NA), @@ -519,10 +549,10 @@ static const struct msm_pingroup msm8226_groups[] = { PINGROUP(60, NA, NA, NA, NA, NA, NA, NA), PINGROUP(61, NA, NA, NA, NA, NA, NA, NA), PINGROUP(62, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(63, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(64, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(65, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(66, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(63, audio_pcm, NA, NA, NA, NA, NA, NA), + PINGROUP(64, audio_pcm, NA, NA, NA, NA, NA, NA), + PINGROUP(65, audio_pcm, NA, NA, NA, NA, NA, NA), + PINGROUP(66, audio_pcm, NA, NA, NA, NA, NA, NA), PINGROUP(67, NA, NA, NA, NA, NA, NA, NA), PINGROUP(68, NA, NA, NA, NA, NA, NA, NA), PINGROUP(69, NA, NA, NA, NA, NA, NA, NA), From patchwork Sat Sep 11 23:26:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luca Weiss X-Patchwork-Id: 12486643 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 74F57C433F5 for ; Sat, 11 Sep 2021 23:28:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5B35C61059 for ; Sat, 11 Sep 2021 23:28:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234535AbhIKX3W (ORCPT ); Sat, 11 Sep 2021 19:29:22 -0400 Received: from mail.z3ntu.xyz ([128.199.32.197]:56438 "EHLO mail.z3ntu.xyz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231745AbhIKX3T (ORCPT ); Sat, 11 Sep 2021 19:29:19 -0400 Received: from localhost.localdomain (ip-213-127-63-121.ip.prioritytelecom.net [213.127.63.121]) by mail.z3ntu.xyz (Postfix) with ESMTPSA id CDEF7CB0EB; Sat, 11 Sep 2021 23:28:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=z3ntu.xyz; s=z3ntu; t=1631402884; bh=wNer6jHcAlMTCQrEt+Z/Z80KUeA53kL3zGKiA7X4cjA=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=pFfaSY3uToNFIG352a3JWSqfZah0umgnY/lvwgqEg5N0OM6JbVKN+VAY54ZiQYnrC yAiXLbLT8WKkdAc2klIH+a6N0U4fGpuXbhzhahn7hKpuILgYthjVXNqPqjawJfiVRq 0IspktjKNufnQU3CCXBbPw2rA2MX6iBXkEP8z4ZM= From: Luca Weiss To: linux-arm-msm@vger.kernel.org Cc: ~postmarketos/upstreaming@lists.sr.ht, bartosz.dudziak@snejp.pl, Luca Weiss , Ulf Hansson , Rob Herring , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/8] dt-bindings: mmc: sdhci-msm: Add compatible string for msm8226 Date: Sun, 12 Sep 2021 01:26:56 +0200 Message-Id: <20210911232707.259615-3-luca@z3ntu.xyz> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210911232707.259615-1-luca@z3ntu.xyz> References: <20210911232707.259615-1-luca@z3ntu.xyz> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add msm8226 SoC specific compatible strings for qcom-sdhci controller. Signed-off-by: Luca Weiss --- Documentation/devicetree/bindings/mmc/sdhci-msm.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt index 365c3fc122ea..50841e2843fc 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt @@ -13,6 +13,7 @@ Required properties: string is added to support this change - "qcom,sdhci-msm-v5". full compatible strings with SoC and version: "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4" + "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4" "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4" "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4" "qcom,msm8992-sdhci", "qcom,sdhci-msm-v4" From patchwork Sat Sep 11 23:26:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luca Weiss X-Patchwork-Id: 12486645 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 590FEC4332F for ; Sat, 11 Sep 2021 23:28:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3362B61221 for ; Sat, 11 Sep 2021 23:28:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234565AbhIKX3W (ORCPT ); Sat, 11 Sep 2021 19:29:22 -0400 Received: from mail.z3ntu.xyz ([128.199.32.197]:56444 "EHLO mail.z3ntu.xyz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231998AbhIKX3T (ORCPT ); Sat, 11 Sep 2021 19:29:19 -0400 Received: from localhost.localdomain (ip-213-127-63-121.ip.prioritytelecom.net [213.127.63.121]) by mail.z3ntu.xyz (Postfix) with ESMTPSA id 2FB0BCB101; Sat, 11 Sep 2021 23:28:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=z3ntu.xyz; s=z3ntu; t=1631402885; bh=xc2aI/Mo8Jh+ukvpd+RhhL1/Pz2izYi7zRfKbpzIg5k=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=l4imMINpyIyl9sg3FaG5yr2vagCMRLGn7JsspAjh2PqYNtDubsRwsmcVlRuMRe0wV TDOxEx+PXrmw4zppjtknDr5mmHPpm7RHoPBfdfy+PXO5PRguJgXEnaTVeN0Vpbj88Z 5GK7gH3o3mm2NfUu1oujyZt3BbWJXV5euT0Ry+9A= From: Luca Weiss To: linux-arm-msm@vger.kernel.org Cc: ~postmarketos/upstreaming@lists.sr.ht, bartosz.dudziak@snejp.pl, Luca Weiss , Andy Gross , Bjorn Andersson , Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/8] dt-bindings: firmware: scm: Add compatible for msm8226 Date: Sun, 12 Sep 2021 01:26:57 +0200 Message-Id: <20210911232707.259615-4-luca@z3ntu.xyz> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210911232707.259615-1-luca@z3ntu.xyz> References: <20210911232707.259615-1-luca@z3ntu.xyz> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add devicetree compatible for SCM present in msm8226 platform. Signed-off-by: Luca Weiss --- Documentation/devicetree/bindings/firmware/qcom,scm.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.txt b/Documentation/devicetree/bindings/firmware/qcom,scm.txt index a7333ad938d2..5a90e84b8dcf 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.txt +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.txt @@ -13,6 +13,7 @@ Required properties: * "qcom,scm-ipq806x" * "qcom,scm-ipq8074" * "qcom,scm-mdm9607" + * "qcom,scm-msm8226" * "qcom,scm-msm8660" * "qcom,scm-msm8916" * "qcom,scm-msm8960" From patchwork Sat Sep 11 23:26:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luca Weiss X-Patchwork-Id: 12486649 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 38C60C433EF for ; Sat, 11 Sep 2021 23:28:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1EEF961205 for ; Sat, 11 Sep 2021 23:28:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234601AbhIKX3X (ORCPT ); Sat, 11 Sep 2021 19:29:23 -0400 Received: from mail.z3ntu.xyz ([128.199.32.197]:56454 "EHLO mail.z3ntu.xyz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233567AbhIKX3T (ORCPT ); Sat, 11 Sep 2021 19:29:19 -0400 Received: from localhost.localdomain (ip-213-127-63-121.ip.prioritytelecom.net [213.127.63.121]) by mail.z3ntu.xyz (Postfix) with ESMTPSA id 984F8CB107; Sat, 11 Sep 2021 23:28:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=z3ntu.xyz; s=z3ntu; t=1631402885; bh=QPLQRjaA9/95ADStR64vs73+dubkS1Hp5JqXy1EMoQ8=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=lznyl8FVZ57mf+DmdHsT1ehYrdN1xYuRgAkIdrplO/5VTDJ2lx7iaR0AVUca+xsOf ISbp8oyLiGbnQcPK9ANfc+2BesFTzauez6HpKXCBAx0WijbajP9gVMENmSg1/t1/+a VkbxjiXiWG3buHeTMQAsaOU91UBEWhNQc/Qh3zzE= From: Luca Weiss To: linux-arm-msm@vger.kernel.org Cc: ~postmarketos/upstreaming@lists.sr.ht, bartosz.dudziak@snejp.pl, Luca Weiss , Andy Gross , Bjorn Andersson , Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/8] ARM: dts: qcom: msm8226: Add more SoC bits Date: Sun, 12 Sep 2021 01:26:58 +0200 Message-Id: <20210911232707.259615-5-luca@z3ntu.xyz> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210911232707.259615-1-luca@z3ntu.xyz> References: <20210911232707.259615-1-luca@z3ntu.xyz> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add nodes for sdhc, uart4, i2c, scm, smem, rpm-requests including dependencies. Signed-off-by: Luca Weiss --- arch/arm/boot/dts/qcom-msm8226.dtsi | 263 +++++++++++++++++++++++++++- 1 file changed, 255 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom-msm8226.dtsi index 2de69d56870d..72efd565c6ae 100644 --- a/arch/arm/boot/dts/qcom-msm8226.dtsi +++ b/arch/arm/boot/dts/qcom-msm8226.dtsi @@ -7,6 +7,7 @@ #include #include +#include / { #address-cells = <1>; @@ -20,6 +21,20 @@ memory@0 { reg = <0x0 0x0>; }; + clocks { + xo_board: xo_board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <19200000>; + }; + + sleep_clk: sleep_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + soc: soc { compatible = "simple-bus"; #address-cells = <1>; @@ -34,6 +49,136 @@ intc: interrupt-controller@f9000000 { #interrupt-cells = <3>; }; + apcs: syscon@f9011000 { + compatible = "syscon"; + reg = <0xf9011000 0x1000>; + }; + + sdhc_1: sdhci@f9824900 { + compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; + reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; + reg-names = "hc_mem", "core_mem"; + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + clocks = <&gcc GCC_SDCC1_APPS_CLK>, + <&gcc GCC_SDCC1_AHB_CLK>, + <&xo_board>; + clock-names = "core", "iface", "xo"; + status = "disabled"; + }; + + sdhc_2: sdhci@f98a4900 { + compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; + reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; + reg-names = "hc_mem", "core_mem"; + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + clocks = <&gcc GCC_SDCC2_APPS_CLK>, + <&gcc GCC_SDCC2_AHB_CLK>, + <&xo_board>; + clock-names = "core", "iface", "xo"; + status = "disabled"; + }; + + sdhc_3: sdhci@f9864900 { + compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; + reg = <0xf9864900 0x11c>, <0xf9864000 0x800>; + reg-names = "hc_mem", "core_mem"; + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + clocks = <&gcc GCC_SDCC3_APPS_CLK>, + <&gcc GCC_SDCC3_AHB_CLK>, + <&xo_board>; + clock-names = "core", "iface", "xo"; + status = "disabled"; + }; + + blsp1_uart3: serial@f991f000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0xf991f000 0x1000>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + blsp1_uart4: serial@f9920000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0xf9920000 0x1000>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + blsp1_i2c1: i2c@f9923000 { + status = "disabled"; + compatible = "qcom,i2c-qup-v2.1.1"; + reg = <0xf9923000 0x1000>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_i2c1_pins>; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp1_i2c2: i2c@f9924000 { + status = "disabled"; + compatible = "qcom,i2c-qup-v2.1.1"; + reg = <0xf9924000 0x1000>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_i2c2_pins>; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp1_i2c3: i2c@f9925000 { + status = "disabled"; + compatible = "qcom,i2c-qup-v2.1.1"; + reg = <0xf9925000 0x1000>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_i2c3_pins>; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp1_i2c4: i2c@f9926000 { + status = "disabled"; + compatible = "qcom,i2c-qup-v2.1.1"; + reg = <0xf9926000 0x1000>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_i2c4_pins>; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp1_i2c5: i2c@f9927000 { + status = "disabled"; + compatible = "qcom,i2c-qup-v2.1.1"; + reg = <0xf9927000 0x1000>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_i2c5_pins>; + #address-cells = <1>; + #size-cells = <0>; + }; + gcc: clock-controller@fc400000 { compatible = "qcom,gcc-msm8226"; reg = <0xfc400000 0x4000>; @@ -51,15 +196,41 @@ tlmm: pinctrl@fd510000 { interrupt-controller; #interrupt-cells = <2>; interrupts = ; - }; - blsp1_uart3: serial@f991f000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0xf991f000 0x1000>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - status = "disabled"; + blsp1_i2c1_pins: blsp1-i2c1 { + pins = "gpio2", "gpio3"; + function = "blsp_i2c1"; + drive-strength = <2>; + bias-disable; + }; + + blsp1_i2c2_pins: blsp1-i2c2 { + pins = "gpio6", "gpio7"; + function = "blsp_i2c2"; + drive-strength = <2>; + bias-disable; + }; + + blsp1_i2c3_pins: blsp1-i2c3 { + pins = "gpio10", "gpio11"; + function = "blsp_i2c3"; + drive-strength = <2>; + bias-disable; + }; + + blsp1_i2c4_pins: blsp1-i2c4 { + pins = "gpio14", "gpio15"; + function = "blsp_i2c4"; + drive-strength = <2>; + bias-disable; + }; + + blsp1_i2c5_pins: blsp1-i2c5 { + pins = "gpio18", "gpio19"; + function = "blsp_i2c5"; + drive-strength = <2>; + bias-disable; + }; }; restart@fc4ab000 { @@ -67,6 +238,22 @@ restart@fc4ab000 { reg = <0xfc4ab000 0x4>; }; + spmi_bus: spmi@fc4cf000 { + compatible = "qcom,spmi-pmic-arb"; + reg-names = "core", "intr", "cnfg"; + reg = <0xfc4cf000 0x1000>, + <0xfc4cb000 0x1000>, + <0xfc4ca000 0x1000>; + interrupt-names = "periph_irq"; + interrupts = ; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + }; + rng@f9bff000 { compatible = "qcom,prng"; reg = <0xf9bff000 0x200>; @@ -131,6 +318,66 @@ frame@f9028000 { status = "disabled"; }; }; + + rpm_msg_ram: memory@fc428000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0xfc428000 0x4000>; + }; + + tcsr_mutex_block: syscon@fd484000 { + compatible = "syscon"; + reg = <0xfd484000 0x2000>; + }; + }; + + firmware { + scm { + compatible = "qcom,scm-msm8226", "qcom,scm"; + clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>; + clock-names = "core", "bus", "iface"; + }; + }; + + tcsr_mutex: hwlock { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_block 0 0x80>; + + #hwlock-cells = <1>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + smem_region: smem@3000000 { + reg = <0x3000000 0x100000>; + no-map; + }; + }; + + smd { + compatible = "qcom,smd"; + + rpm { + interrupts = ; + qcom,ipc = <&apcs 8 0>; + qcom,smd-edge = <15>; + + rpm_requests: rpm-requests { + compatible = "qcom,rpm-msm8226"; + qcom,smd-channels = "rpm_requests"; + }; + }; + }; + + smem { + compatible = "qcom,smem"; + + memory-region = <&smem_region>; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + + hwlocks = <&tcsr_mutex 3>; }; timer { From patchwork Sat Sep 11 23:26:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luca Weiss X-Patchwork-Id: 12486647 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6EFDCC43219 for ; Sat, 11 Sep 2021 23:28:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5F5EC60FDA for ; Sat, 11 Sep 2021 23:28:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234679AbhIKX3Z (ORCPT ); Sat, 11 Sep 2021 19:29:25 -0400 Received: from mail.z3ntu.xyz ([128.199.32.197]:56472 "EHLO mail.z3ntu.xyz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234517AbhIKX3V (ORCPT ); Sat, 11 Sep 2021 19:29:21 -0400 Received: from localhost.localdomain (ip-213-127-63-121.ip.prioritytelecom.net [213.127.63.121]) by mail.z3ntu.xyz (Postfix) with ESMTPSA id 0E01BCB1FB; Sat, 11 Sep 2021 23:28:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=z3ntu.xyz; s=z3ntu; t=1631402887; bh=OcpixR9jeWmLq3TJq/m8MuZTVwFVPOE18f2h11qI8no=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=RmUjf15sPaqGnbtrrMb5OtGyhrH/g4wlKPP7vkBKWy+ukSx1fmmQZEQVWJy880nCB gDow5vjv4iHgfszUqCbeKFSmPQ2G6d1bkeypUMQsY5yuWQ6xo/iHSvvtrcWkB7nHlr 70lVstLqYygd5Bt2GnAWzuePQNRAQBZ9ae3LZcSg= From: Luca Weiss To: linux-arm-msm@vger.kernel.org Cc: ~postmarketos/upstreaming@lists.sr.ht, bartosz.dudziak@snejp.pl, Luca Weiss , Andy Gross , Bjorn Andersson , Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 5/8] ARM: dts: qcom: Add pm8226 PMIC Date: Sun, 12 Sep 2021 01:26:59 +0200 Message-Id: <20210911232707.259615-6-luca@z3ntu.xyz> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210911232707.259615-1-luca@z3ntu.xyz> References: <20210911232707.259615-1-luca@z3ntu.xyz> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The pm8226 is used with Qualcomm platforms, like msm8226. Signed-off-by: Luca Weiss --- arch/arm/boot/dts/qcom-pm8226.dtsi | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 arch/arm/boot/dts/qcom-pm8226.dtsi diff --git a/arch/arm/boot/dts/qcom-pm8226.dtsi b/arch/arm/boot/dts/qcom-pm8226.dtsi new file mode 100644 index 000000000000..dddb5150dfd7 --- /dev/null +++ b/arch/arm/boot/dts/qcom-pm8226.dtsi @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: BSD-3-Clause +#include +#include + +&spmi_bus { + pm8226_0: pm8226@0 { + compatible = "qcom,pm8226", "qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pwrkey@800 { + compatible = "qcom,pm8941-pwrkey"; + reg = <0x800>; + interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + }; + }; + + pm8226_1: pm8226@1 { + compatible = "qcom,pm8226", "qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; +}; From patchwork Sat Sep 11 23:27:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luca Weiss X-Patchwork-Id: 12486651 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 465D1C433EF for ; Sat, 11 Sep 2021 23:28:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2D92460FDA for ; Sat, 11 Sep 2021 23:28:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234699AbhIKX3Z (ORCPT ); Sat, 11 Sep 2021 19:29:25 -0400 Received: from mail.z3ntu.xyz ([128.199.32.197]:56482 "EHLO mail.z3ntu.xyz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234558AbhIKX3X (ORCPT ); Sat, 11 Sep 2021 19:29:23 -0400 Received: from localhost.localdomain (ip-213-127-63-121.ip.prioritytelecom.net [213.127.63.121]) by mail.z3ntu.xyz (Postfix) with ESMTPSA id C9EC9CB1FD; Sat, 11 Sep 2021 23:28:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=z3ntu.xyz; s=z3ntu; t=1631402889; bh=SBiA58xTiqjsvkQsR1y40mscyUIMFk4rOMRYeRucm3Q=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=l1CXgOS5WJOe57V4qUWWREgXuRCi6jen5Gx/jGp5gjWj9/fuUG8ugWCaFgSnBSIAq /zw+xtK/uzpvUNeRP+p44D7EhNZPy9Iu7fK5Kah+E74YZi8TeK36PRj6xfqnuf2OLy 9lE9VdD8BCEucS7bP0zf6Typ/j/41lVUi5yzxI+I= From: Luca Weiss To: linux-arm-msm@vger.kernel.org Cc: ~postmarketos/upstreaming@lists.sr.ht, bartosz.dudziak@snejp.pl, Luca Weiss , Rob Herring , Krzysztof Kozlowski , Shawn Guo , Oleksij Rempel , Sam Ravnborg , Linus Walleij , Daniel Palmer , Max Merchel , Hao Fang , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 6/8] dt-bindings: vendor-prefixes: add LG Electronics Date: Sun, 12 Sep 2021 01:27:00 +0200 Message-Id: <20210911232707.259615-7-luca@z3ntu.xyz> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210911232707.259615-1-luca@z3ntu.xyz> References: <20210911232707.259615-1-luca@z3ntu.xyz> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org LG Electronics is a part of the LG Corporation and produces, amongst other things, consumer electronics such as phones and smartwatches. Signed-off-by: Luca Weiss --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index a867f7102c35..b99af98bf5de 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -635,6 +635,8 @@ patternProperties: description: Lenovo Group Ltd. "^lg,.*": description: LG Corporation + "^lge,.*": + description: LG Electronics Inc. "^lgphilips,.*": description: LG Display "^libretech,.*": From patchwork Sat Sep 11 23:27:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luca Weiss X-Patchwork-Id: 12486653 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A9BF8C4321E for ; Sat, 11 Sep 2021 23:28:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 94E7F61059 for ; Sat, 11 Sep 2021 23:28:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234656AbhIKX31 (ORCPT ); Sat, 11 Sep 2021 19:29:27 -0400 Received: from mail.z3ntu.xyz ([128.199.32.197]:56504 "EHLO mail.z3ntu.xyz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234577AbhIKX3X (ORCPT ); Sat, 11 Sep 2021 19:29:23 -0400 Received: from localhost.localdomain (ip-213-127-63-121.ip.prioritytelecom.net [213.127.63.121]) by mail.z3ntu.xyz (Postfix) with ESMTPSA id 403EBCB1FE; Sat, 11 Sep 2021 23:28:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=z3ntu.xyz; s=z3ntu; t=1631402889; bh=c732++tHiJDMJoYkrOhyilXiLDF0isB13YAKanZXZdE=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=N6ivacqq25+ItskrFKCQ50g2lyXJem031ab4hHnzHZ7ZKyEESPb6HNIq/VC4mnZtd 9NEudKZ0c2uqewhiKLEomaTcIHiD8Dznbj4W69sjS2ipDR4Hc4Cf+uERLtry7c3Vi0 olnEd+5EXiKi1uYjguaVe8brP6Csd0MZQw+aFoo0= From: Luca Weiss To: linux-arm-msm@vger.kernel.org Cc: ~postmarketos/upstreaming@lists.sr.ht, bartosz.dudziak@snejp.pl, Luca Weiss , Andy Gross , Bjorn Andersson , Rob Herring , Stephen Boyd , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 7/8] dt-bindings: arm: qcom: Document APQ8026 SoC binding Date: Sun, 12 Sep 2021 01:27:01 +0200 Message-Id: <20210911232707.259615-8-luca@z3ntu.xyz> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210911232707.259615-1-luca@z3ntu.xyz> References: <20210911232707.259615-1-luca@z3ntu.xyz> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Document the APQ8026 (based on MSM8226) SoC device-tree binding and the LG G Watch R. Signed-off-by: Luca Weiss --- Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 880ddafc634e..da44688133af 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -25,6 +25,7 @@ description: | The 'SoC' element must be one of the following strings: apq8016 + apq8026 apq8074 apq8084 apq8096 @@ -92,6 +93,11 @@ properties: - qcom,apq8016-sbc - const: qcom,apq8016 + - items: + - enum: + - lge,lenok + - const: qcom,apq8026 + - items: - enum: - qcom,apq8064-cm-qs600