From patchwork Mon Sep 13 06:02:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ChiaWei Wang X-Patchwork-Id: 12490059 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 57FA2C433F5 for ; Mon, 13 Sep 2021 16:34:37 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 22A6560EE0 for ; Mon, 13 Sep 2021 16:34:37 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 22A6560EE0 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=aspeedtech.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=/cfEPON7pcT8pNY1UlZD54jpqHNKlaTGos0Z8rqNv40=; b=Zb0ELvbwdNoiod mZk6+VzSoDFLt/40TCEfXy6pIx4tkbR8VpMM5xTH6WHy4cXtR7Y5qcHsy6Rt9t+31p0KMU/APMuXS C4hYRO1h3eklG23zAiEjpuWAa7X0HtNme7+hoZom1ckknAy/c0mP3QbxZVd5eR6xdT+r5hr/ngzyM b4MHrzvzgUgQn2eML7NqwblRUbZ5R0/13fnD6QwCgmJGeM6mYI6BAILrSsxQdUdCFNR2pA3XVDjam v93Ynt5NxkGQYAbvOUr4p8qGKAKsnvq52P317faRmdLdb2tTwjb65cjHnYAFiyby60ySh2hZvBJhA y+hbwxdu7H/kqwPphg2g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mPot3-002O9Y-B4; Mon, 13 Sep 2021 16:32:53 +0000 Received: from desiato.infradead.org ([2001:8b0:10b:1:d65d:64ff:fe57:4e05]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mPosq-002O7E-IH for linux-arm-kernel@bombadil.infradead.org; Mon, 13 Sep 2021 16:32:40 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=desiato.20200630; h=Content-Type:MIME-Version:References: In-Reply-To:Message-ID:Date:Subject:CC:To:From:Sender:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description; bh=r7G6NOqnYOHbPXEA6ILhXB4/jEp0zXBaPvhoh4FEU2k=; b=f7AjEH+VJJ5ZUyDLQWBNN6+Lzb vQxGjJhgCSWcSMYemERAv2y3l5BddVhOmugdgUfZubwHwGimSv+kcdzg5rzKsbteB00P5bG4Vmjl4 sqBGSVsQVFxBP39w3r6+YgjiR+YrINtHRyK8We9Ey0FeMzP5aYxUOSiFBqaDhuG4a+WnsOcATkD5i 2eEJihHV7f6XTgrpL98mr0YyqND8Ixzu9FvbKWst/48P7CGd7WSS6rLLV/+JMaJkwQ03S8ZVVpC5x airD/QjYSwAGKf/qEjWiZLlAI2XzacvItvLLKco3oE/o4UBNIg45ly9XKdhzST8XU4yZEufcSqZkZ qafvSEbg==; Received: from twspam01.aspeedtech.com ([211.20.114.71]) by desiato.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mPf3R-002l5W-Po for linux-arm-kernel@lists.infradead.org; Mon, 13 Sep 2021 06:03:02 +0000 Received: from mail.aspeedtech.com ([192.168.0.24]) by twspam01.aspeedtech.com with ESMTP id 18D5gg90094965; Mon, 13 Sep 2021 13:42:42 +0800 (GMT-8) (envelope-from chiawei_wang@aspeedtech.com) Received: from ChiaWeiWang-PC.aspeed.com (192.168.2.66) by TWMBX02.aspeed.com (192.168.0.24) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 13 Sep 2021 14:02:27 +0800 From: Chia-Wei Wang To: , , , , , , , CC: , Subject: [PATCH v4 1/4] dt-bindings: mfd: aspeed-lpc: Convert to YAML schema Date: Mon, 13 Sep 2021 14:02:28 +0800 Message-ID: <20210913060231.15619-2-chiawei_wang@aspeedtech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210913060231.15619-1-chiawei_wang@aspeedtech.com> References: <20210913060231.15619-1-chiawei_wang@aspeedtech.com> MIME-Version: 1.0 X-Originating-IP: [192.168.2.66] X-ClientProxiedBy: TWMBX02.aspeed.com (192.168.0.24) To TWMBX02.aspeed.com (192.168.0.24) X-DNSRBL: X-MAIL: twspam01.aspeedtech.com 18D5gg90094965 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210913_070258_421876_1A0CDC80 X-CRM114-Status: GOOD ( 22.50 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Convert the bindings of Aspeed LPC from text file into YAML schema. Signed-off-by: Chia-Wei Wang --- .../devicetree/bindings/mfd/aspeed-lpc.txt | 157 --------------- .../devicetree/bindings/mfd/aspeed-lpc.yaml | 187 ++++++++++++++++++ 2 files changed, 187 insertions(+), 157 deletions(-) delete mode 100644 Documentation/devicetree/bindings/mfd/aspeed-lpc.txt create mode 100644 Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt deleted file mode 100644 index 936aa108eab4..000000000000 --- a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt +++ /dev/null @@ -1,157 +0,0 @@ -====================================================================== -Device tree bindings for the Aspeed Low Pin Count (LPC) Bus Controller -====================================================================== - -The LPC bus is a means to bridge a host CPU to a number of low-bandwidth -peripheral devices, replacing the use of the ISA bus in the age of PCI[0]. The -primary use case of the Aspeed LPC controller is as a slave on the bus -(typically in a Baseboard Management Controller SoC), but under certain -conditions it can also take the role of bus master. - -The LPC controller is represented as a multi-function device to account for the -mix of functionality, which includes, but is not limited to: - -* An IPMI Block Transfer[2] Controller - -* An LPC Host Controller: Manages LPC functions such as host vs slave mode, the - physical properties of some LPC pins, configuration of serial IRQs, and - APB-to-LPC bridging amonst other functions. - -* An LPC Host Interface Controller: Manages functions exposed to the host such - as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART - management and bus snoop configuration. - -* A set of SuperIO[3] scratch registers: Enables implementation of e.g. custom - hardware management protocols for handover between the host and baseboard - management controller. - -Additionally the state of the LPC controller influences the pinmux -configuration, therefore the host portion of the controller is exposed as a -syscon as a means to arbitrate access. - -[0] http://www.intel.com/design/chipsets/industry/25128901.pdf -[1] https://www.renesas.com/en-sg/doc/products/mpumcu/001/rej09b0078_h8s2168.pdf?key=7c88837454702128622bee53acbda8f4 -[2] https://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/ipmi-second-gen-interface-spec-v2-rev1-1.pdf -[3] https://en.wikipedia.org/wiki/Super_I/O - -Required properties -=================== - -- compatible: One of: - "aspeed,ast2400-lpc-v2", "simple-mfd", "syscon" - "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon" - "aspeed,ast2600-lpc-v2", "simple-mfd", "syscon" - -- reg: contains the physical address and length values of the Aspeed - LPC memory region. - -- #address-cells: <1> -- #size-cells: <1> -- ranges: Maps 0 to the physical address and length of the LPC memory - region - -Example: - -lpc: lpc@1e789000 { - compatible = "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon"; - reg = <0x1e789000 0x1000>; - - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x1e789000 0x1000>; - - lpc_snoop: lpc-snoop@0 { - compatible = "aspeed,ast2600-lpc-snoop"; - reg = <0x0 0x80>; - interrupts = ; - snoop-ports = <0x80>; - }; -}; - - -LPC Host Interface Controller -------------------- - -The LPC Host Interface Controller manages functions exposed to the host such as -LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART -management and bus snoop configuration. - -Required properties: - -- compatible: One of: - "aspeed,ast2400-lpc-ctrl"; - "aspeed,ast2500-lpc-ctrl"; - "aspeed,ast2600-lpc-ctrl"; - -- reg: contains offset/length values of the host interface controller - memory regions - -- clocks: contains a phandle to the syscon node describing the clocks. - There should then be one cell representing the clock to use - -Optional properties: - -- memory-region: A phandle to a reserved_memory region to be used for the LPC - to AHB mapping - -- flash: A phandle to the SPI flash controller containing the flash to - be exposed over the LPC to AHB mapping - -Example: - -lpc_ctrl: lpc-ctrl@80 { - compatible = "aspeed,ast2500-lpc-ctrl"; - reg = <0x80 0x80>; - clocks = <&syscon ASPEED_CLK_GATE_LCLK>; - memory-region = <&flash_memory>; - flash = <&spi>; -}; - -LPC Host Controller -------------------- - -The Aspeed LPC Host Controller configures the Low Pin Count (LPC) bus behaviour -between the host and the baseboard management controller. The registers exist -in the "host" portion of the Aspeed LPC controller, which must be the parent of -the LPC host controller node. - -Required properties: - -- compatible: One of: - "aspeed,ast2400-lhc"; - "aspeed,ast2500-lhc"; - "aspeed,ast2600-lhc"; - -- reg: contains offset/length values of the LHC memory regions. In the - AST2400 and AST2500 there are two regions. - -Example: - -lhc: lhc@a0 { - compatible = "aspeed,ast2500-lhc"; - reg = <0xa0 0x24 0xc8 0x8>; -}; - -LPC reset control ------------------ - -The UARTs present in the ASPEED SoC can have their resets tied to the reset -state of the LPC bus. Some systems may chose to modify this configuration. - -Required properties: - - - compatible: One of: - "aspeed,ast2600-lpc-reset"; - "aspeed,ast2500-lpc-reset"; - "aspeed,ast2400-lpc-reset"; - - - reg: offset and length of the IP in the LHC memory region - - #reset-controller indicates the number of reset cells expected - -Example: - -lpc_reset: reset-controller@98 { - compatible = "aspeed,ast2500-lpc-reset"; - reg = <0x98 0x4>; - #reset-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml b/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml new file mode 100644 index 000000000000..4e3862cf2a4b --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml @@ -0,0 +1,187 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# # Copyright (c) 2021 Aspeed Tehchnology Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/aspeed-lpc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Aspeed Low Pin Count (LPC) Bus Controller + +maintainers: + - Andrew Jeffery + - Chia-Wei Wang + +description: + The LPC bus is a means to bridge a host CPU to a number of low-bandwidth + peripheral devices, replacing the use of the ISA bus in the age of PCI[0]. The + primary use case of the Aspeed LPC controller is as a slave on the bus + (typically in a Baseboard Management Controller SoC), but under certain + conditions it can also take the role of bus master. + + The LPC controller is represented as a multi-function device to account for the + mix of functionality, which includes, but is not limited to + + * An IPMI Block Transfer[2] Controller + + * An LPC Host Interface Controller manages functions exposed to the host such + as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART + management and bus snoop configuration. + + * A set of SuperIO[3] scratch registers enableing implementation of e.g. custom + hardware management protocols for handover between the host and baseboard + management controller. + + Additionally the state of the LPC controller influences the pinmux + configuration, therefore the host portion of the controller is exposed as a + syscon as a means to arbitrate access. + +properties: + compatible: + items: + - enum: + - aspeed,ast2400-lpc-v2 + - aspeed,ast2500-lpc-v2 + - aspeed,ast2600-lpc-v2 + - const: simple-mfd + - const: syscon + + reg: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + ranges: true + +patternProperties: + "^lpc-ctrl@[0-9a-f]+$": + type: object + + description: + The LPC Host Interface Controller manages functions exposed to the host such as + LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART management + and bus snoop configuration. + + properties: + comptabile: + items: + - enum: + - aspeed,ast2400-lpc-ctrl + - aspeed,ast2500-lpc-ctrl + - aspeed,ast2600-lpc-ctrl + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + memory-region: + $ref: /schemas/types.yaml#/definitions/phandle + description: A reserved_memory region to be used for the LPC to AHB mapping + + flash: + $ref: /schemas/types.yaml#/definitions/phandle + description: The SPI flash controller containing the flash to be exposed over the LPC to AHB mapping + + required: + - compatible + - clocks + + "^reset-controller@[0-9a-f]+$": + type: object + + description: + The UARTs present in the ASPEED SoC can have their resets tied to the reset + state of the LPC bus. Some systems may chose to modify this configuration + + properties: + comptabile: + items: + - enum: + - aspeed,ast2400-lpc-reset + - aspeed,ast2500-lpc-reset + - aspeed,ast2600-lpc-reset + + reg: + maxItems: 1 + + required: + - compatible + + "^lpc-snoop@[0-9a-f]+$": + type: object + + description: + The LPC snoop interface allows the BMC to listen on and record the data + bytes written by the Host to the targeted LPC I/O pots. + + properties: + comptabile: + items: + - enum: + - aspeed,ast2400-lpc-snoop + - aspeed,ast2500-lpc-snoop + - aspeed,ast2600-lpc-snoop + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + snoop-ports: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: The LPC I/O ports to snoop + + required: + - compatible + - interrupts + - snoop-ports + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - ranges + +additionalProperties: false + +examples: + - | + #include + #include + + lpc: lpc@1e789000 { + compatible = "aspeed,ast2600-lpc-v2", "simple-mfd", "syscon"; + reg = <0x1e789000 0x1000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1e789000 0x1000>; + + lpc_ctrl: lpc-ctrl@80 { + compatible = "aspeed,ast2600-lpc-ctrl"; + reg = <0x80 0x80>; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; + memory-region = <&flash_memory>; + flash = <&spi>; + }; + + lpc_reset: reset-controller@98 { + compatible = "aspeed,ast2600-lpc-reset"; + reg = <0x98 0x4>; + #reset-cells = <1>; + }; + + lpc_snoop: lpc-snoop@80 { + compatible = "aspeed,ast2600-lpc-snoop"; + reg = <0x80 0x80>; + interrupts = ; + snoop-ports = <0x80>; + }; + }; From patchwork Mon Sep 13 06:02:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ChiaWei Wang X-Patchwork-Id: 12490057 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B2B04C433FE for ; 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bh=i3Z2kPopaxBRQ6u02CW0eVMClsuUQ+oziQxCCMCV1p0=; b=nDQUhXy3zUAAvjd30fCyNERD3f qbsa7azUE8e3TRRUdqsMzbEuzhDNfje4BiadBeWmeGmi2dm6SG4jOJqHOaTt4vpZPjW8a2H6K7o5J XFS7EnBhfVTeF7r8ILz8JF/lwl00ZFTXX5Me4qEceLXqgUbdFFyCEmGxwqo19iW0ZJCD+6V1zCrRG yh0Az2r+U2zJ/sRcAB/ym8Yes22y8won3whdZ18LW4FSnI4ej0au59dVMTNOsqBUEOoPyyL5HSRpj qBHXNR7uJQkqngNmjGhBw029YDfQqpzHI9XDAnPhNxyNnIW1XYHSRr9lTuJsMIvFdc3Witx8rFnWK QYgYWYbw==; Received: from twspam01.aspeedtech.com ([211.20.114.71]) by desiato.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mPf3R-002l5X-PY for linux-arm-kernel@lists.infradead.org; Mon, 13 Sep 2021 06:03:01 +0000 Received: from mail.aspeedtech.com ([192.168.0.24]) by twspam01.aspeedtech.com with ESMTP id 18D5gg91094965; Mon, 13 Sep 2021 13:42:44 +0800 (GMT-8) (envelope-from chiawei_wang@aspeedtech.com) Received: from ChiaWeiWang-PC.aspeed.com (192.168.2.66) by TWMBX02.aspeed.com (192.168.0.24) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 13 Sep 2021 14:02:27 +0800 From: Chia-Wei Wang To: , , , , , , , CC: , Subject: [PATCH v4 2/4] dt-bindings: aspeed: Add UART routing controller Date: Mon, 13 Sep 2021 14:02:29 +0800 Message-ID: <20210913060231.15619-3-chiawei_wang@aspeedtech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210913060231.15619-1-chiawei_wang@aspeedtech.com> References: <20210913060231.15619-1-chiawei_wang@aspeedtech.com> MIME-Version: 1.0 X-Originating-IP: [192.168.2.66] X-ClientProxiedBy: TWMBX02.aspeed.com (192.168.0.24) To TWMBX02.aspeed.com (192.168.0.24) X-DNSRBL: X-MAIL: twspam01.aspeedtech.com 18D5gg91094965 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210913_070258_421854_F549C248 X-CRM114-Status: GOOD ( 18.14 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add dt-bindings for Aspeed UART routing controller. Signed-off-by: Oskar Senft Signed-off-by: Chia-Wei Wang --- .../devicetree/bindings/mfd/aspeed-lpc.yaml | 4 ++ .../bindings/soc/aspeed/uart-routing.yaml | 70 +++++++++++++++++++ 2 files changed, 74 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/aspeed/uart-routing.yaml diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml b/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml index 4e3862cf2a4b..f9aa431127ee 100644 --- a/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml +++ b/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml @@ -142,6 +142,10 @@ patternProperties: - interrupts - snoop-ports + "^uart-routing@[0-9a-f]+$": + $ref: /schemas/soc/aspeed/uart-routing.yaml# + description: The UART routing control under LPC register space + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/soc/aspeed/uart-routing.yaml b/Documentation/devicetree/bindings/soc/aspeed/uart-routing.yaml new file mode 100644 index 000000000000..534b2a9340ce --- /dev/null +++ b/Documentation/devicetree/bindings/soc/aspeed/uart-routing.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# # Copyright (c) 2018 Google LLC +# # Copyright (c) 2021 Aspeed Technology Inc. +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/soc/aspeed/uart-routing.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Aspeed UART Routing Controller + +maintainers: + - Oskar Senft + - Chia-Wei Wang + +description: + The Aspeed UART routing control allow to dynamically route the inputs for + the built-in UARTS and physical serial I/O ports. + + This allows, for example, to connect the output of UART to another UART. + This can be used to enable Host <-> BMC communication via UARTs, e.g. to + allow access to the Host's serial console. + + This driver is for the BMC side. The sysfs files allow the BMC userspace + which owns the system configuration policy, to configure how UARTs and + physical serial I/O ports are routed. + + Two types of files, uart* and io*, are presented in sysfs. The uart* + configures the input signal of a UART controller whereas io* configures + that of a physical serial port. + + When read, each file shows the list of available options with currently + selected option marked by brackets "[]". The list of available options + depends on the selected file. + + e.g. + cat /sys/bus/platform/drivers/aspeed-uart-routing/*.uart_routing/uart1 + [io1] io2 io3 io4 uart2 uart3 uart4 io6 + + In this case, UART1 gets its input from IO1 (physical serial port 1). + +properties: + compatible: + items: + - enum: + - aspeed,ast2400-uart-routing + - aspeed,ast2500-uart-routing + - aspeed,ast2600-uart-routing + reg: + maxItems: 1 + +required: + - compatible + +additionalProperties: false + +examples: + - | + lpc: lpc@1e789000 { + compatible = "aspeed,ast2600-lpc-v2", "simple-mfd", "syscon"; + reg = <0x1e789000 0x1000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1e789000 0x1000>; + + uart_routing: uart-routing@98 { + compatible = "aspeed,ast2600-uart-routing"; + reg = <0x98 0x8>; + }; + }; From patchwork Mon Sep 13 06:02:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ChiaWei Wang X-Patchwork-Id: 12490063 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8750BC433F5 for ; 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Users can perform runtime configuration of the RX muxes among the UART controllers and the UART IO pins. The sysfs interface is also exported for the convenience of routing paths check and update. Signed-off-by: Oskar Senft Signed-off-by: Chia-Wei Wang Tested-by: Lei YU --- .../testing/sysfs-driver-aspeed-uart-routing | 15 + drivers/soc/aspeed/Kconfig | 10 + drivers/soc/aspeed/Makefile | 9 +- drivers/soc/aspeed/aspeed-uart-routing.c | 603 ++++++++++++++++++ 4 files changed, 633 insertions(+), 4 deletions(-) create mode 100644 Documentation/ABI/testing/sysfs-driver-aspeed-uart-routing create mode 100644 drivers/soc/aspeed/aspeed-uart-routing.c diff --git a/Documentation/ABI/testing/sysfs-driver-aspeed-uart-routing b/Documentation/ABI/testing/sysfs-driver-aspeed-uart-routing new file mode 100644 index 000000000000..65f899f1f055 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-driver-aspeed-uart-routing @@ -0,0 +1,15 @@ +What: /sys/bus/platform/drivers/aspeed-uart-routing/*/uart* +Date: September 2021 +Contact: Chia-Wei Wang +Description: Selects the RX source of the UARTx device. The current + selection will be marked with the '[]' brackets. +Users: OpenBMC. Proposed changes should be mailed to + openbmc@lists.ozlabs.org + +What: /sys/bus/platform/drivers/aspeed-uart-routing/*/io* +Date: September 2021 +Contact: Chia-Wei Wang +Description: Selects the RX source of IOx pins. The current selection + will be marked with the '[]' brackets. +Users: OpenBMC. Proposed changes should be mailed to + openbmc@lists.ozlabs.org diff --git a/drivers/soc/aspeed/Kconfig b/drivers/soc/aspeed/Kconfig index 243ca196e6ad..f579ee0b5afa 100644 --- a/drivers/soc/aspeed/Kconfig +++ b/drivers/soc/aspeed/Kconfig @@ -24,6 +24,16 @@ config ASPEED_LPC_SNOOP allows the BMC to listen on and save the data written by the host to an arbitrary LPC I/O port. +config ASPEED_UART_ROUTING + tristate "ASPEED uart routing control" + select REGMAP + select MFD_SYSCON + default ARCH_ASPEED + help + Provides a driver to control the UART routing paths, allowing + users to perform runtime configuration of the RX muxes among + the UART controllers and I/O pins. + config ASPEED_P2A_CTRL tristate "ASPEED P2A (VGA MMIO to BMC) bridge control" select REGMAP diff --git a/drivers/soc/aspeed/Makefile b/drivers/soc/aspeed/Makefile index fcab7192e1a4..b35d74592964 100644 --- a/drivers/soc/aspeed/Makefile +++ b/drivers/soc/aspeed/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only -obj-$(CONFIG_ASPEED_LPC_CTRL) += aspeed-lpc-ctrl.o -obj-$(CONFIG_ASPEED_LPC_SNOOP) += aspeed-lpc-snoop.o -obj-$(CONFIG_ASPEED_P2A_CTRL) += aspeed-p2a-ctrl.o -obj-$(CONFIG_ASPEED_SOCINFO) += aspeed-socinfo.o +obj-$(CONFIG_ASPEED_LPC_CTRL) += aspeed-lpc-ctrl.o +obj-$(CONFIG_ASPEED_LPC_SNOOP) += aspeed-lpc-snoop.o +obj-$(CONFIG_ASPEED_UART_ROUTING) += aspeed-uart-routing.o +obj-$(CONFIG_ASPEED_P2A_CTRL) += aspeed-p2a-ctrl.o +obj-$(CONFIG_ASPEED_SOCINFO) += aspeed-socinfo.o diff --git a/drivers/soc/aspeed/aspeed-uart-routing.c b/drivers/soc/aspeed/aspeed-uart-routing.c new file mode 100644 index 000000000000..ef8b24fd1851 --- /dev/null +++ b/drivers/soc/aspeed/aspeed-uart-routing.c @@ -0,0 +1,603 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2018 Google LLC + * Copyright (c) 2021 Aspeed Technology Inc. + */ +#include +#include +#include +#include +#include +#include +#include + +/* register offsets */ +#define HICR9 0x98 +#define HICRA 0x9c + +/* attributes options */ +#define UART_ROUTING_IO1 "io1" +#define UART_ROUTING_IO2 "io2" +#define UART_ROUTING_IO3 "io3" +#define UART_ROUTING_IO4 "io4" +#define UART_ROUTING_IO5 "io5" +#define UART_ROUTING_IO6 "io6" +#define UART_ROUTING_IO10 "io10" +#define UART_ROUTING_UART1 "uart1" +#define UART_ROUTING_UART2 "uart2" +#define UART_ROUTING_UART3 "uart3" +#define UART_ROUTING_UART4 "uart4" +#define UART_ROUTING_UART5 "uart5" +#define UART_ROUTING_UART6 "uart6" +#define UART_ROUTING_UART10 "uart10" +#define UART_ROUTING_RES "reserved" + +struct aspeed_uart_routing { + struct regmap *map; + struct attribute_group const *attr_grp; +}; + +struct aspeed_uart_routing_selector { + struct device_attribute dev_attr; + uint8_t reg; + uint8_t mask; + uint8_t shift; + const char *const options[]; +}; + +#define to_routing_selector(_dev_attr) \ + container_of(_dev_attr, struct aspeed_uart_routing_selector, dev_attr) + +static ssize_t aspeed_uart_routing_show(struct device *dev, + struct device_attribute *attr, + char *buf); + +static ssize_t aspeed_uart_routing_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count); + +#define ROUTING_ATTR(_name) { \ + .attr = {.name = _name, \ + .mode = VERIFY_OCTAL_PERMISSIONS(0644) }, \ + .show = aspeed_uart_routing_show, \ + .store = aspeed_uart_routing_store, \ +} + +/* routing selector for AST25xx */ +static struct aspeed_uart_routing_selector ast2500_io6_sel = { + .dev_attr = ROUTING_ATTR(UART_ROUTING_IO6), + .reg = HICR9, + .shift = 8, + .mask = 0xf, + .options = { + UART_ROUTING_UART1, + UART_ROUTING_UART2, + UART_ROUTING_UART3, + UART_ROUTING_UART4, + UART_ROUTING_UART5, + UART_ROUTING_IO1, + UART_ROUTING_IO2, + UART_ROUTING_IO3, + UART_ROUTING_IO4, + UART_ROUTING_IO5, + NULL, + }, +}; + +static struct aspeed_uart_routing_selector ast2500_uart5_sel = { + .dev_attr = ROUTING_ATTR(UART_ROUTING_UART5), + .reg = HICRA, + .shift = 28, + .mask = 0xf, + .options = { + UART_ROUTING_IO5, + UART_ROUTING_IO1, + UART_ROUTING_IO2, + UART_ROUTING_IO3, + UART_ROUTING_IO4, + UART_ROUTING_UART1, + UART_ROUTING_UART2, + UART_ROUTING_UART3, + UART_ROUTING_UART4, + UART_ROUTING_IO6, + NULL, + }, +}; + +static struct aspeed_uart_routing_selector ast2500_uart4_sel = { + .dev_attr = ROUTING_ATTR(UART_ROUTING_UART4), + .reg = HICRA, + .shift = 25, + .mask = 0x7, + .options = { + UART_ROUTING_IO4, + UART_ROUTING_IO1, + UART_ROUTING_IO2, + UART_ROUTING_IO3, + UART_ROUTING_UART1, + UART_ROUTING_UART2, + UART_ROUTING_UART3, + UART_ROUTING_IO6, + NULL, + }, +}; + +static struct aspeed_uart_routing_selector ast2500_uart3_sel = { + .dev_attr = ROUTING_ATTR(UART_ROUTING_UART3), + .reg = HICRA, + .shift = 22, + .mask = 0x7, + .options = { + UART_ROUTING_IO3, + UART_ROUTING_IO4, + UART_ROUTING_IO1, + UART_ROUTING_IO2, + UART_ROUTING_UART4, + UART_ROUTING_UART1, + UART_ROUTING_UART2, + UART_ROUTING_IO6, + NULL, + }, +}; + +static struct aspeed_uart_routing_selector ast2500_uart2_sel = { + .dev_attr = ROUTING_ATTR(UART_ROUTING_UART2), + .reg = HICRA, + .shift = 19, + .mask = 0x7, + .options = { + UART_ROUTING_IO2, + UART_ROUTING_IO3, + UART_ROUTING_IO4, + UART_ROUTING_IO1, + UART_ROUTING_UART3, + UART_ROUTING_UART4, + UART_ROUTING_UART1, + UART_ROUTING_IO6, + NULL, + }, +}; + +static struct aspeed_uart_routing_selector ast2500_uart1_sel = { + .dev_attr = ROUTING_ATTR(UART_ROUTING_UART1), + .reg = HICRA, + .shift = 16, + .mask = 0x7, + .options = { + UART_ROUTING_IO1, + UART_ROUTING_IO2, + UART_ROUTING_IO3, + UART_ROUTING_IO4, + UART_ROUTING_UART2, + UART_ROUTING_UART3, + UART_ROUTING_UART4, + UART_ROUTING_IO6, + NULL, + }, +}; + +static struct aspeed_uart_routing_selector ast2500_io5_sel = { + .dev_attr = ROUTING_ATTR(UART_ROUTING_IO5), + .reg = HICRA, + .shift = 12, + .mask = 0x7, + .options = { + UART_ROUTING_UART5, + UART_ROUTING_UART1, + UART_ROUTING_UART2, + UART_ROUTING_UART3, + UART_ROUTING_UART4, + UART_ROUTING_IO1, + UART_ROUTING_IO3, + UART_ROUTING_IO6, + NULL, + }, +}; + +static struct aspeed_uart_routing_selector ast2500_io4_sel = { + .dev_attr = ROUTING_ATTR(UART_ROUTING_IO4), + .reg = HICRA, + .shift = 9, + .mask = 0x7, + .options = { + UART_ROUTING_UART4, + UART_ROUTING_UART5, + UART_ROUTING_UART1, + UART_ROUTING_UART2, + UART_ROUTING_UART3, + UART_ROUTING_IO1, + UART_ROUTING_IO2, + UART_ROUTING_IO6, + NULL, + }, +}; + +static struct aspeed_uart_routing_selector ast2500_io3_sel = { + .dev_attr = ROUTING_ATTR(UART_ROUTING_IO3), + .reg = HICRA, + .shift = 6, + .mask = 0x7, + .options = { + UART_ROUTING_UART3, + UART_ROUTING_UART4, + UART_ROUTING_UART5, + UART_ROUTING_UART1, + UART_ROUTING_UART2, + UART_ROUTING_IO1, + UART_ROUTING_IO2, + UART_ROUTING_IO6, + NULL, + }, +}; + +static struct aspeed_uart_routing_selector ast2500_io2_sel = { + .dev_attr = ROUTING_ATTR(UART_ROUTING_IO2), + .reg = HICRA, + .shift = 3, + .mask = 0x7, + .options = { + UART_ROUTING_UART2, + UART_ROUTING_UART3, + UART_ROUTING_UART4, + UART_ROUTING_UART5, + UART_ROUTING_UART1, + UART_ROUTING_IO3, + UART_ROUTING_IO4, + UART_ROUTING_IO6, + NULL, + }, +}; + +static struct aspeed_uart_routing_selector ast2500_io1_sel = { + .dev_attr = ROUTING_ATTR(UART_ROUTING_IO1), + .reg = HICRA, + .shift = 0, + .mask = 0x7, + .options = { + UART_ROUTING_UART1, + UART_ROUTING_UART2, + UART_ROUTING_UART3, + UART_ROUTING_UART4, + UART_ROUTING_UART5, + UART_ROUTING_IO3, + UART_ROUTING_IO4, + UART_ROUTING_IO6, + NULL, + }, +}; + +static struct attribute *ast2500_uart_routing_attrs[] = { + &ast2500_io6_sel.dev_attr.attr, + &ast2500_uart5_sel.dev_attr.attr, + &ast2500_uart4_sel.dev_attr.attr, + &ast2500_uart3_sel.dev_attr.attr, + &ast2500_uart2_sel.dev_attr.attr, + &ast2500_uart1_sel.dev_attr.attr, + &ast2500_io5_sel.dev_attr.attr, + &ast2500_io4_sel.dev_attr.attr, + &ast2500_io3_sel.dev_attr.attr, + &ast2500_io2_sel.dev_attr.attr, + &ast2500_io1_sel.dev_attr.attr, + NULL, +}; + +static const struct attribute_group ast2500_uart_routing_attr_group = { + .attrs = ast2500_uart_routing_attrs, +}; + +/* routing selector for AST26xx */ +static struct aspeed_uart_routing_selector ast2600_uart10_sel = { + .dev_attr = ROUTING_ATTR(UART_ROUTING_UART10), + .reg = HICR9, + .shift = 12, + .mask = 0xf, + .options = { + UART_ROUTING_IO10, + UART_ROUTING_IO1, + UART_ROUTING_IO2, + UART_ROUTING_IO3, + UART_ROUTING_IO4, + UART_ROUTING_RES, + UART_ROUTING_UART1, + UART_ROUTING_UART2, + UART_ROUTING_UART3, + UART_ROUTING_UART4, + NULL, + }, +}; + +static struct aspeed_uart_routing_selector ast2600_io10_sel = { + .dev_attr = ROUTING_ATTR(UART_ROUTING_IO10), + .reg = HICR9, + .shift = 8, + .mask = 0xf, + .options = { + UART_ROUTING_UART1, + UART_ROUTING_UART2, + UART_ROUTING_UART3, + UART_ROUTING_UART4, + UART_ROUTING_RES, + UART_ROUTING_IO1, + UART_ROUTING_IO2, + UART_ROUTING_IO3, + UART_ROUTING_IO4, + UART_ROUTING_RES, + UART_ROUTING_UART10, + NULL, + }, +}; + +static struct aspeed_uart_routing_selector ast2600_uart4_sel = { + .dev_attr = ROUTING_ATTR(UART_ROUTING_UART4), + .reg = HICRA, + .shift = 25, + .mask = 0x7, + .options = { + UART_ROUTING_IO4, + UART_ROUTING_IO1, + UART_ROUTING_IO2, + UART_ROUTING_IO3, + UART_ROUTING_UART1, + UART_ROUTING_UART2, + UART_ROUTING_UART3, + UART_ROUTING_IO10, + NULL, + }, +}; + +static struct aspeed_uart_routing_selector ast2600_uart3_sel = { + .dev_attr = ROUTING_ATTR(UART_ROUTING_UART3), + .reg = HICRA, + .shift = 22, + .mask = 0x7, + .options = { + UART_ROUTING_IO3, + UART_ROUTING_IO4, + UART_ROUTING_IO1, + UART_ROUTING_IO2, + UART_ROUTING_UART4, + UART_ROUTING_UART1, + UART_ROUTING_UART2, + UART_ROUTING_IO10, + NULL, + }, +}; + +static struct aspeed_uart_routing_selector ast2600_uart2_sel = { + .dev_attr = ROUTING_ATTR(UART_ROUTING_UART2), + .reg = HICRA, + .shift = 19, + .mask = 0x7, + .options = { + UART_ROUTING_IO2, + UART_ROUTING_IO3, + UART_ROUTING_IO4, + UART_ROUTING_IO1, + UART_ROUTING_UART3, + UART_ROUTING_UART4, + UART_ROUTING_UART1, + UART_ROUTING_IO10, + NULL, + }, +}; + +static struct aspeed_uart_routing_selector ast2600_uart1_sel = { + .dev_attr = ROUTING_ATTR(UART_ROUTING_UART1), + .reg = HICRA, + .shift = 16, + .mask = 0x7, + .options = { + UART_ROUTING_IO1, + UART_ROUTING_IO2, + UART_ROUTING_IO3, + UART_ROUTING_IO4, + UART_ROUTING_UART2, + UART_ROUTING_UART3, + UART_ROUTING_UART4, + UART_ROUTING_IO10, + NULL, + }, +}; + +static struct aspeed_uart_routing_selector ast2600_io4_sel = { + .dev_attr = ROUTING_ATTR(UART_ROUTING_IO4), + .reg = HICRA, + .shift = 9, + .mask = 0x7, + .options = { + UART_ROUTING_UART4, + UART_ROUTING_UART10, + UART_ROUTING_UART1, + UART_ROUTING_UART2, + UART_ROUTING_UART3, + UART_ROUTING_IO1, + UART_ROUTING_IO2, + UART_ROUTING_IO10, + NULL, + }, +}; + +static struct aspeed_uart_routing_selector ast2600_io3_sel = { + .dev_attr = ROUTING_ATTR(UART_ROUTING_IO3), + .reg = HICRA, + .shift = 6, + .mask = 0x7, + .options = { + UART_ROUTING_UART3, + UART_ROUTING_UART4, + UART_ROUTING_UART10, + UART_ROUTING_UART1, + UART_ROUTING_UART2, + UART_ROUTING_IO1, + UART_ROUTING_IO2, + UART_ROUTING_IO10, + NULL, + }, +}; + +static struct aspeed_uart_routing_selector ast2600_io2_sel = { + .dev_attr = ROUTING_ATTR(UART_ROUTING_IO2), + .reg = HICRA, + .shift = 3, + .mask = 0x7, + .options = { + UART_ROUTING_UART2, + UART_ROUTING_UART3, + UART_ROUTING_UART4, + UART_ROUTING_UART10, + UART_ROUTING_UART1, + UART_ROUTING_IO3, + UART_ROUTING_IO4, + UART_ROUTING_IO10, + NULL, + }, +}; + +static struct aspeed_uart_routing_selector ast2600_io1_sel = { + .dev_attr = ROUTING_ATTR(UART_ROUTING_IO1), + .reg = HICRA, + .shift = 0, + .mask = 0x7, + .options = { + UART_ROUTING_UART1, + UART_ROUTING_UART2, + UART_ROUTING_UART3, + UART_ROUTING_UART4, + UART_ROUTING_UART10, + UART_ROUTING_IO3, + UART_ROUTING_IO4, + UART_ROUTING_IO10, + NULL, + }, +}; + +static struct attribute *ast2600_uart_routing_attrs[] = { + &ast2600_uart10_sel.dev_attr.attr, + &ast2600_io10_sel.dev_attr.attr, + &ast2600_uart4_sel.dev_attr.attr, + &ast2600_uart3_sel.dev_attr.attr, + &ast2600_uart2_sel.dev_attr.attr, + &ast2600_uart1_sel.dev_attr.attr, + &ast2600_io4_sel.dev_attr.attr, + &ast2600_io3_sel.dev_attr.attr, + &ast2600_io2_sel.dev_attr.attr, + &ast2600_io1_sel.dev_attr.attr, + NULL, +}; + +static const struct attribute_group ast2600_uart_routing_attr_group = { + .attrs = ast2600_uart_routing_attrs, +}; + +static ssize_t aspeed_uart_routing_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct aspeed_uart_routing *uart_routing = dev_get_drvdata(dev); + struct aspeed_uart_routing_selector *sel = to_routing_selector(attr); + int val, pos, len; + + regmap_read(uart_routing->map, sel->reg, &val); + val = (val >> sel->shift) & sel->mask; + + len = 0; + for (pos = 0; sel->options[pos] != NULL; ++pos) { + if (pos == val) + len += sysfs_emit_at(buf, len, "[%s] ", sel->options[pos]); + else + len += sysfs_emit_at(buf, len, "%s ", sel->options[pos]); + } + + if (val >= pos) + len += sysfs_emit_at(buf, len, "[unknown(%d)]", val); + + len += sysfs_emit_at(buf, len, "\n"); + + return len; +} + +static ssize_t aspeed_uart_routing_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct aspeed_uart_routing *uart_routing = dev_get_drvdata(dev); + struct aspeed_uart_routing_selector *sel = to_routing_selector(attr); + int val; + + val = match_string(sel->options, -1, buf); + if (val < 0) { + dev_err(dev, "invalid value \"%s\"\n", buf); + return -EINVAL; + } + + regmap_update_bits(uart_routing->map, sel->reg, + (sel->mask << sel->shift), + (val & sel->mask) << sel->shift); + + return count; +} + +static int aspeed_uart_routing_probe(struct platform_device *pdev) +{ + int rc; + struct device *dev = &pdev->dev; + struct aspeed_uart_routing *uart_routing; + + uart_routing = devm_kzalloc(&pdev->dev, sizeof(*uart_routing), GFP_KERNEL); + if (!uart_routing) + return -ENOMEM; + + uart_routing->map = syscon_node_to_regmap(dev->parent->of_node); + if (IS_ERR(uart_routing->map)) { + dev_err(dev, "cannot get regmap\n"); + return PTR_ERR(uart_routing->map); + } + + uart_routing->attr_grp = of_device_get_match_data(dev); + + rc = sysfs_create_group(&dev->kobj, uart_routing->attr_grp); + if (rc < 0) + return rc; + + dev_set_drvdata(dev, uart_routing); + + dev_info(dev, "module loaded\n"); + + return 0; +} + +static int aspeed_uart_routing_remove(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct aspeed_uart_routing *uart_routing = platform_get_drvdata(pdev); + + sysfs_remove_group(&dev->kobj, uart_routing->attr_grp); + + return 0; +} + +static const struct of_device_id aspeed_uart_routing_table[] = { + { .compatible = "aspeed,ast2400-uart-routing", + .data = &ast2500_uart_routing_attr_group }, + { .compatible = "aspeed,ast2500-uart-routing", + .data = &ast2500_uart_routing_attr_group }, + { .compatible = "aspeed,ast2600-uart-routing", + .data = &ast2600_uart_routing_attr_group }, + { }, +}; + +static struct platform_driver aspeed_uart_routing_driver = { + .driver = { + .name = "aspeed-uart-routing", + .of_match_table = aspeed_uart_routing_table, + }, + .probe = aspeed_uart_routing_probe, + .remove = aspeed_uart_routing_remove, +}; + +module_platform_driver(aspeed_uart_routing_driver); + +MODULE_AUTHOR("Oskar Senft "); +MODULE_AUTHOR("Chia-Wei Wang "); +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("Driver to configure Aspeed UART routing"); From patchwork Mon Sep 13 06:02:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ChiaWei Wang X-Patchwork-Id: 12490075 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7D965C433F5 for ; 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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add LPC uart routing to the device tree for Aspeed SoCs. Signed-off-by: Oskar Senft Signed-off-by: Chia-Wei Wang Tested-by: Lei YU --- arch/arm/boot/dts/aspeed-g4.dtsi | 6 ++++++ arch/arm/boot/dts/aspeed-g5.dtsi | 6 ++++++ arch/arm/boot/dts/aspeed-g6.dtsi | 6 ++++++ 3 files changed, 18 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi index c5aeb3cf3a09..b313a1cf5f73 100644 --- a/arch/arm/boot/dts/aspeed-g4.dtsi +++ b/arch/arm/boot/dts/aspeed-g4.dtsi @@ -383,6 +383,12 @@ interrupts = <8>; status = "disabled"; }; + + uart_routing: uart-routing@9c { + compatible = "aspeed,ast2400-uart-routing"; + reg = <0x9c 0x4>; + status = "disabled"; + }; }; uart2: serial@1e78d000 { diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index 73ca1ec6fc24..c7049454c7cb 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -491,6 +491,12 @@ #reset-cells = <1>; }; + uart_routing: uart-routing@9c { + compatible = "aspeed,ast2500-uart-routing"; + reg = <0x9c 0x4>; + status = "disabled"; + }; + lhc: lhc@a0 { compatible = "aspeed,ast2500-lhc"; reg = <0xa0 0x24 0xc8 0x8>; diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi index 1b47be1704f8..cdc59c5d86fe 100644 --- a/arch/arm/boot/dts/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed-g6.dtsi @@ -551,6 +551,12 @@ #reset-cells = <1>; }; + uart_routing: uart-routing@98 { + compatible = "aspeed,ast2600-uart-routing"; + reg = <0x98 0x8>; + status = "disabled"; + }; + ibt: ibt@140 { compatible = "aspeed,ast2600-ibt-bmc"; reg = <0x140 0x18>;