From patchwork Tue Sep 14 02:57:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Subbaraman Narayanamurthy X-Patchwork-Id: 12491503 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C7661C433EF for ; Tue, 14 Sep 2021 02:57:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A0F0461108 for ; Tue, 14 Sep 2021 02:57:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238329AbhINC7G (ORCPT ); Mon, 13 Sep 2021 22:59:06 -0400 Received: from alexa-out.qualcomm.com ([129.46.98.28]:62433 "EHLO alexa-out.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237839AbhINC6y (ORCPT ); Mon, 13 Sep 2021 22:58:54 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1631588258; x=1663124258; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=2KEsJQqEBxdh9+Xw/TkLXm39dmRDCs2+Xq0UotlTssU=; b=iFb3gD9M38Ka3wrAS2yNLxiPKShWqjPOOYj+vxs3AEpTIG/19itny9Yr XH8wieVb33srm+pzo00nPBzvsRl8UhUVWDWXKY4NFdJ99UiWreYYYobZO mtG+7fYlV4nBANTWrS2EaULpm7eY+o2JlMOLSmSZA9+wvt4cfFnXo9pu5 E=; Received: from ironmsg-lv-alpha.qualcomm.com ([10.47.202.13]) by alexa-out.qualcomm.com with ESMTP; 13 Sep 2021 19:57:38 -0700 X-QCInternal: smtphost Received: from nalasex01a.na.qualcomm.com ([10.47.209.196]) by ironmsg-lv-alpha.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Sep 2021 19:57:37 -0700 Received: from hu-subbaram-lv.qualcomm.com (10.49.16.6) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.7; Mon, 13 Sep 2021 19:57:37 -0700 From: Subbaraman Narayanamurthy To: Andy Gross , Bjorn Andersson , Linus Walleij , "Rob Herring" CC: , , , , "Subbaraman Narayanamurthy" Subject: [PATCH 1/2] dt-bindings: pinctrl: qcom-pmic-gpio: Add output-{enable,disable} properties Date: Mon, 13 Sep 2021 19:57:25 -0700 Message-ID: <1631588246-4811-2-git-send-email-quic_subbaram@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1631588246-4811-1-git-send-email-quic_subbaram@quicinc.com> References: <1631588246-4811-1-git-send-email-quic_subbaram@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01c.na.qualcomm.com (10.47.97.35) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add support for the pinconf DT property output-enable, output-disable so that output can be enabled/disabled. Signed-off-by: Subbaraman Narayanamurthy Acked-by: Rob Herring --- Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml index 9bd01db..fa7c319 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml @@ -170,6 +170,8 @@ $defs: input-enable: true output-high: true output-low: true + output-enable: true + output-disable: true power-source: true qcom,drive-strength: From patchwork Tue Sep 14 02:57:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Subbaraman Narayanamurthy X-Patchwork-Id: 12491501 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9BD2DC433F5 for ; Tue, 14 Sep 2021 02:57:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7864B61108 for ; Tue, 14 Sep 2021 02:57:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238240AbhINC7F (ORCPT ); Mon, 13 Sep 2021 22:59:05 -0400 Received: from alexa-out.qualcomm.com ([129.46.98.28]:19887 "EHLO alexa-out.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238156AbhINC64 (ORCPT ); Mon, 13 Sep 2021 22:58:56 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1631588260; x=1663124260; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=YYFw3BlcWh0C1EZu1ZanhGDL5SHOWe3x6GtNmiTMOVs=; b=KyWvvQoq1oDDJLheefa6MNOA1Yh2CoQbGt8dqPEr5bjzTMISv1MDKbvX TKMTw+gqciKpQRT+AgqltFonbq1TZ7rKRyfhcPgKoAix9nMZLWIk5m0Wa 2SdKsekAT8HHjjesaH7wDPrLNuJFy/90pvBYvtgc/C+zR9q5TzM4OI1M5 Y=; Received: from ironmsg08-lv.qualcomm.com ([10.47.202.152]) by alexa-out.qualcomm.com with ESMTP; 13 Sep 2021 19:57:40 -0700 X-QCInternal: smtphost Received: from nalasex01a.na.qualcomm.com ([10.47.209.196]) by ironmsg08-lv.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Sep 2021 19:57:39 -0700 Received: from hu-subbaram-lv.qualcomm.com (10.49.16.6) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.7; Mon, 13 Sep 2021 19:57:38 -0700 From: Subbaraman Narayanamurthy To: Andy Gross , Bjorn Andersson , Linus Walleij , "Rob Herring" CC: , , , , "Subbaraman Narayanamurthy" Subject: [PATCH 2/2] pinctrl: qcom: spmi-gpio: add support to enable/disable output Date: Mon, 13 Sep 2021 19:57:26 -0700 Message-ID: <1631588246-4811-3-git-send-email-quic_subbaram@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1631588246-4811-1-git-send-email-quic_subbaram@quicinc.com> References: <1631588246-4811-1-git-send-email-quic_subbaram@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01c.na.qualcomm.com (10.47.97.35) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Currently, if the GPIO is configured as output in the bootloader and user changes the mode to input in HLOS, it would end up getting configured as input/output. Functionally, this is fine; however, there may be some requirements where the output needs to be disabled so that it can be used only for input. Add support to enable/disable output mode through "output-enable" or "output-disable" pinctrl properties. Signed-off-by: Subbaraman Narayanamurthy Reviewed-by: Bjorn Andersson --- drivers/pinctrl/qcom/pinctrl-spmi-gpio.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c index 98bf0e2..39a18aa 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2014, 2021, The Linux Foundation. All rights reserved. */ #include @@ -424,6 +424,9 @@ static int pmic_gpio_config_get(struct pinctrl_dev *pctldev, return -EINVAL; arg = 1; break; + case PIN_CONFIG_OUTPUT_ENABLE: + arg = pad->output_enabled; + break; case PIN_CONFIG_OUTPUT: arg = pad->out_value; break; @@ -503,6 +506,9 @@ static int pmic_gpio_config_set(struct pinctrl_dev *pctldev, unsigned int pin, case PIN_CONFIG_INPUT_ENABLE: pad->input_enabled = arg ? true : false; break; + case PIN_CONFIG_OUTPUT_ENABLE: + pad->output_enabled = arg ? true : false; + break; case PIN_CONFIG_OUTPUT: pad->output_enabled = true; pad->out_value = arg;