From patchwork Tue Sep 14 12:18:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Krzyszkowiak X-Patchwork-Id: 12492989 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 02A8EC433FE for ; Tue, 14 Sep 2021 12:19:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D5AC461159 for ; Tue, 14 Sep 2021 12:19:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232386AbhINMUV (ORCPT ); Tue, 14 Sep 2021 08:20:21 -0400 Received: from comms.puri.sm ([159.203.221.185]:45048 "EHLO comms.puri.sm" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232598AbhINMUU (ORCPT ); Tue, 14 Sep 2021 08:20:20 -0400 Received: from localhost (localhost [127.0.0.1]) by comms.puri.sm (Postfix) with ESMTP id 3622FDF8A6; Tue, 14 Sep 2021 05:18:32 -0700 (PDT) Received: from comms.puri.sm ([127.0.0.1]) by localhost (comms.puri.sm [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 5Rcdb0T1Wqwb; Tue, 14 Sep 2021 05:18:31 -0700 (PDT) From: Sebastian Krzyszkowiak To: Sebastian Reichel , linux-pm@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Dirk Brandewie , kernel@puri.sm, Sebastian Krzyszkowiak , stable@vger.kernel.org Subject: [PATCH v2 1/2] power: supply: max17042_battery: Clear status bits in interrupt handler Date: Tue, 14 Sep 2021 14:18:05 +0200 Message-Id: <20210914121806.1301131-1-sebastian.krzyszkowiak@puri.sm> Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The gauge requires us to clear the status bits manually for some alerts to be properly dismissed. Previously the IRQ was configured to react only on falling edge, which wasn't technically correct (the ALRT line is active low), but it had a happy side-effect of preventing interrupt storms on uncleared alerts from happening. Fixes: 7fbf6b731bca ("power: supply: max17042: Do not enforce (incorrect) interrupt trigger type") Cc: Signed-off-by: Sebastian Krzyszkowiak Reviewed-by: Krzysztof Kozlowski --- v2: added a comment on why it clears all alert bits --- drivers/power/supply/max17042_battery.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/power/supply/max17042_battery.c b/drivers/power/supply/max17042_battery.c index 8dffae76b6a3..da78ffe6a3ec 100644 --- a/drivers/power/supply/max17042_battery.c +++ b/drivers/power/supply/max17042_battery.c @@ -876,6 +876,10 @@ static irqreturn_t max17042_thread_handler(int id, void *dev) max17042_set_soc_threshold(chip, 1); } + /* we implicitly handle all alerts via power_supply_changed */ + regmap_clear_bits(chip->regmap, MAX17042_STATUS, + 0xFFFF & ~(STATUS_POR_BIT | STATUS_BST_BIT)); + power_supply_changed(chip->battery); return IRQ_HANDLED; } From patchwork Tue Sep 14 12:18:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Krzyszkowiak X-Patchwork-Id: 12492991 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CFF33C433F5 for ; Tue, 14 Sep 2021 12:19:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B8AA961175 for ; Tue, 14 Sep 2021 12:19:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232677AbhINMUZ (ORCPT ); Tue, 14 Sep 2021 08:20:25 -0400 Received: from comms.puri.sm ([159.203.221.185]:45054 "EHLO comms.puri.sm" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232606AbhINMUX (ORCPT ); Tue, 14 Sep 2021 08:20:23 -0400 Received: from localhost (localhost [127.0.0.1]) by comms.puri.sm (Postfix) with ESMTP id C305DDFA69; Tue, 14 Sep 2021 05:18:36 -0700 (PDT) Received: from comms.puri.sm ([127.0.0.1]) by localhost (comms.puri.sm [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id NiOnI3NDwrju; Tue, 14 Sep 2021 05:18:36 -0700 (PDT) From: Sebastian Krzyszkowiak To: Sebastian Reichel , linux-pm@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Dirk Brandewie , kernel@puri.sm, Sebastian Krzyszkowiak , stable@vger.kernel.org Subject: [PATCH v2 2/2] power: supply: max17042_battery: Prevent int underflow in set_soc_threshold Date: Tue, 14 Sep 2021 14:18:06 +0200 Message-Id: <20210914121806.1301131-2-sebastian.krzyszkowiak@puri.sm> In-Reply-To: <20210914121806.1301131-1-sebastian.krzyszkowiak@puri.sm> References: <20210914121806.1301131-1-sebastian.krzyszkowiak@puri.sm> Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org max17042_set_soc_threshold gets called with offset set to 1, which means that minimum threshold value would underflow once SOC got down to 0, causing invalid alerts from the gauge. Fixes: e5f3872d2044 ("max17042: Add support for signalling change in SOC") Cc: Signed-off-by: Sebastian Krzyszkowiak Reviewed-by: Krzysztof Kozlowski --- v2: added commit description --- drivers/power/supply/max17042_battery.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/power/supply/max17042_battery.c b/drivers/power/supply/max17042_battery.c index da78ffe6a3ec..189c1979bc7b 100644 --- a/drivers/power/supply/max17042_battery.c +++ b/drivers/power/supply/max17042_battery.c @@ -857,7 +857,8 @@ static void max17042_set_soc_threshold(struct max17042_chip *chip, u16 off) regmap_read(map, MAX17042_RepSOC, &soc); soc >>= 8; soc_tr = (soc + off) << 8; - soc_tr |= (soc - off); + if (off < soc) + soc_tr |= soc - off; regmap_write(map, MAX17042_SALRT_Th, soc_tr); }