From patchwork Fri Sep 17 06:32:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fenglin Wu X-Patchwork-Id: 12501205 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E746DC433EF for ; Fri, 17 Sep 2021 06:33:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C756060F4A for ; Fri, 17 Sep 2021 06:33:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232934AbhIQGeh (ORCPT ); Fri, 17 Sep 2021 02:34:37 -0400 Received: from alexa-out.qualcomm.com ([129.46.98.28]:60418 "EHLO alexa-out.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234182AbhIQGeg (ORCPT ); Fri, 17 Sep 2021 02:34:36 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1631860394; x=1663396394; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=tAnC1etYTMo3V+Modhj6QJR1D5QTZ5y6YOqeoMVCGsg=; b=n+DJ+kpzZWfW5hWVTuQyS2fxEPa0mDxX0fYAFOWLEBxatR63Mz69dlZD G+GsEph5hA21wtPZSrgzPdDJZObQIyTYc7766uTX3TLvWiIpasT0XPROM eG6vzHm1Q37fOOXWUcjaXhjLBoLCl0ikx2WT9JdsrgJCTtJs6MsWvCum6 g=; Received: from ironmsg08-lv.qualcomm.com ([10.47.202.152]) by alexa-out.qualcomm.com with ESMTP; 16 Sep 2021 23:33:14 -0700 X-QCInternal: smtphost Received: from nalasex01a.na.qualcomm.com ([10.47.209.196]) by ironmsg08-lv.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Sep 2021 23:33:14 -0700 Received: from fenglinw-gv.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.7; Thu, 16 Sep 2021 23:33:12 -0700 From: Fenglin Wu To: , , CC: , , , Abhijeet Dharmapurikar Subject: [RESEND PATCH v1 1/9] spmi: pmic-arb: add a print in cleanup_irq Date: Fri, 17 Sep 2021 14:32:56 +0800 Message-ID: <1631860384-26608-2-git-send-email-quic_fenglinw@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1631860384-26608-1-git-send-email-quic_fenglinw@quicinc.com> References: <1631860384-26608-1-git-send-email-quic_fenglinw@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Abhijeet Dharmapurikar The cleanup_irq() was meant to clear and mask interrupts that were left enabled in the hardware but there was no interrupt handler registered for it. Add an error print when it gets invoked. Signed-off-by: Abhijeet Dharmapurikar Signed-off-by: David Collins Signed-off-by: Fenglin Wu --- drivers/spmi/spmi-pmic-arb.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/spmi/spmi-pmic-arb.c b/drivers/spmi/spmi-pmic-arb.c index bbbd311..295e19f 100644 --- a/drivers/spmi/spmi-pmic-arb.c +++ b/drivers/spmi/spmi-pmic-arb.c @@ -489,6 +489,8 @@ static void cleanup_irq(struct spmi_pmic_arb *pmic_arb, u16 apid, int id) u8 per = ppid & 0xFF; u8 irq_mask = BIT(id); + dev_err_ratelimited(&pmic_arb->spmic->dev, "%s apid=%d sid=0x%x per=0x%x irq=%d\n", + __func__, apid, sid, per, id); writel_relaxed(irq_mask, pmic_arb->ver_ops->irq_clear(pmic_arb, apid)); if (pmic_arb_write_cmd(pmic_arb->spmic, SPMI_CMD_EXT_WRITEL, sid, From patchwork Fri Sep 17 06:32:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fenglin Wu X-Patchwork-Id: 12501207 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DF180C433F5 for ; Fri, 17 Sep 2021 06:33:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C7FEE6103B for ; Fri, 17 Sep 2021 06:33:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234838AbhIQGek (ORCPT ); Fri, 17 Sep 2021 02:34:40 -0400 Received: from alexa-out.qualcomm.com ([129.46.98.28]:60418 "EHLO alexa-out.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234642AbhIQGej (ORCPT ); Fri, 17 Sep 2021 02:34:39 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1631860397; x=1663396397; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=UFm4lH1VdjgBOuPIWDR8+t74A8qgSRQhFYsN706Pxow=; b=QYcb210icU2bH4mfAJsUD54yUJuDcHXBh4iEjP44UiLay4WewcjLLUk4 So48SciSbiw3nF/NRq/Nk85OOPV9jSPc83/EHmO9LZYGrfygMm8ntygLI bGQ5B+M9kwmdNMzX35rG9YfrVOZKypvAQ1Dqi09bEEVjqFx/UV+t3HiE0 4=; Received: from ironmsg09-lv.qualcomm.com ([10.47.202.153]) by alexa-out.qualcomm.com with ESMTP; 16 Sep 2021 23:33:17 -0700 X-QCInternal: smtphost Received: from nalasex01a.na.qualcomm.com ([10.47.209.196]) by ironmsg09-lv.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Sep 2021 23:33:17 -0700 Received: from fenglinw-gv.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.7; Thu, 16 Sep 2021 23:33:14 -0700 From: Fenglin Wu To: , , CC: , , Subject: [RESEND PATCH v1 2/9] spmi: pmic-arb: do not ack and clear peripheral interrupts in cleanup_irq Date: Fri, 17 Sep 2021 14:32:57 +0800 Message-ID: <1631860384-26608-3-git-send-email-quic_fenglinw@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1631860384-26608-1-git-send-email-quic_fenglinw@quicinc.com> References: <1631860384-26608-1-git-send-email-quic_fenglinw@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Subbaraman Narayanamurthy Currently, cleanup_irq() is invoked when a peripheral's interrupt fires and there is no mapping present in the interrupt domain of spmi interrupt controller. The cleanup_irq clears the arbiter bit, clears the pmic interrupt and disables it at the pmic in that order. The last disable in cleanup_irq races with request_irq() in that it stomps over the enable issued by request_irq. Fix this by not writing to the pmic in cleanup_irq. The latched bit will be left set in the pmic, which will not send us more interrupts even if the enable bit stays enabled. When a client wants to request an interrupt, use the activate callback on the irq_domain to clear latched bit. This ensures that the latched, if set due to the above changes in cleanup_irq or when the bootloader leaves it set, gets cleaned up, paving way for upcoming interrupts to trigger. With this, there is a possibility of unwanted triggering of interrupt right after the latched bit is cleared - the interrupt may be left enabled too. To avoid that, clear the enable first followed by clearing the latched bit in the activate callback. Signed-off-by: Subbaraman Narayanamurthy [collinsd@codeaurora.org: fix merge conflict] Signed-off-by: David Collins Signed-off-by: Fenglin Wu --- drivers/spmi/spmi-pmic-arb.c | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/drivers/spmi/spmi-pmic-arb.c b/drivers/spmi/spmi-pmic-arb.c index 295e19f..4d7ad004 100644 --- a/drivers/spmi/spmi-pmic-arb.c +++ b/drivers/spmi/spmi-pmic-arb.c @@ -492,16 +492,6 @@ static void cleanup_irq(struct spmi_pmic_arb *pmic_arb, u16 apid, int id) dev_err_ratelimited(&pmic_arb->spmic->dev, "%s apid=%d sid=0x%x per=0x%x irq=%d\n", __func__, apid, sid, per, id); writel_relaxed(irq_mask, pmic_arb->ver_ops->irq_clear(pmic_arb, apid)); - - if (pmic_arb_write_cmd(pmic_arb->spmic, SPMI_CMD_EXT_WRITEL, sid, - (per << 8) + QPNPINT_REG_LATCHED_CLR, &irq_mask, 1)) - dev_err_ratelimited(&pmic_arb->spmic->dev, "failed to ack irq_mask = 0x%x for ppid = %x\n", - irq_mask, ppid); - - if (pmic_arb_write_cmd(pmic_arb->spmic, SPMI_CMD_EXT_WRITEL, sid, - (per << 8) + QPNPINT_REG_EN_CLR, &irq_mask, 1)) - dev_err_ratelimited(&pmic_arb->spmic->dev, "failed to ack irq_mask = 0x%x for ppid = %x\n", - irq_mask, ppid); } static void periph_interrupt(struct spmi_pmic_arb *pmic_arb, u16 apid) @@ -667,6 +657,7 @@ static int qpnpint_irq_domain_activate(struct irq_domain *domain, u16 apid = hwirq_to_apid(d->hwirq); u16 sid = hwirq_to_sid(d->hwirq); u16 irq = hwirq_to_irq(d->hwirq); + u8 buf; if (pmic_arb->apid_data[apid].irq_ee != pmic_arb->ee) { dev_err(&pmic_arb->spmic->dev, "failed to xlate sid = %#x, periph = %#x, irq = %u: ee=%u but owner=%u\n", @@ -675,6 +666,10 @@ static int qpnpint_irq_domain_activate(struct irq_domain *domain, return -ENODEV; } + buf = BIT(irq); + qpnpint_spmi_write(d, QPNPINT_REG_EN_CLR, &buf, 1); + qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &buf, 1); + return 0; } From patchwork Fri Sep 17 06:32:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fenglin Wu X-Patchwork-Id: 12501209 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E8D8FC433F5 for ; Fri, 17 Sep 2021 06:33:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C8BE9610A7 for ; Fri, 17 Sep 2021 06:33:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235219AbhIQGem (ORCPT ); Fri, 17 Sep 2021 02:34:42 -0400 Received: from alexa-out.qualcomm.com ([129.46.98.28]:60418 "EHLO alexa-out.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235031AbhIQGel (ORCPT ); Fri, 17 Sep 2021 02:34:41 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1631860399; x=1663396399; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=XwhljndGA6Jv2ltbwzx88Ni9Naz4wDVBE/5XzjZwT4c=; b=fg73tiagLJ3HZIx7lNAgIPDZgr2n6NZ8vVh2u3FZSeGLreYApsFKvgMy IAna4YyzCdUyPSsN44MAMqU/eNN18BPAc9mo8T2DKX1xNoLGvpkacOl2X g35zOZgOTQ9YjEydyeCFGaWaLuSG3B2uPDPvX6gxqjAh+3jNkzNG+JaGW U=; Received: from ironmsg08-lv.qualcomm.com ([10.47.202.152]) by alexa-out.qualcomm.com with ESMTP; 16 Sep 2021 23:33:19 -0700 X-QCInternal: smtphost Received: from nalasex01a.na.qualcomm.com ([10.47.209.196]) by ironmsg08-lv.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Sep 2021 23:33:19 -0700 Received: from fenglinw-gv.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.7; Thu, 16 Sep 2021 23:33:17 -0700 From: Fenglin Wu To: , , CC: , , Subject: [RESEND PATCH v1 3/9] spmi: pmic-arb: check apid against limits before calling irq handler Date: Fri, 17 Sep 2021 14:32:58 +0800 Message-ID: <1631860384-26608-4-git-send-email-quic_fenglinw@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1631860384-26608-1-git-send-email-quic_fenglinw@quicinc.com> References: <1631860384-26608-1-git-send-email-quic_fenglinw@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: David Collins Check that the apid for an SPMI interrupt falls between the min_apid and max_apid that can be handled by the APPS processor before invoking the per-apid interrupt handler: periph_interrupt(). This avoids an access violation in rare cases where the status bit is set for an interrupt that is not owned by the APPS processor. Signed-off-by: David Collins Signed-off-by: Fenglin Wu --- drivers/spmi/spmi-pmic-arb.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/spmi/spmi-pmic-arb.c b/drivers/spmi/spmi-pmic-arb.c index 4d7ad004..c4adc06 100644 --- a/drivers/spmi/spmi-pmic-arb.c +++ b/drivers/spmi/spmi-pmic-arb.c @@ -535,6 +535,12 @@ static void pmic_arb_chained_irq(struct irq_desc *desc) id = ffs(status) - 1; status &= ~BIT(id); apid = id + i * 32; + if (apid < pmic_arb->min_apid + || apid > pmic_arb->max_apid) { + WARN_ONCE(true, "spurious spmi irq received for apid=%d\n", + apid); + continue; + } enable = readl_relaxed( ver_ops->acc_enable(pmic_arb, apid)); if (enable & SPMI_PIC_ACC_ENABLE_BIT) From patchwork Fri Sep 17 06:32:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fenglin Wu X-Patchwork-Id: 12501211 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E4866C433EF for ; Fri, 17 Sep 2021 06:33:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CE2EC6103B for ; Fri, 17 Sep 2021 06:33:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236103AbhIQGeq (ORCPT ); Fri, 17 Sep 2021 02:34:46 -0400 Received: from alexa-out.qualcomm.com ([129.46.98.28]:60418 "EHLO alexa-out.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235541AbhIQGen (ORCPT ); Fri, 17 Sep 2021 02:34:43 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1631860402; x=1663396402; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=p82VOXmbjdo886MdyqYqr8kAUG2iDKw6pyvPODt1jVg=; b=JpsbDo0hG4QsbMjcUZRLQ9k4HfCwBt7PVMEFAp7HCap8J1+agrfMaMTZ QWISUjK+qRDdMZ1ac6efNC2q0wx7y30eTiG56GcgkzqkrHNCQwM3uVsSj KAK3nphOENBZHfxguw6Negmy2qBHDRVZwrYZ8yVqh9914OJnWL2gYeM6U M=; Received: from ironmsg-lv-alpha.qualcomm.com ([10.47.202.13]) by alexa-out.qualcomm.com with ESMTP; 16 Sep 2021 23:33:22 -0700 X-QCInternal: smtphost Received: from nalasex01a.na.qualcomm.com ([10.47.209.196]) by ironmsg-lv-alpha.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Sep 2021 23:33:21 -0700 Received: from fenglinw-gv.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.7; Thu, 16 Sep 2021 23:33:19 -0700 From: Fenglin Wu To: , , CC: , , , Ashay Jaiswal Subject: [RESEND PATCH v1 4/9] spmi: pmic-arb: add support to dispatch interrupt based on IRQ status Date: Fri, 17 Sep 2021 14:32:59 +0800 Message-ID: <1631860384-26608-5-git-send-email-quic_fenglinw@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1631860384-26608-1-git-send-email-quic_fenglinw@quicinc.com> References: <1631860384-26608-1-git-send-email-quic_fenglinw@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Ashay Jaiswal Current implementation of SPMI arbiter dispatches interrupt based on the Arbiter's accumulator status, in some cases the accumulator status may remain zero and the interrupt remains un-handled. Add logic to dispatch interrupts based Arbiter's IRQ status if the accumulator status is zero. Signed-off-by: Ashay Jaiswal Signed-off-by: David Collins Signed-off-by: Fenglin Wu --- drivers/spmi/spmi-pmic-arb.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/drivers/spmi/spmi-pmic-arb.c b/drivers/spmi/spmi-pmic-arb.c index c4adc06..59c445b 100644 --- a/drivers/spmi/spmi-pmic-arb.c +++ b/drivers/spmi/spmi-pmic-arb.c @@ -525,12 +525,18 @@ static void pmic_arb_chained_irq(struct irq_desc *desc) u8 ee = pmic_arb->ee; u32 status, enable; int i, id, apid; + /* status based dispatch */ + bool acc_valid = false; + u32 irq_status = 0; chained_irq_enter(chip, desc); for (i = first; i <= last; ++i) { status = readl_relaxed( ver_ops->owner_acc_status(pmic_arb, ee, i)); + if (status) + acc_valid = true; + while (status) { id = ffs(status) - 1; status &= ~BIT(id); @@ -548,6 +554,28 @@ static void pmic_arb_chained_irq(struct irq_desc *desc) } } + /* ACC_STATUS is empty but IRQ fired check IRQ_STATUS */ + if (!acc_valid) { + for (i = pmic_arb->min_apid; i <= pmic_arb->max_apid; i++) { + /* skip if APPS is not irq owner */ + if (pmic_arb->apid_data[i].irq_ee != pmic_arb->ee) + continue; + + irq_status = readl_relaxed( + ver_ops->irq_status(pmic_arb, i)); + if (irq_status) { + enable = readl_relaxed( + ver_ops->acc_enable(pmic_arb, i)); + if (enable & SPMI_PIC_ACC_ENABLE_BIT) { + dev_dbg(&pmic_arb->spmic->dev, + "Dispatching IRQ for apid=%d status=%x\n", + i, irq_status); + periph_interrupt(pmic_arb, i); + } + } + } + } + chained_irq_exit(chip, desc); } From patchwork Fri Sep 17 06:33:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fenglin Wu X-Patchwork-Id: 12501213 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 88B14C433EF for ; Fri, 17 Sep 2021 06:33:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 719A361152 for ; Fri, 17 Sep 2021 06:33:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235575AbhIQGew (ORCPT ); Fri, 17 Sep 2021 02:34:52 -0400 Received: from alexa-out.qualcomm.com ([129.46.98.28]:60418 "EHLO alexa-out.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236090AbhIQGeq (ORCPT ); Fri, 17 Sep 2021 02:34:46 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1631860405; x=1663396405; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=kUnSUC/8VBwiIC+PWxEBDggi0X6pA5u756A7g/HYUYs=; b=Wdxy/ol0V0Zgbs0Q1JrWkNu0SeKRmPlkUeedUjUrc0CDR3ia3JuP1u1D RKMX3cv3KYLJihmZP2Ua7MrHXGjG5bu2eRUkCA3LKFmpT9RD43C/ercbL wt4Aq/L7Wx/Ceeie7fMbzYA51g1nNUNak3FR1oGaABK7k3Tg/SS3rPUjw 4=; Received: from ironmsg07-lv.qualcomm.com ([10.47.202.151]) by alexa-out.qualcomm.com with ESMTP; 16 Sep 2021 23:33:24 -0700 X-QCInternal: smtphost Received: from nalasex01a.na.qualcomm.com ([10.47.209.196]) by ironmsg07-lv.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Sep 2021 23:33:24 -0700 Received: from fenglinw-gv.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.7; Thu, 16 Sep 2021 23:33:22 -0700 From: Fenglin Wu To: , , CC: , , Subject: [RESEND PATCH v1 5/9] spmi: pmic-arb: correct duplicate APID to PPID mapping logic Date: Fri, 17 Sep 2021 14:33:00 +0800 Message-ID: <1631860384-26608-6-git-send-email-quic_fenglinw@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1631860384-26608-1-git-send-email-quic_fenglinw@quicinc.com> References: <1631860384-26608-1-git-send-email-quic_fenglinw@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: David Collins Correct the way that duplicate PPID mappings are handled for PMIC arbiter v5. The final APID mapped to a given PPID should be the one which has write owner = APPS EE, if it exists, or if not that, then the first APID mapped to the PPID, if it exists. Signed-off-by: David Collins Signed-off-by: Fenglin Wu --- drivers/spmi/spmi-pmic-arb.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/spmi/spmi-pmic-arb.c b/drivers/spmi/spmi-pmic-arb.c index 59c445b..f1b72d8 100644 --- a/drivers/spmi/spmi-pmic-arb.c +++ b/drivers/spmi/spmi-pmic-arb.c @@ -918,7 +918,8 @@ static int pmic_arb_read_apid_map_v5(struct spmi_pmic_arb *pmic_arb) * version 5, there is more than one APID mapped to each PPID. * The owner field for each of these mappings specifies the EE which is * allowed to write to the APID. The owner of the last (highest) APID - * for a given PPID will receive interrupts from the PPID. + * which has the IRQ owner bit set for a given PPID will receive + * interrupts from the PPID. */ for (i = 0; ; i++, apidd++) { offset = pmic_arb->ver_ops->apid_map_offset(i); @@ -941,16 +942,16 @@ static int pmic_arb_read_apid_map_v5(struct spmi_pmic_arb *pmic_arb) apid = pmic_arb->ppid_to_apid[ppid] & ~PMIC_ARB_APID_VALID; prev_apidd = &pmic_arb->apid_data[apid]; - if (valid && is_irq_ee && - prev_apidd->write_ee == pmic_arb->ee) { + if (!valid || apidd->write_ee == pmic_arb->ee) { + /* First PPID mapping or one for this EE */ + pmic_arb->ppid_to_apid[ppid] = i | PMIC_ARB_APID_VALID; + } else if (valid && is_irq_ee && + prev_apidd->write_ee == pmic_arb->ee) { /* * Duplicate PPID mapping after the one for this EE; * override the irq owner */ prev_apidd->irq_ee = apidd->irq_ee; - } else if (!valid || is_irq_ee) { - /* First PPID mapping or duplicate for another EE */ - pmic_arb->ppid_to_apid[ppid] = i | PMIC_ARB_APID_VALID; } apidd->ppid = ppid; From patchwork Fri Sep 17 06:33:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fenglin Wu X-Patchwork-Id: 12501215 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 13AB1C433EF for ; Fri, 17 Sep 2021 06:33:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EC512610A7 for ; Fri, 17 Sep 2021 06:33:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240998AbhIQGew (ORCPT ); Fri, 17 Sep 2021 02:34:52 -0400 Received: from alexa-out.qualcomm.com ([129.46.98.28]:56066 "EHLO alexa-out.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235541AbhIQGes (ORCPT ); Fri, 17 Sep 2021 02:34:48 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1631860407; x=1663396407; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=OtSq+ort8B4nCsCM1w2vsb0LnoZeXWiSQQkCUckld2I=; b=vF/j250OwGzm9ZrGhC+UMnRewwnD3lN0fTplO5pr0VkcKeF3fP9eofJ+ /QCaXfhKBnkdMgsr07gdifvHURoNYA9XdoS195TVRLAzZPxHHlMybmvwn aR5SwXoQlOwMDP+lQuaYSkMT9dAzbusYihR1SfLv+r0VjyFXCBcOTMi64 M=; Received: from ironmsg09-lv.qualcomm.com ([10.47.202.153]) by alexa-out.qualcomm.com with ESMTP; 16 Sep 2021 23:33:26 -0700 X-QCInternal: smtphost Received: from nalasex01a.na.qualcomm.com ([10.47.209.196]) by ironmsg09-lv.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Sep 2021 23:33:26 -0700 Received: from fenglinw-gv.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.7; Thu, 16 Sep 2021 23:33:24 -0700 From: Fenglin Wu To: , , CC: , , Subject: [RESEND PATCH v1 6/9] spmi: pmic-arb: block access for invalid PMIC arbiter v5 SPMI writes Date: Fri, 17 Sep 2021 14:33:01 +0800 Message-ID: <1631860384-26608-7-git-send-email-quic_fenglinw@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1631860384-26608-1-git-send-email-quic_fenglinw@quicinc.com> References: <1631860384-26608-1-git-send-email-quic_fenglinw@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: David Collins The system crashes due to an access permission violation when writing to a PMIC peripheral which is not owned by the current ee. Add a check for PMIC arbiter version 5 for such invalid write requests and return an error instead of crashing the system. Signed-off-by: David Collins Signed-off-by: Fenglin Wu --- drivers/spmi/spmi-pmic-arb.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/spmi/spmi-pmic-arb.c b/drivers/spmi/spmi-pmic-arb.c index f1b72d8..9239830 100644 --- a/drivers/spmi/spmi-pmic-arb.c +++ b/drivers/spmi/spmi-pmic-arb.c @@ -1020,6 +1020,11 @@ static int pmic_arb_offset_v5(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr, offset = 0x10000 * pmic_arb->ee + 0x80 * apid; break; case PMIC_ARB_CHANNEL_RW: + if (pmic_arb->apid_data[apid].write_ee != pmic_arb->ee) { + dev_err(&pmic_arb->spmic->dev, "disallowed SPMI write to sid=%u, addr=0x%04X\n", + sid, addr); + return -EPERM; + } offset = 0x10000 * apid; break; } From patchwork Fri Sep 17 06:33:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fenglin Wu X-Patchwork-Id: 12501221 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C66FAC433FE for ; Fri, 17 Sep 2021 06:33:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B1744611C3 for ; Fri, 17 Sep 2021 06:33:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235820AbhIQGfB (ORCPT ); Fri, 17 Sep 2021 02:35:01 -0400 Received: from alexa-out.qualcomm.com ([129.46.98.28]:14950 "EHLO alexa-out.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238174AbhIQGeu (ORCPT ); Fri, 17 Sep 2021 02:34:50 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1631860409; x=1663396409; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=kOj1T/M9/T/1A0YLEYHMt7zmOnXmigoTevu8jxHooAU=; b=Odl4i+Wc7HX4FxpZXEVk0wwCX5nQu2iFR+uYEQtxFCjfu2GdOfYuqX6a jrudeTwa/F+KS12kazDOMQPXxADRPVLiJDN02kJGaD5d4a8FNmOgLruCt OAELanGWvDa5nNd/OiAmUrzmCSbuj3trWReBD54LbYaQlbAvRjKZMJAUs U=; Received: from ironmsg-lv-alpha.qualcomm.com ([10.47.202.13]) by alexa-out.qualcomm.com with ESMTP; 16 Sep 2021 23:33:29 -0700 X-QCInternal: smtphost Received: from nalasex01a.na.qualcomm.com ([10.47.209.196]) by ironmsg-lv-alpha.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Sep 2021 23:33:28 -0700 Received: from fenglinw-gv.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.7; Thu, 16 Sep 2021 23:33:26 -0700 From: Fenglin Wu To: , , CC: , , , Yimin Peng Subject: [RESEND PATCH v1 7/9] spmi: pmic-arb: support updating interrupt type flags Date: Fri, 17 Sep 2021 14:33:02 +0800 Message-ID: <1631860384-26608-8-git-send-email-quic_fenglinw@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1631860384-26608-1-git-send-email-quic_fenglinw@quicinc.com> References: <1631860384-26608-1-git-send-email-quic_fenglinw@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Yimin Peng Have the qpnpint_irq_set_type function clear unwanted high/low trigger bits when updating the interrupt flags. Signed-off-by: Yimin Peng Signed-off-by: Subbaraman Narayanamurthy Signed-off-by: Fenglin Wu --- drivers/spmi/spmi-pmic-arb.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/spmi/spmi-pmic-arb.c b/drivers/spmi/spmi-pmic-arb.c index 9239830..988204c 100644 --- a/drivers/spmi/spmi-pmic-arb.c +++ b/drivers/spmi/spmi-pmic-arb.c @@ -636,8 +636,12 @@ static int qpnpint_irq_set_type(struct irq_data *d, unsigned int flow_type) type.type |= BIT(irq); if (flow_type & IRQF_TRIGGER_RISING) type.polarity_high |= BIT(irq); + else + type.polarity_high &= ~BIT(irq); if (flow_type & IRQF_TRIGGER_FALLING) type.polarity_low |= BIT(irq); + else + type.polarity_low &= ~BIT(irq); flow_handler = handle_edge_irq; } else { @@ -646,10 +650,13 @@ static int qpnpint_irq_set_type(struct irq_data *d, unsigned int flow_type) return -EINVAL; type.type &= ~BIT(irq); /* level trig */ - if (flow_type & IRQF_TRIGGER_HIGH) + if (flow_type & IRQF_TRIGGER_HIGH) { type.polarity_high |= BIT(irq); - else + type.polarity_low &= ~BIT(irq); + } else { type.polarity_low |= BIT(irq); + type.polarity_high &= ~BIT(irq); + } flow_handler = handle_level_irq; } From patchwork Fri Sep 17 06:33:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fenglin Wu X-Patchwork-Id: 12501219 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3B920C433EF for ; Fri, 17 Sep 2021 06:33:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 25A176103B for ; Fri, 17 Sep 2021 06:33:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244647AbhIQGfA (ORCPT ); Fri, 17 Sep 2021 02:35:00 -0400 Received: from alexa-out.qualcomm.com ([129.46.98.28]:56066 "EHLO alexa-out.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240745AbhIQGew (ORCPT ); Fri, 17 Sep 2021 02:34:52 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1631860411; x=1663396411; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=hCWrDSqZz1/MJx0Y2r+Vv1EF0PQcvg19mxnobpT+a9s=; b=ZXwXe+ds5Rair7nLlt9hWLmKFH1V7gE0hRilWp1Zd00MF0RV87l3JunP ADuFgVNAd6u+Pc6FaCSoXID3R5UkVtKLvdtEWS5L7MbXrDfmeDStz1TsR 02r06AzGMcbLdZhpsCzG2XxtMnRfPWPZu7uAMgKMc3IZVGS5oYJLBS3tP s=; Received: from ironmsg09-lv.qualcomm.com ([10.47.202.153]) by alexa-out.qualcomm.com with ESMTP; 16 Sep 2021 23:33:31 -0700 X-QCInternal: smtphost Received: from nalasex01a.na.qualcomm.com ([10.47.209.196]) by ironmsg09-lv.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Sep 2021 23:33:31 -0700 Received: from fenglinw-gv.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.7; Thu, 16 Sep 2021 23:33:29 -0700 From: Fenglin Wu To: , , CC: , , Subject: [RESEND PATCH v1 8/9] spmi: pmic-arb: make interrupt support optional Date: Fri, 17 Sep 2021 14:33:03 +0800 Message-ID: <1631860384-26608-9-git-send-email-quic_fenglinw@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1631860384-26608-1-git-send-email-quic_fenglinw@quicinc.com> References: <1631860384-26608-1-git-send-email-quic_fenglinw@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: David Collins Make the support of PMIC peripheral interrupts optional for spmi-pmic-arb devices. This is useful in situations where SPMI address mapping is required without the need for IRQ support. Signed-off-by: David Collins Signed-off-by: Fenglin Wu --- drivers/spmi/spmi-pmic-arb.c | 45 +++++++++++++++++++++++++++----------------- 1 file changed, 28 insertions(+), 17 deletions(-) diff --git a/drivers/spmi/spmi-pmic-arb.c b/drivers/spmi/spmi-pmic-arb.c index 988204c..55fa981 100644 --- a/drivers/spmi/spmi-pmic-arb.c +++ b/drivers/spmi/spmi-pmic-arb.c @@ -1280,10 +1280,12 @@ static int spmi_pmic_arb_probe(struct platform_device *pdev) goto err_put_ctrl; } - pmic_arb->irq = platform_get_irq_byname(pdev, "periph_irq"); - if (pmic_arb->irq < 0) { - err = pmic_arb->irq; - goto err_put_ctrl; + if (of_find_property(pdev->dev.of_node, "interrupt-names", NULL)) { + pmic_arb->irq = platform_get_irq_byname(pdev, "periph_irq"); + if (pmic_arb->irq < 0) { + err = pmic_arb->irq; + goto err_put_ctrl; + } } err = of_property_read_u32(pdev->dev.of_node, "qcom,channel", &channel); @@ -1343,17 +1345,22 @@ static int spmi_pmic_arb_probe(struct platform_device *pdev) } } - dev_dbg(&pdev->dev, "adding irq domain\n"); - pmic_arb->domain = irq_domain_add_tree(pdev->dev.of_node, - &pmic_arb_irq_domain_ops, pmic_arb); - if (!pmic_arb->domain) { - dev_err(&pdev->dev, "unable to create irq_domain\n"); - err = -ENOMEM; - goto err_put_ctrl; + if (pmic_arb->irq > 0) { + dev_dbg(&pdev->dev, "adding irq domain\n"); + pmic_arb->domain = irq_domain_add_tree(pdev->dev.of_node, + &pmic_arb_irq_domain_ops, pmic_arb); + if (!pmic_arb->domain) { + dev_err(&pdev->dev, "unable to create irq_domain\n"); + err = -ENOMEM; + goto err_put_ctrl; + } + + irq_set_chained_handler_and_data(pmic_arb->irq, + pmic_arb_chained_irq, pmic_arb); + } else { + dev_dbg(&pdev->dev, "not supporting PMIC interrupts\n"); } - irq_set_chained_handler_and_data(pmic_arb->irq, pmic_arb_chained_irq, - pmic_arb); err = spmi_controller_add(ctrl); if (err) goto err_domain_remove; @@ -1361,8 +1368,10 @@ static int spmi_pmic_arb_probe(struct platform_device *pdev) return 0; err_domain_remove: - irq_set_chained_handler_and_data(pmic_arb->irq, NULL, NULL); - irq_domain_remove(pmic_arb->domain); + if (pmic_arb->irq > 0) { + irq_set_chained_handler_and_data(pmic_arb->irq, NULL, NULL); + irq_domain_remove(pmic_arb->domain); + } err_put_ctrl: spmi_controller_put(ctrl); return err; @@ -1373,8 +1382,10 @@ static int spmi_pmic_arb_remove(struct platform_device *pdev) struct spmi_controller *ctrl = platform_get_drvdata(pdev); struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl); spmi_controller_remove(ctrl); - irq_set_chained_handler_and_data(pmic_arb->irq, NULL, NULL); - irq_domain_remove(pmic_arb->domain); + if (pmic_arb->irq > 0) { + irq_set_chained_handler_and_data(pmic_arb->irq, NULL, NULL); + irq_domain_remove(pmic_arb->domain); + } spmi_controller_put(ctrl); return 0; } From patchwork Fri Sep 17 06:33:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fenglin Wu X-Patchwork-Id: 12501217 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D119FC433F5 for ; Fri, 17 Sep 2021 06:33:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BAC7561152 for ; Fri, 17 Sep 2021 06:33:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244245AbhIQGe7 (ORCPT ); Fri, 17 Sep 2021 02:34:59 -0400 Received: from alexa-out.qualcomm.com ([129.46.98.28]:63132 "EHLO alexa-out.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243221AbhIQGez (ORCPT ); Fri, 17 Sep 2021 02:34:55 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1631860414; x=1663396414; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=/rJWYNLEshjtrC1IGOED6acbfsbHHmLBFIvrAeJEFiI=; b=MBdthKwijV/pCdARgBtZf1ISGQD2aAokrM7eNebH0XWYi3g5COTWyNBe k90HDMLvmZ8JZ3h42lzDPrq76nDYX6meNCNUyzYVihlVGJcniUJid79E0 YPKOUhcKsX7QDk9StiJnB8jaErF3s28FzWYpYllwq2ukXa3zwCxVfJOHo A=; Received: from ironmsg09-lv.qualcomm.com ([10.47.202.153]) by alexa-out.qualcomm.com with ESMTP; 16 Sep 2021 23:33:34 -0700 X-QCInternal: smtphost Received: from nalasex01a.na.qualcomm.com ([10.47.209.196]) by ironmsg09-lv.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Sep 2021 23:33:34 -0700 Received: from fenglinw-gv.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.7; Thu, 16 Sep 2021 23:33:31 -0700 From: Fenglin Wu To: , , CC: , , Subject: [RESEND PATCH v1 9/9] spmi: pmic-arb: increase SPMI transaction timeout delay Date: Fri, 17 Sep 2021 14:33:04 +0800 Message-ID: <1631860384-26608-10-git-send-email-quic_fenglinw@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1631860384-26608-1-git-send-email-quic_fenglinw@quicinc.com> References: <1631860384-26608-1-git-send-email-quic_fenglinw@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: David Collins Increase the SPMI transaction timeout delay from 100 us to 1000 us in order to account for the slower execution time found on some simulator targets. Signed-off-by: David Collins Signed-off-by: Fenglin Wu --- drivers/spmi/spmi-pmic-arb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spmi/spmi-pmic-arb.c b/drivers/spmi/spmi-pmic-arb.c index 55fa981..08c2566 100644 --- a/drivers/spmi/spmi-pmic-arb.c +++ b/drivers/spmi/spmi-pmic-arb.c @@ -91,7 +91,7 @@ enum pmic_arb_channel { /* Maximum number of support PMIC peripherals */ #define PMIC_ARB_MAX_PERIPHS 512 -#define PMIC_ARB_TIMEOUT_US 100 +#define PMIC_ARB_TIMEOUT_US 1000 #define PMIC_ARB_MAX_TRANS_BYTES (8) #define PMIC_ARB_APID_MASK 0xFF