From patchwork Mon Sep 20 08:04:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: WANG Xuerui X-Patchwork-Id: 12505483 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DAA86C433F5 for ; Mon, 20 Sep 2021 14:22:56 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 41913610A0 for ; Mon, 20 Sep 2021 14:22:56 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 41913610A0 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=xen0n.name Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:47198 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mSKC6-0004Ey-Ed for qemu-devel@archiver.kernel.org; Mon, 20 Sep 2021 10:22:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49572) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mSEP8-0008Vo-VT for qemu-devel@nongnu.org; Mon, 20 Sep 2021 04:11:59 -0400 Received: from [115.28.160.31] (port=35602 helo=mailbox.box.xen0n.name) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mSEP5-0005Sz-Rl for qemu-devel@nongnu.org; Mon, 20 Sep 2021 04:11:58 -0400 Received: from ld50.lan (unknown [101.88.25.142]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by mailbox.box.xen0n.name (Postfix) with ESMTPSA id D0BB9633F2; Mon, 20 Sep 2021 16:05:05 +0800 (CST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=xen0n.name; s=mail; t=1632125105; bh=+iUspIXOsG/uaNec4qlFLc69K3AZxcAoGJIJBpYxthc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=dnZ/Vpa4P3fLESHo0eFY/2IE5kHhecMyy8hhF7nT25ilZvBodUShiqUzyWOFspyou QvyGrCiYdFVrUp+TKJcNzFWs93eZA88FkSnyxXiksy2tXwrnQHCiqSbUy7gBuzh+4F ZlY1MXmiD1TJIvbjlSGGZjTZtsDhmY2vs6bRFH8U= From: WANG Xuerui To: qemu-devel@nongnu.org Subject: [PATCH 01/30] elf: Add machine type value for LoongArch Date: Mon, 20 Sep 2021 16:04:22 +0800 Message-Id: <20210920080451.408655-2-git@xen0n.name> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210920080451.408655-1-git@xen0n.name> References: <20210920080451.408655-1-git@xen0n.name> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.28.160.31 (failed) Received-SPF: pass client-ip=115.28.160.31; envelope-from=git@xen0n.name; helo=mailbox.box.xen0n.name X-Spam_score_int: 6 X-Spam_score: 0.6 X-Spam_bar: / X-Spam_report: (0.6 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 20 Sep 2021 09:57:24 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: WANG Xuerui Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: WANG Xuerui --- include/elf.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/elf.h b/include/elf.h index 811bf4a1cb..3a4bcb646a 100644 --- a/include/elf.h +++ b/include/elf.h @@ -182,6 +182,8 @@ typedef struct mips_elf_abiflags_v0 { #define EM_NANOMIPS 249 /* Wave Computing nanoMIPS */ +#define EM_LOONGARCH 258 /* LoongArch */ + /* * This is an interim value that we will use until the committee comes * up with a final number. From patchwork Mon Sep 20 08:04:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: WANG Xuerui X-Patchwork-Id: 12505395 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D963EC4332F for ; Mon, 20 Sep 2021 13:59:41 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3B968610A3 for ; Mon, 20 Sep 2021 13:59:41 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 3B968610A3 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=xen0n.name Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:54002 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mSJpc-0004O5-DT for qemu-devel@archiver.kernel.org; Mon, 20 Sep 2021 09:59:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49496) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mSEP6-0008Mi-9z for qemu-devel@nongnu.org; Mon, 20 Sep 2021 04:11:56 -0400 Received: from [115.28.160.31] (port=35588 helo=mailbox.box.xen0n.name) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mSEP3-0005QO-QD for qemu-devel@nongnu.org; Mon, 20 Sep 2021 04:11:56 -0400 Received: from ld50.lan (unknown [101.88.25.142]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by mailbox.box.xen0n.name (Postfix) with ESMTPSA id 8AEBA633F3; Mon, 20 Sep 2021 16:05:09 +0800 (CST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=xen0n.name; s=mail; t=1632125109; bh=0IY6fouHN1eV7whv2WjiBoKwWOUwhGcvaIKax7Wtakk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UdaBb9rPF/UTW7HpQi5VGMdSxLrGaRse+QEMMjzZj3l/fU7s5+MR7Eix00SZlSRDN AxKoOnkyUXQT2viJoozWF1hH71als80ogrYCTQsGt65OGLhdsaHZi1LiKAb7uTNref ULRPsL6P9yvaoPEoEU0fVcL3M+0u/qEm6ZyHHO84= From: WANG Xuerui To: qemu-devel@nongnu.org Subject: [PATCH 02/30] MAINTAINERS: Add tcg/loongarch entry with myself as maintainer Date: Mon, 20 Sep 2021 16:04:23 +0800 Message-Id: <20210920080451.408655-3-git@xen0n.name> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210920080451.408655-1-git@xen0n.name> References: <20210920080451.408655-1-git@xen0n.name> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.28.160.31 (failed) Received-SPF: pass client-ip=115.28.160.31; envelope-from=git@xen0n.name; helo=mailbox.box.xen0n.name X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 20 Sep 2021 09:57:24 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: WANG Xuerui Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" I wrote the initial code, so I should maintain it of course. Signed-off-by: WANG Xuerui Reviewed-by: Richard Henderson --- MAINTAINERS | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 6c20634d63..0e9942cc00 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3109,6 +3109,11 @@ S: Maintained F: tcg/i386/ F: disas/i386.c +LoongArch TCG target +M: WANG Xuerui +S: Maintained +F: tcg/loongarch/ + MIPS TCG target M: Philippe Mathieu-Daudé R: Aurelien Jarno From patchwork Mon Sep 20 08:04:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: WANG Xuerui X-Patchwork-Id: 12505425 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3FF42C433EF for ; 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Mon, 20 Sep 2021 04:11:42 -0400 Received: from ld50.lan (unknown [101.88.25.142]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by mailbox.box.xen0n.name (Postfix) with ESMTPSA id 6B0DC633F4; Mon, 20 Sep 2021 16:05:13 +0800 (CST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=xen0n.name; s=mail; t=1632125113; bh=xSfeItzcfMD8IYz/Fy3/zbhtYCYXITo9Vx7DfqCMk4M=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=vBh8hYkXRxJ5n6Row1HCAVSJRUV4SsXl/1UnkJWr9X+XGBJvb3FGetqjF+4hrVP01 Ktk/dQLZN6EwhE6O+8jWa3rEVqUYSToELEkTyZD/T7+CUUyvGkjaCQuCRsdBODiQ1W GwuAbwnD28oHSKmIex92GLz5+/xFWtWq9FdNOmow= From: WANG Xuerui To: qemu-devel@nongnu.org Subject: [PATCH 03/30] tcg/loongarch: Add the tcg-target.h file Date: Mon, 20 Sep 2021 16:04:24 +0800 Message-Id: <20210920080451.408655-4-git@xen0n.name> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210920080451.408655-1-git@xen0n.name> References: <20210920080451.408655-1-git@xen0n.name> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.28.160.31 (failed) Received-SPF: pass client-ip=115.28.160.31; envelope-from=git@xen0n.name; helo=mailbox.box.xen0n.name X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 20 Sep 2021 09:57:24 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: WANG Xuerui Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: WANG Xuerui --- tcg/loongarch/tcg-target.h | 183 +++++++++++++++++++++++++++++++++++++ 1 file changed, 183 insertions(+) create mode 100644 tcg/loongarch/tcg-target.h diff --git a/tcg/loongarch/tcg-target.h b/tcg/loongarch/tcg-target.h new file mode 100644 index 0000000000..b5e70e01b5 --- /dev/null +++ b/tcg/loongarch/tcg-target.h @@ -0,0 +1,183 @@ +/* + * Tiny Code Generator for QEMU + * + * Copyright (c) 2021 WANG Xuerui + * + * Based on tcg/riscv/tcg-target.h + * + * Copyright (c) 2018 SiFive, Inc + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef LOONGARCH_TCG_TARGET_H +#define LOONGARCH_TCG_TARGET_H + +/* + * Loongson removed the (incomplete) 32-bit support from kernel and toolchain + * for the initial upstreaming of this architecture, so don't bother and just + * support the LP64 ABI for now. + */ +#if defined(__loongarch64) +# define TCG_TARGET_REG_BITS 64 +#else +# error unsupported LoongArch bitness +#endif + +#define TCG_TARGET_INSN_UNIT_SIZE 4 +#define TCG_TARGET_TLB_DISPLACEMENT_BITS 20 +#define TCG_TARGET_NB_REGS 32 +#define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1) + +typedef enum { + TCG_REG_ZERO, + TCG_REG_RA, + TCG_REG_TP, + TCG_REG_SP, + TCG_REG_A0, + TCG_REG_A1, + TCG_REG_A2, + TCG_REG_A3, + TCG_REG_A4, + TCG_REG_A5, + TCG_REG_A6, + TCG_REG_A7, + TCG_REG_T0, + TCG_REG_T1, + TCG_REG_T2, + TCG_REG_T3, + TCG_REG_T4, + TCG_REG_T5, + TCG_REG_T6, + TCG_REG_T7, + TCG_REG_T8, + TCG_REG_RESERVED, + TCG_REG_S9, + TCG_REG_S0, + TCG_REG_S1, + TCG_REG_S2, + TCG_REG_S3, + TCG_REG_S4, + TCG_REG_S5, + TCG_REG_S6, + TCG_REG_S7, + TCG_REG_S8, + + /* aliases */ + TCG_AREG0 = TCG_REG_S0, + TCG_GUEST_BASE_REG = TCG_REG_S1, + TCG_REG_TMP0 = TCG_REG_T8, + TCG_REG_TMP1 = TCG_REG_T7, + TCG_REG_TMP2 = TCG_REG_T6, +} TCGReg; + +/* used for function call generation */ +#define TCG_REG_CALL_STACK TCG_REG_SP +#define TCG_TARGET_STACK_ALIGN 16 +#define TCG_TARGET_CALL_ALIGN_ARGS 1 +#define TCG_TARGET_CALL_STACK_OFFSET 0 + +/* optional instructions */ +#define TCG_TARGET_HAS_movcond_i32 0 +#define TCG_TARGET_HAS_div_i32 1 +#define TCG_TARGET_HAS_rem_i32 1 +#define TCG_TARGET_HAS_div2_i32 0 +#define TCG_TARGET_HAS_rot_i32 1 +#define TCG_TARGET_HAS_deposit_i32 1 +#define TCG_TARGET_HAS_extract_i32 1 +#define TCG_TARGET_HAS_sextract_i32 0 +#define TCG_TARGET_HAS_extract2_i32 0 +#define TCG_TARGET_HAS_add2_i32 0 +#define TCG_TARGET_HAS_sub2_i32 0 +#define TCG_TARGET_HAS_mulu2_i32 0 +#define TCG_TARGET_HAS_muls2_i32 0 +#define TCG_TARGET_HAS_muluh_i32 1 +#define TCG_TARGET_HAS_mulsh_i32 1 +#define TCG_TARGET_HAS_ext8s_i32 1 +#define TCG_TARGET_HAS_ext16s_i32 1 +#define TCG_TARGET_HAS_ext8u_i32 1 +#define TCG_TARGET_HAS_ext16u_i32 1 +#define TCG_TARGET_HAS_bswap16_i32 0 +#define TCG_TARGET_HAS_bswap32_i32 1 +#define TCG_TARGET_HAS_not_i32 1 +#define TCG_TARGET_HAS_neg_i32 1 +#define TCG_TARGET_HAS_andc_i32 1 +#define TCG_TARGET_HAS_orc_i32 1 +#define TCG_TARGET_HAS_eqv_i32 0 +#define TCG_TARGET_HAS_nand_i32 0 +#define TCG_TARGET_HAS_nor_i32 1 +#define TCG_TARGET_HAS_clz_i32 1 +#define TCG_TARGET_HAS_ctz_i32 1 +#define TCG_TARGET_HAS_ctpop_i32 0 +#define TCG_TARGET_HAS_direct_jump 0 +#define TCG_TARGET_HAS_brcond2 0 +#define TCG_TARGET_HAS_setcond2 0 +#define TCG_TARGET_HAS_qemu_st8_i32 0 + +#if TCG_TARGET_REG_BITS == 64 +#define TCG_TARGET_HAS_movcond_i64 0 +#define TCG_TARGET_HAS_div_i64 1 +#define TCG_TARGET_HAS_rem_i64 1 +#define TCG_TARGET_HAS_div2_i64 0 +#define TCG_TARGET_HAS_rot_i64 1 +#define TCG_TARGET_HAS_deposit_i64 1 +#define TCG_TARGET_HAS_extract_i64 1 +#define TCG_TARGET_HAS_sextract_i64 0 +#define TCG_TARGET_HAS_extract2_i64 0 +#define TCG_TARGET_HAS_extrl_i64_i32 1 +#define TCG_TARGET_HAS_extrh_i64_i32 1 +#define TCG_TARGET_HAS_ext8s_i64 1 +#define TCG_TARGET_HAS_ext16s_i64 1 +#define TCG_TARGET_HAS_ext32s_i64 1 +#define TCG_TARGET_HAS_ext8u_i64 1 +#define TCG_TARGET_HAS_ext16u_i64 1 +#define TCG_TARGET_HAS_ext32u_i64 1 +#define TCG_TARGET_HAS_bswap16_i64 0 +#define TCG_TARGET_HAS_bswap32_i64 0 +#define TCG_TARGET_HAS_bswap64_i64 1 +#define TCG_TARGET_HAS_not_i64 1 +#define TCG_TARGET_HAS_neg_i64 1 +#define TCG_TARGET_HAS_andc_i64 1 +#define TCG_TARGET_HAS_orc_i64 1 +#define TCG_TARGET_HAS_eqv_i64 0 +#define TCG_TARGET_HAS_nand_i64 0 +#define TCG_TARGET_HAS_nor_i64 1 +#define TCG_TARGET_HAS_clz_i64 1 +#define TCG_TARGET_HAS_ctz_i64 1 +#define TCG_TARGET_HAS_ctpop_i64 0 +#define TCG_TARGET_HAS_add2_i64 0 +#define TCG_TARGET_HAS_sub2_i64 0 +#define TCG_TARGET_HAS_mulu2_i64 0 +#define TCG_TARGET_HAS_muls2_i64 0 +#define TCG_TARGET_HAS_muluh_i64 1 +#define TCG_TARGET_HAS_mulsh_i64 1 +#endif + +/* not defined -- call should be eliminated at compile time */ +void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); + +#define TCG_TARGET_DEFAULT_MO (0) + +#ifdef CONFIG_SOFTMMU +#define TCG_TARGET_NEED_LDST_LABELS +#endif + +#define TCG_TARGET_HAS_MEMORY_BSWAP 0 + +#endif /* LOONGARCH_TCG_TARGET_H */ From patchwork Mon Sep 20 08:04:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: WANG Xuerui X-Patchwork-Id: 12505489 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-21.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9A874C433EF for ; Mon, 20 Sep 2021 14:26:52 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 18C8160E76 for ; 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Mon, 20 Sep 2021 16:05:17 +0800 (CST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=xen0n.name; s=mail; t=1632125117; bh=Lu5mLUyhQt1LqmrXXY0yo4NwJg17Ezz8k5d+Ck61Fgk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mxEVxQ8ak9d5CeABj/xIdBrzGWNNjwtcW6jLw0HGQjptujCGIbOzwW4IAQoXBFxDj uiK3WkhxuMqZXI3gM9/HEMCEiEAEurrORp+ZlQtVQnayL+H4Bs++rtm5zHYXw0z1zy P6LZi54DhUskbMDCZQwieD0FcmMf1GW0A+lNqDLQ= From: WANG Xuerui To: qemu-devel@nongnu.org Subject: [PATCH 04/30] tcg/loongarch: Add generated instruction opcodes and encoding helpers Date: Mon, 20 Sep 2021 16:04:25 +0800 Message-Id: <20210920080451.408655-5-git@xen0n.name> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210920080451.408655-1-git@xen0n.name> References: <20210920080451.408655-1-git@xen0n.name> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.28.160.31 (failed) Received-SPF: pass client-ip=115.28.160.31; envelope-from=git@xen0n.name; helo=mailbox.box.xen0n.name X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 20 Sep 2021 09:57:24 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: WANG Xuerui Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: WANG Xuerui Acked-by: Richard Henderson --- tcg/loongarch/tcg-insn-defs.c.inc | 1080 +++++++++++++++++++++++++++++ 1 file changed, 1080 insertions(+) create mode 100644 tcg/loongarch/tcg-insn-defs.c.inc diff --git a/tcg/loongarch/tcg-insn-defs.c.inc b/tcg/loongarch/tcg-insn-defs.c.inc new file mode 100644 index 0000000000..413f7ffc12 --- /dev/null +++ b/tcg/loongarch/tcg-insn-defs.c.inc @@ -0,0 +1,1080 @@ +/* SPDX-License-Identifier: MIT */ +/* + * LoongArch instruction formats, opcodes, and encoders for TCG use. + * + * Code generated by genqemutcgdefs from + * https://github.com/loongson-community/loongarch-opcodes, + * from commit bb5234081663faaefb6b921a7848b18e19519890. + * DO NOT EDIT. + */ + +typedef enum { + OPC_CLZ_W = 0x00001400, + OPC_CTZ_W = 0x00001c00, + OPC_CLZ_D = 0x00002400, + OPC_CTZ_D = 0x00002c00, + OPC_REVB_2H = 0x00003000, + OPC_REVB_D = 0x00003c00, + OPC_SEXT_H = 0x00005800, + OPC_SEXT_B = 0x00005c00, + OPC_ADD_W = 0x00100000, + OPC_ADD_D = 0x00108000, + OPC_SUB_W = 0x00110000, + OPC_SUB_D = 0x00118000, + OPC_SLT = 0x00120000, + OPC_SLTU = 0x00128000, + OPC_MASKEQZ = 0x00130000, + OPC_MASKNEZ = 0x00138000, + OPC_NOR = 0x00140000, + OPC_AND = 0x00148000, + OPC_OR = 0x00150000, + OPC_XOR = 0x00158000, + OPC_ORN = 0x00160000, + OPC_ANDN = 0x00168000, + OPC_SLL_W = 0x00170000, + OPC_SRL_W = 0x00178000, + OPC_SRA_W = 0x00180000, + OPC_SLL_D = 0x00188000, + OPC_SRL_D = 0x00190000, + OPC_SRA_D = 0x00198000, + OPC_ROTR_W = 0x001b0000, + OPC_ROTR_D = 0x001b8000, + OPC_MUL_W = 0x001c0000, + OPC_MULH_W = 0x001c8000, + OPC_MULH_WU = 0x001d0000, + OPC_MUL_D = 0x001d8000, + OPC_MULH_D = 0x001e0000, + OPC_MULH_DU = 0x001e8000, + OPC_DIV_W = 0x00200000, + OPC_MOD_W = 0x00208000, + OPC_DIV_WU = 0x00210000, + OPC_MOD_WU = 0x00218000, + OPC_DIV_D = 0x00220000, + OPC_MOD_D = 0x00228000, + OPC_DIV_DU = 0x00230000, + OPC_MOD_DU = 0x00238000, + OPC_SLLI_W = 0x00408000, + OPC_SLLI_D = 0x00410000, + OPC_SRLI_W = 0x00448000, + OPC_SRLI_D = 0x00450000, + OPC_SRAI_W = 0x00488000, + OPC_SRAI_D = 0x00490000, + OPC_ROTRI_W = 0x004c8000, + OPC_ROTRI_D = 0x004d0000, + OPC_BSTRINS_W = 0x00600000, + OPC_BSTRPICK_W = 0x00608000, + OPC_BSTRINS_D = 0x00800000, + OPC_BSTRPICK_D = 0x00c00000, + OPC_SLTI = 0x02000000, + OPC_SLTUI = 0x02400000, + OPC_ADDI_W = 0x02800000, + OPC_ADDI_D = 0x02c00000, + OPC_CU52I_D = 0x03000000, + OPC_ANDI = 0x03400000, + OPC_ORI = 0x03800000, + OPC_XORI = 0x03c00000, + OPC_LU12I_W = 0x14000000, + OPC_CU32I_D = 0x16000000, + OPC_PCADDU12I = 0x1c000000, + OPC_LD_B = 0x28000000, + OPC_LD_H = 0x28400000, + OPC_LD_W = 0x28800000, + OPC_LD_D = 0x28c00000, + OPC_ST_B = 0x29000000, + OPC_ST_H = 0x29400000, + OPC_ST_W = 0x29800000, + OPC_ST_D = 0x29c00000, + OPC_LD_BU = 0x2a000000, + OPC_LD_HU = 0x2a400000, + OPC_LD_WU = 0x2a800000, + OPC_DBAR = 0x38720000, + OPC_JIRL = 0x4c000000, + OPC_B = 0x50000000, + OPC_BL = 0x54000000, + OPC_BEQ = 0x58000000, + OPC_BNE = 0x5c000000, + OPC_BGT = 0x60000000, + OPC_BLE = 0x64000000, + OPC_BGTU = 0x68000000, + OPC_BLEU = 0x6c000000, +} LoongArchInsn; + +static int32_t encode_d_slot(LoongArchInsn opc, uint32_t d) + __attribute__((unused)); + +static int32_t encode_d_slot(LoongArchInsn opc, uint32_t d) +{ + return opc | d; +} + +static int32_t encode_dj_slots(LoongArchInsn opc, uint32_t d, uint32_t j) + __attribute__((unused)); + +static int32_t encode_dj_slots(LoongArchInsn opc, uint32_t d, uint32_t j) +{ + return opc | d | j << 5; +} + +static int32_t encode_djk_slots(LoongArchInsn opc, uint32_t d, uint32_t j, + uint32_t k) __attribute__((unused)); + +static int32_t encode_djk_slots(LoongArchInsn opc, uint32_t d, uint32_t j, + uint32_t k) +{ + return opc | d | j << 5 | k << 10; +} + +static int32_t encode_djkm_slots(LoongArchInsn opc, uint32_t d, uint32_t j, + uint32_t k, uint32_t m) + __attribute__((unused)); + +static int32_t encode_djkm_slots(LoongArchInsn opc, uint32_t d, uint32_t j, + uint32_t k, uint32_t m) +{ + return opc | d | j << 5 | k << 10 | m << 16; +} + +static int32_t encode_dk_slots(LoongArchInsn opc, uint32_t d, uint32_t k) + __attribute__((unused)); + +static int32_t encode_dk_slots(LoongArchInsn opc, uint32_t d, uint32_t k) +{ + return opc | d | k << 10; +} + +static int32_t encode_dj_insn(LoongArchInsn opc, TCGReg d, TCGReg j) + __attribute__((unused)); + +static int32_t encode_dj_insn(LoongArchInsn opc, TCGReg d, TCGReg j) +{ + d &= 0x1f; + j &= 0x1f; + return encode_dj_slots(opc, d, j); +} + +static int32_t encode_djk_insn(LoongArchInsn opc, TCGReg d, TCGReg j, TCGReg k) + __attribute__((unused)); + +static int32_t encode_djk_insn(LoongArchInsn opc, TCGReg d, TCGReg j, TCGReg k) +{ + d &= 0x1f; + j &= 0x1f; + k &= 0x1f; + return encode_djk_slots(opc, d, j, k); +} + +static int32_t encode_djsk12_insn(LoongArchInsn opc, TCGReg d, TCGReg j, + int32_t sk12) __attribute__((unused)); + +static int32_t encode_djsk12_insn(LoongArchInsn opc, TCGReg d, TCGReg j, + int32_t sk12) +{ + d &= 0x1f; + j &= 0x1f; + sk12 &= 0xfff; + return encode_djk_slots(opc, d, j, sk12); +} + +static int32_t encode_djsk16_insn(LoongArchInsn opc, TCGReg d, TCGReg j, + int32_t sk16) __attribute__((unused)); + +static int32_t encode_djsk16_insn(LoongArchInsn opc, TCGReg d, TCGReg j, + int32_t sk16) +{ + d &= 0x1f; + j &= 0x1f; + sk16 &= 0xffff; + return encode_djk_slots(opc, d, j, sk16); +} + +static int32_t encode_djuk12_insn(LoongArchInsn opc, TCGReg d, TCGReg j, + uint32_t uk12) __attribute__((unused)); + +static int32_t encode_djuk12_insn(LoongArchInsn opc, TCGReg d, TCGReg j, + uint32_t uk12) +{ + d &= 0x1f; + j &= 0x1f; + uk12 &= 0xfff; + return encode_djk_slots(opc, d, j, uk12); +} + +static int32_t encode_djuk5_insn(LoongArchInsn opc, TCGReg d, TCGReg j, + uint32_t uk5) __attribute__((unused)); + +static int32_t encode_djuk5_insn(LoongArchInsn opc, TCGReg d, TCGReg j, + uint32_t uk5) +{ + d &= 0x1f; + j &= 0x1f; + uk5 &= 0x1f; + return encode_djk_slots(opc, d, j, uk5); +} + +static int32_t encode_djuk5um5_insn(LoongArchInsn opc, TCGReg d, TCGReg j, + uint32_t uk5, uint32_t um5) + __attribute__((unused)); + +static int32_t encode_djuk5um5_insn(LoongArchInsn opc, TCGReg d, TCGReg j, + uint32_t uk5, uint32_t um5) +{ + d &= 0x1f; + j &= 0x1f; + uk5 &= 0x1f; + um5 &= 0x1f; + return encode_djkm_slots(opc, d, j, uk5, um5); +} + +static int32_t encode_djuk6_insn(LoongArchInsn opc, TCGReg d, TCGReg j, + uint32_t uk6) __attribute__((unused)); + +static int32_t encode_djuk6_insn(LoongArchInsn opc, TCGReg d, TCGReg j, + uint32_t uk6) +{ + d &= 0x1f; + j &= 0x1f; + uk6 &= 0x3f; + return encode_djk_slots(opc, d, j, uk6); +} + +static int32_t encode_djuk6um6_insn(LoongArchInsn opc, TCGReg d, TCGReg j, + uint32_t uk6, uint32_t um6) + __attribute__((unused)); + +static int32_t encode_djuk6um6_insn(LoongArchInsn opc, TCGReg d, TCGReg j, + uint32_t uk6, uint32_t um6) +{ + d &= 0x1f; + j &= 0x1f; + uk6 &= 0x3f; + um6 &= 0x3f; + return encode_djkm_slots(opc, d, j, uk6, um6); +} + +static int32_t encode_dsj20_insn(LoongArchInsn opc, TCGReg d, int32_t sj20) + __attribute__((unused)); + +static int32_t encode_dsj20_insn(LoongArchInsn opc, TCGReg d, int32_t sj20) +{ + d &= 0x1f; + sj20 &= 0xfffff; + return encode_dj_slots(opc, d, sj20); +} + +static int32_t encode_sd10k16_insn(LoongArchInsn opc, int32_t sd10k16) + __attribute__((unused)); + +static int32_t encode_sd10k16_insn(LoongArchInsn opc, int32_t sd10k16) +{ + sd10k16 &= 0x3ffffff; + return encode_dk_slots(opc, (sd10k16 >> 16) & 0x3ff, sd10k16 & 0xffff); +} + +static int32_t encode_ud15_insn(LoongArchInsn opc, uint32_t ud15) + __attribute__((unused)); + +static int32_t encode_ud15_insn(LoongArchInsn opc, uint32_t ud15) +{ + ud15 &= 0x7fff; + return encode_d_slot(opc, ud15); +} + +/* Emits the `clz.w d, j` instruction. */ +static void tcg_out_opc_clz_w(TCGContext *s, TCGReg d, TCGReg j) + __attribute__((unused)); + +static void tcg_out_opc_clz_w(TCGContext *s, TCGReg d, TCGReg j) +{ + tcg_out32(s, encode_dj_insn(OPC_CLZ_W, d, j)); +} + +/* Emits the `ctz.w d, j` instruction. */ +static void tcg_out_opc_ctz_w(TCGContext *s, TCGReg d, TCGReg j) + __attribute__((unused)); + +static void tcg_out_opc_ctz_w(TCGContext *s, TCGReg d, TCGReg j) +{ + tcg_out32(s, encode_dj_insn(OPC_CTZ_W, d, j)); +} + +/* Emits the `clz.d d, j` instruction. */ +static void tcg_out_opc_clz_d(TCGContext *s, TCGReg d, TCGReg j) + __attribute__((unused)); + +static void tcg_out_opc_clz_d(TCGContext *s, TCGReg d, TCGReg j) +{ + tcg_out32(s, encode_dj_insn(OPC_CLZ_D, d, j)); +} + +/* Emits the `ctz.d d, j` instruction. */ +static void tcg_out_opc_ctz_d(TCGContext *s, TCGReg d, TCGReg j) + __attribute__((unused)); + +static void tcg_out_opc_ctz_d(TCGContext *s, TCGReg d, TCGReg j) +{ + tcg_out32(s, encode_dj_insn(OPC_CTZ_D, d, j)); +} + +/* Emits the `revb.2h d, j` instruction. */ +static void tcg_out_opc_revb_2h(TCGContext *s, TCGReg d, TCGReg j) + __attribute__((unused)); + +static void tcg_out_opc_revb_2h(TCGContext *s, TCGReg d, TCGReg j) +{ + tcg_out32(s, encode_dj_insn(OPC_REVB_2H, d, j)); +} + +/* Emits the `revb.d d, j` instruction. */ +static void tcg_out_opc_revb_d(TCGContext *s, TCGReg d, TCGReg j) + __attribute__((unused)); + +static void tcg_out_opc_revb_d(TCGContext *s, TCGReg d, TCGReg j) +{ + tcg_out32(s, encode_dj_insn(OPC_REVB_D, d, j)); +} + +/* Emits the `sext.h d, j` instruction. */ +static void tcg_out_opc_sext_h(TCGContext *s, TCGReg d, TCGReg j) + __attribute__((unused)); + +static void tcg_out_opc_sext_h(TCGContext *s, TCGReg d, TCGReg j) +{ + tcg_out32(s, encode_dj_insn(OPC_SEXT_H, d, j)); +} + +/* Emits the `sext.b d, j` instruction. */ +static void tcg_out_opc_sext_b(TCGContext *s, TCGReg d, TCGReg j) + __attribute__((unused)); + +static void tcg_out_opc_sext_b(TCGContext *s, TCGReg d, TCGReg j) +{ + tcg_out32(s, encode_dj_insn(OPC_SEXT_B, d, j)); +} + +/* Emits the `add.w d, j, k` instruction. */ +static void tcg_out_opc_add_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) + __attribute__((unused)); + +static void tcg_out_opc_add_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +{ + tcg_out32(s, encode_djk_insn(OPC_ADD_W, d, j, k)); +} + +/* Emits the `add.d d, j, k` instruction. */ +static void tcg_out_opc_add_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) + __attribute__((unused)); + +static void tcg_out_opc_add_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +{ + tcg_out32(s, encode_djk_insn(OPC_ADD_D, d, j, k)); +} + +/* Emits the `sub.w d, j, k` instruction. */ +static void tcg_out_opc_sub_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) + __attribute__((unused)); + +static void tcg_out_opc_sub_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +{ + tcg_out32(s, encode_djk_insn(OPC_SUB_W, d, j, k)); +} + +/* Emits the `sub.d d, j, k` instruction. */ +static void tcg_out_opc_sub_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) + __attribute__((unused)); + +static void tcg_out_opc_sub_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +{ + tcg_out32(s, encode_djk_insn(OPC_SUB_D, d, j, k)); +} + +/* Emits the `slt d, j, k` instruction. */ +static void tcg_out_opc_slt(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) + __attribute__((unused)); + +static void tcg_out_opc_slt(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +{ + tcg_out32(s, encode_djk_insn(OPC_SLT, d, j, k)); +} + +/* Emits the `sltu d, j, k` instruction. */ +static void tcg_out_opc_sltu(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) + __attribute__((unused)); + +static void tcg_out_opc_sltu(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +{ + tcg_out32(s, encode_djk_insn(OPC_SLTU, d, j, k)); +} + +/* Emits the `maskeqz d, j, k` instruction. */ +static void tcg_out_opc_maskeqz(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) + __attribute__((unused)); + +static void tcg_out_opc_maskeqz(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +{ + tcg_out32(s, encode_djk_insn(OPC_MASKEQZ, d, j, k)); +} + +/* Emits the `masknez d, j, k` instruction. */ +static void tcg_out_opc_masknez(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) + __attribute__((unused)); + +static void tcg_out_opc_masknez(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +{ + tcg_out32(s, encode_djk_insn(OPC_MASKNEZ, d, j, k)); +} + +/* Emits the `nor d, j, k` instruction. */ +static void tcg_out_opc_nor(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) + __attribute__((unused)); + +static void tcg_out_opc_nor(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +{ + tcg_out32(s, encode_djk_insn(OPC_NOR, d, j, k)); +} + +/* Emits the `and d, j, k` instruction. */ +static void tcg_out_opc_and(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) + __attribute__((unused)); + +static void tcg_out_opc_and(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +{ + tcg_out32(s, encode_djk_insn(OPC_AND, d, j, k)); +} + +/* Emits the `or d, j, k` instruction. */ +static void tcg_out_opc_or(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) + __attribute__((unused)); + +static void tcg_out_opc_or(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +{ + tcg_out32(s, encode_djk_insn(OPC_OR, d, j, k)); +} + +/* Emits the `xor d, j, k` instruction. */ +static void tcg_out_opc_xor(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) + __attribute__((unused)); + +static void tcg_out_opc_xor(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +{ + tcg_out32(s, encode_djk_insn(OPC_XOR, d, j, k)); +} + +/* Emits the `orn d, j, k` instruction. */ +static void tcg_out_opc_orn(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) + __attribute__((unused)); + +static void tcg_out_opc_orn(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +{ + tcg_out32(s, encode_djk_insn(OPC_ORN, d, j, k)); +} + +/* Emits the `andn d, j, k` instruction. */ +static void tcg_out_opc_andn(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) + __attribute__((unused)); + +static void tcg_out_opc_andn(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +{ + tcg_out32(s, encode_djk_insn(OPC_ANDN, d, j, k)); +} + +/* Emits the `sll.w d, j, k` instruction. */ +static void tcg_out_opc_sll_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) + __attribute__((unused)); + +static void tcg_out_opc_sll_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +{ + tcg_out32(s, encode_djk_insn(OPC_SLL_W, d, j, k)); +} + +/* Emits the `srl.w d, j, k` instruction. */ +static void tcg_out_opc_srl_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) + __attribute__((unused)); + +static void tcg_out_opc_srl_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +{ + tcg_out32(s, encode_djk_insn(OPC_SRL_W, d, j, k)); +} + +/* Emits the `sra.w d, j, k` instruction. */ +static void tcg_out_opc_sra_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) + __attribute__((unused)); + +static void tcg_out_opc_sra_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +{ + tcg_out32(s, encode_djk_insn(OPC_SRA_W, d, j, k)); +} + +/* Emits the `sll.d d, j, k` instruction. */ +static void tcg_out_opc_sll_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) + __attribute__((unused)); + +static void tcg_out_opc_sll_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +{ + tcg_out32(s, encode_djk_insn(OPC_SLL_D, d, j, k)); +} + +/* Emits the `srl.d d, j, k` instruction. */ +static void tcg_out_opc_srl_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) + __attribute__((unused)); + +static void tcg_out_opc_srl_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +{ + tcg_out32(s, encode_djk_insn(OPC_SRL_D, d, j, k)); +} + +/* Emits the `sra.d d, j, k` instruction. */ +static void tcg_out_opc_sra_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) + __attribute__((unused)); + +static void tcg_out_opc_sra_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +{ + tcg_out32(s, encode_djk_insn(OPC_SRA_D, d, j, k)); +} + +/* Emits the `rotr.w d, j, k` instruction. */ +static void tcg_out_opc_rotr_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) + __attribute__((unused)); + +static void tcg_out_opc_rotr_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +{ + tcg_out32(s, encode_djk_insn(OPC_ROTR_W, d, j, k)); +} + +/* Emits the `rotr.d d, j, k` instruction. */ +static void tcg_out_opc_rotr_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) + __attribute__((unused)); + +static void tcg_out_opc_rotr_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +{ + tcg_out32(s, encode_djk_insn(OPC_ROTR_D, d, j, k)); +} + +/* Emits the `mul.w d, j, k` instruction. */ +static void tcg_out_opc_mul_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) + __attribute__((unused)); + +static void tcg_out_opc_mul_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +{ + tcg_out32(s, encode_djk_insn(OPC_MUL_W, d, j, k)); +} + +/* Emits the `mulh.w d, j, k` instruction. */ +static void tcg_out_opc_mulh_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) + __attribute__((unused)); + +static void tcg_out_opc_mulh_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +{ + tcg_out32(s, encode_djk_insn(OPC_MULH_W, d, j, k)); +} + +/* Emits the `mulh.wu d, j, k` instruction. */ +static void tcg_out_opc_mulh_wu(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) + __attribute__((unused)); + +static void tcg_out_opc_mulh_wu(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +{ + tcg_out32(s, encode_djk_insn(OPC_MULH_WU, d, j, k)); +} + +/* Emits the `mul.d d, j, k` instruction. */ +static void tcg_out_opc_mul_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) + __attribute__((unused)); + +static void tcg_out_opc_mul_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +{ + tcg_out32(s, encode_djk_insn(OPC_MUL_D, d, j, k)); +} + +/* Emits the `mulh.d d, j, k` instruction. */ +static void tcg_out_opc_mulh_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) + __attribute__((unused)); + +static void tcg_out_opc_mulh_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +{ + tcg_out32(s, encode_djk_insn(OPC_MULH_D, d, j, k)); +} + +/* Emits the `mulh.du d, j, k` instruction. */ +static void tcg_out_opc_mulh_du(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) + __attribute__((unused)); + +static void tcg_out_opc_mulh_du(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +{ + tcg_out32(s, encode_djk_insn(OPC_MULH_DU, d, j, k)); +} + +/* Emits the `div.w d, j, k` instruction. */ +static void tcg_out_opc_div_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) + __attribute__((unused)); + +static void tcg_out_opc_div_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +{ + tcg_out32(s, encode_djk_insn(OPC_DIV_W, d, j, k)); +} + +/* Emits the `mod.w d, j, k` instruction. */ +static void tcg_out_opc_mod_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) + __attribute__((unused)); + +static void tcg_out_opc_mod_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +{ + tcg_out32(s, encode_djk_insn(OPC_MOD_W, d, j, k)); +} + +/* Emits the `div.wu d, j, k` instruction. */ +static void tcg_out_opc_div_wu(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) + __attribute__((unused)); + +static void tcg_out_opc_div_wu(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +{ + tcg_out32(s, encode_djk_insn(OPC_DIV_WU, d, j, k)); +} + +/* Emits the `mod.wu d, j, k` instruction. */ +static void tcg_out_opc_mod_wu(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) + __attribute__((unused)); + +static void tcg_out_opc_mod_wu(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +{ + tcg_out32(s, encode_djk_insn(OPC_MOD_WU, d, j, k)); +} + +/* Emits the `div.d d, j, k` instruction. */ +static void tcg_out_opc_div_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) + __attribute__((unused)); + +static void tcg_out_opc_div_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +{ + tcg_out32(s, encode_djk_insn(OPC_DIV_D, d, j, k)); +} + +/* Emits the `mod.d d, j, k` instruction. */ +static void tcg_out_opc_mod_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) + __attribute__((unused)); + +static void tcg_out_opc_mod_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +{ + tcg_out32(s, encode_djk_insn(OPC_MOD_D, d, j, k)); +} + +/* Emits the `div.du d, j, k` instruction. */ +static void tcg_out_opc_div_du(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) + __attribute__((unused)); + +static void tcg_out_opc_div_du(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +{ + tcg_out32(s, encode_djk_insn(OPC_DIV_DU, d, j, k)); +} + +/* Emits the `mod.du d, j, k` instruction. */ +static void tcg_out_opc_mod_du(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) + __attribute__((unused)); + +static void tcg_out_opc_mod_du(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) +{ + tcg_out32(s, encode_djk_insn(OPC_MOD_DU, d, j, k)); +} + +/* Emits the `slli.w d, j, uk5` instruction. */ +static void tcg_out_opc_slli_w(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk5) + __attribute__((unused)); + +static void tcg_out_opc_slli_w(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk5) +{ + tcg_out32(s, encode_djuk5_insn(OPC_SLLI_W, d, j, uk5)); +} + +/* Emits the `slli.d d, j, uk6` instruction. */ +static void tcg_out_opc_slli_d(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk6) + __attribute__((unused)); + +static void tcg_out_opc_slli_d(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk6) +{ + tcg_out32(s, encode_djuk6_insn(OPC_SLLI_D, d, j, uk6)); +} + +/* Emits the `srli.w d, j, uk5` instruction. */ +static void tcg_out_opc_srli_w(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk5) + __attribute__((unused)); + +static void tcg_out_opc_srli_w(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk5) +{ + tcg_out32(s, encode_djuk5_insn(OPC_SRLI_W, d, j, uk5)); +} + +/* Emits the `srli.d d, j, uk6` instruction. */ +static void tcg_out_opc_srli_d(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk6) + __attribute__((unused)); + +static void tcg_out_opc_srli_d(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk6) +{ + tcg_out32(s, encode_djuk6_insn(OPC_SRLI_D, d, j, uk6)); +} + +/* Emits the `srai.w d, j, uk5` instruction. */ +static void tcg_out_opc_srai_w(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk5) + __attribute__((unused)); + +static void tcg_out_opc_srai_w(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk5) +{ + tcg_out32(s, encode_djuk5_insn(OPC_SRAI_W, d, j, uk5)); +} + +/* Emits the `srai.d d, j, uk6` instruction. */ +static void tcg_out_opc_srai_d(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk6) + __attribute__((unused)); + +static void tcg_out_opc_srai_d(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk6) +{ + tcg_out32(s, encode_djuk6_insn(OPC_SRAI_D, d, j, uk6)); +} + +/* Emits the `rotri.w d, j, uk5` instruction. */ +static void tcg_out_opc_rotri_w(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk5) + __attribute__((unused)); + +static void tcg_out_opc_rotri_w(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk5) +{ + tcg_out32(s, encode_djuk5_insn(OPC_ROTRI_W, d, j, uk5)); +} + +/* Emits the `rotri.d d, j, uk6` instruction. */ +static void tcg_out_opc_rotri_d(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk6) + __attribute__((unused)); + +static void tcg_out_opc_rotri_d(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk6) +{ + tcg_out32(s, encode_djuk6_insn(OPC_ROTRI_D, d, j, uk6)); +} + +/* Emits the `bstrins.w d, j, uk5, um5` instruction. */ +static void tcg_out_opc_bstrins_w(TCGContext *s, TCGReg d, TCGReg j, + uint32_t uk5, uint32_t um5) + __attribute__((unused)); + +static void tcg_out_opc_bstrins_w(TCGContext *s, TCGReg d, TCGReg j, + uint32_t uk5, uint32_t um5) +{ + tcg_out32(s, encode_djuk5um5_insn(OPC_BSTRINS_W, d, j, uk5, um5)); +} + +/* Emits the `bstrpick.w d, j, uk5, um5` instruction. */ +static void tcg_out_opc_bstrpick_w(TCGContext *s, TCGReg d, TCGReg j, + uint32_t uk5, uint32_t um5) + __attribute__((unused)); + +static void tcg_out_opc_bstrpick_w(TCGContext *s, TCGReg d, TCGReg j, + uint32_t uk5, uint32_t um5) +{ + tcg_out32(s, encode_djuk5um5_insn(OPC_BSTRPICK_W, d, j, uk5, um5)); +} + +/* Emits the `bstrins.d d, j, uk6, um6` instruction. */ +static void tcg_out_opc_bstrins_d(TCGContext *s, TCGReg d, TCGReg j, + uint32_t uk6, uint32_t um6) + __attribute__((unused)); + +static void tcg_out_opc_bstrins_d(TCGContext *s, TCGReg d, TCGReg j, + uint32_t uk6, uint32_t um6) +{ + tcg_out32(s, encode_djuk6um6_insn(OPC_BSTRINS_D, d, j, uk6, um6)); +} + +/* Emits the `bstrpick.d d, j, uk6, um6` instruction. */ +static void tcg_out_opc_bstrpick_d(TCGContext *s, TCGReg d, TCGReg j, + uint32_t uk6, uint32_t um6) + __attribute__((unused)); + +static void tcg_out_opc_bstrpick_d(TCGContext *s, TCGReg d, TCGReg j, + uint32_t uk6, uint32_t um6) +{ + tcg_out32(s, encode_djuk6um6_insn(OPC_BSTRPICK_D, d, j, uk6, um6)); +} + +/* Emits the `slti d, j, sk12` instruction. */ +static void tcg_out_opc_slti(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12) + __attribute__((unused)); + +static void tcg_out_opc_slti(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12) +{ + tcg_out32(s, encode_djsk12_insn(OPC_SLTI, d, j, sk12)); +} + +/* Emits the `sltui d, j, sk12` instruction. */ +static void tcg_out_opc_sltui(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12) + __attribute__((unused)); + +static void tcg_out_opc_sltui(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12) +{ + tcg_out32(s, encode_djsk12_insn(OPC_SLTUI, d, j, sk12)); +} + +/* Emits the `addi.w d, j, sk12` instruction. */ +static void tcg_out_opc_addi_w(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12) + __attribute__((unused)); + +static void tcg_out_opc_addi_w(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12) +{ + tcg_out32(s, encode_djsk12_insn(OPC_ADDI_W, d, j, sk12)); +} + +/* Emits the `addi.d d, j, sk12` instruction. */ +static void tcg_out_opc_addi_d(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12) + __attribute__((unused)); + +static void tcg_out_opc_addi_d(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12) +{ + tcg_out32(s, encode_djsk12_insn(OPC_ADDI_D, d, j, sk12)); +} + +/* Emits the `cu52i.d d, j, sk12` instruction. */ +static void tcg_out_opc_cu52i_d(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12) + __attribute__((unused)); + +static void tcg_out_opc_cu52i_d(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12) +{ + tcg_out32(s, encode_djsk12_insn(OPC_CU52I_D, d, j, sk12)); +} + +/* Emits the `andi d, j, uk12` instruction. */ +static void tcg_out_opc_andi(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk12) + __attribute__((unused)); + +static void tcg_out_opc_andi(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk12) +{ + tcg_out32(s, encode_djuk12_insn(OPC_ANDI, d, j, uk12)); +} + +/* Emits the `ori d, j, uk12` instruction. */ +static void tcg_out_opc_ori(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk12) + __attribute__((unused)); + +static void tcg_out_opc_ori(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk12) +{ + tcg_out32(s, encode_djuk12_insn(OPC_ORI, d, j, uk12)); +} + +/* Emits the `xori d, j, uk12` instruction. */ +static void tcg_out_opc_xori(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk12) + __attribute__((unused)); + +static void tcg_out_opc_xori(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk12) +{ + tcg_out32(s, encode_djuk12_insn(OPC_XORI, d, j, uk12)); +} + +/* Emits the `lu12i.w d, sj20` instruction. */ +static void tcg_out_opc_lu12i_w(TCGContext *s, TCGReg d, int32_t sj20) + __attribute__((unused)); + +static void tcg_out_opc_lu12i_w(TCGContext *s, TCGReg d, int32_t sj20) +{ + tcg_out32(s, encode_dsj20_insn(OPC_LU12I_W, d, sj20)); +} + +/* Emits the `cu32i.d d, sj20` instruction. */ +static void tcg_out_opc_cu32i_d(TCGContext *s, TCGReg d, int32_t sj20) + __attribute__((unused)); + +static void tcg_out_opc_cu32i_d(TCGContext *s, TCGReg d, int32_t sj20) +{ + tcg_out32(s, encode_dsj20_insn(OPC_CU32I_D, d, sj20)); +} + +/* Emits the `pcaddu12i d, sj20` instruction. */ +static void tcg_out_opc_pcaddu12i(TCGContext *s, TCGReg d, int32_t sj20) + __attribute__((unused)); + +static void tcg_out_opc_pcaddu12i(TCGContext *s, TCGReg d, int32_t sj20) +{ + tcg_out32(s, encode_dsj20_insn(OPC_PCADDU12I, d, sj20)); +} + +/* Emits the `ld.b d, j, sk12` instruction. */ +static void tcg_out_opc_ld_b(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12) + __attribute__((unused)); + +static void tcg_out_opc_ld_b(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12) +{ + tcg_out32(s, encode_djsk12_insn(OPC_LD_B, d, j, sk12)); +} + +/* Emits the `ld.h d, j, sk12` instruction. */ +static void tcg_out_opc_ld_h(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12) + __attribute__((unused)); + +static void tcg_out_opc_ld_h(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12) +{ + tcg_out32(s, encode_djsk12_insn(OPC_LD_H, d, j, sk12)); +} + +/* Emits the `ld.w d, j, sk12` instruction. */ +static void tcg_out_opc_ld_w(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12) + __attribute__((unused)); + +static void tcg_out_opc_ld_w(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12) +{ + tcg_out32(s, encode_djsk12_insn(OPC_LD_W, d, j, sk12)); +} + +/* Emits the `ld.d d, j, sk12` instruction. */ +static void tcg_out_opc_ld_d(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12) + __attribute__((unused)); + +static void tcg_out_opc_ld_d(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12) +{ + tcg_out32(s, encode_djsk12_insn(OPC_LD_D, d, j, sk12)); +} + +/* Emits the `st.b d, j, sk12` instruction. */ +static void tcg_out_opc_st_b(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12) + __attribute__((unused)); + +static void tcg_out_opc_st_b(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12) +{ + tcg_out32(s, encode_djsk12_insn(OPC_ST_B, d, j, sk12)); +} + +/* Emits the `st.h d, j, sk12` instruction. */ +static void tcg_out_opc_st_h(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12) + __attribute__((unused)); + +static void tcg_out_opc_st_h(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12) +{ + tcg_out32(s, encode_djsk12_insn(OPC_ST_H, d, j, sk12)); +} + +/* Emits the `st.w d, j, sk12` instruction. */ +static void tcg_out_opc_st_w(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12) + __attribute__((unused)); + +static void tcg_out_opc_st_w(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12) +{ + tcg_out32(s, encode_djsk12_insn(OPC_ST_W, d, j, sk12)); +} + +/* Emits the `st.d d, j, sk12` instruction. */ +static void tcg_out_opc_st_d(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12) + __attribute__((unused)); + +static void tcg_out_opc_st_d(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12) +{ + tcg_out32(s, encode_djsk12_insn(OPC_ST_D, d, j, sk12)); +} + +/* Emits the `ld.bu d, j, sk12` instruction. */ +static void tcg_out_opc_ld_bu(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12) + __attribute__((unused)); + +static void tcg_out_opc_ld_bu(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12) +{ + tcg_out32(s, encode_djsk12_insn(OPC_LD_BU, d, j, sk12)); +} + +/* Emits the `ld.hu d, j, sk12` instruction. */ +static void tcg_out_opc_ld_hu(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12) + __attribute__((unused)); + +static void tcg_out_opc_ld_hu(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12) +{ + tcg_out32(s, encode_djsk12_insn(OPC_LD_HU, d, j, sk12)); +} + +/* Emits the `ld.wu d, j, sk12` instruction. */ +static void tcg_out_opc_ld_wu(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12) + __attribute__((unused)); + +static void tcg_out_opc_ld_wu(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12) +{ + tcg_out32(s, encode_djsk12_insn(OPC_LD_WU, d, j, sk12)); +} + +/* Emits the `dbar ud15` instruction. */ +static void tcg_out_opc_dbar(TCGContext *s, uint32_t ud15) + __attribute__((unused)); + +static void tcg_out_opc_dbar(TCGContext *s, uint32_t ud15) +{ + tcg_out32(s, encode_ud15_insn(OPC_DBAR, ud15)); +} + +/* Emits the `jirl d, j, sk16` instruction. */ +static void tcg_out_opc_jirl(TCGContext *s, TCGReg d, TCGReg j, int32_t sk16) + __attribute__((unused)); + +static void tcg_out_opc_jirl(TCGContext *s, TCGReg d, TCGReg j, int32_t sk16) +{ + tcg_out32(s, encode_djsk16_insn(OPC_JIRL, d, j, sk16)); +} + +/* Emits the `b sd10k16` instruction. */ +static void tcg_out_opc_b(TCGContext *s, int32_t sd10k16) + __attribute__((unused)); + +static void tcg_out_opc_b(TCGContext *s, int32_t sd10k16) +{ + tcg_out32(s, encode_sd10k16_insn(OPC_B, sd10k16)); +} + +/* Emits the `bl sd10k16` instruction. */ +static void tcg_out_opc_bl(TCGContext *s, int32_t sd10k16) + __attribute__((unused)); + +static void tcg_out_opc_bl(TCGContext *s, int32_t sd10k16) +{ + tcg_out32(s, encode_sd10k16_insn(OPC_BL, sd10k16)); +} + +/* Emits the `beq d, j, sk16` instruction. */ +static void tcg_out_opc_beq(TCGContext *s, TCGReg d, TCGReg j, int32_t sk16) + __attribute__((unused)); + +static void tcg_out_opc_beq(TCGContext *s, TCGReg d, TCGReg j, int32_t sk16) +{ + tcg_out32(s, encode_djsk16_insn(OPC_BEQ, d, j, sk16)); +} + +/* Emits the `bne d, j, sk16` instruction. */ +static void tcg_out_opc_bne(TCGContext *s, TCGReg d, TCGReg j, int32_t sk16) + __attribute__((unused)); + +static void tcg_out_opc_bne(TCGContext *s, TCGReg d, TCGReg j, int32_t sk16) +{ + tcg_out32(s, encode_djsk16_insn(OPC_BNE, d, j, sk16)); +} + +/* Emits the `bgt d, j, sk16` instruction. */ +static void tcg_out_opc_bgt(TCGContext *s, TCGReg d, TCGReg j, int32_t sk16) + __attribute__((unused)); + +static void tcg_out_opc_bgt(TCGContext *s, TCGReg d, TCGReg j, int32_t sk16) +{ + tcg_out32(s, encode_djsk16_insn(OPC_BGT, d, j, sk16)); +} + +/* Emits the `ble d, j, sk16` instruction. */ +static void tcg_out_opc_ble(TCGContext *s, TCGReg d, TCGReg j, int32_t sk16) + __attribute__((unused)); + +static void tcg_out_opc_ble(TCGContext *s, TCGReg d, TCGReg j, int32_t sk16) +{ + tcg_out32(s, encode_djsk16_insn(OPC_BLE, d, j, sk16)); +} + +/* Emits the `bgtu d, j, sk16` instruction. */ +static void tcg_out_opc_bgtu(TCGContext *s, TCGReg d, TCGReg j, int32_t sk16) + __attribute__((unused)); + +static void tcg_out_opc_bgtu(TCGContext *s, TCGReg d, TCGReg j, int32_t sk16) +{ + tcg_out32(s, encode_djsk16_insn(OPC_BGTU, d, j, sk16)); +} + +/* Emits the `bleu d, j, sk16` instruction. */ +static void tcg_out_opc_bleu(TCGContext *s, TCGReg d, TCGReg j, int32_t sk16) + __attribute__((unused)); + +static void tcg_out_opc_bleu(TCGContext *s, TCGReg d, TCGReg j, int32_t sk16) +{ + tcg_out32(s, encode_djsk16_insn(OPC_BLEU, d, j, sk16)); +} From patchwork Mon Sep 20 08:04:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: WANG Xuerui X-Patchwork-Id: 12505517 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9549AC433F5 for ; Mon, 20 Sep 2021 14:29:31 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5D68560E76 for ; Mon, 20 Sep 2021 14:29:31 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 5D68560E76 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=xen0n.name Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:34756 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mSKIU-0006NS-Eb for qemu-devel@archiver.kernel.org; Mon, 20 Sep 2021 10:29:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49544) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mSEP8-0008So-3o for qemu-devel@nongnu.org; Mon, 20 Sep 2021 04:11:58 -0400 Received: from [115.28.160.31] (port=35594 helo=mailbox.box.xen0n.name) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mSEP4-0005Rv-TH for qemu-devel@nongnu.org; Mon, 20 Sep 2021 04:11:57 -0400 Received: from ld50.lan (unknown [101.88.25.142]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by mailbox.box.xen0n.name (Postfix) with ESMTPSA id 58E6A633F6; Mon, 20 Sep 2021 16:05:20 +0800 (CST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=xen0n.name; s=mail; t=1632125120; bh=nF0dD5rXpn3iAv89iZn770hRkI5mAF0I5USphofDLdI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GgtxUCMeDRSAAfFCOSM7YqASk7c4wrCYBefTN4zc8VV9XF4ZpSyzmUA2vztfsYEC/ BgdwKivrJ5eqakr33/UbiRmF3Tl7BVVF6VCWmSIbKpiIJUKpSkK4A12BjUUgHwns+m L3qgf8Nr1cpRspv3OtmwqzLfFUzBKgIw0kp6ibqo= From: WANG Xuerui To: qemu-devel@nongnu.org Subject: [PATCH 05/30] tcg/loongarch: Add register names, allocation order and input/output sets Date: Mon, 20 Sep 2021 16:04:26 +0800 Message-Id: <20210920080451.408655-6-git@xen0n.name> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210920080451.408655-1-git@xen0n.name> References: <20210920080451.408655-1-git@xen0n.name> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.28.160.31 (failed) Received-SPF: pass client-ip=115.28.160.31; envelope-from=git@xen0n.name; helo=mailbox.box.xen0n.name X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 20 Sep 2021 09:57:24 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: WANG Xuerui Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: WANG Xuerui Reviewed-by: Richard Henderson --- tcg/loongarch/tcg-target.c.inc | 118 +++++++++++++++++++++++++++++++++ 1 file changed, 118 insertions(+) create mode 100644 tcg/loongarch/tcg-target.c.inc diff --git a/tcg/loongarch/tcg-target.c.inc b/tcg/loongarch/tcg-target.c.inc new file mode 100644 index 0000000000..f8c71bbaf4 --- /dev/null +++ b/tcg/loongarch/tcg-target.c.inc @@ -0,0 +1,118 @@ +/* + * Tiny Code Generator for QEMU + * + * Copyright (c) 2021 WANG Xuerui + * + * Based on tcg/riscv/tcg-target.c.inc + * + * Copyright (c) 2018 SiFive, Inc + * Copyright (c) 2008-2009 Arnaud Patard + * Copyright (c) 2009 Aurelien Jarno + * Copyright (c) 2008 Fabrice Bellard + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifdef CONFIG_DEBUG_TCG +static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { + "zero", + "ra", + "tp", + "sp", + "a0", + "a1", + "a2", + "a3", + "a4", + "a5", + "a6", + "a7", + "t0", + "t1", + "t2", + "t3", + "t4", + "t5", + "t6", + "t7", + "t8", + "r21", /* reserved in the LP64 ABI, hence no ABI name */ + "s9", + "s0", + "s1", + "s2", + "s3", + "s4", + "s5", + "s6", + "s7", + "s8" +}; +#endif + +static const int tcg_target_reg_alloc_order[] = { + /* Registers preserved across calls */ + /* TCG_REG_S0 reserved for TCG_AREG0 */ + TCG_REG_S1, + TCG_REG_S2, + TCG_REG_S3, + TCG_REG_S4, + TCG_REG_S5, + TCG_REG_S6, + TCG_REG_S7, + TCG_REG_S8, + TCG_REG_S9, + + /* Registers (potentially) clobbered across calls */ + TCG_REG_T0, + TCG_REG_T1, + TCG_REG_T2, + TCG_REG_T3, + TCG_REG_T4, + TCG_REG_T5, + TCG_REG_T6, + TCG_REG_T7, + TCG_REG_T8, + + /* Argument registers */ + TCG_REG_A0, + TCG_REG_A1, + TCG_REG_A2, + TCG_REG_A3, + TCG_REG_A4, + TCG_REG_A5, + TCG_REG_A6, + TCG_REG_A7, +}; + +static const int tcg_target_call_iarg_regs[] = { + TCG_REG_A0, + TCG_REG_A1, + TCG_REG_A2, + TCG_REG_A3, + TCG_REG_A4, + TCG_REG_A5, + TCG_REG_A6, + TCG_REG_A7, +}; + +static const int tcg_target_call_oarg_regs[] = { + TCG_REG_A0, + TCG_REG_A1, +}; From patchwork Mon Sep 20 08:04:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: WANG Xuerui X-Patchwork-Id: 12505403 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6434AC433FE for ; Mon, 20 Sep 2021 14:03:10 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2852A610A3 for ; Mon, 20 Sep 2021 14:03:10 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 2852A610A3 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=xen0n.name Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:34236 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mSJsz-0001de-9c for qemu-devel@archiver.kernel.org; Mon, 20 Sep 2021 10:03:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49542) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mSEP8-0008Sn-3q for qemu-devel@nongnu.org; Mon, 20 Sep 2021 04:11:58 -0400 Received: from [115.28.160.31] (port=35596 helo=mailbox.box.xen0n.name) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mSEP4-0005S0-Ub for qemu-devel@nongnu.org; Mon, 20 Sep 2021 04:11:57 -0400 Received: from ld50.lan (unknown [101.88.25.142]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by mailbox.box.xen0n.name (Postfix) with ESMTPSA id 5E19C633F7; Mon, 20 Sep 2021 16:05:24 +0800 (CST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=xen0n.name; s=mail; t=1632125124; bh=JjGvGTm/hfL3wf1oD+V32xyrO6JJpGky7/ONN6+KVmw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Mef00k/DYRfdijpb0ALSVCvtf+xsT9aKQM77LFT4Q7ww89Kfiv5rJ6PS95ly0m59G gS60OzF5TSmzRa+brNgOOBD+oltBcPbJ839w5Fs0tjNisV5xSIEsMhXIHQezJVdPEQ TM+oTZZ2ZLCWVPHXEh5D6VxvLEFFhXhLfYZ+NdrQ= From: WANG Xuerui To: qemu-devel@nongnu.org Subject: [PATCH 06/30] tcg/loongarch: Define the operand constraints Date: Mon, 20 Sep 2021 16:04:27 +0800 Message-Id: <20210920080451.408655-7-git@xen0n.name> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210920080451.408655-1-git@xen0n.name> References: <20210920080451.408655-1-git@xen0n.name> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.28.160.31 (failed) Received-SPF: pass client-ip=115.28.160.31; envelope-from=git@xen0n.name; helo=mailbox.box.xen0n.name X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 20 Sep 2021 09:57:24 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: WANG Xuerui Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: WANG Xuerui --- tcg/loongarch/tcg-target-con-str.h | 26 ++++++++++++++++ tcg/loongarch/tcg-target.c.inc | 48 ++++++++++++++++++++++++++++++ 2 files changed, 74 insertions(+) create mode 100644 tcg/loongarch/tcg-target-con-str.h diff --git a/tcg/loongarch/tcg-target-con-str.h b/tcg/loongarch/tcg-target-con-str.h new file mode 100644 index 0000000000..30b42d83a4 --- /dev/null +++ b/tcg/loongarch/tcg-target-con-str.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Define LoongArch target-specific operand constraints. + * + * Copyright (c) 2021 WANG Xuerui + * + * Based on tcg/riscv/tcg-target-con-str.h + * + * Copyright (c) 2021 Linaro + */ + +/* + * Define constraint letters for register sets: + * REGS(letter, register_mask) + */ +REGS('r', ALL_GENERAL_REGS) +REGS('L', ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS) + +/* + * Define constraint letters for constants: + * CONST(letter, TCG_CT_CONST_* bit set) + */ +CONST('I', TCG_CT_CONST_S12) +CONST('N', TCG_CT_CONST_N12) +CONST('U', TCG_CT_CONST_U12) +CONST('Z', TCG_CT_CONST_ZERO) diff --git a/tcg/loongarch/tcg-target.c.inc b/tcg/loongarch/tcg-target.c.inc index f8c71bbaf4..594b434b47 100644 --- a/tcg/loongarch/tcg-target.c.inc +++ b/tcg/loongarch/tcg-target.c.inc @@ -116,3 +116,51 @@ static const int tcg_target_call_oarg_regs[] = { TCG_REG_A0, TCG_REG_A1, }; + +#define TCG_CT_CONST_ZERO 0x100 +#define TCG_CT_CONST_S12 0x200 +#define TCG_CT_CONST_N12 0x400 +#define TCG_CT_CONST_U12 0x800 + +#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32) +/* + * For softmmu, we need to avoid conflicts with the first 5 + * argument registers to call the helper. Some of these are + * also used for the tlb lookup. + */ +#ifdef CONFIG_SOFTMMU +#define SOFTMMU_RESERVE_REGS MAKE_64BIT_MASK(TCG_REG_A0, 5) +#else +#define SOFTMMU_RESERVE_REGS 0 +#endif + + +static inline tcg_target_long sextreg(tcg_target_long val, int pos, int len) +{ + if (TCG_TARGET_REG_BITS == 32) { + return sextract32(val, pos, len); + } else { + return sextract64(val, pos, len); + } +} + +/* test if a constant matches the constraint */ +static bool tcg_target_const_match(int64_t val, TCGType type, int ct) +{ + if (ct & TCG_CT_CONST) { + return 1; + } + if ((ct & TCG_CT_CONST_ZERO) && val == 0) { + return 1; + } + if ((ct & TCG_CT_CONST_S12) && val == sextreg(val, 0, 12)) { + return 1; + } + if ((ct & TCG_CT_CONST_N12) && -val == sextreg(-val, 0, 12)) { + return 1; + } + if ((ct & TCG_CT_CONST_U12) && val >= 0 && val <= 0xfff) { + return 1; + } + return 0; +} From patchwork Mon Sep 20 08:04:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: WANG Xuerui X-Patchwork-Id: 12505453 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D5790C433FE for ; Mon, 20 Sep 2021 14:16:52 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7BFB461077 for ; Mon, 20 Sep 2021 14:16:52 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 7BFB461077 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=xen0n.name Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:39628 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mSK6F-0007MM-JA for qemu-devel@archiver.kernel.org; Mon, 20 Sep 2021 10:16:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49426) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mSEP3-0008B7-15 for qemu-devel@nongnu.org; Mon, 20 Sep 2021 04:11:53 -0400 Received: from [115.28.160.31] (port=35580 helo=mailbox.box.xen0n.name) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mSEOz-0005Md-Mk for qemu-devel@nongnu.org; Mon, 20 Sep 2021 04:11:52 -0400 Received: from ld50.lan (unknown [101.88.25.142]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by mailbox.box.xen0n.name (Postfix) with ESMTPSA id E3DE4633F8; Mon, 20 Sep 2021 16:05:26 +0800 (CST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=xen0n.name; s=mail; t=1632125126; bh=k4doJBiQClVLGSIZcy6JlQUdedkmWKu23BamxbIJRF4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=wn5BWgMdtATROvQGtkNmRnIUlwC/C2exXWhcNzBIfsFUZ8H9PGMxUCwQtET1qlFml vm8XeDVSaSzyUueHzZvKwZbgQu4YtczYFBX4YOs+bxx4A7Z8WSjY75mBgwhcqugSlk xAtRuzXaiDKlcXF0ptFJ4Z6D6Gjzq0MEqEI9fHPU= From: WANG Xuerui To: qemu-devel@nongnu.org Subject: [PATCH 07/30] tcg/loongarch: Implement necessary relocation operations Date: Mon, 20 Sep 2021 16:04:28 +0800 Message-Id: <20210920080451.408655-8-git@xen0n.name> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210920080451.408655-1-git@xen0n.name> References: <20210920080451.408655-1-git@xen0n.name> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.28.160.31 (failed) Received-SPF: pass client-ip=115.28.160.31; envelope-from=git@xen0n.name; helo=mailbox.box.xen0n.name X-Spam_score_int: 6 X-Spam_score: 0.6 X-Spam_bar: / X-Spam_report: (0.6 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 20 Sep 2021 09:57:24 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: WANG Xuerui Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: WANG Xuerui --- tcg/loongarch/tcg-target.c.inc | 84 ++++++++++++++++++++++++++++++++++ 1 file changed, 84 insertions(+) diff --git a/tcg/loongarch/tcg-target.c.inc b/tcg/loongarch/tcg-target.c.inc index 594b434b47..8be34f8275 100644 --- a/tcg/loongarch/tcg-target.c.inc +++ b/tcg/loongarch/tcg-target.c.inc @@ -164,3 +164,87 @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct) } return 0; } + +/* + * Relocations + */ + +/* + * Relocation records defined in LoongArch ELF psABI v1.00 is way too much + * complicated; a whopping stack machine is needed to stuff the fields, at + * the very least one SOP_PUSH and one SOP_POP (of the correct format) are + * needed. + * + * Hence, define our own simpler relocation types. Numbers are chosen as to + * not collide with potential future additions to the true ELF relocation + * type enum. + */ + +/* Field Sk16; suitable for conditional jumps */ +#define R_LOONGARCH_SK16 256 +/* Field Sd10k16; suitable for B and BL */ +#define R_LOONGARCH_SD10K16 257 + +static bool reloc_sk16(tcg_insn_unit *src_rw, const tcg_insn_unit *target) +{ + const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); + intptr_t offset = (intptr_t)target - (intptr_t)src_rx; + + tcg_debug_assert((offset & 2) == 0); + offset >>= 2; + if (offset == sextreg(offset, 0, 16)) { + *src_rw |= (offset << 10) & 0x3fffc00; + return true; + } + + return false; +} + +static bool reloc_sd10k16(tcg_insn_unit *src_rw, const tcg_insn_unit *target) +{ + const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); + intptr_t offset = (intptr_t)target - (intptr_t)src_rx; + + tcg_debug_assert((offset & 2) == 0); + offset >>= 2; + if (offset == sextreg(offset, 0, 26)) { + *src_rw |= (offset >> 16) & 0x3ff; /* slot d10 */ + *src_rw |= ((offset & 0xffff) << 10) & 0x3fffc00; /* slot k16 */ + return true; + } + + return false; +} + +static bool reloc_call(tcg_insn_unit *src_rw, const tcg_insn_unit *target) +{ + const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); + intptr_t offset = (intptr_t)target - (intptr_t)src_rx; + int32_t lo = sextreg(offset, 0, 12); + int32_t hi = offset - lo; + + tcg_debug_assert((offset & 2) == 0); + if (offset == hi + lo) { + hi >>= 12; + src_rw[0] |= (hi << 5) & 0x1ffffe0; /* pcaddu12i's Sj20 imm */ + lo >>= 2; + src_rw[1] |= (lo << 10) & 0x3fffc00; /* jirl's Sk16 imm */ + return true; + } + + return false; +} + +static bool patch_reloc(tcg_insn_unit *code_ptr, int type, + intptr_t value, intptr_t addend) +{ + tcg_debug_assert(addend == 0); + switch (type) { + case R_LOONGARCH_SK16: + return reloc_sk16(code_ptr, (tcg_insn_unit *)value); + case R_LOONGARCH_SD10K16: + return reloc_sd10k16(code_ptr, (tcg_insn_unit *)value); + default: + g_assert_not_reached(); + } +} From patchwork Mon Sep 20 08:04:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: WANG Xuerui X-Patchwork-Id: 12505429 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2B09DC4332F for ; Mon, 20 Sep 2021 14:13:07 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C0774610FB for ; Mon, 20 Sep 2021 14:13:06 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org C0774610FB Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=xen0n.name Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:59820 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mSK2b-0001wg-VY for qemu-devel@archiver.kernel.org; Mon, 20 Sep 2021 10:13:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49404) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mSEP1-000866-Ho for qemu-devel@nongnu.org; Mon, 20 Sep 2021 04:11:51 -0400 Received: from [115.28.160.31] (port=35578 helo=mailbox.box.xen0n.name) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mSEOz-0005Ma-Op for qemu-devel@nongnu.org; Mon, 20 Sep 2021 04:11:51 -0400 Received: from ld50.lan (unknown [101.88.25.142]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by mailbox.box.xen0n.name (Postfix) with ESMTPSA id 96D07633F9; Mon, 20 Sep 2021 16:05:29 +0800 (CST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=xen0n.name; s=mail; t=1632125129; bh=tQo2Jk9T916EHodWVi5R/SJp4gVXrLiLL0nctftLKPo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=miTGJ1Cxmp8Xd89hhNMwk6ZtfWeS+ee6CMF2kmJ2faCbtH3PKBO/utiDljOKpXnIs eL1fmgR4tifMOSVdrkdjwMdDgIZEIbd4ME0AnqjVFiGFSmF8Z3ViOmayiUzzvEDhrn mLFim1Hox7onEyh07x+VcyBbMpHahuLJx3dLMJfs= From: WANG Xuerui To: qemu-devel@nongnu.org Subject: [PATCH 08/30] tcg/loongarch: Implement the memory barrier op Date: Mon, 20 Sep 2021 16:04:29 +0800 Message-Id: <20210920080451.408655-9-git@xen0n.name> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210920080451.408655-1-git@xen0n.name> References: <20210920080451.408655-1-git@xen0n.name> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.28.160.31 (failed) Received-SPF: pass client-ip=115.28.160.31; envelope-from=git@xen0n.name; helo=mailbox.box.xen0n.name X-Spam_score_int: 6 X-Spam_score: 0.6 X-Spam_bar: / X-Spam_report: (0.6 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 20 Sep 2021 09:57:24 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: WANG Xuerui Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: WANG Xuerui --- tcg/loongarch/tcg-target.c.inc | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/tcg/loongarch/tcg-target.c.inc b/tcg/loongarch/tcg-target.c.inc index 8be34f8275..71564e3246 100644 --- a/tcg/loongarch/tcg-target.c.inc +++ b/tcg/loongarch/tcg-target.c.inc @@ -248,3 +248,35 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type, g_assert_not_reached(); } } + +#include "tcg-insn-defs.c.inc" + +/* + * TCG intrinsics + */ + +static void tcg_out_mb(TCGContext *s, TCGArg a0) +{ + /* Baseline LoongArch only has the full barrier, unfortunately. */ + tcg_out_opc_dbar(s, 0); +} + +/* + * Entry-points + */ + +static void tcg_out_op(TCGContext *s, TCGOpcode opc, + const TCGArg args[TCG_MAX_OP_ARGS], + const int const_args[TCG_MAX_OP_ARGS]) +{ + TCGArg a0 = args[0]; + + switch (opc) { + case INDEX_op_mb: + tcg_out_mb(s, a0); + break; + + default: + g_assert_not_reached(); + } +} From patchwork Mon Sep 20 08:04:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: WANG Xuerui X-Patchwork-Id: 12505481 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id ACF3AC433EF for ; Mon, 20 Sep 2021 14:22:53 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4BD2460F5D for ; Mon, 20 Sep 2021 14:22:53 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 4BD2460F5D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=xen0n.name Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:47048 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mSKC4-00048z-9y for qemu-devel@archiver.kernel.org; Mon, 20 Sep 2021 10:22:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49460) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mSEP4-0008Hg-U1 for qemu-devel@nongnu.org; Mon, 20 Sep 2021 04:11:54 -0400 Received: from [115.28.160.31] (port=35584 helo=mailbox.box.xen0n.name) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mSEP3-0005Pn-2Y for qemu-devel@nongnu.org; Mon, 20 Sep 2021 04:11:54 -0400 Received: from ld50.lan (unknown [101.88.25.142]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by mailbox.box.xen0n.name (Postfix) with ESMTPSA id 725E3633FA; Mon, 20 Sep 2021 16:05:32 +0800 (CST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=xen0n.name; s=mail; t=1632125132; bh=0JvSb40nJ2+yUg7sI7nualzuPAioCQD9X0JAhkQvCT0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=c/zftdv7vD9S5wbnLJquu5/KwouxquqvKjoSL7zbxgRTZ1AU9uItKlyu/3wbIAX5B cim0O/yjLgWoiTF1pxHGKlmN4oRakDnezUukRdi7ySzQGp+kjg+PNn6ZEaKm2xsU4D /YfjbKBB9BZV4G8AhL1JfW63xGcL7DyJ9mrkD6iM= From: WANG Xuerui To: qemu-devel@nongnu.org Subject: [PATCH 09/30] tcg/loongarch: Implement tcg_out_mov and tcg_out_movi Date: Mon, 20 Sep 2021 16:04:30 +0800 Message-Id: <20210920080451.408655-10-git@xen0n.name> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210920080451.408655-1-git@xen0n.name> References: <20210920080451.408655-1-git@xen0n.name> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.28.160.31 (failed) Received-SPF: pass client-ip=115.28.160.31; envelope-from=git@xen0n.name; helo=mailbox.box.xen0n.name X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 20 Sep 2021 09:57:24 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: WANG Xuerui Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: WANG Xuerui --- tcg/loongarch/tcg-target.c.inc | 73 ++++++++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/tcg/loongarch/tcg-target.c.inc b/tcg/loongarch/tcg-target.c.inc index 71564e3246..60783d7ddc 100644 --- a/tcg/loongarch/tcg-target.c.inc +++ b/tcg/loongarch/tcg-target.c.inc @@ -261,6 +261,77 @@ static void tcg_out_mb(TCGContext *s, TCGArg a0) tcg_out_opc_dbar(s, 0); } +static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) +{ + if (ret == arg) { + return true; + } + switch (type) { + case TCG_TYPE_I32: + case TCG_TYPE_I64: + /* + * Conventional register-register move used in LoongArch is + * `or dst, src, zero`. + */ + tcg_out_opc_or(s, ret, arg, TCG_REG_ZERO); + break; + default: + g_assert_not_reached(); + } + return true; +} + +static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd, + tcg_target_long val) +{ + tcg_target_long low, upper, higher, top; + + if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) { + val = (int32_t)val; + } + + /* Single-instruction cases. */ + low = sextreg(val, 0, 12); + if (low == val) { + /* val fits in simm12: addi.w rd, zero, val */ + tcg_out_opc_addi_w(s, rd, TCG_REG_ZERO, val); + return; + } + if (0x800 <= val && val <= 0xfff) { + /* val fits in uimm12: ori rd, zero, val */ + tcg_out_opc_ori(s, rd, TCG_REG_ZERO, val); + return; + } + + /* Chop upper bits into 3 immediate-field-sized segments respectively. */ + upper = (val >> 12) & 0xfffff; + higher = (val >> 32) & 0xfffff; + top = val >> 52; + + tcg_out_opc_lu12i_w(s, rd, upper); + if (low != 0) { + tcg_out_opc_ori(s, rd, rd, low); + } + + if (sextreg(val, 0, 32) == val) { + /* + * Fits in 32-bits, upper bits are already properly sign-extended by + * lu12i.w. + */ + return; + } + tcg_out_opc_cu32i_d(s, rd, higher); + + if (sextreg(val, 0, 52) == val) { + /* + * Fits in 52-bits, upper bits are already properly sign-extended by + * cu32i.d. + */ + return; + } + tcg_out_opc_cu52i_d(s, rd, rd, top); +} + /* * Entry-points */ @@ -276,6 +347,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_mb(s, a0); break; + case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ + case INDEX_op_mov_i64: default: g_assert_not_reached(); } From patchwork Mon Sep 20 08:04:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: WANG Xuerui X-Patchwork-Id: 12505451 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7C73BC433F5 for ; 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Mon, 20 Sep 2021 04:11:52 -0400 Received: from ld50.lan (unknown [101.88.25.142]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by mailbox.box.xen0n.name (Postfix) with ESMTPSA id 14928633FB; Mon, 20 Sep 2021 16:05:36 +0800 (CST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=xen0n.name; s=mail; t=1632125136; bh=SowlM2FwLXG6VZdngQBEwULtzZ+Rf9X4PscNFTSk3Ns=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=j43znKRGbq7C16T/kDknW7wZk6/NwFWz/fSrX/Hji2Ux4iFHZe4B68FhwyDBFrjfY 9zztjS9B+oWk95b4ugGRWZEnAGCbytHHNuAj5mzkz/8oY5RBHAzAL3CEyKoCbQFVgC 9t/Oa9QXUWM/3jcVw0e7szoubMeYWwUe/alG6VQw= From: WANG Xuerui To: qemu-devel@nongnu.org Subject: [PATCH 10/30] tcg/loongarch: Implement goto_ptr Date: Mon, 20 Sep 2021 16:04:31 +0800 Message-Id: <20210920080451.408655-11-git@xen0n.name> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210920080451.408655-1-git@xen0n.name> References: <20210920080451.408655-1-git@xen0n.name> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.28.160.31 (failed) Received-SPF: pass client-ip=115.28.160.31; envelope-from=git@xen0n.name; helo=mailbox.box.xen0n.name X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 20 Sep 2021 09:57:24 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: WANG Xuerui Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: WANG Xuerui Reviewed-by: Richard Henderson --- tcg/loongarch/tcg-target-con-set.h | 17 +++++++++++++++++ tcg/loongarch/tcg-target.c.inc | 15 +++++++++++++++ 2 files changed, 32 insertions(+) create mode 100644 tcg/loongarch/tcg-target-con-set.h diff --git a/tcg/loongarch/tcg-target-con-set.h b/tcg/loongarch/tcg-target-con-set.h new file mode 100644 index 0000000000..5cc4407367 --- /dev/null +++ b/tcg/loongarch/tcg-target-con-set.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Define LoongArch target-specific constraint sets. + * + * Copyright (c) 2021 WANG Xuerui + * + * Based on tcg/riscv/tcg-target-con-set.h + * + * Copyright (c) 2021 Linaro + */ + +/* + * C_On_Im(...) defines a constraint set with outputs and inputs. + * Each operand should be a sequence of constraint letters as defined by + * tcg-target-con-str.h; the constraint combination is inclusive or. + */ +C_O0_I1(r) diff --git a/tcg/loongarch/tcg-target.c.inc b/tcg/loongarch/tcg-target.c.inc index 60783d7ddc..9d78146fb9 100644 --- a/tcg/loongarch/tcg-target.c.inc +++ b/tcg/loongarch/tcg-target.c.inc @@ -347,9 +347,24 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_mb(s, a0); break; + case INDEX_op_goto_ptr: + tcg_out_opc_jirl(s, TCG_REG_ZERO, a0, 0); + break; + case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: default: g_assert_not_reached(); } } + +static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) +{ + switch (op) { + case INDEX_op_goto_ptr: + return C_O0_I1(r); + + default: + g_assert_not_reached(); + } +} From patchwork Mon Sep 20 08:04:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: WANG Xuerui X-Patchwork-Id: 12505397 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DA8E9C433FE for ; Mon, 20 Sep 2021 13:59:41 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 894B9610A8 for ; Mon, 20 Sep 2021 13:59:41 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 894B9610A8 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=xen0n.name Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:53904 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mSJpc-0004KY-Nm for qemu-devel@archiver.kernel.org; Mon, 20 Sep 2021 09:59:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49528) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mSEP7-0008QD-6Q for qemu-devel@nongnu.org; Mon, 20 Sep 2021 04:11:57 -0400 Received: from [115.28.160.31] (port=35590 helo=mailbox.box.xen0n.name) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mSEP3-0005QW-QU for qemu-devel@nongnu.org; Mon, 20 Sep 2021 04:11:56 -0400 Received: from ld50.lan (unknown [101.88.25.142]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by mailbox.box.xen0n.name (Postfix) with ESMTPSA id 8C91F633FC; Mon, 20 Sep 2021 16:05:38 +0800 (CST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=xen0n.name; s=mail; t=1632125138; bh=308pSI3noletgNm4kWAuskzQYp1vSo1DvVeQb5SpkHs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=H6wi2xcvIAhKq+qehl1qcQ9xIe4L231UFoCm62X5L3807qh//O9aXU/UftdW+8j31 rI4pwYRu3EoIFv0gZa3mansztSk5R1oirCpP3SFJ5JIulecLC0ApbXoD5K+KkIo4T/ pDFRlSrz3nH3VtlG650cx8+NzQhe1mBEa/17iVsM= From: WANG Xuerui To: qemu-devel@nongnu.org Subject: [PATCH 11/30] tcg/loongarch: Implement sign-/zero-extension ops Date: Mon, 20 Sep 2021 16:04:32 +0800 Message-Id: <20210920080451.408655-12-git@xen0n.name> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210920080451.408655-1-git@xen0n.name> References: <20210920080451.408655-1-git@xen0n.name> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.28.160.31 (failed) Received-SPF: pass client-ip=115.28.160.31; envelope-from=git@xen0n.name; helo=mailbox.box.xen0n.name X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 20 Sep 2021 09:57:24 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: WANG Xuerui Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: WANG Xuerui Reviewed-by: Richard Henderson --- tcg/loongarch/tcg-target-con-set.h | 1 + tcg/loongarch/tcg-target.c.inc | 82 ++++++++++++++++++++++++++++++ 2 files changed, 83 insertions(+) diff --git a/tcg/loongarch/tcg-target-con-set.h b/tcg/loongarch/tcg-target-con-set.h index 5cc4407367..7e459490ea 100644 --- a/tcg/loongarch/tcg-target-con-set.h +++ b/tcg/loongarch/tcg-target-con-set.h @@ -15,3 +15,4 @@ * tcg-target-con-str.h; the constraint combination is inclusive or. */ C_O0_I1(r) +C_O1_I1(r, r) diff --git a/tcg/loongarch/tcg-target.c.inc b/tcg/loongarch/tcg-target.c.inc index 9d78146fb9..0ee389fdaa 100644 --- a/tcg/loongarch/tcg-target.c.inc +++ b/tcg/loongarch/tcg-target.c.inc @@ -332,6 +332,36 @@ static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd, tcg_out_opc_cu52i_d(s, rd, rd, top); } +static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg) +{ + tcg_out_opc_andi(s, ret, arg, 0xff); +} + +static void tcg_out_ext16u(TCGContext *s, TCGReg ret, TCGReg arg) +{ + tcg_out_opc_bstrpick_w(s, ret, arg, 0, 15); +} + +static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) +{ + tcg_out_opc_bstrpick_d(s, ret, arg, 0, 31); +} + +static void tcg_out_ext8s(TCGContext *s, TCGReg ret, TCGReg arg) +{ + tcg_out_opc_sext_b(s, ret, arg); +} + +static void tcg_out_ext16s(TCGContext *s, TCGReg ret, TCGReg arg) +{ + tcg_out_opc_sext_h(s, ret, arg); +} + +static void tcg_out_ext32s(TCGContext *s, TCGReg ret, TCGReg arg) +{ + tcg_out_opc_addi_w(s, ret, arg, 0); +} + /* * Entry-points */ @@ -341,6 +371,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const int const_args[TCG_MAX_OP_ARGS]) { TCGArg a0 = args[0]; + TCGArg a1 = args[1]; switch (opc) { case INDEX_op_mb: @@ -351,6 +382,41 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_opc_jirl(s, TCG_REG_ZERO, a0, 0); break; + case INDEX_op_ext8s_i32: + case INDEX_op_ext8s_i64: + tcg_out_ext8s(s, a0, a1); + break; + + case INDEX_op_ext8u_i32: + case INDEX_op_ext8u_i64: + tcg_out_ext8u(s, a0, a1); + break; + + case INDEX_op_ext16s_i32: + case INDEX_op_ext16s_i64: + tcg_out_ext16s(s, a0, a1); + break; + + case INDEX_op_ext16u_i32: + case INDEX_op_ext16u_i64: + tcg_out_ext16u(s, a0, a1); + break; + + case INDEX_op_ext32u_i64: + case INDEX_op_extu_i32_i64: + tcg_out_ext32u(s, a0, a1); + break; + + case INDEX_op_ext32s_i64: + case INDEX_op_extrl_i64_i32: + case INDEX_op_ext_i32_i64: + tcg_out_ext32s(s, a0, a1); + break; + + case INDEX_op_extrh_i64_i32: + tcg_out_opc_srai_d(s, a0, a1, 32); + break; + case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: default: @@ -364,6 +430,22 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_goto_ptr: return C_O0_I1(r); + case INDEX_op_ext8s_i32: + case INDEX_op_ext8s_i64: + case INDEX_op_ext8u_i32: + case INDEX_op_ext8u_i64: + case INDEX_op_ext16s_i32: + case INDEX_op_ext16s_i64: + case INDEX_op_ext16u_i32: + case INDEX_op_ext16u_i64: + case INDEX_op_ext32s_i64: + case INDEX_op_ext32u_i64: + case INDEX_op_extu_i32_i64: + case INDEX_op_extrl_i64_i32: + case INDEX_op_extrh_i64_i32: + case INDEX_op_ext_i32_i64: + return C_O1_I1(r, r); + default: g_assert_not_reached(); } From patchwork Mon Sep 20 08:04:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: WANG Xuerui X-Patchwork-Id: 12505449 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C29C0C433EF for ; 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Mon, 20 Sep 2021 04:11:42 -0400 Received: from ld50.lan (unknown [101.88.25.142]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by mailbox.box.xen0n.name (Postfix) with ESMTPSA id BDA55633FD; Mon, 20 Sep 2021 16:05:41 +0800 (CST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=xen0n.name; s=mail; t=1632125141; bh=ni7MWMxkDe5yTRg++aAg75SiilVWWQXzPUrFKLp2tbQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=wOd+LZZJ34HcZ0pKP3xSi3v/QIwlj7RR2LRvOZPJqCADE/IpnVillW0HVdtcuBvSN audbo2qA2s8ffHB6gyvpKUxU/UCqR/blG3+eDeG6sqVne/TXmorP7tsR3gWl5heNeo Lxu7SBE3RumNgaK3ZMseJNo/MknYDFsJZFTDhInY= From: WANG Xuerui To: qemu-devel@nongnu.org Subject: [PATCH 12/30] tcg/loongarch: Implement not/and/or/xor/nor/andc/orc ops Date: Mon, 20 Sep 2021 16:04:33 +0800 Message-Id: <20210920080451.408655-13-git@xen0n.name> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210920080451.408655-1-git@xen0n.name> References: <20210920080451.408655-1-git@xen0n.name> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.28.160.31 (failed) Received-SPF: pass client-ip=115.28.160.31; envelope-from=git@xen0n.name; helo=mailbox.box.xen0n.name X-Spam_score_int: 6 X-Spam_score: 0.6 X-Spam_bar: / X-Spam_report: (0.6 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 20 Sep 2021 09:57:24 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: WANG Xuerui Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: WANG Xuerui Reviewed-by: Richard Henderson --- tcg/loongarch/tcg-target-con-set.h | 2 + tcg/loongarch/tcg-target.c.inc | 69 ++++++++++++++++++++++++++++++ 2 files changed, 71 insertions(+) diff --git a/tcg/loongarch/tcg-target-con-set.h b/tcg/loongarch/tcg-target-con-set.h index 7e459490ea..385f503552 100644 --- a/tcg/loongarch/tcg-target-con-set.h +++ b/tcg/loongarch/tcg-target-con-set.h @@ -16,3 +16,5 @@ */ C_O0_I1(r) C_O1_I1(r, r) +C_O1_I2(r, r, r) +C_O1_I2(r, r, rU) diff --git a/tcg/loongarch/tcg-target.c.inc b/tcg/loongarch/tcg-target.c.inc index 0ee389fdaa..e364b6c1da 100644 --- a/tcg/loongarch/tcg-target.c.inc +++ b/tcg/loongarch/tcg-target.c.inc @@ -372,6 +372,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, { TCGArg a0 = args[0]; TCGArg a1 = args[1]; + TCGArg a2 = args[2]; + int c2 = const_args[2]; switch (opc) { case INDEX_op_mb: @@ -417,6 +419,53 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_opc_srai_d(s, a0, a1, 32); break; + case INDEX_op_not_i32: + case INDEX_op_not_i64: + tcg_out_opc_nor(s, a0, a1, TCG_REG_ZERO); + break; + + case INDEX_op_nor_i32: + case INDEX_op_nor_i64: + tcg_out_opc_nor(s, a0, a1, a2); + break; + + case INDEX_op_andc_i32: + case INDEX_op_andc_i64: + tcg_out_opc_andn(s, a0, a1, a2); + break; + + case INDEX_op_orc_i32: + case INDEX_op_orc_i64: + tcg_out_opc_orn(s, a0, a1, a2); + break; + + case INDEX_op_and_i32: + case INDEX_op_and_i64: + if (c2) { + tcg_out_opc_andi(s, a0, a1, a2); + } else { + tcg_out_opc_and(s, a0, a1, a2); + } + break; + + case INDEX_op_or_i32: + case INDEX_op_or_i64: + if (c2) { + tcg_out_opc_ori(s, a0, a1, a2); + } else { + tcg_out_opc_or(s, a0, a1, a2); + } + break; + + case INDEX_op_xor_i32: + case INDEX_op_xor_i64: + if (c2) { + tcg_out_opc_xori(s, a0, a1, a2); + } else { + tcg_out_opc_xor(s, a0, a1, a2); + } + break; + case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: default: @@ -444,8 +493,28 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_extrl_i64_i32: case INDEX_op_extrh_i64_i32: case INDEX_op_ext_i32_i64: + case INDEX_op_not_i32: + case INDEX_op_not_i64: return C_O1_I1(r, r); + case INDEX_op_nor_i32: + case INDEX_op_andc_i32: + case INDEX_op_orc_i32: + case INDEX_op_nor_i64: + case INDEX_op_andc_i64: + case INDEX_op_orc_i64: + /* LoongArch insns for these ops don't have reg-imm forms */ + return C_O1_I2(r, r, r); + + case INDEX_op_and_i32: + case INDEX_op_or_i32: + case INDEX_op_xor_i32: + case INDEX_op_and_i64: + case INDEX_op_or_i64: + case INDEX_op_xor_i64: + /* LoongArch reg-imm bitops have their imms ZERO-extended */ + return C_O1_I2(r, r, rU); + default: g_assert_not_reached(); } From patchwork Mon Sep 20 08:04:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: WANG Xuerui X-Patchwork-Id: 12505393 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D760DC433F5 for ; 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Mon, 20 Sep 2021 04:11:35 -0400 Received: from ld50.lan (unknown [101.88.25.142]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by mailbox.box.xen0n.name (Postfix) with ESMTPSA id C3E5A633FE; Mon, 20 Sep 2021 16:05:44 +0800 (CST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=xen0n.name; s=mail; t=1632125144; bh=Zp5S2fmrEC8THDT2k9t1RfS5KYvOE8cn8vkKyGNeX74=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=meiZ+DmDVROYLSxO3Wax9Z1tiTLkSPw161LFFhfWhn5DlIi46cAIKgUsnfYeAwNKG uKe1czvDcHTgA1tJb2zjcCw6Iy/ya+wmbPYJhU0NWo2RID8jfJPzWoNRh0n2WcgT3u T6OyzjgWzG7ZdbxDs/21OQzK6riZ//+apQ7i93i4= From: WANG Xuerui To: qemu-devel@nongnu.org Subject: [PATCH 13/30] tcg/loongarch: Implement deposit/extract ops Date: Mon, 20 Sep 2021 16:04:34 +0800 Message-Id: <20210920080451.408655-14-git@xen0n.name> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210920080451.408655-1-git@xen0n.name> References: <20210920080451.408655-1-git@xen0n.name> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.28.160.31 (failed) Received-SPF: pass client-ip=115.28.160.31; envelope-from=git@xen0n.name; helo=mailbox.box.xen0n.name X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 20 Sep 2021 09:57:24 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: WANG Xuerui Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: WANG Xuerui Reviewed-by: Richard Henderson --- tcg/loongarch/tcg-target-con-set.h | 1 + tcg/loongarch/tcg-target.c.inc | 21 +++++++++++++++++++++ 2 files changed, 22 insertions(+) diff --git a/tcg/loongarch/tcg-target-con-set.h b/tcg/loongarch/tcg-target-con-set.h index 385f503552..b0751c4bb0 100644 --- a/tcg/loongarch/tcg-target-con-set.h +++ b/tcg/loongarch/tcg-target-con-set.h @@ -18,3 +18,4 @@ C_O0_I1(r) C_O1_I1(r, r) C_O1_I2(r, r, r) C_O1_I2(r, r, rU) +C_O1_I2(r, 0, rZ) diff --git a/tcg/loongarch/tcg-target.c.inc b/tcg/loongarch/tcg-target.c.inc index e364b6c1da..e5356bdaf8 100644 --- a/tcg/loongarch/tcg-target.c.inc +++ b/tcg/loongarch/tcg-target.c.inc @@ -466,6 +466,20 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, } break; + case INDEX_op_extract_i32: + tcg_out_opc_bstrpick_w(s, a0, a1, a2, a2 + args[3] - 1); + break; + case INDEX_op_extract_i64: + tcg_out_opc_bstrpick_d(s, a0, a1, a2, a2 + args[3] - 1); + break; + + case INDEX_op_deposit_i32: + tcg_out_opc_bstrins_w(s, a0, a2, args[3], args[3] + args[4] - 1); + break; + case INDEX_op_deposit_i64: + tcg_out_opc_bstrins_d(s, a0, a2, args[3], args[3] + args[4] - 1); + break; + case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: default: @@ -495,6 +509,8 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_ext_i32_i64: case INDEX_op_not_i32: case INDEX_op_not_i64: + case INDEX_op_extract_i32: + case INDEX_op_extract_i64: return C_O1_I1(r, r); case INDEX_op_nor_i32: @@ -515,6 +531,11 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) /* LoongArch reg-imm bitops have their imms ZERO-extended */ return C_O1_I2(r, r, rU); + case INDEX_op_deposit_i32: + case INDEX_op_deposit_i64: + /* Must deposit into the same register as input */ + return C_O1_I2(r, 0, rZ); + default: g_assert_not_reached(); } From patchwork Mon Sep 20 08:04:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: WANG Xuerui X-Patchwork-Id: 12505421 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 15CE6C433F5 for ; Mon, 20 Sep 2021 14:09:59 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D1617610CE for ; Mon, 20 Sep 2021 14:09:58 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org D1617610CE Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=xen0n.name Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:51234 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mSJza-0004bS-0r for qemu-devel@archiver.kernel.org; Mon, 20 Sep 2021 10:09:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49406) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mSEP1-000867-Hp for qemu-devel@nongnu.org; Mon, 20 Sep 2021 04:11:51 -0400 Received: from [115.28.160.31] (port=35582 helo=mailbox.box.xen0n.name) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mSEOz-0005Mh-O1 for qemu-devel@nongnu.org; Mon, 20 Sep 2021 04:11:51 -0400 Received: from ld50.lan (unknown [101.88.25.142]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by mailbox.box.xen0n.name (Postfix) with ESMTPSA id 222F0633FF; Mon, 20 Sep 2021 16:05:47 +0800 (CST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=xen0n.name; s=mail; t=1632125147; bh=4RTeXJDumW5t51oaUN2uPmpSnltUKOsvZZ4fyZPmnbA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fRd6hsp18eEhPyYdCO+aIdMurV3p463eqhY5B4K7PAMY+z7fPEGICHIkZXuZz64vV oF3aI9nYBO7cEPzOjq/IrjjFqq0X/nsxCufsAopYeyfNxD9RkxiqaXunu724sJn1gW J1qHfVaZRsD4i4jEdsDzsndDCXYtKzD4LcYTr7Vs= From: WANG Xuerui To: qemu-devel@nongnu.org Subject: [PATCH 14/30] tcg/loongarch: Implement bswap32_i32/bswap64_i64 Date: Mon, 20 Sep 2021 16:04:35 +0800 Message-Id: <20210920080451.408655-15-git@xen0n.name> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210920080451.408655-1-git@xen0n.name> References: <20210920080451.408655-1-git@xen0n.name> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.28.160.31 (failed) Received-SPF: pass client-ip=115.28.160.31; envelope-from=git@xen0n.name; helo=mailbox.box.xen0n.name X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 20 Sep 2021 09:57:24 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: WANG Xuerui Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: WANG Xuerui --- tcg/loongarch/tcg-target.c.inc | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/tcg/loongarch/tcg-target.c.inc b/tcg/loongarch/tcg-target.c.inc index e5356bdaf8..d617b833e5 100644 --- a/tcg/loongarch/tcg-target.c.inc +++ b/tcg/loongarch/tcg-target.c.inc @@ -480,6 +480,14 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_opc_bstrins_d(s, a0, a2, args[3], args[3] + args[4] - 1); break; + case INDEX_op_bswap32_i32: + tcg_out_opc_revb_2h(s, a0, a1); + tcg_out_opc_rotri_w(s, a0, a0, 16); + break; + case INDEX_op_bswap64_i64: + tcg_out_opc_revb_d(s, a0, a1); + break; + case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: default: @@ -511,6 +519,8 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_not_i64: case INDEX_op_extract_i32: case INDEX_op_extract_i64: + case INDEX_op_bswap32_i32: + case INDEX_op_bswap64_i64: return C_O1_I1(r, r); case INDEX_op_nor_i32: From patchwork Mon Sep 20 08:04:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: WANG Xuerui X-Patchwork-Id: 12505419 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 99614C433FE for ; Mon, 20 Sep 2021 14:09:58 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 61E9F610CE for ; Mon, 20 Sep 2021 14:09:58 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 61E9F610CE Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=xen0n.name Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:51186 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mSJzZ-0004ZT-Cg for qemu-devel@archiver.kernel.org; Mon, 20 Sep 2021 10:09:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49284) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mSEOn-0007he-7b for qemu-devel@nongnu.org; Mon, 20 Sep 2021 04:11:37 -0400 Received: from [115.28.160.31] (port=35554 helo=mailbox.box.xen0n.name) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mSEOj-0005Df-49 for qemu-devel@nongnu.org; Mon, 20 Sep 2021 04:11:37 -0400 Received: from ld50.lan (unknown [101.88.25.142]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by mailbox.box.xen0n.name (Postfix) with ESMTPSA id 3E33F63400; Mon, 20 Sep 2021 16:05:50 +0800 (CST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=xen0n.name; s=mail; t=1632125150; bh=CNbYzy9iyb7PL6X4R0+qyf9GBLd1LhfpCtVtZ5W5r4s=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cU/fiHayVN7GSYDjEURZB/xv0YGuvNFy1jnQizoma4Gv19yi1nsnfSrEjon+QVQML k7sUeR0aiMa02mQE3+3R3pPcuB2dMh3IpVQlJ8bYtYhBQN7qRhNFvfV5E0HSMjBiw0 mh2TWhPOkyFm/YnjEZ1LivSU0PTuY0EWg97Y04aY= From: WANG Xuerui To: qemu-devel@nongnu.org Subject: [PATCH 15/30] tcg/loongarch: Implement clz/ctz ops Date: Mon, 20 Sep 2021 16:04:36 +0800 Message-Id: <20210920080451.408655-16-git@xen0n.name> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210920080451.408655-1-git@xen0n.name> References: <20210920080451.408655-1-git@xen0n.name> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.28.160.31 (failed) Received-SPF: pass client-ip=115.28.160.31; envelope-from=git@xen0n.name; helo=mailbox.box.xen0n.name X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 20 Sep 2021 09:57:24 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: WANG Xuerui Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: WANG Xuerui Reviewed-by: Richard Henderson --- tcg/loongarch/tcg-target-con-set.h | 1 + tcg/loongarch/tcg-target.c.inc | 31 ++++++++++++++++++++++++++++++ 2 files changed, 32 insertions(+) diff --git a/tcg/loongarch/tcg-target-con-set.h b/tcg/loongarch/tcg-target-con-set.h index b0751c4bb0..417c97549a 100644 --- a/tcg/loongarch/tcg-target-con-set.h +++ b/tcg/loongarch/tcg-target-con-set.h @@ -18,4 +18,5 @@ C_O0_I1(r) C_O1_I1(r, r) C_O1_I2(r, r, r) C_O1_I2(r, r, rU) +C_O1_I2(r, r, rZ) C_O1_I2(r, 0, rZ) diff --git a/tcg/loongarch/tcg-target.c.inc b/tcg/loongarch/tcg-target.c.inc index d617b833e5..e817964a7e 100644 --- a/tcg/loongarch/tcg-target.c.inc +++ b/tcg/loongarch/tcg-target.c.inc @@ -362,6 +362,17 @@ static void tcg_out_ext32s(TCGContext *s, TCGReg ret, TCGReg arg) tcg_out_opc_addi_w(s, ret, arg, 0); } +static void tcg_out_clzctz(TCGContext *s, LoongArchInsn opc, + TCGReg a0, TCGReg a1, TCGReg a2) +{ + /* all clz/ctz insns belong to DJ-format */ + tcg_out32(s, encode_dj_insn(opc, TCG_REG_TMP0, a1)); + /* a0 = a1 ? REG_TMP0 : a2 */ + tcg_out_opc_maskeqz(s, TCG_REG_TMP0, TCG_REG_TMP0, a1); + tcg_out_opc_masknez(s, a0, a2, a1); + tcg_out_opc_or(s, a0, TCG_REG_TMP0, a0); +} + /* * Entry-points */ @@ -488,6 +499,20 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_opc_revb_d(s, a0, a1); break; + case INDEX_op_clz_i32: + tcg_out_clzctz(s, OPC_CLZ_W, a0, a1, a2); + break; + case INDEX_op_clz_i64: + tcg_out_clzctz(s, OPC_CLZ_D, a0, a1, a2); + break; + + case INDEX_op_ctz_i32: + tcg_out_clzctz(s, OPC_CTZ_W, a0, a1, a2); + break; + case INDEX_op_ctz_i64: + tcg_out_clzctz(s, OPC_CTZ_D, a0, a1, a2); + break; + case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: default: @@ -541,6 +566,12 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) /* LoongArch reg-imm bitops have their imms ZERO-extended */ return C_O1_I2(r, r, rU); + case INDEX_op_clz_i32: + case INDEX_op_clz_i64: + case INDEX_op_ctz_i32: + case INDEX_op_ctz_i64: + return C_O1_I2(r, r, rZ); + case INDEX_op_deposit_i32: case INDEX_op_deposit_i64: /* Must deposit into the same register as input */ From patchwork Mon Sep 20 08:04:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: WANG Xuerui X-Patchwork-Id: 12505411 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 57B1FC433EF for ; Mon, 20 Sep 2021 14:07:33 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1E3626109E for ; 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Mon, 20 Sep 2021 16:05:52 +0800 (CST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=xen0n.name; s=mail; t=1632125152; bh=0QMTsi0TahJH4m+7t0jhPvrCiFBVkSLpJenID01b+DA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cwtaE8ne1Ipo5y8fOUZf/Aftf/0OMXQWbJcDmgvMiWq/jUNNCvn29EvlWv+h0OowA KEuVZ4rxeamJygAMoyzgnypcoJPnDXddTl4ay1DJmMti35F3VOXCCdnvu96z7QIjJ9 t/q8KuTArQHjuNDwu2cEuv4Svpk3iAN16X4sMnxE= From: WANG Xuerui To: qemu-devel@nongnu.org Subject: [PATCH 16/30] tcg/loongarch: Implement shl/shr/sar/rotl/rotr ops Date: Mon, 20 Sep 2021 16:04:37 +0800 Message-Id: <20210920080451.408655-17-git@xen0n.name> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210920080451.408655-1-git@xen0n.name> References: <20210920080451.408655-1-git@xen0n.name> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.28.160.31 (failed) Received-SPF: pass client-ip=115.28.160.31; envelope-from=git@xen0n.name; helo=mailbox.box.xen0n.name X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 20 Sep 2021 09:57:24 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: WANG Xuerui Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: WANG Xuerui --- tcg/loongarch/tcg-target-con-set.h | 1 + tcg/loongarch/tcg-target.c.inc | 91 ++++++++++++++++++++++++++++++ 2 files changed, 92 insertions(+) diff --git a/tcg/loongarch/tcg-target-con-set.h b/tcg/loongarch/tcg-target-con-set.h index 417c97549a..8630d1ee6e 100644 --- a/tcg/loongarch/tcg-target-con-set.h +++ b/tcg/loongarch/tcg-target-con-set.h @@ -17,6 +17,7 @@ C_O0_I1(r) C_O1_I1(r, r) C_O1_I2(r, r, r) +C_O1_I2(r, r, ri) C_O1_I2(r, r, rU) C_O1_I2(r, r, rZ) C_O1_I2(r, 0, rZ) diff --git a/tcg/loongarch/tcg-target.c.inc b/tcg/loongarch/tcg-target.c.inc index e817964a7e..acbd0e65ef 100644 --- a/tcg/loongarch/tcg-target.c.inc +++ b/tcg/loongarch/tcg-target.c.inc @@ -513,6 +513,85 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_clzctz(s, OPC_CTZ_D, a0, a1, a2); break; + case INDEX_op_shl_i32: + if (c2) { + tcg_out_opc_slli_w(s, a0, a1, a2 & 0x1f); + } else { + tcg_out_opc_sll_w(s, a0, a1, a2); + } + break; + case INDEX_op_shl_i64: + if (c2) { + tcg_out_opc_slli_d(s, a0, a1, a2 & 0x3f); + } else { + tcg_out_opc_sll_d(s, a0, a1, a2); + } + break; + + case INDEX_op_shr_i32: + if (c2) { + tcg_out_opc_srli_w(s, a0, a1, a2 & 0x1f); + } else { + tcg_out_opc_srl_w(s, a0, a1, a2); + } + break; + case INDEX_op_shr_i64: + if (c2) { + tcg_out_opc_srli_d(s, a0, a1, a2 & 0x3f); + } else { + tcg_out_opc_srl_d(s, a0, a1, a2); + } + break; + + case INDEX_op_sar_i32: + if (c2) { + tcg_out_opc_srai_w(s, a0, a1, a2 & 0x1f); + } else { + tcg_out_opc_sra_w(s, a0, a1, a2); + } + break; + case INDEX_op_sar_i64: + if (c2) { + tcg_out_opc_srai_d(s, a0, a1, a2 & 0x3f); + } else { + tcg_out_opc_sra_d(s, a0, a1, a2); + } + break; + + case INDEX_op_rotl_i32: + /* transform into equivalent rotr_i32 */ + if (c2) { + a2 = 32 - a2; + } else { + tcg_out_opc_sub_w(s, a2, TCG_REG_ZERO, a2); + tcg_out_opc_addi_w(s, a2, a2, 32); + } + /* fallthrough */ + case INDEX_op_rotr_i32: + if (c2) { + tcg_out_opc_rotri_w(s, a0, a1, a2 & 0x1f); + } else { + tcg_out_opc_rotr_w(s, a0, a1, a2); + } + break; + + case INDEX_op_rotl_i64: + /* transform into equivalent rotr_i64 */ + if (c2) { + a2 = 64 - a2; + } else { + tcg_out_opc_sub_w(s, a2, TCG_REG_ZERO, a2); + tcg_out_opc_addi_w(s, a2, a2, 64); + } + /* fallthrough */ + case INDEX_op_rotr_i64: + if (c2) { + tcg_out_opc_rotri_d(s, a0, a1, a2 & 0x3f); + } else { + tcg_out_opc_rotr_d(s, a0, a1, a2); + } + break; + case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: default: @@ -557,6 +636,18 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) /* LoongArch insns for these ops don't have reg-imm forms */ return C_O1_I2(r, r, r); + case INDEX_op_shl_i32: + case INDEX_op_shl_i64: + case INDEX_op_shr_i32: + case INDEX_op_shr_i64: + case INDEX_op_sar_i32: + case INDEX_op_sar_i64: + case INDEX_op_rotl_i32: + case INDEX_op_rotl_i64: + case INDEX_op_rotr_i32: + case INDEX_op_rotr_i64: + return C_O1_I2(r, r, ri); + case INDEX_op_and_i32: case INDEX_op_or_i32: case INDEX_op_xor_i32: From patchwork Mon Sep 20 08:04:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: WANG Xuerui X-Patchwork-Id: 12505391 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E2ADEC433EF for ; Mon, 20 Sep 2021 13:59:39 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7F322610A0 for ; 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Mon, 20 Sep 2021 16:05:55 +0800 (CST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=xen0n.name; s=mail; t=1632125155; bh=RzCAPeUwu1c6n1MA5068MRQwMrVm4D1AJAPgv08dO7U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Vp+fIZsagoF/3VRS609bM2u1G+6YAmZiZKWYOOiyuOnfx/KP/wBw/+sT6HKKyCbRL 7ltBZJv5sGUHti50oTkCf7SifEaaQodTgeOCJ3XbPwz9jbxDt4kZzHGX1T4GNkpiXU nSUV6j4FRaST1lZOQrCfnuAWQHHl2OLO0V+r2QqE= From: WANG Xuerui To: qemu-devel@nongnu.org Subject: [PATCH 17/30] tcg/loongarch: Implement neg/add/sub ops Date: Mon, 20 Sep 2021 16:04:38 +0800 Message-Id: <20210920080451.408655-18-git@xen0n.name> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210920080451.408655-1-git@xen0n.name> References: <20210920080451.408655-1-git@xen0n.name> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.28.160.31 (failed) Received-SPF: pass client-ip=115.28.160.31; envelope-from=git@xen0n.name; helo=mailbox.box.xen0n.name X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 20 Sep 2021 09:57:24 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: WANG Xuerui Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: WANG Xuerui Reviewed-by: Richard Henderson --- tcg/loongarch/tcg-target-con-set.h | 2 ++ tcg/loongarch/tcg-target.c.inc | 47 ++++++++++++++++++++++++++++++ 2 files changed, 49 insertions(+) diff --git a/tcg/loongarch/tcg-target-con-set.h b/tcg/loongarch/tcg-target-con-set.h index 8630d1ee6e..58b5c487e2 100644 --- a/tcg/loongarch/tcg-target-con-set.h +++ b/tcg/loongarch/tcg-target-con-set.h @@ -18,6 +18,8 @@ C_O0_I1(r) C_O1_I1(r, r) C_O1_I2(r, r, r) C_O1_I2(r, r, ri) +C_O1_I2(r, r, rI) C_O1_I2(r, r, rU) C_O1_I2(r, r, rZ) C_O1_I2(r, 0, rZ) +C_O1_I2(r, rZ, rN) diff --git a/tcg/loongarch/tcg-target.c.inc b/tcg/loongarch/tcg-target.c.inc index acbd0e65ef..e5518c0102 100644 --- a/tcg/loongarch/tcg-target.c.inc +++ b/tcg/loongarch/tcg-target.c.inc @@ -592,6 +592,43 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, } break; + case INDEX_op_neg_i32: + tcg_out_opc_sub_w(s, a0, TCG_REG_ZERO, a1); + break; + case INDEX_op_neg_i64: + tcg_out_opc_sub_d(s, a0, TCG_REG_ZERO, a1); + break; + + case INDEX_op_add_i32: + if (c2) { + tcg_out_opc_addi_w(s, a0, a1, a2); + } else { + tcg_out_opc_add_w(s, a0, a1, a2); + } + break; + case INDEX_op_add_i64: + if (c2) { + tcg_out_opc_addi_d(s, a0, a1, a2); + } else { + tcg_out_opc_add_d(s, a0, a1, a2); + } + break; + + case INDEX_op_sub_i32: + if (c2) { + tcg_out_opc_addi_w(s, a0, a1, -a2); + } else { + tcg_out_opc_sub_w(s, a0, a1, a2); + } + break; + case INDEX_op_sub_i64: + if (c2) { + tcg_out_opc_addi_d(s, a0, a1, -a2); + } else { + tcg_out_opc_sub_d(s, a0, a1, a2); + } + break; + case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: default: @@ -625,6 +662,8 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_extract_i64: case INDEX_op_bswap32_i32: case INDEX_op_bswap64_i64: + case INDEX_op_neg_i32: + case INDEX_op_neg_i64: return C_O1_I1(r, r); case INDEX_op_nor_i32: @@ -648,6 +687,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_rotr_i64: return C_O1_I2(r, r, ri); + case INDEX_op_add_i32: + case INDEX_op_add_i64: + return C_O1_I2(r, r, rI); + case INDEX_op_and_i32: case INDEX_op_or_i32: case INDEX_op_xor_i32: @@ -668,6 +711,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) /* Must deposit into the same register as input */ return C_O1_I2(r, 0, rZ); + case INDEX_op_sub_i32: + case INDEX_op_sub_i64: + return C_O1_I2(r, rZ, rN); + default: g_assert_not_reached(); } From patchwork Mon Sep 20 08:04:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: WANG Xuerui X-Patchwork-Id: 12505427 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4387FC433F5 for ; Mon, 20 Sep 2021 14:13:05 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id F372E610F9 for ; Mon, 20 Sep 2021 14:13:04 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org F372E610F9 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=xen0n.name Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:59710 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mSK2a-0001sM-6D for qemu-devel@archiver.kernel.org; Mon, 20 Sep 2021 10:13:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49312) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mSEOq-0007m1-QS for qemu-devel@nongnu.org; Mon, 20 Sep 2021 04:11:40 -0400 Received: from [115.28.160.31] (port=35570 helo=mailbox.box.xen0n.name) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mSEOo-0005LN-Rb for qemu-devel@nongnu.org; Mon, 20 Sep 2021 04:11:40 -0400 Received: from ld50.lan (unknown [101.88.25.142]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by mailbox.box.xen0n.name (Postfix) with ESMTPSA id 602D263403; Mon, 20 Sep 2021 16:05:58 +0800 (CST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=xen0n.name; s=mail; t=1632125158; bh=Bx5Igy9scfbtlcRjTjyLHOgkdmOVit9KGmrjkea4qGg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=T93BXRmMBr+2W50XK3D8xrisYmoeHVKbjeKea0jFwfdx/hFwCOQj8BiFkodjh4+Bk q2iwfHuSaDcULjplCb3XRc41Y7LECrjKvJkeR2ISoE3p4wWMEAvq72WFRTithAn0jR rlQV7D3J9nfIdv0xhlPgwufKnTq31dgBVDlpLOOg= From: WANG Xuerui To: qemu-devel@nongnu.org Subject: [PATCH 18/30] tcg/loongarch: Implement mul/mulsh/muluh/div/divu/rem/remu ops Date: Mon, 20 Sep 2021 16:04:39 +0800 Message-Id: <20210920080451.408655-19-git@xen0n.name> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210920080451.408655-1-git@xen0n.name> References: <20210920080451.408655-1-git@xen0n.name> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.28.160.31 (failed) Received-SPF: pass client-ip=115.28.160.31; envelope-from=git@xen0n.name; helo=mailbox.box.xen0n.name X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 20 Sep 2021 09:57:24 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: WANG Xuerui Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: WANG Xuerui Reviewed-by: Richard Henderson --- tcg/loongarch/tcg-target-con-set.h | 1 + tcg/loongarch/tcg-target.c.inc | 65 ++++++++++++++++++++++++++++++ 2 files changed, 66 insertions(+) diff --git a/tcg/loongarch/tcg-target-con-set.h b/tcg/loongarch/tcg-target-con-set.h index 58b5c487e2..57b2846d82 100644 --- a/tcg/loongarch/tcg-target-con-set.h +++ b/tcg/loongarch/tcg-target-con-set.h @@ -23,3 +23,4 @@ C_O1_I2(r, r, rU) C_O1_I2(r, r, rZ) C_O1_I2(r, 0, rZ) C_O1_I2(r, rZ, rN) +C_O1_I2(r, rZ, rZ) diff --git a/tcg/loongarch/tcg-target.c.inc b/tcg/loongarch/tcg-target.c.inc index e5518c0102..eaa155ad68 100644 --- a/tcg/loongarch/tcg-target.c.inc +++ b/tcg/loongarch/tcg-target.c.inc @@ -629,6 +629,55 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, } break; + case INDEX_op_mul_i32: + tcg_out_opc_mul_w(s, a0, a1, a2); + break; + case INDEX_op_mul_i64: + tcg_out_opc_mul_d(s, a0, a1, a2); + break; + + case INDEX_op_mulsh_i32: + tcg_out_opc_mulh_w(s, a0, a1, a2); + break; + case INDEX_op_mulsh_i64: + tcg_out_opc_mulh_d(s, a0, a1, a2); + break; + + case INDEX_op_muluh_i32: + tcg_out_opc_mulh_wu(s, a0, a1, a2); + break; + case INDEX_op_muluh_i64: + tcg_out_opc_mulh_du(s, a0, a1, a2); + break; + + case INDEX_op_div_i32: + tcg_out_opc_div_w(s, a0, a1, a2); + break; + case INDEX_op_div_i64: + tcg_out_opc_div_d(s, a0, a1, a2); + break; + + case INDEX_op_divu_i32: + tcg_out_opc_div_wu(s, a0, a1, a2); + break; + case INDEX_op_divu_i64: + tcg_out_opc_div_du(s, a0, a1, a2); + break; + + case INDEX_op_rem_i32: + tcg_out_opc_mod_w(s, a0, a1, a2); + break; + case INDEX_op_rem_i64: + tcg_out_opc_mod_d(s, a0, a1, a2); + break; + + case INDEX_op_remu_i32: + tcg_out_opc_mod_wu(s, a0, a1, a2); + break; + case INDEX_op_remu_i64: + tcg_out_opc_mod_du(s, a0, a1, a2); + break; + case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: default: @@ -715,6 +764,22 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_sub_i64: return C_O1_I2(r, rZ, rN); + case INDEX_op_mul_i32: + case INDEX_op_mul_i64: + case INDEX_op_mulsh_i32: + case INDEX_op_mulsh_i64: + case INDEX_op_muluh_i32: + case INDEX_op_muluh_i64: + case INDEX_op_div_i32: + case INDEX_op_div_i64: + case INDEX_op_divu_i32: + case INDEX_op_divu_i64: + case INDEX_op_rem_i32: + case INDEX_op_rem_i64: + case INDEX_op_remu_i32: + case INDEX_op_remu_i64: + return C_O1_I2(r, rZ, rZ); + default: g_assert_not_reached(); } From patchwork Mon Sep 20 08:04:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: WANG Xuerui X-Patchwork-Id: 12505401 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A24DCC433EF for ; Mon, 20 Sep 2021 14:03:09 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 633DA610A0 for ; Mon, 20 Sep 2021 14:03:09 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 633DA610A0 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=xen0n.name Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:34156 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mSJsy-0001ai-CW for qemu-devel@archiver.kernel.org; Mon, 20 Sep 2021 10:03:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49282) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mSEOn-0007hd-82 for qemu-devel@nongnu.org; Mon, 20 Sep 2021 04:11:37 -0400 Received: from [115.28.160.31] (port=35556 helo=mailbox.box.xen0n.name) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mSEOj-0005Dg-4B for qemu-devel@nongnu.org; Mon, 20 Sep 2021 04:11:36 -0400 Received: from ld50.lan (unknown [101.88.25.142]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by mailbox.box.xen0n.name (Postfix) with ESMTPSA id C932263404; Mon, 20 Sep 2021 16:06:00 +0800 (CST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=xen0n.name; s=mail; t=1632125160; bh=U/JY2ROj+DDqB84lxVVDTEUnyURoOCo5VKOMBJpWSNA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=bcjGrfjKXb3OwcyplM/shRit9UcCA96EYwTxJ67XPZ3WrVLE+IhSAVVHkQEXPJzL9 OdLBhar8FjW5latWHVfVkVhWB2cwggWyzTmafBzoUbcZYiD2FZDuv+7vOs+rsu7CLs ryizP+1LAulvoDzpjMfBwGiNXAT0M9cwMtxbCG5w= From: WANG Xuerui To: qemu-devel@nongnu.org Subject: [PATCH 19/30] tcg/loongarch: Implement br/brcond ops Date: Mon, 20 Sep 2021 16:04:40 +0800 Message-Id: <20210920080451.408655-20-git@xen0n.name> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210920080451.408655-1-git@xen0n.name> References: <20210920080451.408655-1-git@xen0n.name> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.28.160.31 (failed) Received-SPF: pass client-ip=115.28.160.31; envelope-from=git@xen0n.name; helo=mailbox.box.xen0n.name X-Spam_score_int: 6 X-Spam_score: 0.6 X-Spam_bar: / X-Spam_report: (0.6 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 20 Sep 2021 09:57:24 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: WANG Xuerui Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: WANG Xuerui Reviewed-by: Richard Henderson --- tcg/loongarch/tcg-target-con-set.h | 1 + tcg/loongarch/tcg-target.c.inc | 52 ++++++++++++++++++++++++++++++ 2 files changed, 53 insertions(+) diff --git a/tcg/loongarch/tcg-target-con-set.h b/tcg/loongarch/tcg-target-con-set.h index 57b2846d82..bcbf0780ff 100644 --- a/tcg/loongarch/tcg-target-con-set.h +++ b/tcg/loongarch/tcg-target-con-set.h @@ -15,6 +15,7 @@ * tcg-target-con-str.h; the constraint combination is inclusive or. */ C_O0_I1(r) +C_O0_I2(rZ, rZ) C_O1_I1(r, r) C_O1_I2(r, r, r) C_O1_I2(r, r, ri) diff --git a/tcg/loongarch/tcg-target.c.inc b/tcg/loongarch/tcg-target.c.inc index eaa155ad68..a533a5619d 100644 --- a/tcg/loongarch/tcg-target.c.inc +++ b/tcg/loongarch/tcg-target.c.inc @@ -373,6 +373,44 @@ static void tcg_out_clzctz(TCGContext *s, LoongArchInsn opc, tcg_out_opc_or(s, a0, TCG_REG_TMP0, a0); } +/* + * Branch helpers + */ + +static const struct { + LoongArchInsn op; + bool swap; +} tcg_brcond_to_loongarch[] = { + [TCG_COND_EQ] = { OPC_BEQ, false }, + [TCG_COND_NE] = { OPC_BNE, false }, + [TCG_COND_LT] = { OPC_BGT, true }, + [TCG_COND_GE] = { OPC_BLE, true }, + [TCG_COND_LE] = { OPC_BLE, false }, + [TCG_COND_GT] = { OPC_BGT, false }, + [TCG_COND_LTU] = { OPC_BGTU, true }, + [TCG_COND_GEU] = { OPC_BLEU, true }, + [TCG_COND_LEU] = { OPC_BLEU, false }, + [TCG_COND_GTU] = { OPC_BGTU, false } +}; + +static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1, + TCGReg arg2, TCGLabel *l) +{ + LoongArchInsn op = tcg_brcond_to_loongarch[cond].op; + + tcg_debug_assert(op != 0); + + if (tcg_brcond_to_loongarch[cond].swap) { + TCGReg t = arg1; + arg1 = arg2; + arg2 = t; + } + + /* all conditional branch insns belong to DJSk16-format */ + tcg_out_reloc(s, s->code_ptr, R_LOONGARCH_SK16, l, 0); + tcg_out32(s, encode_djsk16_insn(op, arg1, arg2, 0)); +} + /* * Entry-points */ @@ -395,6 +433,16 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_opc_jirl(s, TCG_REG_ZERO, a0, 0); break; + case INDEX_op_br: + tcg_out_reloc(s, s->code_ptr, R_LOONGARCH_SD10K16, arg_label(a0), 0); + tcg_out_opc_b(s, 0); + break; + + case INDEX_op_brcond_i32: + case INDEX_op_brcond_i64: + tcg_out_brcond(s, a2, a0, a1, arg_label(args[3])); + break; + case INDEX_op_ext8s_i32: case INDEX_op_ext8s_i64: tcg_out_ext8s(s, a0, a1); @@ -691,6 +739,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_goto_ptr: return C_O0_I1(r); + case INDEX_op_brcond_i32: + case INDEX_op_brcond_i64: + return C_O0_I2(rZ, rZ); + case INDEX_op_ext8s_i32: case INDEX_op_ext8s_i64: case INDEX_op_ext8u_i32: From patchwork Mon Sep 20 08:04:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: WANG Xuerui X-Patchwork-Id: 12505417 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 21BEBC433EF for ; Mon, 20 Sep 2021 14:09:58 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D6F3B610A3 for ; Mon, 20 Sep 2021 14:09:57 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org D6F3B610A3 Authentication-Results: mail.kernel.org; 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Mon, 20 Sep 2021 16:06:02 +0800 (CST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=xen0n.name; s=mail; t=1632125162; bh=j4EjGiVRLTHDBonKZ1vRz9k/sx0JNUED3iBUWqcCYYw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=HsamA/uq9EM7iYp9VVl4DJlDci8cenzgP3ePzGVSGENKfC5Z8GepcKsekvlrgcPur b+HAw8/Q/7Vxt3QqC8e4K3VGuEtpjuMqV7xdJx1ZOKEIBLLlAYYZsyvTVC9/NCOn1a G9KSZmyAX4oh5YbltM2iXZhgP359iuBCZkl64DB0= From: WANG Xuerui To: qemu-devel@nongnu.org Subject: [PATCH 20/30] tcg/loongarch: Implement setcond ops Date: Mon, 20 Sep 2021 16:04:41 +0800 Message-Id: <20210920080451.408655-21-git@xen0n.name> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210920080451.408655-1-git@xen0n.name> References: <20210920080451.408655-1-git@xen0n.name> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.28.160.31 (failed) Received-SPF: pass client-ip=115.28.160.31; envelope-from=git@xen0n.name; helo=mailbox.box.xen0n.name X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 20 Sep 2021 09:57:24 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: WANG Xuerui Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: WANG Xuerui --- tcg/loongarch/tcg-target.c.inc | 53 ++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/tcg/loongarch/tcg-target.c.inc b/tcg/loongarch/tcg-target.c.inc index a533a5619d..fb0143474a 100644 --- a/tcg/loongarch/tcg-target.c.inc +++ b/tcg/loongarch/tcg-target.c.inc @@ -373,6 +373,52 @@ static void tcg_out_clzctz(TCGContext *s, LoongArchInsn opc, tcg_out_opc_or(s, a0, TCG_REG_TMP0, a0); } +static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret, + TCGReg arg1, TCGReg arg2) +{ + switch (cond) { + case TCG_COND_EQ: + tcg_out_opc_sub_d(s, ret, arg1, arg2); + tcg_out_opc_sltui(s, ret, ret, 1); + break; + case TCG_COND_NE: + tcg_out_opc_sub_d(s, ret, arg1, arg2); + tcg_out_opc_sltu(s, ret, TCG_REG_ZERO, ret); + break; + case TCG_COND_LT: + tcg_out_opc_slt(s, ret, arg1, arg2); + break; + case TCG_COND_GE: + tcg_out_opc_slt(s, ret, arg1, arg2); + tcg_out_opc_xori(s, ret, ret, 1); + break; + case TCG_COND_LE: + tcg_out_opc_slt(s, ret, arg2, arg1); + tcg_out_opc_xori(s, ret, ret, 1); + break; + case TCG_COND_GT: + tcg_out_opc_slt(s, ret, arg2, arg1); + break; + case TCG_COND_LTU: + tcg_out_opc_sltu(s, ret, arg1, arg2); + break; + case TCG_COND_GEU: + tcg_out_opc_sltu(s, ret, arg1, arg2); + tcg_out_opc_xori(s, ret, ret, 1); + break; + case TCG_COND_LEU: + tcg_out_opc_sltu(s, ret, arg2, arg1); + tcg_out_opc_xori(s, ret, ret, 1); + break; + case TCG_COND_GTU: + tcg_out_opc_sltu(s, ret, arg2, arg1); + break; + default: + g_assert_not_reached(); + break; + } +} + /* * Branch helpers */ @@ -726,6 +772,11 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_opc_mod_du(s, a0, a1, a2); break; + case INDEX_op_setcond_i32: + case INDEX_op_setcond_i64: + tcg_out_setcond(s, args[3], a0, a1, a2); + break; + case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: default: @@ -830,6 +881,8 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_rem_i64: case INDEX_op_remu_i32: case INDEX_op_remu_i64: + case INDEX_op_setcond_i32: + case INDEX_op_setcond_i64: return C_O1_I2(r, rZ, rZ); default: From patchwork Mon Sep 20 08:04:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: WANG Xuerui X-Patchwork-Id: 12505409 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BD196C433FE for ; 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Mon, 20 Sep 2021 04:11:36 -0400 Received: from ld50.lan (unknown [101.88.25.142]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by mailbox.box.xen0n.name (Postfix) with ESMTPSA id 3524C63406; Mon, 20 Sep 2021 16:06:05 +0800 (CST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=xen0n.name; s=mail; t=1632125165; bh=YMTlbote+jZVGnAyPC9IZ5S0JP/N577aC42WFM/ARxE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=qqYT8x2bXQVgqORA2A/PuSD4urZZKzKfFJwiNB2Ln5/AnAg8nWOLsgdqfZoz7Qite a6krojO0c8ORviV5dmSkNEwzdYgW/6M5k2RgY6MCmEYx2SoNlEbig2T7O2juNNURRj WLFQXmYFBRyJ0ywyQKPkFObKqJobAZRv9LyO+eNg= From: WANG Xuerui To: qemu-devel@nongnu.org Subject: [PATCH 21/30] tcg/loongarch: Implement tcg_out_call Date: Mon, 20 Sep 2021 16:04:42 +0800 Message-Id: <20210920080451.408655-22-git@xen0n.name> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210920080451.408655-1-git@xen0n.name> References: <20210920080451.408655-1-git@xen0n.name> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.28.160.31 (failed) Received-SPF: pass client-ip=115.28.160.31; envelope-from=git@xen0n.name; helo=mailbox.box.xen0n.name X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 20 Sep 2021 09:57:24 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: WANG Xuerui Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: WANG Xuerui --- tcg/loongarch/tcg-target.c.inc | 37 ++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/tcg/loongarch/tcg-target.c.inc b/tcg/loongarch/tcg-target.c.inc index fb0143474a..01c6002fdb 100644 --- a/tcg/loongarch/tcg-target.c.inc +++ b/tcg/loongarch/tcg-target.c.inc @@ -457,6 +457,42 @@ static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1, tcg_out32(s, encode_djsk16_insn(op, arg1, arg2, 0)); } +static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail) +{ + TCGReg link = tail ? TCG_REG_ZERO : TCG_REG_RA; + ptrdiff_t offset = tcg_pcrel_diff(s, arg); + int ret; + + tcg_debug_assert((offset & 2) == 0); + if (offset == sextreg(offset, 0, 28)) { + /* short jump: +/- 256MiB */ + if (tail) { + tcg_out_opc_b(s, offset >> 2); + } else { + tcg_out_opc_bl(s, offset >> 2); + } + } else if (TCG_TARGET_REG_BITS == 32 || offset == (int32_t)offset) { + /* long jump: +/- 2GiB */ + tcg_out_opc_pcaddu12i(s, TCG_REG_TMP0, 0); + tcg_out_opc_jirl(s, link, TCG_REG_TMP0, 0); + ret = reloc_call(s->code_ptr - 2, arg); + tcg_debug_assert(ret == true); + } else if (TCG_TARGET_REG_BITS == 64) { + /* far jump: 64-bit */ + tcg_target_long imm = sextreg((tcg_target_long)arg, 0, 12); + tcg_target_long base = (tcg_target_long)arg - imm; + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, base); + tcg_out_opc_jirl(s, link, TCG_REG_TMP0, imm >> 2); + } else { + g_assert_not_reached(); + } +} + +static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg) +{ + tcg_out_call_int(s, arg, false); +} + /* * Entry-points */ @@ -779,6 +815,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: + case INDEX_op_call: /* Always emitted via tcg_out_call. */ default: g_assert_not_reached(); } From patchwork Mon Sep 20 08:04:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: WANG Xuerui X-Patchwork-Id: 12505523 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D6375C433EF for ; Mon, 20 Sep 2021 14:32:56 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 340E3610A3 for ; Mon, 20 Sep 2021 14:32:56 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 340E3610A3 Authentication-Results: mail.kernel.org; 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Mon, 20 Sep 2021 16:06:06 +0800 (CST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=xen0n.name; s=mail; t=1632125166; bh=9u3BC/bHiJ/PXZjOrjrHgqnCbd+S74rf9nWWo9kO5gY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=IHiaEAmvpU5iQ+H5Bt8iIonzhU4Ps+gy2OC2RW2l4qXKnbtU1JeIVOBflDkwsXtrL p/N2pJyk9UmhxGl07qu5n1wfnFG5pKr5/3IH3z2MzKprea3GMWK9LHQMPE5kFPblp/ Zo3JcI8cLbYuASl7kHNCyr1KQWWOlZB9c92pRJWw= From: WANG Xuerui To: qemu-devel@nongnu.org Subject: [PATCH 22/30] tcg/loongarch: Implement simple load/store ops Date: Mon, 20 Sep 2021 16:04:43 +0800 Message-Id: <20210920080451.408655-23-git@xen0n.name> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210920080451.408655-1-git@xen0n.name> References: <20210920080451.408655-1-git@xen0n.name> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.28.160.31 (failed) Received-SPF: pass client-ip=115.28.160.31; envelope-from=git@xen0n.name; helo=mailbox.box.xen0n.name X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 20 Sep 2021 09:57:24 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: WANG Xuerui Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: WANG Xuerui Reviewed-by: Richard Henderson --- tcg/loongarch/tcg-target-con-set.h | 1 + tcg/loongarch/tcg-target.c.inc | 131 +++++++++++++++++++++++++++++ 2 files changed, 132 insertions(+) diff --git a/tcg/loongarch/tcg-target-con-set.h b/tcg/loongarch/tcg-target-con-set.h index bcbf0780ff..cdbfe9cd8d 100644 --- a/tcg/loongarch/tcg-target-con-set.h +++ b/tcg/loongarch/tcg-target-con-set.h @@ -15,6 +15,7 @@ * tcg-target-con-str.h; the constraint combination is inclusive or. */ C_O0_I1(r) +C_O0_I2(rZ, r) C_O0_I2(rZ, rZ) C_O1_I1(r, r) C_O1_I2(r, r, r) diff --git a/tcg/loongarch/tcg-target.c.inc b/tcg/loongarch/tcg-target.c.inc index 01c6002fdb..3947a2d9fa 100644 --- a/tcg/loongarch/tcg-target.c.inc +++ b/tcg/loongarch/tcg-target.c.inc @@ -493,6 +493,73 @@ static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg) tcg_out_call_int(s, arg, false); } +/* + * Load/store helpers + */ + +static void tcg_out_ldst(TCGContext *s, LoongArchInsn opc, TCGReg data, + TCGReg addr, intptr_t offset) +{ + intptr_t imm12 = sextreg(offset, 0, 12); + + if (offset != imm12) { + intptr_t diff = offset - (uintptr_t)s->code_ptr; + + if (addr == TCG_REG_ZERO && diff == (int32_t)diff) { + imm12 = sextreg(diff, 0, 12); + tcg_out_opc_pcaddu12i(s, TCG_REG_TMP2, (diff - imm12) >> 12); + } else { + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP2, offset - imm12); + if (addr != TCG_REG_ZERO) { + tcg_out_opc_add_d(s, TCG_REG_TMP2, TCG_REG_TMP2, addr); + } + } + addr = TCG_REG_TMP2; + } + + switch (opc) { + case OPC_LD_B: + case OPC_LD_BU: + case OPC_LD_H: + case OPC_LD_HU: + case OPC_LD_W: + case OPC_LD_WU: + case OPC_LD_D: + case OPC_ST_B: + case OPC_ST_H: + case OPC_ST_W: + case OPC_ST_D: + tcg_out32(s, encode_djsk12_insn(opc, data, addr, imm12)); + break; + default: + g_assert_not_reached(); + } +} + +static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, + TCGReg arg1, intptr_t arg2) +{ + bool is_32bit = (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32); + tcg_out_ldst(s, is_32bit ? OPC_LD_W : OPC_LD_D, arg, arg1, arg2); +} + +static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, + TCGReg arg1, intptr_t arg2) +{ + bool is_32bit = (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32); + tcg_out_ldst(s, is_32bit ? OPC_ST_W : OPC_ST_D, arg, arg1, arg2); +} + +static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, + TCGReg base, intptr_t ofs) +{ + if (val == 0) { + tcg_out_st(s, type, TCG_REG_ZERO, base, ofs); + return true; + } + return false; +} + /* * Entry-points */ @@ -813,6 +880,49 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_setcond(s, args[3], a0, a1, a2); break; + case INDEX_op_ld8s_i32: + case INDEX_op_ld8s_i64: + tcg_out_ldst(s, OPC_LD_B, a0, a1, a2); + break; + case INDEX_op_ld8u_i32: + case INDEX_op_ld8u_i64: + tcg_out_ldst(s, OPC_LD_BU, a0, a1, a2); + break; + case INDEX_op_ld16s_i32: + case INDEX_op_ld16s_i64: + tcg_out_ldst(s, OPC_LD_H, a0, a1, a2); + break; + case INDEX_op_ld16u_i32: + case INDEX_op_ld16u_i64: + tcg_out_ldst(s, OPC_LD_HU, a0, a1, a2); + break; + case INDEX_op_ld_i32: + case INDEX_op_ld32s_i64: + tcg_out_ldst(s, OPC_LD_W, a0, a1, a2); + break; + case INDEX_op_ld32u_i64: + tcg_out_ldst(s, OPC_LD_WU, a0, a1, a2); + break; + case INDEX_op_ld_i64: + tcg_out_ldst(s, OPC_LD_D, a0, a1, a2); + break; + + case INDEX_op_st8_i32: + case INDEX_op_st8_i64: + tcg_out_ldst(s, OPC_ST_B, a0, a1, a2); + break; + case INDEX_op_st16_i32: + case INDEX_op_st16_i64: + tcg_out_ldst(s, OPC_ST_H, a0, a1, a2); + break; + case INDEX_op_st_i32: + case INDEX_op_st32_i64: + tcg_out_ldst(s, OPC_ST_W, a0, a1, a2); + break; + case INDEX_op_st_i64: + tcg_out_ldst(s, OPC_ST_D, a0, a1, a2); + break; + case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: case INDEX_op_call: /* Always emitted via tcg_out_call. */ @@ -827,6 +937,15 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_goto_ptr: return C_O0_I1(r); + case INDEX_op_st8_i32: + case INDEX_op_st8_i64: + case INDEX_op_st16_i32: + case INDEX_op_st16_i64: + case INDEX_op_st32_i64: + case INDEX_op_st_i32: + case INDEX_op_st_i64: + return C_O0_I2(rZ, r); + case INDEX_op_brcond_i32: case INDEX_op_brcond_i64: return C_O0_I2(rZ, rZ); @@ -853,6 +972,18 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_bswap64_i64: case INDEX_op_neg_i32: case INDEX_op_neg_i64: + case INDEX_op_ld8s_i32: + case INDEX_op_ld8s_i64: + case INDEX_op_ld8u_i32: + case INDEX_op_ld8u_i64: + case INDEX_op_ld16s_i32: + case INDEX_op_ld16s_i64: + case INDEX_op_ld16u_i32: + case INDEX_op_ld16u_i64: + case INDEX_op_ld32s_i64: + case INDEX_op_ld32u_i64: + case INDEX_op_ld_i32: + case INDEX_op_ld_i64: return C_O1_I1(r, r); case INDEX_op_nor_i32: From patchwork Mon Sep 20 08:04:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: WANG Xuerui X-Patchwork-Id: 12505405 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3F97AC433F5 for ; Mon, 20 Sep 2021 14:03:14 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id F3B8A610A3 for ; Mon, 20 Sep 2021 14:03:13 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org F3B8A610A3 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=xen0n.name Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:34408 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mSJt3-0001mw-64 for qemu-devel@archiver.kernel.org; Mon, 20 Sep 2021 10:03:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49324) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mSEOr-0007ng-Et for qemu-devel@nongnu.org; Mon, 20 Sep 2021 04:11:41 -0400 Received: from [115.28.160.31] (port=35568 helo=mailbox.box.xen0n.name) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mSEOo-0005LL-R7 for qemu-devel@nongnu.org; Mon, 20 Sep 2021 04:11:41 -0400 Received: from ld50.lan (unknown [101.88.25.142]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by mailbox.box.xen0n.name (Postfix) with ESMTPSA id B468C63408; Mon, 20 Sep 2021 16:06:08 +0800 (CST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=xen0n.name; s=mail; t=1632125168; bh=2+kjYFjMGtRWoGYU08ogRAYZvkpruEPb8DQ1Nf80ObA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=M4Y7cFll2kwaxxPz3qR3MqKhWS0Jy5xzh/OhD8TgzMkkYGRAsYEhIo5QxcfLIIH97 vScor9MJ6uBnZMXp6hGVl+Di3jvdCxGZwcthGPgC25GIO2c/xL9zheEX+FpD1ZoZqO Mk9pNOJKDyWpe0P6EnDXNtJgz2BBmFlZRkjpWI4w= From: WANG Xuerui To: qemu-devel@nongnu.org Subject: [PATCH 23/30] tcg/loongarch: Add softmmu load/store helpers, implement qemu_ld/qemu_st ops Date: Mon, 20 Sep 2021 16:04:44 +0800 Message-Id: <20210920080451.408655-24-git@xen0n.name> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210920080451.408655-1-git@xen0n.name> References: <20210920080451.408655-1-git@xen0n.name> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.28.160.31 (failed) Received-SPF: pass client-ip=115.28.160.31; envelope-from=git@xen0n.name; helo=mailbox.box.xen0n.name X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 20 Sep 2021 09:57:24 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: WANG Xuerui Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: WANG Xuerui --- tcg/loongarch/tcg-target-con-set.h | 2 + tcg/loongarch/tcg-target.c.inc | 344 +++++++++++++++++++++++++++++ 2 files changed, 346 insertions(+) diff --git a/tcg/loongarch/tcg-target-con-set.h b/tcg/loongarch/tcg-target-con-set.h index cdbfe9cd8d..b990da6b26 100644 --- a/tcg/loongarch/tcg-target-con-set.h +++ b/tcg/loongarch/tcg-target-con-set.h @@ -17,7 +17,9 @@ C_O0_I1(r) C_O0_I2(rZ, r) C_O0_I2(rZ, rZ) +C_O0_I2(LZ, L) C_O1_I1(r, r) +C_O1_I1(r, L) C_O1_I2(r, r, r) C_O1_I2(r, r, ri) C_O1_I2(r, r, rI) diff --git a/tcg/loongarch/tcg-target.c.inc b/tcg/loongarch/tcg-target.c.inc index 3947a2d9fa..0b6f16bde0 100644 --- a/tcg/loongarch/tcg-target.c.inc +++ b/tcg/loongarch/tcg-target.c.inc @@ -560,6 +560,329 @@ static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, return false; } +/* + * Load/store helpers for SoftMMU, and qemu_ld/st implementations + */ + +#if defined(CONFIG_SOFTMMU) +#include "../tcg-ldst.c.inc" + +/* + * helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, + * TCGMemOpIdx oi, uintptr_t ra) + */ +static void * const qemu_ld_helpers[8] = { + [MO_UB] = helper_ret_ldub_mmu, + [MO_SB] = helper_ret_ldsb_mmu, + [MO_UW] = helper_le_lduw_mmu, + [MO_SW] = helper_le_ldsw_mmu, + [MO_UL] = helper_le_ldul_mmu, +#if TCG_TARGET_REG_BITS == 64 + [MO_SL] = helper_le_ldsl_mmu, +#endif + [MO_Q] = helper_le_ldq_mmu, +}; + +/* + * helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr, + * uintxx_t val, TCGMemOpIdx oi, + * uintptr_t ra) + */ +static void * const qemu_st_helpers[4] = { + [MO_8] = helper_ret_stb_mmu, + [MO_16] = helper_le_stw_mmu, + [MO_32] = helper_le_stl_mmu, + [MO_64] = helper_le_stq_mmu, +}; + +/* We don't support oversize guests */ +QEMU_BUILD_BUG_ON(TCG_TARGET_REG_BITS < TARGET_LONG_BITS); + +/* We expect to use a 12-bit negative offset from ENV. */ +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 11)); + +static void tcg_out_goto(TCGContext *s, const tcg_insn_unit *target) +{ + tcg_out_opc_b(s, 0); + bool ok = reloc_sd10k16(s->code_ptr - 1, target); + tcg_debug_assert(ok); +} + +static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl, TCGMemOpIdx oi, + tcg_insn_unit **label_ptr, bool is_load) +{ + MemOp opc = get_memop(oi); + unsigned s_bits = opc & MO_SIZE; + unsigned a_bits = get_alignment_bits(opc); + tcg_target_long compare_mask; + int mem_index = get_mmuidx(oi); + int fast_ofs = TLB_MASK_TABLE_OFS(mem_index); + int mask_ofs = fast_ofs + offsetof(CPUTLBDescFast, mask); + int table_ofs = fast_ofs + offsetof(CPUTLBDescFast, table); + TCGReg mask_base = TCG_AREG0, table_base = TCG_AREG0; + + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, mask_base, mask_ofs); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, table_base, table_ofs); + + tcg_out_opc_srli_d(s, TCG_REG_TMP2, addrl, + TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); + tcg_out_opc_and(s, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP0); + tcg_out_opc_add_d(s, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP1); + + /* Load the tlb comparator and the addend. */ + tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP0, TCG_REG_TMP2, + is_load ? offsetof(CPUTLBEntry, addr_read) + : offsetof(CPUTLBEntry, addr_write)); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_REG_TMP2, + offsetof(CPUTLBEntry, addend)); + + /* We don't support unaligned accesses. */ + if (a_bits < s_bits) { + a_bits = s_bits; + } + /* Clear the non-page, non-alignment bits from the address. */ + compare_mask = (tcg_target_long)TARGET_PAGE_MASK | ((1 << a_bits) - 1); + if (compare_mask == sextreg(compare_mask, 0, 12)) { + tcg_out_opc_andi(s, TCG_REG_TMP1, addrl, compare_mask); + } else { + tcg_out_movi(s, TCG_TYPE_TL, TCG_REG_TMP1, compare_mask); + tcg_out_opc_and(s, TCG_REG_TMP1, TCG_REG_TMP1, addrl); + } + + /* Compare masked address with the TLB entry. */ + label_ptr[0] = s->code_ptr; + tcg_out_opc_bne(s, TCG_REG_TMP0, TCG_REG_TMP1, 0); + + /* TLB Hit - translate address using addend. */ + if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { + tcg_out_ext32u(s, TCG_REG_TMP0, addrl); + addrl = TCG_REG_TMP0; + } + tcg_out_opc_add_d(s, TCG_REG_TMP0, TCG_REG_TMP2, addrl); +} + +static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi, + TCGType ext, + TCGReg datalo, TCGReg addrlo, + void *raddr, tcg_insn_unit **label_ptr) +{ + TCGLabelQemuLdst *label = new_ldst_label(s); + + label->is_ld = is_ld; + label->oi = oi; + label->type = ext; + label->datalo_reg = datalo; + label->datahi_reg = 0; + label->addrlo_reg = addrlo; + label->addrhi_reg = 0; + label->raddr = tcg_splitwx_to_rx(raddr); + label->label_ptr[0] = label_ptr[0]; +} + +static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) +{ + TCGMemOpIdx oi = l->oi; + MemOp opc = get_memop(oi); + TCGReg a0 = tcg_target_call_iarg_regs[0]; + TCGReg a1 = tcg_target_call_iarg_regs[1]; + TCGReg a2 = tcg_target_call_iarg_regs[2]; + TCGReg a3 = tcg_target_call_iarg_regs[3]; + + /* We don't support oversize guests */ + if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { + g_assert_not_reached(); + } + + /* resolve label address */ + if (!reloc_sk16(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { + return false; + } + + /* call load helper */ + tcg_out_mov(s, TCG_TYPE_PTR, a0, TCG_AREG0); + tcg_out_mov(s, TCG_TYPE_PTR, a1, l->addrlo_reg); + tcg_out_movi(s, TCG_TYPE_PTR, a2, oi); + tcg_out_movi(s, TCG_TYPE_PTR, a3, (tcg_target_long)l->raddr); + + tcg_out_call(s, qemu_ld_helpers[opc & MO_SSIZE]); + tcg_out_mov(s, (opc & MO_SIZE) == MO_64, l->datalo_reg, a0); + + tcg_out_goto(s, l->raddr); + return true; +} + +static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) +{ + TCGMemOpIdx oi = l->oi; + MemOp opc = get_memop(oi); + MemOp s_bits = opc & MO_SIZE; + TCGReg a0 = tcg_target_call_iarg_regs[0]; + TCGReg a1 = tcg_target_call_iarg_regs[1]; + TCGReg a2 = tcg_target_call_iarg_regs[2]; + TCGReg a3 = tcg_target_call_iarg_regs[3]; + TCGReg a4 = tcg_target_call_iarg_regs[4]; + + /* We don't support oversize guests */ + if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { + g_assert_not_reached(); + } + + /* resolve label address */ + if (!reloc_sk16(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { + return false; + } + + /* call store helper */ + tcg_out_mov(s, TCG_TYPE_PTR, a0, TCG_AREG0); + tcg_out_mov(s, TCG_TYPE_PTR, a1, l->addrlo_reg); + tcg_out_mov(s, TCG_TYPE_PTR, a2, l->datalo_reg); + switch (s_bits) { + case MO_8: + tcg_out_ext8u(s, a2, a2); + break; + case MO_16: + tcg_out_ext16u(s, a2, a2); + break; + default: + break; + } + tcg_out_movi(s, TCG_TYPE_PTR, a3, oi); + tcg_out_movi(s, TCG_TYPE_PTR, a4, (tcg_target_long)l->raddr); + + tcg_out_call(s, qemu_st_helpers[opc & MO_SIZE]); + + tcg_out_goto(s, l->raddr); + return true; +} +#endif /* CONFIG_SOFTMMU */ + +static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg base, + MemOp opc, bool is_64) +{ + /* Byte swapping is left to middle-end expansion. */ + tcg_debug_assert((opc & MO_BSWAP) == 0); + + switch (opc & (MO_SSIZE)) { + case MO_UB: + tcg_out_opc_ld_bu(s, lo, base, 0); + break; + case MO_SB: + tcg_out_opc_ld_b(s, lo, base, 0); + break; + case MO_UW: + tcg_out_opc_ld_hu(s, lo, base, 0); + break; + case MO_SW: + tcg_out_opc_ld_h(s, lo, base, 0); + break; + case MO_UL: + if (TCG_TARGET_REG_BITS == 64 && is_64) { + tcg_out_opc_ld_wu(s, lo, base, 0); + break; + } + /* fallthrough */ + case MO_SL: + tcg_out_opc_ld_w(s, lo, base, 0); + break; + case MO_Q: + tcg_out_opc_ld_d(s, lo, base, 0); + break; + default: + g_assert_not_reached(); + } +} + +static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) +{ + TCGReg addr_regl; + TCGReg data_regl; + TCGMemOpIdx oi; + MemOp opc; +#if defined(CONFIG_SOFTMMU) + tcg_insn_unit *label_ptr[1]; +#endif + TCGReg base = TCG_REG_TMP0; + + data_regl = *args++; + addr_regl = *args++; + oi = *args++; + opc = get_memop(oi); + +#if defined(CONFIG_SOFTMMU) + tcg_out_tlb_load(s, addr_regl, oi, label_ptr, 1); + tcg_out_qemu_ld_direct(s, data_regl, base, opc, is_64); + add_qemu_ldst_label(s, 1, oi, + (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), + data_regl, addr_regl, + s->code_ptr, label_ptr); +#else + if (guest_base == 0) { + tcg_out_opc_add_d(s, base, addr_regl, TCG_REG_ZERO); + } else { + tcg_out_opc_add_d(s, base, TCG_GUEST_BASE_REG, addr_regl); + } + tcg_out_qemu_ld_direct(s, data_regl, base, opc, is_64); +#endif +} + +static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, + TCGReg base, MemOp opc) +{ + /* Byte swapping is left to middle-end expansion. */ + tcg_debug_assert((opc & MO_BSWAP) == 0); + + switch (opc & (MO_SSIZE)) { + case MO_8: + tcg_out_opc_st_b(s, lo, base, 0); + break; + case MO_16: + tcg_out_opc_st_h(s, lo, base, 0); + break; + case MO_32: + tcg_out_opc_st_w(s, lo, base, 0); + break; + case MO_64: + tcg_out_opc_st_d(s, lo, base, 0); + break; + default: + g_assert_not_reached(); + } +} + +static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) +{ + TCGReg addr_regl; + TCGReg data_regl; + TCGMemOpIdx oi; + MemOp opc; +#if defined(CONFIG_SOFTMMU) + tcg_insn_unit *label_ptr[1]; +#endif + TCGReg base = TCG_REG_TMP0; + + data_regl = *args++; + addr_regl = *args++; + oi = *args++; + opc = get_memop(oi); + +#if defined(CONFIG_SOFTMMU) + tcg_out_tlb_load(s, addr_regl, oi, label_ptr, 0); + tcg_out_qemu_st_direct(s, data_regl, base, opc); + add_qemu_ldst_label(s, 0, oi, + (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), + data_regl, addr_regl, + s->code_ptr, label_ptr); +#else + if (guest_base == 0) { + tcg_out_opc_add_d(s, base, addr_regl, TCG_REG_ZERO); + } else { + tcg_out_opc_add_d(s, base, TCG_GUEST_BASE_REG, addr_regl); + } + tcg_out_qemu_st_direct(s, data_regl, base, opc); +#endif +} + /* * Entry-points */ @@ -923,6 +1246,19 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_ldst(s, OPC_ST_D, a0, a1, a2); break; + case INDEX_op_qemu_ld_i32: + tcg_out_qemu_ld(s, args, false); + break; + case INDEX_op_qemu_ld_i64: + tcg_out_qemu_ld(s, args, true); + break; + case INDEX_op_qemu_st_i32: + tcg_out_qemu_st(s, args, false); + break; + case INDEX_op_qemu_st_i64: + tcg_out_qemu_st(s, args, true); + break; + case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: case INDEX_op_call: /* Always emitted via tcg_out_call. */ @@ -950,6 +1286,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_brcond_i64: return C_O0_I2(rZ, rZ); + case INDEX_op_qemu_st_i32: + case INDEX_op_qemu_st_i64: + return C_O0_I2(LZ, L); + case INDEX_op_ext8s_i32: case INDEX_op_ext8s_i64: case INDEX_op_ext8u_i32: @@ -986,6 +1326,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_ld_i64: return C_O1_I1(r, r); + case INDEX_op_qemu_ld_i32: + case INDEX_op_qemu_ld_i64: + return C_O1_I1(r, L); + case INDEX_op_nor_i32: case INDEX_op_andc_i32: case INDEX_op_orc_i32: From patchwork Mon Sep 20 08:04:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: WANG Xuerui X-Patchwork-Id: 12505399 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B549EC433F5 for ; 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Mon, 20 Sep 2021 04:12:00 -0400 Received: from ld50.lan (unknown [101.88.25.142]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by mailbox.box.xen0n.name (Postfix) with ESMTPSA id A6E5763409; Mon, 20 Sep 2021 16:06:10 +0800 (CST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=xen0n.name; s=mail; t=1632125170; bh=Q9oBbBpC4cxD0x+pbaGsc3akHZSv9dGWPw0p0YmNOdM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=c/L/l9YO1PR9uRDeC0q7TMexbMit6PRs3IXHvLnmzrYyU25zoHyEUiwDp9/DqUXrJ BTtyQbSrjwFOFJDtLCjPpi5uFnINZYfcZj1GKX6TvUoritYaXUSisIt5X4bEyanXuS bKNE6gbiSpGrpC0R9nEhbW4WdZjjcAT/9OZzXfc0= From: WANG Xuerui To: qemu-devel@nongnu.org Subject: [PATCH 24/30] tcg/loongarch: Implement tcg_target_qemu_prologue Date: Mon, 20 Sep 2021 16:04:45 +0800 Message-Id: <20210920080451.408655-25-git@xen0n.name> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210920080451.408655-1-git@xen0n.name> References: <20210920080451.408655-1-git@xen0n.name> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.28.160.31 (failed) Received-SPF: pass client-ip=115.28.160.31; envelope-from=git@xen0n.name; helo=mailbox.box.xen0n.name X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 20 Sep 2021 09:57:24 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: WANG Xuerui Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: WANG Xuerui Reviewed-by: Richard Henderson --- tcg/loongarch/tcg-target.c.inc | 66 ++++++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/tcg/loongarch/tcg-target.c.inc b/tcg/loongarch/tcg-target.c.inc index 0b6f16bde0..10df007087 100644 --- a/tcg/loongarch/tcg-target.c.inc +++ b/tcg/loongarch/tcg-target.c.inc @@ -887,6 +887,8 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) * Entry-points */ +static const tcg_insn_unit *tb_ret_addr; + static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg args[TCG_MAX_OP_ARGS], const int const_args[TCG_MAX_OP_ARGS]) @@ -1401,3 +1403,67 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) g_assert_not_reached(); } } + +static const int tcg_target_callee_save_regs[] = { + TCG_REG_S0, /* used for the global env (TCG_AREG0) */ + TCG_REG_S1, + TCG_REG_S2, + TCG_REG_S3, + TCG_REG_S4, + TCG_REG_S5, + TCG_REG_S6, + TCG_REG_S7, + TCG_REG_S8, + TCG_REG_S9, + TCG_REG_RA, /* should be last for ABI compliance */ +}; + +/* Stack frame parameters. */ +#define REG_SIZE (TCG_TARGET_REG_BITS / 8) +#define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE) +#define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long)) +#define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \ + + TCG_TARGET_STACK_ALIGN - 1) \ + & -TCG_TARGET_STACK_ALIGN) +#define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE) + +/* We're expecting to be able to use an immediate for frame allocation. */ +QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7ff); + +/* Generate global QEMU prologue and epilogue code */ +static void tcg_target_qemu_prologue(TCGContext *s) +{ + int i; + + tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE); + + /* TB prologue */ + tcg_out_opc_addi_d(s, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE); + for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { + tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], + TCG_REG_SP, SAVE_OFS + i * REG_SIZE); + } + +#if !defined(CONFIG_SOFTMMU) + tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base); + tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); +#endif + + /* Call generated code */ + tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); + tcg_out_opc_jirl(s, TCG_REG_ZERO, tcg_target_call_iarg_regs[1], 0); + + /* Return path for goto_ptr. Set return value to 0 */ + tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); + tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_A0, TCG_REG_ZERO); + + /* TB epilogue */ + tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr); + for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { + tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], + TCG_REG_SP, SAVE_OFS + i * REG_SIZE); + } + + tcg_out_opc_addi_d(s, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE); + tcg_out_opc_jirl(s, TCG_REG_ZERO, TCG_REG_RA, 0); +} From patchwork Mon Sep 20 08:04:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: WANG Xuerui X-Patchwork-Id: 12505515 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 85927C433F5 for ; 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Mon, 20 Sep 2021 04:16:35 -0400 Received: from ld50.lan (unknown [101.88.25.142]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by mailbox.box.xen0n.name (Postfix) with ESMTPSA id E3F156340A; Mon, 20 Sep 2021 16:06:12 +0800 (CST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=xen0n.name; s=mail; t=1632125172; bh=VtbntofemEsOm7UqG3/evjLaoLVj9ThUM57Q0GFNT18=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jcZMzhPWnbE+Y6PrSMHZi8xqeGHr6xcSQGg6hs02VBJYSpPpRfVKAC6R0v/+Kt7dJ 3Yg8F/lt8AhlFaXGV6jAxdX9IGmaLqctRJKC6JYNRmfbpdoPBym2N9gxBvU8byMvuT MNL969h/gSPyGsAu//TvblCzSSqWM8ut3pZfn8tQ= From: WANG Xuerui To: qemu-devel@nongnu.org Subject: [PATCH 25/30] tcg/loongarch: Implement exit_tb/goto_tb Date: Mon, 20 Sep 2021 16:04:46 +0800 Message-Id: <20210920080451.408655-26-git@xen0n.name> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210920080451.408655-1-git@xen0n.name> References: <20210920080451.408655-1-git@xen0n.name> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.28.160.31 (failed) Received-SPF: pass client-ip=115.28.160.31; envelope-from=git@xen0n.name; helo=mailbox.box.xen0n.name X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 20 Sep 2021 09:57:24 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: WANG Xuerui Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: WANG Xuerui Reviewed-by: Richard Henderson --- tcg/loongarch/tcg-target.c.inc | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/tcg/loongarch/tcg-target.c.inc b/tcg/loongarch/tcg-target.c.inc index 10df007087..585bf8dba0 100644 --- a/tcg/loongarch/tcg-target.c.inc +++ b/tcg/loongarch/tcg-target.c.inc @@ -899,6 +899,25 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, int c2 = const_args[2]; switch (opc) { + case INDEX_op_exit_tb: + /* Reuse the zeroing that exists for goto_ptr. */ + if (a0 == 0) { + tcg_out_call_int(s, tcg_code_gen_epilogue, true); + } else { + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A0, a0); + tcg_out_call_int(s, tb_ret_addr, true); + } + break; + + case INDEX_op_goto_tb: + assert(s->tb_jmp_insn_offset == 0); + /* indirect jump method */ + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_REG_ZERO, + (uintptr_t)(s->tb_jmp_target_addr + a0)); + tcg_out_opc_jirl(s, TCG_REG_ZERO, TCG_REG_TMP0, 0); + set_jmp_reset_offset(s, a0); + break; + case INDEX_op_mb: tcg_out_mb(s, a0); break; From patchwork Mon Sep 20 08:04:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: WANG Xuerui X-Patchwork-Id: 12505423 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,TVD_SPACE_RATIO,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 773D3C433F5 for ; Mon, 20 Sep 2021 14:10:01 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4126B610CE for ; Mon, 20 Sep 2021 14:10:01 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 4126B610CE Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=xen0n.name Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:51506 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mSJzc-0004nG-GG for qemu-devel@archiver.kernel.org; Mon, 20 Sep 2021 10:10:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50278) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mSETW-0008RC-L5 for qemu-devel@nongnu.org; Mon, 20 Sep 2021 04:16:31 -0400 Received: from [115.28.160.31] (port=35648 helo=mailbox.box.xen0n.name) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mSETT-0000pW-D6 for qemu-devel@nongnu.org; Mon, 20 Sep 2021 04:16:30 -0400 Received: from ld50.lan (unknown [101.88.25.142]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by mailbox.box.xen0n.name (Postfix) with ESMTPSA id C0A6A6340B; Mon, 20 Sep 2021 16:06:14 +0800 (CST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=xen0n.name; s=mail; t=1632125174; bh=jpr1oy1wQbUshahrmgEkxsSF14Hd/0cCNV/8BTZide4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=xv2M0edlHPZakgB959YmJ8CYyklGJGCQata0xcSdWLPKNxTaO78ZK+cqvDngRG/Yl JoqivM1XGIGmyQYos+zxtlO7m8/MlvfN4Ph8z4gfBGVfXHvz9Bb/OOuW/FyZakDA8I Q/yfI2sWhVj/Tmg5XQfamyRJrvdiSO6DtTD/3P4w= From: WANG Xuerui To: qemu-devel@nongnu.org Subject: [PATCH 26/30] tcg/loongarch: Implement tcg_target_init Date: Mon, 20 Sep 2021 16:04:47 +0800 Message-Id: <20210920080451.408655-27-git@xen0n.name> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210920080451.408655-1-git@xen0n.name> References: <20210920080451.408655-1-git@xen0n.name> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.28.160.31 (failed) Received-SPF: pass client-ip=115.28.160.31; envelope-from=git@xen0n.name; helo=mailbox.box.xen0n.name X-Spam_score_int: 6 X-Spam_score: 0.6 X-Spam_bar: / X-Spam_report: (0.6 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, TVD_SPACE_RATIO=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 20 Sep 2021 09:57:24 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: WANG Xuerui Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: WANG Xuerui Reviewed-by: Richard Henderson --- tcg/loongarch/tcg-target.c.inc | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/tcg/loongarch/tcg-target.c.inc b/tcg/loongarch/tcg-target.c.inc index 585bf8dba0..107682e1fa 100644 --- a/tcg/loongarch/tcg-target.c.inc +++ b/tcg/loongarch/tcg-target.c.inc @@ -1486,3 +1486,32 @@ static void tcg_target_qemu_prologue(TCGContext *s) tcg_out_opc_addi_d(s, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE); tcg_out_opc_jirl(s, TCG_REG_ZERO, TCG_REG_RA, 0); } + +static void tcg_target_init(TCGContext *s) +{ + tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff; + if (TCG_TARGET_REG_BITS == 64) { + tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff; + } + + tcg_target_call_clobber_regs = -1u; + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S0); + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S1); + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S2); + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S3); + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S4); + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S5); + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S6); + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S7); + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S8); + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S9); + + s->reserved_regs = 0; + tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); + tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP0); + tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1); + tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP2); + tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); + tcg_regset_set_reg(s->reserved_regs, TCG_REG_TP); + tcg_regset_set_reg(s->reserved_regs, TCG_REG_RESERVED); +} From patchwork Mon Sep 20 08:04:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: WANG Xuerui X-Patchwork-Id: 12505407 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CAE41C433F5 for ; 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Mon, 20 Sep 2021 04:16:30 -0400 Received: from ld50.lan (unknown [101.88.25.142]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by mailbox.box.xen0n.name (Postfix) with ESMTPSA id C06126340C; Mon, 20 Sep 2021 16:06:16 +0800 (CST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=xen0n.name; s=mail; t=1632125176; bh=Xdrgo5XG9zmkiQQAkBxj6W5xUj49FqUf2M8bdgZeaY4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=hlLAyrFZHfj5XA06qA70ZBkOMS6cIqC6YD0QWa1AlnZ+7cTLIsrtyz6KLzyrofZnC xOCQ9G/vmxRYKhQezWUsVQab2poZyl27+IEFvf3YYKK81nD2gMR4hSw5883v/pn8lo PxRqHZF14KiN5eTL1YHV4bJMkz/CDo7hAv0PWDJw= From: WANG Xuerui To: qemu-devel@nongnu.org Subject: [PATCH 27/30] tcg/loongarch: Register the JIT Date: Mon, 20 Sep 2021 16:04:48 +0800 Message-Id: <20210920080451.408655-28-git@xen0n.name> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210920080451.408655-1-git@xen0n.name> References: <20210920080451.408655-1-git@xen0n.name> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.28.160.31 (failed) Received-SPF: pass client-ip=115.28.160.31; envelope-from=git@xen0n.name; helo=mailbox.box.xen0n.name X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 20 Sep 2021 09:57:24 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: WANG Xuerui Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: WANG Xuerui Reviewed-by: Richard Henderson --- tcg/loongarch/tcg-target.c.inc | 44 ++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/tcg/loongarch/tcg-target.c.inc b/tcg/loongarch/tcg-target.c.inc index 107682e1fa..59adc92d26 100644 --- a/tcg/loongarch/tcg-target.c.inc +++ b/tcg/loongarch/tcg-target.c.inc @@ -1515,3 +1515,47 @@ static void tcg_target_init(TCGContext *s) tcg_regset_set_reg(s->reserved_regs, TCG_REG_TP); tcg_regset_set_reg(s->reserved_regs, TCG_REG_RESERVED); } + +typedef struct { + DebugFrameHeader h; + uint8_t fde_def_cfa[4]; + uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2]; +} DebugFrame; + +#define ELF_HOST_MACHINE EM_LOONGARCH + +static const DebugFrame debug_frame = { + .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */ + .h.cie.id = -1, + .h.cie.version = 1, + .h.cie.code_align = 1, + .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */ + .h.cie.return_column = TCG_REG_RA, + + /* Total FDE size does not include the "len" member. */ + .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), + + .fde_def_cfa = { + 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */ + (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ + (FRAME_SIZE >> 7) + }, + .fde_reg_ofs = { + 0x80 + 23, 11, /* DW_CFA_offset, s0, -88 */ + 0x80 + 24, 10, /* DW_CFA_offset, s1, -80 */ + 0x80 + 25, 9, /* DW_CFA_offset, s2, -72 */ + 0x80 + 26, 8, /* DW_CFA_offset, s3, -64 */ + 0x80 + 27, 7, /* DW_CFA_offset, s4, -56 */ + 0x80 + 28, 6, /* DW_CFA_offset, s5, -48 */ + 0x80 + 29, 5, /* DW_CFA_offset, s6, -40 */ + 0x80 + 30, 4, /* DW_CFA_offset, s7, -32 */ + 0x80 + 31, 3, /* DW_CFA_offset, s8, -24 */ + 0x80 + 22, 2, /* DW_CFA_offset, s9, -16 */ + 0x80 + 1 , 1, /* DW_CFA_offset, ra, -8 */ + } +}; + +void tcg_register_jit(const void *buf, size_t buf_size) +{ + tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); +} From patchwork Mon Sep 20 08:04:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: WANG Xuerui X-Patchwork-Id: 12505487 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BAF5EC433F5 for ; Mon, 20 Sep 2021 14:26:46 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5D83061168 for ; Mon, 20 Sep 2021 14:26:46 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 5D83061168 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=xen0n.name Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:54338 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mSKFp-0000Z5-9W for qemu-devel@archiver.kernel.org; Mon, 20 Sep 2021 10:26:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50282) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mSETW-0008RF-OO for qemu-devel@nongnu.org; Mon, 20 Sep 2021 04:16:31 -0400 Received: from [115.28.160.31] (port=35650 helo=mailbox.box.xen0n.name) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mSETT-0000pX-MO for qemu-devel@nongnu.org; Mon, 20 Sep 2021 04:16:30 -0400 Received: from ld50.lan (unknown [101.88.25.142]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by mailbox.box.xen0n.name (Postfix) with ESMTPSA id B4E0A6340D; Mon, 20 Sep 2021 16:06:18 +0800 (CST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=xen0n.name; s=mail; t=1632125178; bh=XKhdqEM3fakRZEgCsNFnG1+88yBx48o+yAIIu6yO60k=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=HKbp89uqMuG7OPfFcdMWO616ojNEv1CXziyhw5/kvnCDCFnKhkJjvSsC1FlKeFSd+ bOmb2XOpxai9sSNCEH4PcZDYrfhr3GywbTnnPNGopADVZRO7ZS8i2wpftJ6b2x+XY5 lXuDLl9pZXRPpNccggF56wPrNquwjeuurrK07xl0= From: WANG Xuerui To: qemu-devel@nongnu.org Subject: [PATCH 28/30] configure, meson.build: Mark support for 64-bit LoongArch hosts Date: Mon, 20 Sep 2021 16:04:49 +0800 Message-Id: <20210920080451.408655-29-git@xen0n.name> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210920080451.408655-1-git@xen0n.name> References: <20210920080451.408655-1-git@xen0n.name> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.28.160.31 (failed) Received-SPF: pass client-ip=115.28.160.31; envelope-from=git@xen0n.name; helo=mailbox.box.xen0n.name X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 20 Sep 2021 09:57:24 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: WANG Xuerui Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: WANG Xuerui --- configure | 4 +++- meson.build | 4 +++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/configure b/configure index 1043ccce4f..f1bc85e71b 100755 --- a/configure +++ b/configure @@ -659,6 +659,8 @@ elif check_define __arm__ ; then cpu="arm" elif check_define __aarch64__ ; then cpu="aarch64" +elif check_define __loongarch64 ; then + cpu="loongarch64" else cpu=$(uname -m) fi @@ -667,7 +669,7 @@ ARCH= # Normalise host CPU name and set ARCH. # Note that this case should only have supported host CPUs, not guests. case "$cpu" in - ppc|ppc64|s390x|sparc64|x32|riscv32|riscv64) + ppc|ppc64|s390x|sparc64|x32|riscv32|riscv64|loongarch64) ;; ppc64le) ARCH="ppc64" diff --git a/meson.build b/meson.build index 2711cbb789..fb3befead5 100644 --- a/meson.build +++ b/meson.build @@ -57,7 +57,7 @@ python = import('python').find_installation() supported_oses = ['windows', 'freebsd', 'netbsd', 'openbsd', 'darwin', 'sunos', 'linux'] supported_cpus = ['ppc', 'ppc64', 's390x', 'riscv32', 'riscv64', 'x86', 'x86_64', - 'arm', 'aarch64', 'mips', 'mips64', 'sparc', 'sparc64'] + 'arm', 'aarch64', 'loongarch64', 'mips', 'mips64', 'sparc', 'sparc64'] cpu = host_machine.cpu_family() targetos = host_machine.system() @@ -269,6 +269,8 @@ if not get_option('tcg').disabled() tcg_arch = 's390' elif config_host['ARCH'] in ['x86_64', 'x32'] tcg_arch = 'i386' + elif config_host['ARCH'] == 'loongarch64' + tcg_arch = 'loongarch' elif config_host['ARCH'] == 'ppc64' tcg_arch = 'ppc' elif config_host['ARCH'] in ['riscv32', 'riscv64'] From patchwork Mon Sep 20 08:04:50 2021 Content-Type: text/plain; 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Mon, 20 Sep 2021 16:06:20 +0800 (CST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=xen0n.name; s=mail; t=1632125180; bh=fpSQtYgNWkiF6RriJDEQ8PrNe2lg1EUb631GLusOZt4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=pL5trb4eVDiD4aiZefsXPmjdSvjRZo0w5U646z0Aw72F3bNZGyOHFeOelWC+d+2yN gssF+xxBLjk0G32r6bkHT70toZkRjvzTDI33PDdy772VHqSYQHoe9UtW5hPamWrZ+J 3h2/5s/vH2RRroNZtKcwsFzC86cqb90UAGcnNNEA= From: WANG Xuerui To: qemu-devel@nongnu.org Subject: [PATCH 29/30] linux-user: Add host dependency for 64-bit LoongArch Date: Mon, 20 Sep 2021 16:04:50 +0800 Message-Id: <20210920080451.408655-30-git@xen0n.name> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210920080451.408655-1-git@xen0n.name> References: <20210920080451.408655-1-git@xen0n.name> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.28.160.31 (failed) Received-SPF: pass client-ip=115.28.160.31; envelope-from=git@xen0n.name; helo=mailbox.box.xen0n.name X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 20 Sep 2021 09:57:24 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: WANG Xuerui Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Currently nothing special is needed for LoongArch hosts to work, so only leave a placeholder there. Signed-off-by: WANG Xuerui --- linux-user/host/loongarch64/hostdep.h | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 linux-user/host/loongarch64/hostdep.h diff --git a/linux-user/host/loongarch64/hostdep.h b/linux-user/host/loongarch64/hostdep.h new file mode 100644 index 0000000000..4e55695155 --- /dev/null +++ b/linux-user/host/loongarch64/hostdep.h @@ -0,0 +1,11 @@ +/* + * hostdep.h : things which are dependent on the host architecture + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#ifndef LOONGARCH64_HOSTDEP_H +#define LOONGARCH64_HOSTDEP_H + +#endif From patchwork Mon Sep 20 08:04:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: WANG Xuerui X-Patchwork-Id: 12505431 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 44920C433EF for ; Mon, 20 Sep 2021 14:13:13 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id F1BE860F0F for ; Mon, 20 Sep 2021 14:13:12 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org F1BE860F0F Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=xen0n.name Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:60168 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mSK2i-0002Ai-4j for qemu-devel@archiver.kernel.org; Mon, 20 Sep 2021 10:13:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50280) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mSETW-0008RD-L4 for qemu-devel@nongnu.org; Mon, 20 Sep 2021 04:16:31 -0400 Received: from [115.28.160.31] (port=35652 helo=mailbox.box.xen0n.name) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mSETT-0000pY-3u for qemu-devel@nongnu.org; Mon, 20 Sep 2021 04:16:30 -0400 Received: from ld50.lan (unknown [101.88.25.142]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by mailbox.box.xen0n.name (Postfix) with ESMTPSA id 127246340F; Mon, 20 Sep 2021 16:06:22 +0800 (CST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=xen0n.name; s=mail; t=1632125182; bh=0eHzsl2x/Qi54fYRqdqvLO1ukdxYXSVcFQeFmk/nHbA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=f4v3cBl3pSfJ4bTgZaADidgsf0YtpVpfdLBZFCoJAOXMjuiNptoCTmsQItmBuMakf 29SUt4BqAe2NEQeqRLozH24Bjondegr81SYMDbAaSoG5ekeZx1nM9Dc4gOg5Izr9Vz e85um5b5wD7nrD5t1Wyyihz79ggFI0LszLyiOkPI= From: WANG Xuerui To: qemu-devel@nongnu.org Subject: [PATCH 30/30] accel/tcg/user-exec: Implement CPU-specific signal handler for LoongArch hosts Date: Mon, 20 Sep 2021 16:04:51 +0800 Message-Id: <20210920080451.408655-31-git@xen0n.name> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210920080451.408655-1-git@xen0n.name> References: <20210920080451.408655-1-git@xen0n.name> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.28.160.31 (failed) Received-SPF: pass client-ip=115.28.160.31; envelope-from=git@xen0n.name; helo=mailbox.box.xen0n.name X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 20 Sep 2021 09:57:24 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: WANG Xuerui Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: WANG Xuerui --- accel/tcg/user-exec.c | 83 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 83 insertions(+) diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 8fed542622..0f85062e61 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -878,6 +878,89 @@ int cpu_signal_handler(int host_signum, void *pinfo, return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); } +#elif defined(__loongarch__) + +/* + * This logic is bitness-agnostic, so the generic __loongarch__ guard is used + * instead of explicit ones like __loongarch64. + */ + +int cpu_signal_handler(int host_signum, void *pinfo, + void *puc) +{ + siginfo_t *info = pinfo; + ucontext_t *uc = puc; + greg_t pc = uc->uc_mcontext.__pc; + uint32_t insn = *(uint32_t *)pc; + int is_write = 0; + + /* Detect store by reading the instruction at the program counter. */ + switch ((insn >> 26) & 0b111111) { + case 0b001000: /* {ll,sc}.[wd] */ + switch ((insn >> 24) & 0b11) { + case 0b01: /* sc.w */ + case 0b11: /* sc.d */ + is_write = 1; + break; + } + break; + case 0b001001: /* {ld,st}ox4.[wd] ({ld,st}ptr.[wd]) */ + switch ((insn >> 24) & 0b11) { + case 0b01: /* stox4.w (stptr.w) */ + case 0b11: /* stox4.d (stptr.d) */ + is_write = 1; + break; + } + break; + case 0b001010: /* {ld,st}.* family */ + switch ((insn >> 22) & 0b1111) { + case 0b0100: /* st.b */ + case 0b0101: /* st.h */ + case 0b0110: /* st.w */ + case 0b0111: /* st.d */ + case 0b1101: /* fst.s */ + case 0b1111: /* fst.d */ + is_write = 1; + break; + } + break; + case 0b001110: /* indexed, atomic, bounds-checking memory operations */ + uint32_t sel = (insn >> 15) & 0b11111111111; + + switch (sel) { + case 0b00000100000: /* stx.b */ + case 0b00000101000: /* stx.h */ + case 0b00000110000: /* stx.w */ + case 0b00000111000: /* stx.d */ + case 0b00001110000: /* fstx.s */ + case 0b00001111000: /* fstx.d */ + case 0b00011101100: /* fstgt.s */ + case 0b00011101101: /* fstgt.d */ + case 0b00011101110: /* fstle.s */ + case 0b00011101111: /* fstle.d */ + case 0b00011111000: /* stgt.b */ + case 0b00011111001: /* stgt.h */ + case 0b00011111010: /* stgt.w */ + case 0b00011111011: /* stgt.d */ + case 0b00011111100: /* stle.b */ + case 0b00011111101: /* stle.h */ + case 0b00011111110: /* stle.w */ + case 0b00011111111: /* stle.d */ + is_write = 1; + break; + default: + /* test for am* instruction range */ + if (0b00011000000 <= sel && sel <= 0b00011100011) { + is_write = 1; + } + break; + } + break; + } + + return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); +} + #else #error host CPU specific signal handler needed