From patchwork Mon Sep 20 14:19:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 12505573 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B92D2C433F5 for ; Mon, 20 Sep 2021 14:47:06 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 57BC260F70 for ; Mon, 20 Sep 2021 14:47:06 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 57BC260F70 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:51076 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mSKZV-0002dR-FZ for qemu-devel@archiver.kernel.org; Mon, 20 Sep 2021 10:47:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37082) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mSK9c-0002ly-0T for qemu-devel@nongnu.org; Mon, 20 Sep 2021 10:20:20 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]:33763) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mSK9D-0000kH-PT for qemu-devel@nongnu.org; Mon, 20 Sep 2021 10:20:13 -0400 Received: by mail-wr1-x434.google.com with SMTP id t18so30265288wrb.0 for ; Mon, 20 Sep 2021 07:19:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=oJWGG0JdBpLhOwy/LInBc6DCuO9q1gJ124d/ZYIe79E=; b=MhwQMSCdCC/nzqcHe1OdBzaE6Z9wDfyNqo4XgGuinbf8V82HM7Zx0W53AKiwCvb88V Y9I30metp94JWlwHwwyAAFfrthf3VghBioUtipHx1OwG9cvii6HLvLtufbyUAwSuM1in sUbaeaHrPt2XFEXXZIWG/AuAWF8eTkgPOOZbOLBZp+pzrryykWkhXvpQxWfXtJxjWXqs SIeVr/UiUvDaiYoPL0pI1VTsC9u4euHQNKfCdEWZsKJupQI6Q+iPEyCyRvyUwGawx/5C TE6IvDyMiP9ArQ65ILx6r13/jxVIf1DJd1FWK0M9tgn4EsNiCS5sCvUz6/t8KJvGZDz2 AIug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oJWGG0JdBpLhOwy/LInBc6DCuO9q1gJ124d/ZYIe79E=; b=b3YCxbkS0g7PF0QSSvAiFG/6ecP70E7hYrCCsDbn67Lws3IwscbTXhC1L9TgxoG7LH VA1MzlHe51HJIdvjit0sQxFyVPPls25ezVOa7EDA5awesBkAKmFZtnymc7rQNSGSFrPC NWzTX3gOOaPgYU7BTf0uNX9kt9yEEPK57jA+Ny2LCEqR88AC3uvAnW9kTYoY7N8OJ9Kq Y5M8br8MKbIgiveBUtnKh0fK2JPfwrE1CpE/fyzKCHvMdSI5ACFV8J8Ui6o02twaCSIy 2ITn1EPUO+F7AIxaRdhufkKeSwTJaIfooteo0O4EB1pnoyKtgMQfKdHUPSYXkAxM2b2g YYqg== X-Gm-Message-State: AOAM532MhRVonS2egT5/eLqczKWReuJJ5A9b6DPIsOxW2DXrPRdmYF5x 4EL8JlQYauMBwzgJX/Kw2Zyoj/6iTqIOoA== X-Google-Smtp-Source: ABdhPJzp7OTyPVo9nVTA+AEYIq2zUyYz0JDnIwuT2kxmTcHmWIfyixHQyD2wLsXGkkCNKsCG9y8EQA== X-Received: by 2002:adf:8b52:: with SMTP id v18mr28267153wra.1.1632147590109; Mon, 20 Sep 2021 07:19:50 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id n17sm16229693wrp.17.2021.09.20.07.19.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Sep 2021 07:19:49 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/27] elf2dmp: Check curl_easy_setopt() return value Date: Mon, 20 Sep 2021 15:19:21 +0100 Message-Id: <20210920141947.5537-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210920141947.5537-1-peter.maydell@linaro.org> References: <20210920141947.5537-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: 2 X-Spam_score: 0.2 X-Spam_bar: / X-Spam_report: (0.2 / 5.0 requ) DKIM_INVALID=0.1, DKIM_SIGNED=0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Coverity points out that we aren't checking the return value from curl_easy_setopt(). Fixes: Coverity CID 1458895 Inspired-by: Peter Maydell Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Viktor Prutyanov Tested-by: Viktor Prutyanov Message-id: 20210910170656.366592-2-philmd@redhat.com Signed-off-by: Peter Maydell --- contrib/elf2dmp/download.c | 22 ++++++++++------------ 1 file changed, 10 insertions(+), 12 deletions(-) diff --git a/contrib/elf2dmp/download.c b/contrib/elf2dmp/download.c index d09e607431f..bd7650a7a27 100644 --- a/contrib/elf2dmp/download.c +++ b/contrib/elf2dmp/download.c @@ -25,21 +25,19 @@ int download_url(const char *name, const char *url) goto out_curl; } - curl_easy_setopt(curl, CURLOPT_URL, url); - curl_easy_setopt(curl, CURLOPT_WRITEFUNCTION, NULL); - curl_easy_setopt(curl, CURLOPT_WRITEDATA, file); - curl_easy_setopt(curl, CURLOPT_FOLLOWLOCATION, 1); - curl_easy_setopt(curl, CURLOPT_NOPROGRESS, 0); - - if (curl_easy_perform(curl) != CURLE_OK) { - err = 1; - fclose(file); + if (curl_easy_setopt(curl, CURLOPT_URL, url) != CURLE_OK + || curl_easy_setopt(curl, CURLOPT_WRITEFUNCTION, NULL) != CURLE_OK + || curl_easy_setopt(curl, CURLOPT_WRITEDATA, file) != CURLE_OK + || curl_easy_setopt(curl, CURLOPT_FOLLOWLOCATION, 1) != CURLE_OK + || curl_easy_setopt(curl, CURLOPT_NOPROGRESS, 0) != CURLE_OK + || curl_easy_perform(curl) != CURLE_OK) { unlink(name); - goto out_curl; + fclose(file); + err = 1; + } else { + err = fclose(file); } - err = fclose(file); - out_curl: curl_easy_cleanup(curl); From patchwork Mon Sep 20 14:19:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 12505561 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0040AC433F5 for ; Mon, 20 Sep 2021 14:43:20 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 88D0360F6B for ; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n17sm16229693wrp.17.2021.09.20.07.19.50 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Sep 2021 07:19:50 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/27] elf2dmp: Fail cleanly if PDB file specifies zero block_size Date: Mon, 20 Sep 2021 15:19:22 +0100 Message-Id: <20210920141947.5537-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210920141947.5537-1-peter.maydell@linaro.org> References: <20210920141947.5537-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Coverity points out that if the PDB file we're trying to read has a header specifying a block_size of zero then we will end up trying to divide by zero in pdb_ds_read_file(). Check for this and fail cleanly instead. Fixes: Coverity CID 1458869 Signed-off-by: Peter Maydell Reviewed-by: Viktor Prutyanov Signed-off-by: Philippe Mathieu-Daudé Tested-by: Viktor Prutyanov Message-id: 20210910170656.366592-3-philmd@redhat.com Message-Id: <20210901143910.17112-3-peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé --- contrib/elf2dmp/pdb.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/contrib/elf2dmp/pdb.c b/contrib/elf2dmp/pdb.c index b3a65470680..adcfa7e154c 100644 --- a/contrib/elf2dmp/pdb.c +++ b/contrib/elf2dmp/pdb.c @@ -215,6 +215,10 @@ out_symbols: static int pdb_reader_ds_init(struct pdb_reader *r, PDB_DS_HEADER *hdr) { + if (hdr->block_size == 0) { + return 1; + } + memset(r->file_used, 0, sizeof(r->file_used)); r->ds.header = hdr; r->ds.toc = pdb_ds_read(hdr, (uint32_t *)((uint8_t *)hdr + From patchwork Mon Sep 20 14:19:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 12505569 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-23.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D61C7C433F5 for ; Mon, 20 Sep 2021 14:44:09 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 936C361077 for ; Mon, 20 Sep 2021 14:44:09 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 936C361077 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:45130 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mSKWe-00071m-Nc for qemu-devel@archiver.kernel.org; Mon, 20 Sep 2021 10:44:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36910) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mSK9G-0002Zh-Rf for qemu-devel@nongnu.org; Mon, 20 Sep 2021 10:19:58 -0400 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:41508) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mSK9D-0000nD-Ko for qemu-devel@nongnu.org; Mon, 20 Sep 2021 10:19:57 -0400 Received: by mail-wr1-x42b.google.com with SMTP id w29so30193173wra.8 for ; Mon, 20 Sep 2021 07:19:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=pEPR4cXzCE7ylWGFdInCkdZZDyzNIPwfTQoI/xgwREk=; b=Zfn+KPVsf0BiDgxk/ZHSPEsTVhrx/FOyw59F8vGXjBv75WcjzudoMUWJwBdaAZbTaQ r1hshLUDZHq25TTSAl+loNcegwH10QU5EP2Rw2/ujh1NVI3Ct8UeND1LwzO6vXp9t04x 4zcPdEz5NXlAdiDI9GegFztIbMXxP/B2UpnSq5NPkawP87uPEElvW/LUJqVcUh0SDd3S Ns8DSGirgTwagSn7Rjv/SkTmI1eYjuqmxtC7Bs+uB0+BhL7o4VyTqm/bDYkfW89dyWHo 25iMY+bbkoexJFgJr/7nZwr78mTIhhK9S3jJDKEio272DjFcShC0dctklfY0aRVIKsC9 OoAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pEPR4cXzCE7ylWGFdInCkdZZDyzNIPwfTQoI/xgwREk=; b=Fp6K6pNHBSbbgbkiG2Tr8RIwTt+uO8ehjUaxNUbYc6YqYYEH2mtEqNHjAPw2MhVu5G LUL9v19q3SzfvGOdSP5+CwpkF0Do7Wxk/j7gYlGdGpF7Ms1bZ+k8H7aNwS9Q9agxMg1R 8FlhHrmV35X7PDiCVZ4Vhd0sJXpaNXmdfCddvSCLNPHFFWw9w5fldgNaIa2GTDsSLhw7 0tE0FjRSDUR81C/AUOpEkBMfEQwT3JEBLUAfne73h//sKH1ufkpg3MNyztkkzfCHW1wy UU9XCaQlRWz6IQpaMlP8mpTu6c6W/qd4CUxPP964us0gTjfNlihjpMRaeODx7ko9rF6X /MzQ== X-Gm-Message-State: AOAM5326ZR2eCuTCjGrrWXhqLtSnlFGrO/SGmskw6rKIMQhd/xkUNCap U3eTWSMo6WWWfskZFq3or7zBM/L2l9Z4qA== X-Google-Smtp-Source: ABdhPJxpW27aIPsoChkhxJQx6NAgWiUu7roh6q5yey5KiQdnn3pPqN/ADS6v+fb0c+KM23yKd2reTw== X-Received: by 2002:a5d:64c3:: with SMTP id f3mr27643369wri.73.1632147591422; Mon, 20 Sep 2021 07:19:51 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id n17sm16229693wrp.17.2021.09.20.07.19.50 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Sep 2021 07:19:51 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/27] target/arm: Don't skip M-profile reset entirely in user mode Date: Mon, 20 Sep 2021 15:19:23 +0100 Message-Id: <20210920141947.5537-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210920141947.5537-1-peter.maydell@linaro.org> References: <20210920141947.5537-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Currently all of the M-profile specific code in arm_cpu_reset() is inside a !defined(CONFIG_USER_ONLY) ifdef block. This is unintentional: it happened because originally the only M-profile-specific handling was the setup of the initial SP and PC from the vector table, which is system-emulation only. But then we added a lot of other M-profile setup to the same "if (ARM_FEATURE_M)" code block without noticing that it was all inside a not-user-mode ifdef. This has generally been harmless, but with the addition of v8.1M low-overhead-loop support we ran into a problem: the reset of FPSCR.LTPSIZE to 4 was only being done for system emulation mode, so if a user-mode guest tried to execute the LE instruction it would incorrectly take a UsageFault. Adjust the ifdefs so only the really system-emulation specific parts are covered. Because this means we now run some reset code that sets up initial values in the FPCCR and similar FPU related registers, explicitly set up the registers controlling FPU context handling in user-emulation mode so that the FPU works by design and not by chance. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/613 Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20210914120725.24992-2-peter.maydell@linaro.org --- target/arm/cpu.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index ba0741b20e4..3f750d5bfea 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -265,12 +265,15 @@ static void arm_cpu_reset(DeviceState *dev) env->uncached_cpsr = ARM_CPU_MODE_SVC; } env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; +#endif if (arm_feature(env, ARM_FEATURE_M)) { +#ifndef CONFIG_USER_ONLY uint32_t initial_msp; /* Loaded from 0x0 */ uint32_t initial_pc; /* Loaded from 0x4 */ uint8_t *rom; uint32_t vecbase; +#endif if (cpu_isar_feature(aa32_lob, cpu)) { /* @@ -324,6 +327,8 @@ static void arm_cpu_reset(DeviceState *dev) env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK | R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK; } + +#ifndef CONFIG_USER_ONLY /* Unlike A/R profile, M profile defines the reset LR value */ env->regs[14] = 0xffffffff; @@ -352,8 +357,22 @@ static void arm_cpu_reset(DeviceState *dev) env->regs[13] = initial_msp & 0xFFFFFFFC; env->regs[15] = initial_pc & ~1; env->thumb = initial_pc & 1; +#else + /* + * For user mode we run non-secure and with access to the FPU. + * The FPU context is active (ie does not need further setup) + * and is owned by non-secure. + */ + env->v7m.secure = false; + env->v7m.nsacr = 0xcff; + env->v7m.cpacr[M_REG_NS] = 0xf0ffff; + env->v7m.fpccr[M_REG_S] &= + ~(R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK); + env->v7m.control[M_REG_S] |= R_V7M_CONTROL_FPCA_MASK; +#endif } +#ifndef CONFIG_USER_ONLY /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently * executing as AArch32 then check if highvecs are enabled and * adjust the PC accordingly. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n17sm16229693wrp.17.2021.09.20.07.19.51 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Sep 2021 07:19:51 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/27] target/arm: Always clear exclusive monitor on reset Date: Mon, 20 Sep 2021 15:19:24 +0100 Message-Id: <20210920141947.5537-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210920141947.5537-1-peter.maydell@linaro.org> References: <20210920141947.5537-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" There's no particular reason why the exclusive monitor should be only cleared on reset in system emulation mode. It doesn't hurt if it isn't cleared in user mode, but we might as well reduce the amount of code we have that's inside an ifdef. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20210914120725.24992-3-peter.maydell@linaro.org --- target/arm/cpu.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 3f750d5bfea..1dff1d33473 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -381,15 +381,15 @@ static void arm_cpu_reset(DeviceState *dev) env->regs[15] = 0xFFFF0000; } + env->vfp.xregs[ARM_VFP_FPEXC] = 0; +#endif + /* M profile requires that reset clears the exclusive monitor; * A profile does not, but clearing it makes more sense than having it * set with an exclusive access on address zero. */ arm_clear_exclusive(env); - env->vfp.xregs[ARM_VFP_FPEXC] = 0; -#endif - if (arm_feature(env, ARM_FEATURE_PMSA)) { if (cpu->pmsav7_dregion > 0) { if (arm_feature(env, ARM_FEATURE_V8)) { From patchwork Mon Sep 20 14:19:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 12505611 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D51FAC433F5 for ; Mon, 20 Sep 2021 14:56:57 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8612B60F21 for ; Mon, 20 Sep 2021 14:56:57 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 8612B60F21 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:45250 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mSKj2-0000q1-IC for qemu-devel@archiver.kernel.org; Mon, 20 Sep 2021 10:56:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37086) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mSK9c-0002m2-0J for qemu-devel@nongnu.org; Mon, 20 Sep 2021 10:20:20 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]:43831) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mSK9E-0000nK-Pn for qemu-devel@nongnu.org; Mon, 20 Sep 2021 10:20:18 -0400 Received: by mail-wr1-x430.google.com with SMTP id w17so22053370wrv.10 for ; Mon, 20 Sep 2021 07:19:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=88G84b42GJok2EnsSzQ7YM/ll9HQz4JeN74TyzxvSDk=; b=UAsGnl41k3DiDMrdHKhBbMUEJMUhGAKDRtGZUy3Vfh+MW00IxobZGEWrwLd0WVk+TI dexLk+N7jNi63F2ro1VERSFID6BAoKYaBAuj5pnzE+Bx24Oun3la8IDpUbC7LHaO9Yyh CVtXR+krYYf1xkgGDw65KKVjgbj0Nxo/xbFA/UnX8xvsuYPg9AhhvPj0w/nW/as7IZ/R JMXaVOX7+jlivQ0vAfhJldtQv0cC7sWT9u/1n3Z5R31HTs/ZZZDFbJC6J6G9abbSVkuk UG/caeKswZ8T07yqj5pVqPh3cVcxZ+9KAuOHmapRcGvLvUVxX3x49E1EuA1/JY7J6fnP k0LQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=88G84b42GJok2EnsSzQ7YM/ll9HQz4JeN74TyzxvSDk=; b=iDTratSamTF75jhl2hDF0oc2WZWssflkwYZqL1EC1OXbL0KDgNvj9HOA2JMpIq5Cg1 Aj7KDCX243TH7+zBZZ8hdw9lfywPk6CMo8+PLdsFsRT9fZlvldPtW2/2DGhna5mYPblf j5M8HtMrrVOpdX0YuuqRdP+pvhpiotwyn5YK1z8wnG57F7XLiyMU/lDqtLQRlA0TLSeS FtFfMMyVbdy2oW790isEsPBI8xCR+bgiCTOWldX2PQtOPkIKDAxtMloKkfHrYHeD253s pTzl5oEZvpOP1G8T3dSoliNoUMkLYIS/iWMEpsol2hiSIwF0nyHI2W18EqGXvaBrg7++ ITsg== X-Gm-Message-State: AOAM530/cxPFRsZQHEgA3CcbpK8tVwmUdJ7r5rbUXiNnRA7ARFeruYdJ 8B2pO3lLwC6FVmwneBVm/T2oifRwqB8cug== X-Google-Smtp-Source: ABdhPJwUt3RPQQMDsXE060G/DJl1nwzJZK9J8yQs8NTEVdM1RNQAXIAPWcLWj5SXib8lws85vPNWnA== X-Received: by 2002:a5d:4608:: with SMTP id t8mr28825563wrq.136.1632147592840; Mon, 20 Sep 2021 07:19:52 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id n17sm16229693wrp.17.2021.09.20.07.19.52 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Sep 2021 07:19:52 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/27] target/arm: Consolidate ifdef blocks in reset Date: Mon, 20 Sep 2021 15:19:25 +0100 Message-Id: <20210920141947.5537-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210920141947.5537-1-peter.maydell@linaro.org> References: <20210920141947.5537-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Move an ifndef CONFIG_USER_ONLY code block up in arm_cpu_reset() so it can be merged with another earlier one. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20210914120725.24992-4-peter.maydell@linaro.org --- target/arm/cpu.c | 22 ++++++++++------------ 1 file changed, 10 insertions(+), 12 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 1dff1d33473..30e2cb9224d 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -265,6 +265,16 @@ static void arm_cpu_reset(DeviceState *dev) env->uncached_cpsr = ARM_CPU_MODE_SVC; } env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; + + /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently + * executing as AArch32 then check if highvecs are enabled and + * adjust the PC accordingly. + */ + if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { + env->regs[15] = 0xFFFF0000; + } + + env->vfp.xregs[ARM_VFP_FPEXC] = 0; #endif if (arm_feature(env, ARM_FEATURE_M)) { @@ -372,18 +382,6 @@ static void arm_cpu_reset(DeviceState *dev) #endif } -#ifndef CONFIG_USER_ONLY - /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently - * executing as AArch32 then check if highvecs are enabled and - * adjust the PC accordingly. - */ - if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { - env->regs[15] = 0xFFFF0000; - } - - env->vfp.xregs[ARM_VFP_FPEXC] = 0; -#endif - /* M profile requires that reset clears the exclusive monitor; * A profile does not, but clearing it makes more sense than having it * set with an exclusive access on address zero. From patchwork Mon Sep 20 14:19:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 12505557 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E8D4CC433EF for ; Mon, 20 Sep 2021 14:39:06 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9212360F6B for ; Mon, 20 Sep 2021 14:39:06 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 9212360F6B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:33858 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mSKRl-0007pw-Pp for qemu-devel@archiver.kernel.org; Mon, 20 Sep 2021 10:39:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37016) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mSK9S-0002iv-Uj for qemu-devel@nongnu.org; Mon, 20 Sep 2021 10:20:10 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:42993) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mSK9D-0000nQ-PW for qemu-devel@nongnu.org; Mon, 20 Sep 2021 10:20:09 -0400 Received: by mail-wr1-x436.google.com with SMTP id q11so30193545wrr.9 for ; Mon, 20 Sep 2021 07:19:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=habRdyVLAcbkdz94dGzbRaHOGiITwOvcI0H5zqLes+M=; b=LAXhi+fQp1QEnJfqWf+4nrVDwzBSr/p15ugm7iVM/8DSdtSDxLAohIJhCQ4GRKuuAu UY3OT2bzSI6aRtXVmG2fiBD8bWUWlH2WJTskW7erxBPUChpbBGfSQAYZArql4VcG7aod wKGo1fF6D5b58ide8aYg+NYRyiLRyfrEOTEDb65yl/eB0Qm3bQpotkOuD/ZltIDioiXn 8uWtUlyvU/UQIGKI8dO0c7m5osK05Ly8xDpKTgKB5lFEv0h1ORt1+QzXP3tWRIiUOFG9 8VEGyLLdduhYoJH4JAEKCgMzT/Ghl6oLLzdOZ84pkYit5PZtgnVOyVW+/eClCQZVVa62 vvuA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=habRdyVLAcbkdz94dGzbRaHOGiITwOvcI0H5zqLes+M=; b=S/0aHGoxM+n4VHTo15fyLp5YyqJak2M4Mct27uNizcGmA5HI5mEC971CSSvckv0xEp o5yuH+9hzIl8JmYwiAK42RfpZswwlEKhN/7NQ0SaXdXIhaCGO/ahNdm2a6ZA9pT7dtj7 7a/HgJwwfdtd+RvF77Cm/fjRRmIPXvzl/13LGdv8PU62nCOYamWMDwRoCqZRNysPDg1B irNvA++ocxVlBJDQeb7zx2k4juX2RDSYeq28Fb1BagRXl/g7DiCrca7pFGHgomxf9Xwr ph8mu08sIBgz2wcIRalHXT8DCrNsFu1OqmuRYrL+yYWfL8uQvrevdiEbePqepKJ/BHsG RqvQ== X-Gm-Message-State: AOAM533H/jrjbkq1znFi3pzmUB0IoziSWtqQN9JVh2i2nVCd+puW/66Z S+aqPnQL9cmWq2sfMl29lxV3hjz94gE+iQ== X-Google-Smtp-Source: ABdhPJw8BpkqErA9FGifhom3JetaTcbRGKgeLGT6XCd3EQHHoMPOJQal33V5NGcb+UC3tSLKWvQ0og== X-Received: by 2002:a05:600c:4c09:: with SMTP id d9mr16435406wmp.194.1632147593480; Mon, 20 Sep 2021 07:19:53 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id n17sm16229693wrp.17.2021.09.20.07.19.52 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Sep 2021 07:19:53 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/27] hw/intc: Set GIC maintenance interrupt level to only 0 or 1 Date: Mon, 20 Sep 2021 15:19:26 +0100 Message-Id: <20210920141947.5537-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210920141947.5537-1-peter.maydell@linaro.org> References: <20210920141947.5537-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Shashi Mallela During sbsa acs level 3 testing, it is seen that the GIC maintenance interrupts are not triggered and the related test cases fail. This is because we were incorrectly passing the value of the MISR register (from maintenance_interrupt_state()) to qemu_set_irq() as the level argument, whereas the device on the other end of this irq line expects a 0/1 value. Fix the logic to pass a 0/1 level indication, rather than a 0/not-0 value. Fixes: c5fc89b36c0 ("hw/intc/arm_gicv3: Implement gicv3_cpuif_virt_update()") Signed-off-by: Shashi Mallela Reviewed-by: Philippe Mathieu-Daudé Message-id: 20210915205809.59068-1-shashi.mallela@linaro.org [PMM: tweaked commit message; collapsed nested if()s into one] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/intc/arm_gicv3_cpuif.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index 462a35f66eb..3fe5de8ad7d 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -417,8 +417,9 @@ static void gicv3_cpuif_virt_update(GICv3CPUState *cs) } } - if (cs->ich_hcr_el2 & ICH_HCR_EL2_EN) { - maintlevel = maintenance_interrupt_state(cs); + if ((cs->ich_hcr_el2 & ICH_HCR_EL2_EN) && + maintenance_interrupt_state(cs) != 0) { + maintlevel = 1; } trace_gicv3_cpuif_virt_set_irqs(gicv3_redist_affid(cs), fiqlevel, From patchwork Mon Sep 20 14:19:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 12505581 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 25FE8C433F5 for ; Mon, 20 Sep 2021 14:51:13 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 747FA610A3 for ; Mon, 20 Sep 2021 14:51:12 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 747FA610A3 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:60908 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mSKdT-0000jY-Kg for qemu-devel@archiver.kernel.org; Mon, 20 Sep 2021 10:51:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37026) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mSK9U-0002jn-CT for qemu-devel@nongnu.org; Mon, 20 Sep 2021 10:20:17 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]:36366) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mSK9F-0000na-0Q for qemu-devel@nongnu.org; Mon, 20 Sep 2021 10:20:11 -0400 Received: by mail-wr1-x432.google.com with SMTP id g16so30209229wrb.3 for ; Mon, 20 Sep 2021 07:19:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ElpkO5lvR+fOZJJ49bbotftILklqiS7p06HuORoOP0w=; b=YtyZ8FqrH/JAWdvPdtq3pClCqdIv6TwmHl23w/x2IOHnU+7sxSv0W+eG87gglazcZW cYltuEpO36IWRtnNop1n45tWkKWQGr15fcQPXHNXQtL4IA03dGByJxmvbXCZKAFe3l+u /E420YM8r2w8qaZr8ei42QenqSYJPpzK8hCq7lrtmeYzzo6b6gTcoYwJ2m7yQfDCsTXh XzrGsmKMbB5QPQgz1qs0v6L64J/x8QdMDUHEQ3lBItX1rf5iPXwdA6m3j6S8Zpqf8k1i FZPMWb2hvV/UuFDsez3Qwnj+MFu4gL9ZvLQWolLcf4pT/8eoTRb8rHPRa+6fvu+XqOed sxKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ElpkO5lvR+fOZJJ49bbotftILklqiS7p06HuORoOP0w=; b=oeii1XBxXCx9tTqphElMRXxtqt8bcd9gXTP8uNoHSK4HD9LZjsBpnf082rk/AEGhLg jAUye4HKjQ28MNeOTAmhIsIK18zZCZ8PXcWrT+m/k0DUienVccREnhg/yrqmkqqCphCm LF+06oofj/Ktby+xp+kfwDfb9vSO5kaAtu/W2cUkUFsyniksYc6wy4MtB6j3s2ynLUeU fdvpLLguckXkETjCaDpySbFcrt37MzOHJSN0+X23xjbHyQHmjFSS4CXNjimw70I8ut+l kD9G7xQZcwTj36Cx03AZ7DdE/aX9batP/pOAqmU6JMlKvJBTMgzw48MoS/McGwrrQukm Pv8g== X-Gm-Message-State: AOAM533g01Mqhs/+muwvVCnwjrcpB7CacZUFkZz4wgME3nP85yoWUhAB UnFNT+fydZEzRqm/BfXqGBUI7i0f1ALc0g== X-Google-Smtp-Source: ABdhPJwB/fjFmKsYAxbsVUM4xjGbTQTPb3FreOtGrV5F3JI3SivWhVocAKtUr9KluQTTmDYHG3Yjow== X-Received: by 2002:a05:600c:3790:: with SMTP id o16mr29510275wmr.157.1632147594375; Mon, 20 Sep 2021 07:19:54 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id n17sm16229693wrp.17.2021.09.20.07.19.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Sep 2021 07:19:53 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/27] arm: Move PMC register definitions to internals.h Date: Mon, 20 Sep 2021 15:19:27 +0100 Message-Id: <20210920141947.5537-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210920141947.5537-1-peter.maydell@linaro.org> References: <20210920141947.5537-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Alexander Graf We will need PMC register definitions in accel specific code later. Move all constant definitions to common arm headers so we can reuse them. Signed-off-by: Alexander Graf Reviewed-by: Peter Maydell Message-id: 20210916155404.86958-2-agraf@csgraf.de Signed-off-by: Peter Maydell --- target/arm/internals.h | 44 ++++++++++++++++++++++++++++++++++++++++++ target/arm/helper.c | 44 ------------------------------------------ 2 files changed, 44 insertions(+), 44 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index cd2ea8a3883..777f9687648 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1226,4 +1226,48 @@ enum MVEECIState { /* All other values reserved */ }; +/* Definitions for the PMU registers */ +#define PMCRN_MASK 0xf800 +#define PMCRN_SHIFT 11 +#define PMCRLC 0x40 +#define PMCRDP 0x20 +#define PMCRX 0x10 +#define PMCRD 0x8 +#define PMCRC 0x4 +#define PMCRP 0x2 +#define PMCRE 0x1 +/* + * Mask of PMCR bits writeable by guest (not including WO bits like C, P, + * which can be written as 1 to trigger behaviour but which stay RAZ). + */ +#define PMCR_WRITEABLE_MASK (PMCRLC | PMCRDP | PMCRX | PMCRD | PMCRE) + +#define PMXEVTYPER_P 0x80000000 +#define PMXEVTYPER_U 0x40000000 +#define PMXEVTYPER_NSK 0x20000000 +#define PMXEVTYPER_NSU 0x10000000 +#define PMXEVTYPER_NSH 0x08000000 +#define PMXEVTYPER_M 0x04000000 +#define PMXEVTYPER_MT 0x02000000 +#define PMXEVTYPER_EVTCOUNT 0x0000ffff +#define PMXEVTYPER_MASK (PMXEVTYPER_P | PMXEVTYPER_U | PMXEVTYPER_NSK | \ + PMXEVTYPER_NSU | PMXEVTYPER_NSH | \ + PMXEVTYPER_M | PMXEVTYPER_MT | \ + PMXEVTYPER_EVTCOUNT) + +#define PMCCFILTR 0xf8000000 +#define PMCCFILTR_M PMXEVTYPER_M +#define PMCCFILTR_EL0 (PMCCFILTR | PMCCFILTR_M) + +static inline uint32_t pmu_num_counters(CPUARMState *env) +{ + return (env->cp15.c9_pmcr & PMCRN_MASK) >> PMCRN_SHIFT; +} + +/* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */ +static inline uint64_t pmu_counter_mask(CPUARMState *env) +{ + return (1 << 31) | ((1 << pmu_num_counters(env)) - 1); +} + #endif diff --git a/target/arm/helper.c b/target/arm/helper.c index b210da2bc26..21ee94ec2e7 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1114,50 +1114,6 @@ static const ARMCPRegInfo v6_cp_reginfo[] = { REGINFO_SENTINEL }; -/* Definitions for the PMU registers */ -#define PMCRN_MASK 0xf800 -#define PMCRN_SHIFT 11 -#define PMCRLC 0x40 -#define PMCRDP 0x20 -#define PMCRX 0x10 -#define PMCRD 0x8 -#define PMCRC 0x4 -#define PMCRP 0x2 -#define PMCRE 0x1 -/* - * Mask of PMCR bits writeable by guest (not including WO bits like C, P, - * which can be written as 1 to trigger behaviour but which stay RAZ). - */ -#define PMCR_WRITEABLE_MASK (PMCRLC | PMCRDP | PMCRX | PMCRD | PMCRE) - -#define PMXEVTYPER_P 0x80000000 -#define PMXEVTYPER_U 0x40000000 -#define PMXEVTYPER_NSK 0x20000000 -#define PMXEVTYPER_NSU 0x10000000 -#define PMXEVTYPER_NSH 0x08000000 -#define PMXEVTYPER_M 0x04000000 -#define PMXEVTYPER_MT 0x02000000 -#define PMXEVTYPER_EVTCOUNT 0x0000ffff -#define PMXEVTYPER_MASK (PMXEVTYPER_P | PMXEVTYPER_U | PMXEVTYPER_NSK | \ - PMXEVTYPER_NSU | PMXEVTYPER_NSH | \ - PMXEVTYPER_M | PMXEVTYPER_MT | \ - PMXEVTYPER_EVTCOUNT) - -#define PMCCFILTR 0xf8000000 -#define PMCCFILTR_M PMXEVTYPER_M -#define PMCCFILTR_EL0 (PMCCFILTR | PMCCFILTR_M) - -static inline uint32_t pmu_num_counters(CPUARMState *env) -{ - return (env->cp15.c9_pmcr & PMCRN_MASK) >> PMCRN_SHIFT; -} - -/* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */ -static inline uint64_t pmu_counter_mask(CPUARMState *env) -{ - return (1 << 31) | ((1 << pmu_num_counters(env)) - 1); -} - typedef struct pm_event { uint16_t number; /* PMEVTYPER.evtCount is 16 bits wide */ /* If the event is supported on this CPU (used to generate PMCEID[01]) */ From patchwork Mon Sep 20 14:19:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 12505521 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BFAA3C433F5 for ; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n17sm16229693wrp.17.2021.09.20.07.19.54 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Sep 2021 07:19:54 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/27] hvf: Add execute to dirty log permission bitmap Date: Mon, 20 Sep 2021 15:19:28 +0100 Message-Id: <20210920141947.5537-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210920141947.5537-1-peter.maydell@linaro.org> References: <20210920141947.5537-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Alexander Graf Hvf's permission bitmap during and after dirty logging does not include the HV_MEMORY_EXEC permission. At least on Apple Silicon, this leads to instruction faults once dirty logging was enabled. Add the bit to make it work properly. Signed-off-by: Alexander Graf Reviewed-by: Peter Maydell Message-id: 20210916155404.86958-3-agraf@csgraf.de Signed-off-by: Peter Maydell --- accel/hvf/hvf-accel-ops.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/accel/hvf/hvf-accel-ops.c b/accel/hvf/hvf-accel-ops.c index d1691be9896..71cc2fa70fa 100644 --- a/accel/hvf/hvf-accel-ops.c +++ b/accel/hvf/hvf-accel-ops.c @@ -239,12 +239,12 @@ static void hvf_set_dirty_tracking(MemoryRegionSection *section, bool on) if (on) { slot->flags |= HVF_SLOT_LOG; hv_vm_protect((uintptr_t)slot->start, (size_t)slot->size, - HV_MEMORY_READ); + HV_MEMORY_READ | HV_MEMORY_EXEC); /* stop tracking region*/ } else { slot->flags &= ~HVF_SLOT_LOG; hv_vm_protect((uintptr_t)slot->start, (size_t)slot->size, - HV_MEMORY_READ | HV_MEMORY_WRITE); + HV_MEMORY_READ | HV_MEMORY_WRITE | HV_MEMORY_EXEC); } } From patchwork Mon Sep 20 14:19:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 12505585 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8EB1AC433EF for ; Mon, 20 Sep 2021 14:53:25 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 467176112D for ; Mon, 20 Sep 2021 14:53:25 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 467176112D Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:39954 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mSKfc-0005d9-H1 for qemu-devel@archiver.kernel.org; Mon, 20 Sep 2021 10:53:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37078) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mSK9b-0002lq-S9 for qemu-devel@nongnu.org; Mon, 20 Sep 2021 10:20:20 -0400 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]:46775) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mSK9F-0000nt-4V for qemu-devel@nongnu.org; Mon, 20 Sep 2021 10:20:17 -0400 Received: by mail-wr1-x42d.google.com with SMTP id x6so30159139wrv.13 for ; Mon, 20 Sep 2021 07:19:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=sFTdYfwW6b0P/b9Km2EVlduVHBBgi2g9eSVhZ+7nQY8=; b=dz3umfXKJA1R4kKSHzyujB9fmfm28rtMGvLdguF5BN2TvyJ00Yk1Jr9Uips86ucObU TqiLp7Uq5kNtTZ4rnwgZWgiAutvoJ7XhGyqOV4dmqvt2ewEOPr5gj9Cz793gKxx8rclN QYnVjdy13YJhBRiq/nbbU8mUg6/MqLC7AHmSb91RTqI9qY8Be+8kU/CkPCjACPJ72enr 6VqQ8R+2Vkg6cPjLHKmNFJrCyCMwWlZbU9WIAHhDdiYav2sR30BVPd5XZnxPtpswwmUc ycUX0FGLf2cAF2noINjuBzQ9Vf4BN/6eewKGEzjXPRdB75uWfaQTLTguNlwp9o6BpIEr BmWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sFTdYfwW6b0P/b9Km2EVlduVHBBgi2g9eSVhZ+7nQY8=; b=BaQ+549npIq/hFjhmmBoWXhH0hKMQbF3vnRscFLQvjQYmGZnjaMqFM/ra9e5JpKJbB 5nnvMHYoIjB7JOJk/F08Q6DnGm6lJyHxM502GJQ1eapqhRKF3CDdWYEuwGeJIGDY4f/q moY1K3Qt9jsZU11KBd1MTrkIhynSvIdcHeG5TbINi+xeql2DoG3KB9iDzokhEOyUqiZ1 NCVZbFxQaEhieO3123BsBzmQ21WYD+hIBJ4mci+qV8SlxP2IE7+OyTlUzAEj0OMzcWDi zxxmXBSJPidtc+GRfEHUEA3tvBMiRYjmrfNr0P6WfbDsOfSGKvop5J2ZlNfucoXAoofX Nbkg== X-Gm-Message-State: AOAM533dfJQ8zj+4Lsm2E/IzmPDD7Zrc9JY7FbP/agoGP5whkRIj/BJ4 Ub3u6qVjTZ7nedFDYBYFVE4CAd1TvlNNDg== X-Google-Smtp-Source: ABdhPJwvUECHP8OgCPFlPEsdHHALvq0sRHISI1MtIN4+J9IXt5VqX6EKndaF0Jjok1eQ3kMmPiUeTA== X-Received: by 2002:a05:600c:2049:: with SMTP id p9mr13489426wmg.47.1632147595753; Mon, 20 Sep 2021 07:19:55 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id n17sm16229693wrp.17.2021.09.20.07.19.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Sep 2021 07:19:55 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/27] hvf: Introduce hvf_arch_init() callback Date: Mon, 20 Sep 2021 15:19:29 +0100 Message-Id: <20210920141947.5537-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210920141947.5537-1-peter.maydell@linaro.org> References: <20210920141947.5537-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Alexander Graf We will need to install a migration helper for the ARM hvf backend. Let's introduce an arch callback for the overall hvf init chain to do so. Signed-off-by: Alexander Graf Reviewed-by: Peter Maydell Message-id: 20210916155404.86958-4-agraf@csgraf.de Signed-off-by: Peter Maydell --- include/sysemu/hvf_int.h | 1 + accel/hvf/hvf-accel-ops.c | 3 ++- target/i386/hvf/hvf.c | 5 +++++ 3 files changed, 8 insertions(+), 1 deletion(-) diff --git a/include/sysemu/hvf_int.h b/include/sysemu/hvf_int.h index 8b66a4e7d0d..0466106d160 100644 --- a/include/sysemu/hvf_int.h +++ b/include/sysemu/hvf_int.h @@ -48,6 +48,7 @@ struct hvf_vcpu_state { }; void assert_hvf_ok(hv_return_t ret); +int hvf_arch_init(void); int hvf_arch_init_vcpu(CPUState *cpu); void hvf_arch_vcpu_destroy(CPUState *cpu); int hvf_vcpu_exec(CPUState *); diff --git a/accel/hvf/hvf-accel-ops.c b/accel/hvf/hvf-accel-ops.c index 71cc2fa70fa..65d431868fb 100644 --- a/accel/hvf/hvf-accel-ops.c +++ b/accel/hvf/hvf-accel-ops.c @@ -324,7 +324,8 @@ static int hvf_accel_init(MachineState *ms) hvf_state = s; memory_listener_register(&hvf_memory_listener, &address_space_memory); - return 0; + + return hvf_arch_init(); } static void hvf_accel_class_init(ObjectClass *oc, void *data) diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c index 79ba4ed93ab..abef24a9c84 100644 --- a/target/i386/hvf/hvf.c +++ b/target/i386/hvf/hvf.c @@ -206,6 +206,11 @@ static inline bool apic_bus_freq_is_known(CPUX86State *env) return env->apic_bus_freq != 0; } +int hvf_arch_init(void) +{ + return 0; +} + int hvf_arch_init_vcpu(CPUState *cpu) { X86CPU *x86cpu = X86_CPU(cpu); From patchwork Mon Sep 20 14:19:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 12505485 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EFC49C433F5 for ; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n17sm16229693wrp.17.2021.09.20.07.19.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Sep 2021 07:19:56 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/27] hvf: Add Apple Silicon support Date: Mon, 20 Sep 2021 15:19:30 +0100 Message-Id: <20210920141947.5537-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210920141947.5537-1-peter.maydell@linaro.org> References: <20210920141947.5537-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Alexander Graf With Apple Silicon available to the masses, it's a good time to add support for driving its virtualization extensions from QEMU. This patch adds all necessary architecture specific code to get basic VMs working, including save/restore. Known limitations: - WFI handling is missing (follows in later patch) - No watchpoint/breakpoint support Signed-off-by: Alexander Graf Reviewed-by: Roman Bolshakov Reviewed-by: Sergio Lopez Reviewed-by: Peter Maydell Message-id: 20210916155404.86958-5-agraf@csgraf.de Signed-off-by: Peter Maydell --- meson.build | 1 + include/sysemu/hvf_int.h | 10 +- accel/hvf/hvf-accel-ops.c | 9 + target/arm/hvf/hvf.c | 794 ++++++++++++++++++++++++++++++++++++ target/i386/hvf/hvf.c | 5 + MAINTAINERS | 5 + target/arm/hvf/trace-events | 10 + 7 files changed, 833 insertions(+), 1 deletion(-) create mode 100644 target/arm/hvf/hvf.c create mode 100644 target/arm/hvf/trace-events diff --git a/meson.build b/meson.build index 2711cbb789c..baa28d7d62e 100644 --- a/meson.build +++ b/meson.build @@ -2169,6 +2169,7 @@ if have_system or have_user 'accel/tcg', 'hw/core', 'target/arm', + 'target/arm/hvf', 'target/hppa', 'target/i386', 'target/i386/kvm', diff --git a/include/sysemu/hvf_int.h b/include/sysemu/hvf_int.h index 0466106d160..7c245c7b111 100644 --- a/include/sysemu/hvf_int.h +++ b/include/sysemu/hvf_int.h @@ -11,7 +11,11 @@ #ifndef HVF_INT_H #define HVF_INT_H +#ifdef __aarch64__ +#include +#else #include +#endif /* hvf_slot flags */ #define HVF_SLOT_LOG (1 << 0) @@ -40,11 +44,14 @@ struct HVFState { int num_slots; hvf_vcpu_caps *hvf_caps; + uint64_t vtimer_offset; }; extern HVFState *hvf_state; struct hvf_vcpu_state { - int fd; + uint64_t fd; + void *exit; + bool vtimer_masked; }; void assert_hvf_ok(hv_return_t ret); @@ -55,5 +62,6 @@ int hvf_vcpu_exec(CPUState *); hvf_slot *hvf_find_overlap_slot(uint64_t, uint64_t); int hvf_put_registers(CPUState *); int hvf_get_registers(CPUState *); +void hvf_kick_vcpu_thread(CPUState *cpu); #endif diff --git a/accel/hvf/hvf-accel-ops.c b/accel/hvf/hvf-accel-ops.c index 65d431868fb..4f75927a8ef 100644 --- a/accel/hvf/hvf-accel-ops.c +++ b/accel/hvf/hvf-accel-ops.c @@ -60,6 +60,10 @@ HVFState *hvf_state; +#ifdef __aarch64__ +#define HV_VM_DEFAULT NULL +#endif + /* Memory slots */ hvf_slot *hvf_find_overlap_slot(uint64_t start, uint64_t size) @@ -376,7 +380,11 @@ static int hvf_init_vcpu(CPUState *cpu) pthread_sigmask(SIG_BLOCK, NULL, &set); sigdelset(&set, SIG_IPI); +#ifdef __aarch64__ + r = hv_vcpu_create(&cpu->hvf->fd, (hv_vcpu_exit_t **)&cpu->hvf->exit, NULL); +#else r = hv_vcpu_create((hv_vcpuid_t *)&cpu->hvf->fd, HV_VCPU_DEFAULT); +#endif cpu->vcpu_dirty = 1; assert_hvf_ok(r); @@ -452,6 +460,7 @@ static void hvf_accel_ops_class_init(ObjectClass *oc, void *data) AccelOpsClass *ops = ACCEL_OPS_CLASS(oc); ops->create_vcpu_thread = hvf_start_vcpu_thread; + ops->kick_vcpu_thread = hvf_kick_vcpu_thread; ops->synchronize_post_reset = hvf_cpu_synchronize_post_reset; ops->synchronize_post_init = hvf_cpu_synchronize_post_init; diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c new file mode 100644 index 00000000000..f3b4023030a --- /dev/null +++ b/target/arm/hvf/hvf.c @@ -0,0 +1,794 @@ +/* + * QEMU Hypervisor.framework support for Apple Silicon + + * Copyright 2020 Alexander Graf + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + * + */ + +#include "qemu/osdep.h" +#include "qemu-common.h" +#include "qemu/error-report.h" + +#include "sysemu/runstate.h" +#include "sysemu/hvf.h" +#include "sysemu/hvf_int.h" +#include "sysemu/hw_accel.h" + +#include + +#include "exec/address-spaces.h" +#include "hw/irq.h" +#include "qemu/main-loop.h" +#include "sysemu/cpus.h" +#include "target/arm/cpu.h" +#include "target/arm/internals.h" +#include "trace/trace-target_arm_hvf.h" +#include "migration/vmstate.h" + +#define HVF_SYSREG(crn, crm, op0, op1, op2) \ + ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2) +#define PL1_WRITE_MASK 0x4 + +#define SYSREG(op0, op1, crn, crm, op2) \ + ((op0 << 20) | (op2 << 17) | (op1 << 14) | (crn << 10) | (crm << 1)) +#define SYSREG_MASK SYSREG(0x3, 0x7, 0xf, 0xf, 0x7) +#define SYSREG_OSLAR_EL1 SYSREG(2, 0, 1, 0, 4) +#define SYSREG_OSLSR_EL1 SYSREG(2, 0, 1, 1, 4) +#define SYSREG_OSDLR_EL1 SYSREG(2, 0, 1, 3, 4) +#define SYSREG_CNTPCT_EL0 SYSREG(3, 3, 14, 0, 1) + +#define WFX_IS_WFE (1 << 0) + +#define TMR_CTL_ENABLE (1 << 0) +#define TMR_CTL_IMASK (1 << 1) +#define TMR_CTL_ISTATUS (1 << 2) + +typedef struct HVFVTimer { + /* Vtimer value during migration and paused state */ + uint64_t vtimer_val; +} HVFVTimer; + +static HVFVTimer vtimer; + +struct hvf_reg_match { + int reg; + uint64_t offset; +}; + +static const struct hvf_reg_match hvf_reg_match[] = { + { HV_REG_X0, offsetof(CPUARMState, xregs[0]) }, + { HV_REG_X1, offsetof(CPUARMState, xregs[1]) }, + { HV_REG_X2, offsetof(CPUARMState, xregs[2]) }, + { HV_REG_X3, offsetof(CPUARMState, xregs[3]) }, + { HV_REG_X4, offsetof(CPUARMState, xregs[4]) }, + { HV_REG_X5, offsetof(CPUARMState, xregs[5]) }, + { HV_REG_X6, offsetof(CPUARMState, xregs[6]) }, + { HV_REG_X7, offsetof(CPUARMState, xregs[7]) }, + { HV_REG_X8, offsetof(CPUARMState, xregs[8]) }, + { HV_REG_X9, offsetof(CPUARMState, xregs[9]) }, + { HV_REG_X10, offsetof(CPUARMState, xregs[10]) }, + { HV_REG_X11, offsetof(CPUARMState, xregs[11]) }, + { HV_REG_X12, offsetof(CPUARMState, xregs[12]) }, + { HV_REG_X13, offsetof(CPUARMState, xregs[13]) }, + { HV_REG_X14, offsetof(CPUARMState, xregs[14]) }, + { HV_REG_X15, offsetof(CPUARMState, xregs[15]) }, + { HV_REG_X16, offsetof(CPUARMState, xregs[16]) }, + { HV_REG_X17, offsetof(CPUARMState, xregs[17]) }, + { HV_REG_X18, offsetof(CPUARMState, xregs[18]) }, + { HV_REG_X19, offsetof(CPUARMState, xregs[19]) }, + { HV_REG_X20, offsetof(CPUARMState, xregs[20]) }, + { HV_REG_X21, offsetof(CPUARMState, xregs[21]) }, + { HV_REG_X22, offsetof(CPUARMState, xregs[22]) }, + { HV_REG_X23, offsetof(CPUARMState, xregs[23]) }, + { HV_REG_X24, offsetof(CPUARMState, xregs[24]) }, + { HV_REG_X25, offsetof(CPUARMState, xregs[25]) }, + { HV_REG_X26, offsetof(CPUARMState, xregs[26]) }, + { HV_REG_X27, offsetof(CPUARMState, xregs[27]) }, + { HV_REG_X28, offsetof(CPUARMState, xregs[28]) }, + { HV_REG_X29, offsetof(CPUARMState, xregs[29]) }, + { HV_REG_X30, offsetof(CPUARMState, xregs[30]) }, + { HV_REG_PC, offsetof(CPUARMState, pc) }, +}; + +static const struct hvf_reg_match hvf_fpreg_match[] = { + { HV_SIMD_FP_REG_Q0, offsetof(CPUARMState, vfp.zregs[0]) }, + { HV_SIMD_FP_REG_Q1, offsetof(CPUARMState, vfp.zregs[1]) }, + { HV_SIMD_FP_REG_Q2, offsetof(CPUARMState, vfp.zregs[2]) }, + { HV_SIMD_FP_REG_Q3, offsetof(CPUARMState, vfp.zregs[3]) }, + { HV_SIMD_FP_REG_Q4, offsetof(CPUARMState, vfp.zregs[4]) }, + { HV_SIMD_FP_REG_Q5, offsetof(CPUARMState, vfp.zregs[5]) }, + { HV_SIMD_FP_REG_Q6, offsetof(CPUARMState, vfp.zregs[6]) }, + { HV_SIMD_FP_REG_Q7, offsetof(CPUARMState, vfp.zregs[7]) }, + { HV_SIMD_FP_REG_Q8, offsetof(CPUARMState, vfp.zregs[8]) }, + { HV_SIMD_FP_REG_Q9, offsetof(CPUARMState, vfp.zregs[9]) }, + { HV_SIMD_FP_REG_Q10, offsetof(CPUARMState, vfp.zregs[10]) }, + { HV_SIMD_FP_REG_Q11, offsetof(CPUARMState, vfp.zregs[11]) }, + { HV_SIMD_FP_REG_Q12, offsetof(CPUARMState, vfp.zregs[12]) }, + { HV_SIMD_FP_REG_Q13, offsetof(CPUARMState, vfp.zregs[13]) }, + { HV_SIMD_FP_REG_Q14, offsetof(CPUARMState, vfp.zregs[14]) }, + { HV_SIMD_FP_REG_Q15, offsetof(CPUARMState, vfp.zregs[15]) }, + { HV_SIMD_FP_REG_Q16, offsetof(CPUARMState, vfp.zregs[16]) }, + { HV_SIMD_FP_REG_Q17, offsetof(CPUARMState, vfp.zregs[17]) }, + { HV_SIMD_FP_REG_Q18, offsetof(CPUARMState, vfp.zregs[18]) }, + { HV_SIMD_FP_REG_Q19, offsetof(CPUARMState, vfp.zregs[19]) }, + { HV_SIMD_FP_REG_Q20, offsetof(CPUARMState, vfp.zregs[20]) }, + { HV_SIMD_FP_REG_Q21, offsetof(CPUARMState, vfp.zregs[21]) }, + { HV_SIMD_FP_REG_Q22, offsetof(CPUARMState, vfp.zregs[22]) }, + { HV_SIMD_FP_REG_Q23, offsetof(CPUARMState, vfp.zregs[23]) }, + { HV_SIMD_FP_REG_Q24, offsetof(CPUARMState, vfp.zregs[24]) }, + { HV_SIMD_FP_REG_Q25, offsetof(CPUARMState, vfp.zregs[25]) }, + { HV_SIMD_FP_REG_Q26, offsetof(CPUARMState, vfp.zregs[26]) }, + { HV_SIMD_FP_REG_Q27, offsetof(CPUARMState, vfp.zregs[27]) }, + { HV_SIMD_FP_REG_Q28, offsetof(CPUARMState, vfp.zregs[28]) }, + { HV_SIMD_FP_REG_Q29, offsetof(CPUARMState, vfp.zregs[29]) }, + { HV_SIMD_FP_REG_Q30, offsetof(CPUARMState, vfp.zregs[30]) }, + { HV_SIMD_FP_REG_Q31, offsetof(CPUARMState, vfp.zregs[31]) }, +}; + +struct hvf_sreg_match { + int reg; + uint32_t key; + uint32_t cp_idx; +}; + +static struct hvf_sreg_match hvf_sreg_match[] = { + { HV_SYS_REG_DBGBVR0_EL1, HVF_SYSREG(0, 0, 14, 0, 4) }, + { HV_SYS_REG_DBGBCR0_EL1, HVF_SYSREG(0, 0, 14, 0, 5) }, + { HV_SYS_REG_DBGWVR0_EL1, HVF_SYSREG(0, 0, 14, 0, 6) }, + { HV_SYS_REG_DBGWCR0_EL1, HVF_SYSREG(0, 0, 14, 0, 7) }, + + { HV_SYS_REG_DBGBVR1_EL1, HVF_SYSREG(0, 1, 14, 0, 4) }, + { HV_SYS_REG_DBGBCR1_EL1, HVF_SYSREG(0, 1, 14, 0, 5) }, + { HV_SYS_REG_DBGWVR1_EL1, HVF_SYSREG(0, 1, 14, 0, 6) }, + { HV_SYS_REG_DBGWCR1_EL1, HVF_SYSREG(0, 1, 14, 0, 7) }, + + { HV_SYS_REG_DBGBVR2_EL1, HVF_SYSREG(0, 2, 14, 0, 4) }, + { HV_SYS_REG_DBGBCR2_EL1, HVF_SYSREG(0, 2, 14, 0, 5) }, + { HV_SYS_REG_DBGWVR2_EL1, HVF_SYSREG(0, 2, 14, 0, 6) }, + { HV_SYS_REG_DBGWCR2_EL1, HVF_SYSREG(0, 2, 14, 0, 7) }, + + { HV_SYS_REG_DBGBVR3_EL1, HVF_SYSREG(0, 3, 14, 0, 4) }, + { HV_SYS_REG_DBGBCR3_EL1, HVF_SYSREG(0, 3, 14, 0, 5) }, + { HV_SYS_REG_DBGWVR3_EL1, HVF_SYSREG(0, 3, 14, 0, 6) }, + { HV_SYS_REG_DBGWCR3_EL1, HVF_SYSREG(0, 3, 14, 0, 7) }, + + { HV_SYS_REG_DBGBVR4_EL1, HVF_SYSREG(0, 4, 14, 0, 4) }, + { HV_SYS_REG_DBGBCR4_EL1, HVF_SYSREG(0, 4, 14, 0, 5) }, + { HV_SYS_REG_DBGWVR4_EL1, HVF_SYSREG(0, 4, 14, 0, 6) }, + { HV_SYS_REG_DBGWCR4_EL1, HVF_SYSREG(0, 4, 14, 0, 7) }, + + { HV_SYS_REG_DBGBVR5_EL1, HVF_SYSREG(0, 5, 14, 0, 4) }, + { HV_SYS_REG_DBGBCR5_EL1, HVF_SYSREG(0, 5, 14, 0, 5) }, + { HV_SYS_REG_DBGWVR5_EL1, HVF_SYSREG(0, 5, 14, 0, 6) }, + { HV_SYS_REG_DBGWCR5_EL1, HVF_SYSREG(0, 5, 14, 0, 7) }, + + { HV_SYS_REG_DBGBVR6_EL1, HVF_SYSREG(0, 6, 14, 0, 4) }, + { HV_SYS_REG_DBGBCR6_EL1, HVF_SYSREG(0, 6, 14, 0, 5) }, + { HV_SYS_REG_DBGWVR6_EL1, HVF_SYSREG(0, 6, 14, 0, 6) }, + { HV_SYS_REG_DBGWCR6_EL1, HVF_SYSREG(0, 6, 14, 0, 7) }, + + { HV_SYS_REG_DBGBVR7_EL1, HVF_SYSREG(0, 7, 14, 0, 4) }, + { HV_SYS_REG_DBGBCR7_EL1, HVF_SYSREG(0, 7, 14, 0, 5) }, + { HV_SYS_REG_DBGWVR7_EL1, HVF_SYSREG(0, 7, 14, 0, 6) }, + { HV_SYS_REG_DBGWCR7_EL1, HVF_SYSREG(0, 7, 14, 0, 7) }, + + { HV_SYS_REG_DBGBVR8_EL1, HVF_SYSREG(0, 8, 14, 0, 4) }, + { HV_SYS_REG_DBGBCR8_EL1, HVF_SYSREG(0, 8, 14, 0, 5) }, + { HV_SYS_REG_DBGWVR8_EL1, HVF_SYSREG(0, 8, 14, 0, 6) }, + { HV_SYS_REG_DBGWCR8_EL1, HVF_SYSREG(0, 8, 14, 0, 7) }, + + { HV_SYS_REG_DBGBVR9_EL1, HVF_SYSREG(0, 9, 14, 0, 4) }, + { HV_SYS_REG_DBGBCR9_EL1, HVF_SYSREG(0, 9, 14, 0, 5) }, + { HV_SYS_REG_DBGWVR9_EL1, HVF_SYSREG(0, 9, 14, 0, 6) }, + { HV_SYS_REG_DBGWCR9_EL1, HVF_SYSREG(0, 9, 14, 0, 7) }, + + { HV_SYS_REG_DBGBVR10_EL1, HVF_SYSREG(0, 10, 14, 0, 4) }, + { HV_SYS_REG_DBGBCR10_EL1, HVF_SYSREG(0, 10, 14, 0, 5) }, + { HV_SYS_REG_DBGWVR10_EL1, HVF_SYSREG(0, 10, 14, 0, 6) }, + { HV_SYS_REG_DBGWCR10_EL1, HVF_SYSREG(0, 10, 14, 0, 7) }, + + { HV_SYS_REG_DBGBVR11_EL1, HVF_SYSREG(0, 11, 14, 0, 4) }, + { HV_SYS_REG_DBGBCR11_EL1, HVF_SYSREG(0, 11, 14, 0, 5) }, + { HV_SYS_REG_DBGWVR11_EL1, HVF_SYSREG(0, 11, 14, 0, 6) }, + { HV_SYS_REG_DBGWCR11_EL1, HVF_SYSREG(0, 11, 14, 0, 7) }, + + { HV_SYS_REG_DBGBVR12_EL1, HVF_SYSREG(0, 12, 14, 0, 4) }, + { HV_SYS_REG_DBGBCR12_EL1, HVF_SYSREG(0, 12, 14, 0, 5) }, + { HV_SYS_REG_DBGWVR12_EL1, HVF_SYSREG(0, 12, 14, 0, 6) }, + { HV_SYS_REG_DBGWCR12_EL1, HVF_SYSREG(0, 12, 14, 0, 7) }, + + { HV_SYS_REG_DBGBVR13_EL1, HVF_SYSREG(0, 13, 14, 0, 4) }, + { HV_SYS_REG_DBGBCR13_EL1, HVF_SYSREG(0, 13, 14, 0, 5) }, + { HV_SYS_REG_DBGWVR13_EL1, HVF_SYSREG(0, 13, 14, 0, 6) }, + { HV_SYS_REG_DBGWCR13_EL1, HVF_SYSREG(0, 13, 14, 0, 7) }, + + { HV_SYS_REG_DBGBVR14_EL1, HVF_SYSREG(0, 14, 14, 0, 4) }, + { HV_SYS_REG_DBGBCR14_EL1, HVF_SYSREG(0, 14, 14, 0, 5) }, + { HV_SYS_REG_DBGWVR14_EL1, HVF_SYSREG(0, 14, 14, 0, 6) }, + { HV_SYS_REG_DBGWCR14_EL1, HVF_SYSREG(0, 14, 14, 0, 7) }, + + { HV_SYS_REG_DBGBVR15_EL1, HVF_SYSREG(0, 15, 14, 0, 4) }, + { HV_SYS_REG_DBGBCR15_EL1, HVF_SYSREG(0, 15, 14, 0, 5) }, + { HV_SYS_REG_DBGWVR15_EL1, HVF_SYSREG(0, 15, 14, 0, 6) }, + { HV_SYS_REG_DBGWCR15_EL1, HVF_SYSREG(0, 15, 14, 0, 7) }, + +#ifdef SYNC_NO_RAW_REGS + /* + * The registers below are manually synced on init because they are + * marked as NO_RAW. We still list them to make number space sync easier. + */ + { HV_SYS_REG_MDCCINT_EL1, HVF_SYSREG(0, 2, 2, 0, 0) }, + { HV_SYS_REG_MIDR_EL1, HVF_SYSREG(0, 0, 3, 0, 0) }, + { HV_SYS_REG_MPIDR_EL1, HVF_SYSREG(0, 0, 3, 0, 5) }, + { HV_SYS_REG_ID_AA64PFR0_EL1, HVF_SYSREG(0, 4, 3, 0, 0) }, +#endif + { HV_SYS_REG_ID_AA64PFR1_EL1, HVF_SYSREG(0, 4, 3, 0, 2) }, + { HV_SYS_REG_ID_AA64DFR0_EL1, HVF_SYSREG(0, 5, 3, 0, 0) }, + { HV_SYS_REG_ID_AA64DFR1_EL1, HVF_SYSREG(0, 5, 3, 0, 1) }, + { HV_SYS_REG_ID_AA64ISAR0_EL1, HVF_SYSREG(0, 6, 3, 0, 0) }, + { HV_SYS_REG_ID_AA64ISAR1_EL1, HVF_SYSREG(0, 6, 3, 0, 1) }, +#ifdef SYNC_NO_MMFR0 + /* We keep the hardware MMFR0 around. HW limits are there anyway */ + { HV_SYS_REG_ID_AA64MMFR0_EL1, HVF_SYSREG(0, 7, 3, 0, 0) }, +#endif + { HV_SYS_REG_ID_AA64MMFR1_EL1, HVF_SYSREG(0, 7, 3, 0, 1) }, + { HV_SYS_REG_ID_AA64MMFR2_EL1, HVF_SYSREG(0, 7, 3, 0, 2) }, + + { HV_SYS_REG_MDSCR_EL1, HVF_SYSREG(0, 2, 2, 0, 2) }, + { HV_SYS_REG_SCTLR_EL1, HVF_SYSREG(1, 0, 3, 0, 0) }, + { HV_SYS_REG_CPACR_EL1, HVF_SYSREG(1, 0, 3, 0, 2) }, + { HV_SYS_REG_TTBR0_EL1, HVF_SYSREG(2, 0, 3, 0, 0) }, + { HV_SYS_REG_TTBR1_EL1, HVF_SYSREG(2, 0, 3, 0, 1) }, + { HV_SYS_REG_TCR_EL1, HVF_SYSREG(2, 0, 3, 0, 2) }, + + { HV_SYS_REG_APIAKEYLO_EL1, HVF_SYSREG(2, 1, 3, 0, 0) }, + { HV_SYS_REG_APIAKEYHI_EL1, HVF_SYSREG(2, 1, 3, 0, 1) }, + { HV_SYS_REG_APIBKEYLO_EL1, HVF_SYSREG(2, 1, 3, 0, 2) }, + { HV_SYS_REG_APIBKEYHI_EL1, HVF_SYSREG(2, 1, 3, 0, 3) }, + { HV_SYS_REG_APDAKEYLO_EL1, HVF_SYSREG(2, 2, 3, 0, 0) }, + { HV_SYS_REG_APDAKEYHI_EL1, HVF_SYSREG(2, 2, 3, 0, 1) }, + { HV_SYS_REG_APDBKEYLO_EL1, HVF_SYSREG(2, 2, 3, 0, 2) }, + { HV_SYS_REG_APDBKEYHI_EL1, HVF_SYSREG(2, 2, 3, 0, 3) }, + { HV_SYS_REG_APGAKEYLO_EL1, HVF_SYSREG(2, 3, 3, 0, 0) }, + { HV_SYS_REG_APGAKEYHI_EL1, HVF_SYSREG(2, 3, 3, 0, 1) }, + + { HV_SYS_REG_SPSR_EL1, HVF_SYSREG(4, 0, 3, 0, 0) }, + { HV_SYS_REG_ELR_EL1, HVF_SYSREG(4, 0, 3, 0, 1) }, + { HV_SYS_REG_SP_EL0, HVF_SYSREG(4, 1, 3, 0, 0) }, + { HV_SYS_REG_AFSR0_EL1, HVF_SYSREG(5, 1, 3, 0, 0) }, + { HV_SYS_REG_AFSR1_EL1, HVF_SYSREG(5, 1, 3, 0, 1) }, + { HV_SYS_REG_ESR_EL1, HVF_SYSREG(5, 2, 3, 0, 0) }, + { HV_SYS_REG_FAR_EL1, HVF_SYSREG(6, 0, 3, 0, 0) }, + { HV_SYS_REG_PAR_EL1, HVF_SYSREG(7, 4, 3, 0, 0) }, + { HV_SYS_REG_MAIR_EL1, HVF_SYSREG(10, 2, 3, 0, 0) }, + { HV_SYS_REG_AMAIR_EL1, HVF_SYSREG(10, 3, 3, 0, 0) }, + { HV_SYS_REG_VBAR_EL1, HVF_SYSREG(12, 0, 3, 0, 0) }, + { HV_SYS_REG_CONTEXTIDR_EL1, HVF_SYSREG(13, 0, 3, 0, 1) }, + { HV_SYS_REG_TPIDR_EL1, HVF_SYSREG(13, 0, 3, 0, 4) }, + { HV_SYS_REG_CNTKCTL_EL1, HVF_SYSREG(14, 1, 3, 0, 0) }, + { HV_SYS_REG_CSSELR_EL1, HVF_SYSREG(0, 0, 3, 2, 0) }, + { HV_SYS_REG_TPIDR_EL0, HVF_SYSREG(13, 0, 3, 3, 2) }, + { HV_SYS_REG_TPIDRRO_EL0, HVF_SYSREG(13, 0, 3, 3, 3) }, + { HV_SYS_REG_CNTV_CTL_EL0, HVF_SYSREG(14, 3, 3, 3, 1) }, + { HV_SYS_REG_CNTV_CVAL_EL0, HVF_SYSREG(14, 3, 3, 3, 2) }, + { HV_SYS_REG_SP_EL1, HVF_SYSREG(4, 1, 3, 4, 0) }, +}; + +int hvf_get_registers(CPUState *cpu) +{ + ARMCPU *arm_cpu = ARM_CPU(cpu); + CPUARMState *env = &arm_cpu->env; + hv_return_t ret; + uint64_t val; + hv_simd_fp_uchar16_t fpval; + int i; + + for (i = 0; i < ARRAY_SIZE(hvf_reg_match); i++) { + ret = hv_vcpu_get_reg(cpu->hvf->fd, hvf_reg_match[i].reg, &val); + *(uint64_t *)((void *)env + hvf_reg_match[i].offset) = val; + assert_hvf_ok(ret); + } + + for (i = 0; i < ARRAY_SIZE(hvf_fpreg_match); i++) { + ret = hv_vcpu_get_simd_fp_reg(cpu->hvf->fd, hvf_fpreg_match[i].reg, + &fpval); + memcpy((void *)env + hvf_fpreg_match[i].offset, &fpval, sizeof(fpval)); + assert_hvf_ok(ret); + } + + val = 0; + ret = hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_FPCR, &val); + assert_hvf_ok(ret); + vfp_set_fpcr(env, val); + + val = 0; + ret = hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_FPSR, &val); + assert_hvf_ok(ret); + vfp_set_fpsr(env, val); + + ret = hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_CPSR, &val); + assert_hvf_ok(ret); + pstate_write(env, val); + + for (i = 0; i < ARRAY_SIZE(hvf_sreg_match); i++) { + if (hvf_sreg_match[i].cp_idx == -1) { + continue; + } + + ret = hv_vcpu_get_sys_reg(cpu->hvf->fd, hvf_sreg_match[i].reg, &val); + assert_hvf_ok(ret); + + arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx] = val; + } + assert(write_list_to_cpustate(arm_cpu)); + + aarch64_restore_sp(env, arm_current_el(env)); + + return 0; +} + +int hvf_put_registers(CPUState *cpu) +{ + ARMCPU *arm_cpu = ARM_CPU(cpu); + CPUARMState *env = &arm_cpu->env; + hv_return_t ret; + uint64_t val; + hv_simd_fp_uchar16_t fpval; + int i; + + for (i = 0; i < ARRAY_SIZE(hvf_reg_match); i++) { + val = *(uint64_t *)((void *)env + hvf_reg_match[i].offset); + ret = hv_vcpu_set_reg(cpu->hvf->fd, hvf_reg_match[i].reg, val); + assert_hvf_ok(ret); + } + + for (i = 0; i < ARRAY_SIZE(hvf_fpreg_match); i++) { + memcpy(&fpval, (void *)env + hvf_fpreg_match[i].offset, sizeof(fpval)); + ret = hv_vcpu_set_simd_fp_reg(cpu->hvf->fd, hvf_fpreg_match[i].reg, + fpval); + assert_hvf_ok(ret); + } + + ret = hv_vcpu_set_reg(cpu->hvf->fd, HV_REG_FPCR, vfp_get_fpcr(env)); + assert_hvf_ok(ret); + + ret = hv_vcpu_set_reg(cpu->hvf->fd, HV_REG_FPSR, vfp_get_fpsr(env)); + assert_hvf_ok(ret); + + ret = hv_vcpu_set_reg(cpu->hvf->fd, HV_REG_CPSR, pstate_read(env)); + assert_hvf_ok(ret); + + aarch64_save_sp(env, arm_current_el(env)); + + assert(write_cpustate_to_list(arm_cpu, false)); + for (i = 0; i < ARRAY_SIZE(hvf_sreg_match); i++) { + if (hvf_sreg_match[i].cp_idx == -1) { + continue; + } + + val = arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx]; + ret = hv_vcpu_set_sys_reg(cpu->hvf->fd, hvf_sreg_match[i].reg, val); + assert_hvf_ok(ret); + } + + ret = hv_vcpu_set_vtimer_offset(cpu->hvf->fd, hvf_state->vtimer_offset); + assert_hvf_ok(ret); + + return 0; +} + +static void flush_cpu_state(CPUState *cpu) +{ + if (cpu->vcpu_dirty) { + hvf_put_registers(cpu); + cpu->vcpu_dirty = false; + } +} + +static void hvf_set_reg(CPUState *cpu, int rt, uint64_t val) +{ + hv_return_t r; + + flush_cpu_state(cpu); + + if (rt < 31) { + r = hv_vcpu_set_reg(cpu->hvf->fd, HV_REG_X0 + rt, val); + assert_hvf_ok(r); + } +} + +static uint64_t hvf_get_reg(CPUState *cpu, int rt) +{ + uint64_t val = 0; + hv_return_t r; + + flush_cpu_state(cpu); + + if (rt < 31) { + r = hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_X0 + rt, &val); + assert_hvf_ok(r); + } + + return val; +} + +void hvf_arch_vcpu_destroy(CPUState *cpu) +{ +} + +int hvf_arch_init_vcpu(CPUState *cpu) +{ + ARMCPU *arm_cpu = ARM_CPU(cpu); + CPUARMState *env = &arm_cpu->env; + uint32_t sregs_match_len = ARRAY_SIZE(hvf_sreg_match); + uint32_t sregs_cnt = 0; + uint64_t pfr; + hv_return_t ret; + int i; + + env->aarch64 = 1; + asm volatile("mrs %0, cntfrq_el0" : "=r"(arm_cpu->gt_cntfrq_hz)); + + /* Allocate enough space for our sysreg sync */ + arm_cpu->cpreg_indexes = g_renew(uint64_t, arm_cpu->cpreg_indexes, + sregs_match_len); + arm_cpu->cpreg_values = g_renew(uint64_t, arm_cpu->cpreg_values, + sregs_match_len); + arm_cpu->cpreg_vmstate_indexes = g_renew(uint64_t, + arm_cpu->cpreg_vmstate_indexes, + sregs_match_len); + arm_cpu->cpreg_vmstate_values = g_renew(uint64_t, + arm_cpu->cpreg_vmstate_values, + sregs_match_len); + + memset(arm_cpu->cpreg_values, 0, sregs_match_len * sizeof(uint64_t)); + + /* Populate cp list for all known sysregs */ + for (i = 0; i < sregs_match_len; i++) { + const ARMCPRegInfo *ri; + uint32_t key = hvf_sreg_match[i].key; + + ri = get_arm_cp_reginfo(arm_cpu->cp_regs, key); + if (ri) { + assert(!(ri->type & ARM_CP_NO_RAW)); + hvf_sreg_match[i].cp_idx = sregs_cnt; + arm_cpu->cpreg_indexes[sregs_cnt++] = cpreg_to_kvm_id(key); + } else { + hvf_sreg_match[i].cp_idx = -1; + } + } + arm_cpu->cpreg_array_len = sregs_cnt; + arm_cpu->cpreg_vmstate_array_len = sregs_cnt; + + assert(write_cpustate_to_list(arm_cpu, false)); + + /* Set CP_NO_RAW system registers on init */ + ret = hv_vcpu_set_sys_reg(cpu->hvf->fd, HV_SYS_REG_MIDR_EL1, + arm_cpu->midr); + assert_hvf_ok(ret); + + ret = hv_vcpu_set_sys_reg(cpu->hvf->fd, HV_SYS_REG_MPIDR_EL1, + arm_cpu->mp_affinity); + assert_hvf_ok(ret); + + ret = hv_vcpu_get_sys_reg(cpu->hvf->fd, HV_SYS_REG_ID_AA64PFR0_EL1, &pfr); + assert_hvf_ok(ret); + pfr |= env->gicv3state ? (1 << 24) : 0; + ret = hv_vcpu_set_sys_reg(cpu->hvf->fd, HV_SYS_REG_ID_AA64PFR0_EL1, pfr); + assert_hvf_ok(ret); + + /* We're limited to underlying hardware caps, override internal versions */ + ret = hv_vcpu_get_sys_reg(cpu->hvf->fd, HV_SYS_REG_ID_AA64MMFR0_EL1, + &arm_cpu->isar.id_aa64mmfr0); + assert_hvf_ok(ret); + + return 0; +} + +void hvf_kick_vcpu_thread(CPUState *cpu) +{ + hv_vcpus_exit(&cpu->hvf->fd, 1); +} + +static void hvf_raise_exception(CPUState *cpu, uint32_t excp, + uint32_t syndrome) +{ + ARMCPU *arm_cpu = ARM_CPU(cpu); + CPUARMState *env = &arm_cpu->env; + + cpu->exception_index = excp; + env->exception.target_el = 1; + env->exception.syndrome = syndrome; + + arm_cpu_do_interrupt(cpu); +} + +static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt) +{ + ARMCPU *arm_cpu = ARM_CPU(cpu); + CPUARMState *env = &arm_cpu->env; + uint64_t val = 0; + + switch (reg) { + case SYSREG_CNTPCT_EL0: + val = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / + gt_cntfrq_period_ns(arm_cpu); + break; + case SYSREG_OSLSR_EL1: + val = env->cp15.oslsr_el1; + break; + case SYSREG_OSDLR_EL1: + /* Dummy register */ + break; + default: + cpu_synchronize_state(cpu); + trace_hvf_unhandled_sysreg_read(env->pc, reg, + (reg >> 20) & 0x3, + (reg >> 14) & 0x7, + (reg >> 10) & 0xf, + (reg >> 1) & 0xf, + (reg >> 17) & 0x7); + hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); + return 1; + } + + trace_hvf_sysreg_read(reg, + (reg >> 20) & 0x3, + (reg >> 14) & 0x7, + (reg >> 10) & 0xf, + (reg >> 1) & 0xf, + (reg >> 17) & 0x7, + val); + hvf_set_reg(cpu, rt, val); + + return 0; +} + +static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val) +{ + ARMCPU *arm_cpu = ARM_CPU(cpu); + CPUARMState *env = &arm_cpu->env; + + trace_hvf_sysreg_write(reg, + (reg >> 20) & 0x3, + (reg >> 14) & 0x7, + (reg >> 10) & 0xf, + (reg >> 1) & 0xf, + (reg >> 17) & 0x7, + val); + + switch (reg) { + case SYSREG_OSLAR_EL1: + env->cp15.oslsr_el1 = val & 1; + break; + case SYSREG_OSDLR_EL1: + /* Dummy register */ + break; + default: + cpu_synchronize_state(cpu); + trace_hvf_unhandled_sysreg_write(env->pc, reg, + (reg >> 20) & 0x3, + (reg >> 14) & 0x7, + (reg >> 10) & 0xf, + (reg >> 1) & 0xf, + (reg >> 17) & 0x7); + hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); + return 1; + } + + return 0; +} + +static int hvf_inject_interrupts(CPUState *cpu) +{ + if (cpu->interrupt_request & CPU_INTERRUPT_FIQ) { + trace_hvf_inject_fiq(); + hv_vcpu_set_pending_interrupt(cpu->hvf->fd, HV_INTERRUPT_TYPE_FIQ, + true); + } + + if (cpu->interrupt_request & CPU_INTERRUPT_HARD) { + trace_hvf_inject_irq(); + hv_vcpu_set_pending_interrupt(cpu->hvf->fd, HV_INTERRUPT_TYPE_IRQ, + true); + } + + return 0; +} + +static uint64_t hvf_vtimer_val_raw(void) +{ + /* + * mach_absolute_time() returns the vtimer value without the VM + * offset that we define. Add our own offset on top. + */ + return mach_absolute_time() - hvf_state->vtimer_offset; +} + +static void hvf_sync_vtimer(CPUState *cpu) +{ + ARMCPU *arm_cpu = ARM_CPU(cpu); + hv_return_t r; + uint64_t ctl; + bool irq_state; + + if (!cpu->hvf->vtimer_masked) { + /* We will get notified on vtimer changes by hvf, nothing to do */ + return; + } + + r = hv_vcpu_get_sys_reg(cpu->hvf->fd, HV_SYS_REG_CNTV_CTL_EL0, &ctl); + assert_hvf_ok(r); + + irq_state = (ctl & (TMR_CTL_ENABLE | TMR_CTL_IMASK | TMR_CTL_ISTATUS)) == + (TMR_CTL_ENABLE | TMR_CTL_ISTATUS); + qemu_set_irq(arm_cpu->gt_timer_outputs[GTIMER_VIRT], irq_state); + + if (!irq_state) { + /* Timer no longer asserting, we can unmask it */ + hv_vcpu_set_vtimer_mask(cpu->hvf->fd, false); + cpu->hvf->vtimer_masked = false; + } +} + +int hvf_vcpu_exec(CPUState *cpu) +{ + ARMCPU *arm_cpu = ARM_CPU(cpu); + CPUARMState *env = &arm_cpu->env; + hv_vcpu_exit_t *hvf_exit = cpu->hvf->exit; + hv_return_t r; + bool advance_pc = false; + + if (hvf_inject_interrupts(cpu)) { + return EXCP_INTERRUPT; + } + + if (cpu->halted) { + return EXCP_HLT; + } + + flush_cpu_state(cpu); + + qemu_mutex_unlock_iothread(); + assert_hvf_ok(hv_vcpu_run(cpu->hvf->fd)); + + /* handle VMEXIT */ + uint64_t exit_reason = hvf_exit->reason; + uint64_t syndrome = hvf_exit->exception.syndrome; + uint32_t ec = syn_get_ec(syndrome); + + qemu_mutex_lock_iothread(); + switch (exit_reason) { + case HV_EXIT_REASON_EXCEPTION: + /* This is the main one, handle below. */ + break; + case HV_EXIT_REASON_VTIMER_ACTIVATED: + qemu_set_irq(arm_cpu->gt_timer_outputs[GTIMER_VIRT], 1); + cpu->hvf->vtimer_masked = true; + return 0; + case HV_EXIT_REASON_CANCELED: + /* we got kicked, no exit to process */ + return 0; + default: + assert(0); + } + + hvf_sync_vtimer(cpu); + + switch (ec) { + case EC_DATAABORT: { + bool isv = syndrome & ARM_EL_ISV; + bool iswrite = (syndrome >> 6) & 1; + bool s1ptw = (syndrome >> 7) & 1; + uint32_t sas = (syndrome >> 22) & 3; + uint32_t len = 1 << sas; + uint32_t srt = (syndrome >> 16) & 0x1f; + uint64_t val = 0; + + trace_hvf_data_abort(env->pc, hvf_exit->exception.virtual_address, + hvf_exit->exception.physical_address, isv, + iswrite, s1ptw, len, srt); + + assert(isv); + + if (iswrite) { + val = hvf_get_reg(cpu, srt); + address_space_write(&address_space_memory, + hvf_exit->exception.physical_address, + MEMTXATTRS_UNSPECIFIED, &val, len); + } else { + address_space_read(&address_space_memory, + hvf_exit->exception.physical_address, + MEMTXATTRS_UNSPECIFIED, &val, len); + hvf_set_reg(cpu, srt, val); + } + + advance_pc = true; + break; + } + case EC_SYSTEMREGISTERTRAP: { + bool isread = (syndrome >> 0) & 1; + uint32_t rt = (syndrome >> 5) & 0x1f; + uint32_t reg = syndrome & SYSREG_MASK; + uint64_t val; + int ret = 0; + + if (isread) { + ret = hvf_sysreg_read(cpu, reg, rt); + } else { + val = hvf_get_reg(cpu, rt); + ret = hvf_sysreg_write(cpu, reg, val); + } + + advance_pc = !ret; + break; + } + case EC_WFX_TRAP: + advance_pc = true; + break; + case EC_AA64_HVC: + cpu_synchronize_state(cpu); + trace_hvf_unknown_hvc(env->xregs[0]); + /* SMCCC 1.3 section 5.2 says every unknown SMCCC call returns -1 */ + env->xregs[0] = -1; + break; + case EC_AA64_SMC: + cpu_synchronize_state(cpu); + trace_hvf_unknown_smc(env->xregs[0]); + hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); + break; + default: + cpu_synchronize_state(cpu); + trace_hvf_exit(syndrome, ec, env->pc); + error_report("0x%llx: unhandled exception ec=0x%x", env->pc, ec); + } + + if (advance_pc) { + uint64_t pc; + + flush_cpu_state(cpu); + + r = hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_PC, &pc); + assert_hvf_ok(r); + pc += 4; + r = hv_vcpu_set_reg(cpu->hvf->fd, HV_REG_PC, pc); + assert_hvf_ok(r); + } + + return 0; +} + +static const VMStateDescription vmstate_hvf_vtimer = { + .name = "hvf-vtimer", + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT64(vtimer_val, HVFVTimer), + VMSTATE_END_OF_LIST() + }, +}; + +static void hvf_vm_state_change(void *opaque, bool running, RunState state) +{ + HVFVTimer *s = opaque; + + if (running) { + /* Update vtimer offset on all CPUs */ + hvf_state->vtimer_offset = mach_absolute_time() - s->vtimer_val; + cpu_synchronize_all_states(); + } else { + /* Remember vtimer value on every pause */ + s->vtimer_val = hvf_vtimer_val_raw(); + } +} + +int hvf_arch_init(void) +{ + hvf_state->vtimer_offset = mach_absolute_time(); + vmstate_register(NULL, 0, &vmstate_hvf_vtimer, &vtimer); + qemu_add_vm_change_state_handler(hvf_vm_state_change, &vtimer); + return 0; +} diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c index abef24a9c84..33a4e749808 100644 --- a/target/i386/hvf/hvf.c +++ b/target/i386/hvf/hvf.c @@ -206,6 +206,11 @@ static inline bool apic_bus_freq_is_known(CPUX86State *env) return env->apic_bus_freq != 0; } +void hvf_kick_vcpu_thread(CPUState *cpu) +{ + cpus_kick_thread(cpu); +} + int hvf_arch_init(void) { return 0; diff --git a/MAINTAINERS b/MAINTAINERS index 6c20634d630..d7915ec128e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -433,6 +433,11 @@ F: accel/accel-*.c F: accel/Makefile.objs F: accel/stubs/Makefile.objs +Apple Silicon HVF CPUs +M: Alexander Graf +S: Maintained +F: target/arm/hvf/ + X86 HVF CPUs M: Cameron Esfahani M: Roman Bolshakov diff --git a/target/arm/hvf/trace-events b/target/arm/hvf/trace-events new file mode 100644 index 00000000000..db40d54bb22 --- /dev/null +++ b/target/arm/hvf/trace-events @@ -0,0 +1,10 @@ +hvf_unhandled_sysreg_read(uint64_t pc, uint32_t reg, uint32_t op0, uint32_t op1, uint32_t crn, uint32_t crm, uint32_t op2) "unhandled sysreg read at pc=0x%"PRIx64": 0x%08x (op0=%d op1=%d crn=%d crm=%d op2=%d)" +hvf_unhandled_sysreg_write(uint64_t pc, uint32_t reg, uint32_t op0, uint32_t op1, uint32_t crn, uint32_t crm, uint32_t op2) "unhandled sysreg write at pc=0x%"PRIx64": 0x%08x (op0=%d op1=%d crn=%d crm=%d op2=%d)" +hvf_inject_fiq(void) "injecting FIQ" +hvf_inject_irq(void) "injecting IRQ" +hvf_data_abort(uint64_t pc, uint64_t va, uint64_t pa, bool isv, bool iswrite, bool s1ptw, uint32_t len, uint32_t srt) "data abort: [pc=0x%"PRIx64" va=0x%016"PRIx64" pa=0x%016"PRIx64" isv=%d iswrite=%d s1ptw=%d len=%d srt=%d]" +hvf_sysreg_read(uint32_t reg, uint32_t op0, uint32_t op1, uint32_t crn, uint32_t crm, uint32_t op2, uint64_t val) "sysreg read 0x%08x (op0=%d op1=%d crn=%d crm=%d op2=%d) = 0x%016"PRIx64 +hvf_sysreg_write(uint32_t reg, uint32_t op0, uint32_t op1, uint32_t crn, uint32_t crm, uint32_t op2, uint64_t val) "sysreg write 0x%08x (op0=%d op1=%d crn=%d crm=%d op2=%d, val=0x%016"PRIx64")" +hvf_unknown_hvc(uint64_t x0) "unknown HVC! 0x%016"PRIx64 +hvf_unknown_smc(uint64_t x0) "unknown SMC! 0x%016"PRIx64 +hvf_exit(uint64_t syndrome, uint32_t ec, uint64_t pc) "exit: 0x%"PRIx64" [ec=0x%x pc=0x%"PRIx64"]" From patchwork Mon Sep 20 14:19:31 2021 Content-Type: text/plain; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n17sm16229693wrp.17.2021.09.20.07.19.57 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Sep 2021 07:19:57 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/27] arm/hvf: Add a WFI handler Date: Mon, 20 Sep 2021 15:19:31 +0100 Message-Id: <20210920141947.5537-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210920141947.5537-1-peter.maydell@linaro.org> References: <20210920141947.5537-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Peter Collingbourne Sleep on WFI until the VTIMER is due but allow ourselves to be woken up on IPI. In this implementation IPI is blocked on the CPU thread at startup and pselect() is used to atomically unblock the signal and begin sleeping. The signal is sent unconditionally so there's no need to worry about races between actually sleeping and the "we think we're sleeping" state. It may lead to an extra wakeup but that's better than missing it entirely. Signed-off-by: Peter Collingbourne Signed-off-by: Alexander Graf Acked-by: Roman Bolshakov Reviewed-by: Sergio Lopez Message-id: 20210916155404.86958-6-agraf@csgraf.de [agraf: Remove unused 'set' variable, always advance PC on WFX trap, support vm stop / continue operations and cntv offsets] Signed-off-by: Alexander Graf Acked-by: Roman Bolshakov Reviewed-by: Sergio Lopez Signed-off-by: Peter Maydell --- include/sysemu/hvf_int.h | 1 + accel/hvf/hvf-accel-ops.c | 5 +-- target/arm/hvf/hvf.c | 79 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 82 insertions(+), 3 deletions(-) diff --git a/include/sysemu/hvf_int.h b/include/sysemu/hvf_int.h index 7c245c7b111..6545f7cd613 100644 --- a/include/sysemu/hvf_int.h +++ b/include/sysemu/hvf_int.h @@ -52,6 +52,7 @@ struct hvf_vcpu_state { uint64_t fd; void *exit; bool vtimer_masked; + sigset_t unblock_ipi_mask; }; void assert_hvf_ok(hv_return_t ret); diff --git a/accel/hvf/hvf-accel-ops.c b/accel/hvf/hvf-accel-ops.c index 4f75927a8ef..93976f4ecea 100644 --- a/accel/hvf/hvf-accel-ops.c +++ b/accel/hvf/hvf-accel-ops.c @@ -370,15 +370,14 @@ static int hvf_init_vcpu(CPUState *cpu) cpu->hvf = g_malloc0(sizeof(*cpu->hvf)); /* init cpu signals */ - sigset_t set; struct sigaction sigact; memset(&sigact, 0, sizeof(sigact)); sigact.sa_handler = dummy_signal; sigaction(SIG_IPI, &sigact, NULL); - pthread_sigmask(SIG_BLOCK, NULL, &set); - sigdelset(&set, SIG_IPI); + pthread_sigmask(SIG_BLOCK, NULL, &cpu->hvf->unblock_ipi_mask); + sigdelset(&cpu->hvf->unblock_ipi_mask, SIG_IPI); #ifdef __aarch64__ r = hv_vcpu_create(&cpu->hvf->fd, (hv_vcpu_exit_t **)&cpu->hvf->exit, NULL); diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index f3b4023030a..110a9d547d8 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -2,6 +2,7 @@ * QEMU Hypervisor.framework support for Apple Silicon * Copyright 2020 Alexander Graf + * Copyright 2020 Google LLC * * This work is licensed under the terms of the GNU GPL, version 2 or later. * See the COPYING file in the top-level directory. @@ -490,6 +491,7 @@ int hvf_arch_init_vcpu(CPUState *cpu) void hvf_kick_vcpu_thread(CPUState *cpu) { + cpus_kick_thread(cpu); hv_vcpus_exit(&cpu->hvf->fd, 1); } @@ -608,6 +610,80 @@ static uint64_t hvf_vtimer_val_raw(void) return mach_absolute_time() - hvf_state->vtimer_offset; } +static uint64_t hvf_vtimer_val(void) +{ + if (!runstate_is_running()) { + /* VM is paused, the vtimer value is in vtimer.vtimer_val */ + return vtimer.vtimer_val; + } + + return hvf_vtimer_val_raw(); +} + +static void hvf_wait_for_ipi(CPUState *cpu, struct timespec *ts) +{ + /* + * Use pselect to sleep so that other threads can IPI us while we're + * sleeping. + */ + qatomic_mb_set(&cpu->thread_kicked, false); + qemu_mutex_unlock_iothread(); + pselect(0, 0, 0, 0, ts, &cpu->hvf->unblock_ipi_mask); + qemu_mutex_lock_iothread(); +} + +static void hvf_wfi(CPUState *cpu) +{ + ARMCPU *arm_cpu = ARM_CPU(cpu); + struct timespec ts; + hv_return_t r; + uint64_t ctl; + uint64_t cval; + int64_t ticks_to_sleep; + uint64_t seconds; + uint64_t nanos; + uint32_t cntfrq; + + if (cpu->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIQ)) { + /* Interrupt pending, no need to wait */ + return; + } + + r = hv_vcpu_get_sys_reg(cpu->hvf->fd, HV_SYS_REG_CNTV_CTL_EL0, &ctl); + assert_hvf_ok(r); + + if (!(ctl & 1) || (ctl & 2)) { + /* Timer disabled or masked, just wait for an IPI. */ + hvf_wait_for_ipi(cpu, NULL); + return; + } + + r = hv_vcpu_get_sys_reg(cpu->hvf->fd, HV_SYS_REG_CNTV_CVAL_EL0, &cval); + assert_hvf_ok(r); + + ticks_to_sleep = cval - hvf_vtimer_val(); + if (ticks_to_sleep < 0) { + return; + } + + cntfrq = gt_cntfrq_period_ns(arm_cpu); + seconds = muldiv64(ticks_to_sleep, cntfrq, NANOSECONDS_PER_SECOND); + ticks_to_sleep -= muldiv64(seconds, NANOSECONDS_PER_SECOND, cntfrq); + nanos = ticks_to_sleep * cntfrq; + + /* + * Don't sleep for less than the time a context switch would take, + * so that we can satisfy fast timer requests on the same CPU. + * Measurements on M1 show the sweet spot to be ~2ms. + */ + if (!seconds && nanos < (2 * SCALE_MS)) { + return; + } + + ts = (struct timespec) { seconds, nanos }; + hvf_wait_for_ipi(cpu, &ts); +} + static void hvf_sync_vtimer(CPUState *cpu) { ARMCPU *arm_cpu = ARM_CPU(cpu); @@ -728,6 +804,9 @@ int hvf_vcpu_exec(CPUState *cpu) } case EC_WFX_TRAP: advance_pc = true; + if (!(syndrome & WFX_IS_WFE)) { + hvf_wfi(cpu); + } break; case EC_AA64_HVC: cpu_synchronize_state(cpu); From patchwork Mon Sep 20 14:19:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 12505535 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-23.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A1617C433EF for ; Mon, 20 Sep 2021 14:35:10 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2ED5D610CE for ; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n17sm16229693wrp.17.2021.09.20.07.19.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Sep 2021 07:19:58 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/27] hvf: arm: Implement -cpu host Date: Mon, 20 Sep 2021 15:19:32 +0100 Message-Id: <20210920141947.5537-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210920141947.5537-1-peter.maydell@linaro.org> References: <20210920141947.5537-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Now that we have working system register sync, we push more target CPU properties into the virtual machine. That might be useful in some situations, but is not the typical case that users want. So let's add a -cpu host option that allows them to explicitly pass all CPU capabilities of their host CPU into the guest. Signed-off-by: Alexander Graf Acked-by: Roman Bolshakov Reviewed-by: Sergio Lopez Reviewed-by: Peter Maydell Message-id: 20210916155404.86958-7-agraf@csgraf.de [PMM: drop unnecessary #include line from .h file] Signed-off-by: Peter Maydell --- target/arm/cpu.h | 2 + target/arm/hvf_arm.h | 18 +++++++++ target/arm/kvm_arm.h | 2 - target/arm/cpu.c | 13 ++++-- target/arm/hvf/hvf.c | 95 ++++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 124 insertions(+), 6 deletions(-) create mode 100644 target/arm/hvf_arm.h diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 09d90277348..3ed03391a83 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3015,6 +3015,8 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) #define CPU_RESOLVING_TYPE TYPE_ARM_CPU +#define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU + #define cpu_signal_handler cpu_arm_signal_handler #define cpu_list arm_cpu_list diff --git a/target/arm/hvf_arm.h b/target/arm/hvf_arm.h new file mode 100644 index 00000000000..ea238cff83f --- /dev/null +++ b/target/arm/hvf_arm.h @@ -0,0 +1,18 @@ +/* + * QEMU Hypervisor.framework (HVF) support -- ARM specifics + * + * Copyright (c) 2021 Alexander Graf + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + * + */ + +#ifndef QEMU_HVF_ARM_H +#define QEMU_HVF_ARM_H + +#include "cpu.h" + +void hvf_arm_set_cpu_features_from_host(struct ARMCPU *cpu); + +#endif diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 06134549759..b7f78b52154 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -214,8 +214,6 @@ bool kvm_arm_create_scratch_host_vcpu(const uint32_t *cpus_to_try, */ void kvm_arm_destroy_scratch_host_vcpu(int *fdarray); -#define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU - /** * ARMHostCPUFeatures: information about the host CPU (identified * by asking the host kernel) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 30e2cb9224d..1c02b92698b 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -39,6 +39,7 @@ #include "sysemu/tcg.h" #include "sysemu/hw_accel.h" #include "kvm_arm.h" +#include "hvf_arm.h" #include "disas/capstone.h" #include "fpu/softfloat.h" @@ -1417,8 +1418,8 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) * this is the first point where we can report it. */ if (cpu->host_cpu_probe_failed) { - if (!kvm_enabled()) { - error_setg(errp, "The 'host' CPU type can only be used with KVM"); + if (!kvm_enabled() && !hvf_enabled()) { + error_setg(errp, "The 'host' CPU type can only be used with KVM or HVF"); } else { error_setg(errp, "Failed to retrieve host CPU features"); } @@ -2078,15 +2079,19 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data) #endif /* CONFIG_TCG */ } -#ifdef CONFIG_KVM +#if defined(CONFIG_KVM) || defined(CONFIG_HVF) static void arm_host_initfn(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); +#ifdef CONFIG_KVM kvm_arm_set_cpu_features_from_host(cpu); if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { aarch64_add_sve_properties(obj); } +#else + hvf_arm_set_cpu_features_from_host(cpu); +#endif arm_cpu_post_init(obj); } @@ -2146,7 +2151,7 @@ static void arm_cpu_register_types(void) { type_register_static(&arm_cpu_type_info); -#ifdef CONFIG_KVM +#if defined(CONFIG_KVM) || defined(CONFIG_HVF) type_register_static(&host_arm_cpu_type_info); #endif } diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 110a9d547d8..51b7250612f 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -17,6 +17,7 @@ #include "sysemu/hvf.h" #include "sysemu/hvf_int.h" #include "sysemu/hw_accel.h" +#include "hvf_arm.h" #include @@ -54,6 +55,16 @@ typedef struct HVFVTimer { static HVFVTimer vtimer; +typedef struct ARMHostCPUFeatures { + ARMISARegisters isar; + uint64_t features; + uint64_t midr; + uint32_t reset_sctlr; + const char *dtb_compatible; +} ARMHostCPUFeatures; + +static ARMHostCPUFeatures arm_host_cpu_features; + struct hvf_reg_match { int reg; uint64_t offset; @@ -416,6 +427,90 @@ static uint64_t hvf_get_reg(CPUState *cpu, int rt) return val; } +static bool hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) +{ + ARMISARegisters host_isar = {}; + const struct isar_regs { + int reg; + uint64_t *val; + } regs[] = { + { HV_SYS_REG_ID_AA64PFR0_EL1, &host_isar.id_aa64pfr0 }, + { HV_SYS_REG_ID_AA64PFR1_EL1, &host_isar.id_aa64pfr1 }, + { HV_SYS_REG_ID_AA64DFR0_EL1, &host_isar.id_aa64dfr0 }, + { HV_SYS_REG_ID_AA64DFR1_EL1, &host_isar.id_aa64dfr1 }, + { HV_SYS_REG_ID_AA64ISAR0_EL1, &host_isar.id_aa64isar0 }, + { HV_SYS_REG_ID_AA64ISAR1_EL1, &host_isar.id_aa64isar1 }, + { HV_SYS_REG_ID_AA64MMFR0_EL1, &host_isar.id_aa64mmfr0 }, + { HV_SYS_REG_ID_AA64MMFR1_EL1, &host_isar.id_aa64mmfr1 }, + { HV_SYS_REG_ID_AA64MMFR2_EL1, &host_isar.id_aa64mmfr2 }, + }; + hv_vcpu_t fd; + hv_return_t r = HV_SUCCESS; + hv_vcpu_exit_t *exit; + int i; + + ahcf->dtb_compatible = "arm,arm-v8"; + ahcf->features = (1ULL << ARM_FEATURE_V8) | + (1ULL << ARM_FEATURE_NEON) | + (1ULL << ARM_FEATURE_AARCH64) | + (1ULL << ARM_FEATURE_PMU) | + (1ULL << ARM_FEATURE_GENERIC_TIMER); + + /* We set up a small vcpu to extract host registers */ + + if (hv_vcpu_create(&fd, &exit, NULL) != HV_SUCCESS) { + return false; + } + + for (i = 0; i < ARRAY_SIZE(regs); i++) { + r |= hv_vcpu_get_sys_reg(fd, regs[i].reg, regs[i].val); + } + r |= hv_vcpu_get_sys_reg(fd, HV_SYS_REG_MIDR_EL1, &ahcf->midr); + r |= hv_vcpu_destroy(fd); + + ahcf->isar = host_isar; + + /* + * A scratch vCPU returns SCTLR 0, so let's fill our default with the M1 + * boot SCTLR from https://github.com/AsahiLinux/m1n1/issues/97 + */ + ahcf->reset_sctlr = 0x30100180; + /* + * SPAN is disabled by default when SCTLR.SPAN=1. To improve compatibility, + * let's disable it on boot and then allow guest software to turn it on by + * setting it to 0. + */ + ahcf->reset_sctlr |= 0x00800000; + + /* Make sure we don't advertise AArch32 support for EL0/EL1 */ + if ((host_isar.id_aa64pfr0 & 0xff) != 0x11) { + return false; + } + + return r == HV_SUCCESS; +} + +void hvf_arm_set_cpu_features_from_host(ARMCPU *cpu) +{ + if (!arm_host_cpu_features.dtb_compatible) { + if (!hvf_enabled() || + !hvf_arm_get_host_cpu_features(&arm_host_cpu_features)) { + /* + * We can't report this error yet, so flag that we need to + * in arm_cpu_realizefn(). + */ + cpu->host_cpu_probe_failed = true; + return; + } + } + + cpu->dtb_compatible = arm_host_cpu_features.dtb_compatible; + cpu->isar = arm_host_cpu_features.isar; + cpu->env.features = arm_host_cpu_features.features; + cpu->midr = arm_host_cpu_features.midr; + cpu->reset_sctlr = arm_host_cpu_features.reset_sctlr; +} + void hvf_arch_vcpu_destroy(CPUState *cpu) { } From patchwork Mon Sep 20 14:19:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 12505633 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3324C433EF for ; Mon, 20 Sep 2021 15:05:24 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5BA8060F46 for ; Mon, 20 Sep 2021 15:05:24 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 5BA8060F46 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:55656 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mSKrD-000861-GV for qemu-devel@archiver.kernel.org; Mon, 20 Sep 2021 11:05:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37138) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mSK9d-0002pG-JM for qemu-devel@nongnu.org; Mon, 20 Sep 2021 10:20:21 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]:43835) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mSK9J-0000rK-1X for qemu-devel@nongnu.org; Mon, 20 Sep 2021 10:20:21 -0400 Received: by mail-wr1-x432.google.com with SMTP id w17so22054517wrv.10 for ; Mon, 20 Sep 2021 07:20:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ZIUPMhDMQ6U8Anm6yxaUrry91lwAKw8+PAog2/UNjFg=; b=r/oQUH7s/DIP1XO6va9ggBG6PlHzcB1EEgkHZXBdRMhMpS9f+NjEb8/XnHJiFSmHLF vaQURQgMDa7lyTfTRr7VrKUtXZNOJwTzfjpJDIh7VUUD08EUrsBacq0KwOcC/a//PhmT Ubu6EmWfxTprP8Mrw2gKrW58czM8gZlcEwYGF9B3wK2gJEr8tM0/tGZzapFcoCCBcE5t kmz+9xqTA2aMCgCYRQazoTckxe/mcT6bPNbvjGe2kVmkPJEAptOOr93M2dMIW0PEvA1X UwPElO+Lp62nB5B6oS9LY9ydILwteZcpyo1rmcq36kIMTv0slKMtA6IQ8+sRpF3kZHxM wPzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZIUPMhDMQ6U8Anm6yxaUrry91lwAKw8+PAog2/UNjFg=; b=iX8sPYgRV76AlPaLerUggYwrTjQtVd1+rM9SCdZJHr8Yn3FZ+Qwnfno+NHkEiwJwuA P1KoG8KFj7HiUb581MXJQn++HwQi3MkdY3IXAFfEbFdp6az3jito/Zv6BwHXaMjskLDe d+gLuCK+mGCUbbg6QuK41/vJLFGpm3vr5QpWOyN6SEsmgrPPZnaQTnBU7gC+bYGMfEGC 63j9wCQWdvnGLNg0nUTEpYgcK8rvSr8VrpCwrHQpjJM0aJ6hqGJurOPQlCpPiDy291uy fx3KXn7FZVstlV8GtROG1q4GUasNdQ0ZadjrbnNnIRV6cJUg2V1j3SQCmpK9lIwvfVYD E1uw== X-Gm-Message-State: AOAM531FfX1rIQSVCZgc2o8gPnukpEXuos2zapA0lkHW7FV4aoc0SlJd OZ5kuI+fxO56OCEgqfxYjj9ZrDwaVXIvgg== X-Google-Smtp-Source: ABdhPJxiMqZ/ARZyZKv3q3gPn4eNNpq3925VhdysmyUlNBY7FUzhQFHGonYFMivz2m6UmblwYSf1CQ== X-Received: by 2002:adf:e507:: with SMTP id j7mr28970904wrm.103.1632147599717; Mon, 20 Sep 2021 07:19:59 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id n17sm16229693wrp.17.2021.09.20.07.19.59 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Sep 2021 07:19:59 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/27] hvf: arm: Implement PSCI handling Date: Mon, 20 Sep 2021 15:19:33 +0100 Message-Id: <20210920141947.5537-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210920141947.5537-1-peter.maydell@linaro.org> References: <20210920141947.5537-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Alexander Graf We need to handle PSCI calls. Most of the TCG code works for us, but we can simplify it to only handle aa64 mode and we need to handle SUSPEND differently. This patch takes the TCG code as template and duplicates it in HVF. To tell the guest that we support PSCI 0.2 now, update the check in arm_cpu_initfn() as well. Signed-off-by: Alexander Graf Reviewed-by: Sergio Lopez Reviewed-by: Peter Maydell Message-id: 20210916155404.86958-8-agraf@csgraf.de Signed-off-by: Peter Maydell --- target/arm/cpu.c | 4 +- target/arm/hvf/hvf.c | 141 ++++++++++++++++++++++++++++++++++-- target/arm/hvf/trace-events | 1 + 3 files changed, 139 insertions(+), 7 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 1c02b92698b..641a8c2d3d3 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1113,8 +1113,8 @@ static void arm_cpu_initfn(Object *obj) cpu->psci_version = 1; /* By default assume PSCI v0.1 */ cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; - if (tcg_enabled()) { - cpu->psci_version = 2; /* TCG implements PSCI 0.2 */ + if (tcg_enabled() || hvf_enabled()) { + cpu->psci_version = 2; /* TCG and HVF implement PSCI 0.2 */ } } diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 51b7250612f..996f93a69dc 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -25,6 +25,7 @@ #include "hw/irq.h" #include "qemu/main-loop.h" #include "sysemu/cpus.h" +#include "arm-powerctl.h" #include "target/arm/cpu.h" #include "target/arm/internals.h" #include "trace/trace-target_arm_hvf.h" @@ -48,6 +49,8 @@ #define TMR_CTL_IMASK (1 << 1) #define TMR_CTL_ISTATUS (1 << 2) +static void hvf_wfi(CPUState *cpu); + typedef struct HVFVTimer { /* Vtimer value during migration and paused state */ uint64_t vtimer_val; @@ -603,6 +606,117 @@ static void hvf_raise_exception(CPUState *cpu, uint32_t excp, arm_cpu_do_interrupt(cpu); } +static void hvf_psci_cpu_off(ARMCPU *arm_cpu) +{ + int32_t ret = arm_set_cpu_off(arm_cpu->mp_affinity); + assert(ret == QEMU_ARM_POWERCTL_RET_SUCCESS); +} + +/* + * Handle a PSCI call. + * + * Returns 0 on success + * -1 when the PSCI call is unknown, + */ +static bool hvf_handle_psci_call(CPUState *cpu) +{ + ARMCPU *arm_cpu = ARM_CPU(cpu); + CPUARMState *env = &arm_cpu->env; + uint64_t param[4] = { + env->xregs[0], + env->xregs[1], + env->xregs[2], + env->xregs[3] + }; + uint64_t context_id, mpidr; + bool target_aarch64 = true; + CPUState *target_cpu_state; + ARMCPU *target_cpu; + target_ulong entry; + int target_el = 1; + int32_t ret = 0; + + trace_hvf_psci_call(param[0], param[1], param[2], param[3], + arm_cpu->mp_affinity); + + switch (param[0]) { + case QEMU_PSCI_0_2_FN_PSCI_VERSION: + ret = QEMU_PSCI_0_2_RET_VERSION_0_2; + break; + case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE: + ret = QEMU_PSCI_0_2_RET_TOS_MIGRATION_NOT_REQUIRED; /* No trusted OS */ + break; + case QEMU_PSCI_0_2_FN_AFFINITY_INFO: + case QEMU_PSCI_0_2_FN64_AFFINITY_INFO: + mpidr = param[1]; + + switch (param[2]) { + case 0: + target_cpu_state = arm_get_cpu_by_id(mpidr); + if (!target_cpu_state) { + ret = QEMU_PSCI_RET_INVALID_PARAMS; + break; + } + target_cpu = ARM_CPU(target_cpu_state); + + ret = target_cpu->power_state; + break; + default: + /* Everything above affinity level 0 is always on. */ + ret = 0; + } + break; + case QEMU_PSCI_0_2_FN_SYSTEM_RESET: + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); + /* + * QEMU reset and shutdown are async requests, but PSCI + * mandates that we never return from the reset/shutdown + * call, so power the CPU off now so it doesn't execute + * anything further. + */ + hvf_psci_cpu_off(arm_cpu); + break; + case QEMU_PSCI_0_2_FN_SYSTEM_OFF: + qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); + hvf_psci_cpu_off(arm_cpu); + break; + case QEMU_PSCI_0_1_FN_CPU_ON: + case QEMU_PSCI_0_2_FN_CPU_ON: + case QEMU_PSCI_0_2_FN64_CPU_ON: + mpidr = param[1]; + entry = param[2]; + context_id = param[3]; + ret = arm_set_cpu_on(mpidr, entry, context_id, + target_el, target_aarch64); + break; + case QEMU_PSCI_0_1_FN_CPU_OFF: + case QEMU_PSCI_0_2_FN_CPU_OFF: + hvf_psci_cpu_off(arm_cpu); + break; + case QEMU_PSCI_0_1_FN_CPU_SUSPEND: + case QEMU_PSCI_0_2_FN_CPU_SUSPEND: + case QEMU_PSCI_0_2_FN64_CPU_SUSPEND: + /* Affinity levels are not supported in QEMU */ + if (param[1] & 0xfffe0000) { + ret = QEMU_PSCI_RET_INVALID_PARAMS; + break; + } + /* Powerdown is not supported, we always go into WFI */ + env->xregs[0] = 0; + hvf_wfi(cpu); + break; + case QEMU_PSCI_0_1_FN_MIGRATE: + case QEMU_PSCI_0_2_FN_MIGRATE: + ret = QEMU_PSCI_RET_NOT_SUPPORTED; + break; + default: + return false; + } + + env->xregs[0] = ret; + return true; +} + static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt) { ARMCPU *arm_cpu = ARM_CPU(cpu); @@ -905,14 +1019,31 @@ int hvf_vcpu_exec(CPUState *cpu) break; case EC_AA64_HVC: cpu_synchronize_state(cpu); - trace_hvf_unknown_hvc(env->xregs[0]); - /* SMCCC 1.3 section 5.2 says every unknown SMCCC call returns -1 */ - env->xregs[0] = -1; + if (arm_cpu->psci_conduit == QEMU_PSCI_CONDUIT_HVC) { + if (!hvf_handle_psci_call(cpu)) { + trace_hvf_unknown_hvc(env->xregs[0]); + /* SMCCC 1.3 section 5.2 says every unknown SMCCC call returns -1 */ + env->xregs[0] = -1; + } + } else { + trace_hvf_unknown_hvc(env->xregs[0]); + hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); + } break; case EC_AA64_SMC: cpu_synchronize_state(cpu); - trace_hvf_unknown_smc(env->xregs[0]); - hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); + if (arm_cpu->psci_conduit == QEMU_PSCI_CONDUIT_SMC) { + advance_pc = true; + + if (!hvf_handle_psci_call(cpu)) { + trace_hvf_unknown_smc(env->xregs[0]); + /* SMCCC 1.3 section 5.2 says every unknown SMCCC call returns -1 */ + env->xregs[0] = -1; + } + } else { + trace_hvf_unknown_smc(env->xregs[0]); + hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); + } break; default: cpu_synchronize_state(cpu); diff --git a/target/arm/hvf/trace-events b/target/arm/hvf/trace-events index db40d54bb22..820e8e02979 100644 --- a/target/arm/hvf/trace-events +++ b/target/arm/hvf/trace-events @@ -8,3 +8,4 @@ hvf_sysreg_write(uint32_t reg, uint32_t op0, uint32_t op1, uint32_t crn, uint32_ hvf_unknown_hvc(uint64_t x0) "unknown HVC! 0x%016"PRIx64 hvf_unknown_smc(uint64_t x0) "unknown SMC! 0x%016"PRIx64 hvf_exit(uint64_t syndrome, uint32_t ec, uint64_t pc) "exit: 0x%"PRIx64" [ec=0x%x pc=0x%"PRIx64"]" +hvf_psci_call(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3, uint32_t cpuid) "PSCI Call x0=0x%016"PRIx64" x1=0x%016"PRIx64" x2=0x%016"PRIx64" x3=0x%016"PRIx64" cpu=0x%x" From patchwork Mon Sep 20 14:19:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 12505543 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2D393C433F5 for ; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n17sm16229693wrp.17.2021.09.20.07.19.59 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Sep 2021 07:20:00 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/27] arm: Add Hypervisor.framework build target Date: Mon, 20 Sep 2021 15:19:34 +0100 Message-Id: <20210920141947.5537-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210920141947.5537-1-peter.maydell@linaro.org> References: <20210920141947.5537-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Alexander Graf Now that we have all logic in place that we need to handle Hypervisor.framework on Apple Silicon systems, let's add CONFIG_HVF for aarch64 as well so that we can build it. Signed-off-by: Alexander Graf Reviewed-by: Roman Bolshakov Tested-by: Roman Bolshakov (x86 only) Reviewed-by: Peter Maydell Reviewed-by: Sergio Lopez Message-id: 20210916155404.86958-9-agraf@csgraf.de Signed-off-by: Peter Maydell --- meson.build | 7 +++++++ target/arm/hvf/meson.build | 3 +++ target/arm/meson.build | 2 ++ 3 files changed, 12 insertions(+) create mode 100644 target/arm/hvf/meson.build diff --git a/meson.build b/meson.build index baa28d7d62e..15ef4d3c418 100644 --- a/meson.build +++ b/meson.build @@ -77,6 +77,13 @@ else endif accelerator_targets = { 'CONFIG_KVM': kvm_targets } + +if cpu in ['aarch64'] + accelerator_targets += { + 'CONFIG_HVF': ['aarch64-softmmu'] + } +endif + if cpu in ['x86', 'x86_64', 'arm', 'aarch64'] # i386 emulator provides xenpv machine type for multiple architectures accelerator_targets += { diff --git a/target/arm/hvf/meson.build b/target/arm/hvf/meson.build new file mode 100644 index 00000000000..855e6cce5ab --- /dev/null +++ b/target/arm/hvf/meson.build @@ -0,0 +1,3 @@ +arm_softmmu_ss.add(when: [hvf, 'CONFIG_HVF'], if_true: files( + 'hvf.c', +)) diff --git a/target/arm/meson.build b/target/arm/meson.build index 25a02bf2769..50f152214af 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -60,5 +60,7 @@ arm_softmmu_ss.add(files( 'psci.c', )) +subdir('hvf') + target_arch += {'arm': arm_ss} target_softmmu_arch += {'arm': arm_softmmu_ss} From patchwork Mon Sep 20 14:19:35 2021 Content-Type: text/plain; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n17sm16229693wrp.17.2021.09.20.07.20.00 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Sep 2021 07:20:00 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/27] hvf: arm: Add rudimentary PMC support Date: Mon, 20 Sep 2021 15:19:35 +0100 Message-Id: <20210920141947.5537-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210920141947.5537-1-peter.maydell@linaro.org> References: <20210920141947.5537-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Alexander Graf We can expose cycle counters on the PMU easily. To be as compatible as possible, let's do so, but make sure we don't expose any other architectural counters that we can not model yet. This allows OSs to work that require PMU support. Signed-off-by: Alexander Graf Reviewed-by: Peter Maydell Message-id: 20210916155404.86958-10-agraf@csgraf.de Signed-off-by: Peter Maydell --- target/arm/hvf/hvf.c | 179 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 179 insertions(+) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 996f93a69dc..bff3e0cde7c 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -42,6 +42,18 @@ #define SYSREG_OSLSR_EL1 SYSREG(2, 0, 1, 1, 4) #define SYSREG_OSDLR_EL1 SYSREG(2, 0, 1, 3, 4) #define SYSREG_CNTPCT_EL0 SYSREG(3, 3, 14, 0, 1) +#define SYSREG_PMCR_EL0 SYSREG(3, 3, 9, 12, 0) +#define SYSREG_PMUSERENR_EL0 SYSREG(3, 3, 9, 14, 0) +#define SYSREG_PMCNTENSET_EL0 SYSREG(3, 3, 9, 12, 1) +#define SYSREG_PMCNTENCLR_EL0 SYSREG(3, 3, 9, 12, 2) +#define SYSREG_PMINTENCLR_EL1 SYSREG(3, 0, 9, 14, 2) +#define SYSREG_PMOVSCLR_EL0 SYSREG(3, 3, 9, 12, 3) +#define SYSREG_PMSWINC_EL0 SYSREG(3, 3, 9, 12, 4) +#define SYSREG_PMSELR_EL0 SYSREG(3, 3, 9, 12, 5) +#define SYSREG_PMCEID0_EL0 SYSREG(3, 3, 9, 12, 6) +#define SYSREG_PMCEID1_EL0 SYSREG(3, 3, 9, 12, 7) +#define SYSREG_PMCCNTR_EL0 SYSREG(3, 3, 9, 13, 0) +#define SYSREG_PMCCFILTR_EL0 SYSREG(3, 3, 14, 15, 7) #define WFX_IS_WFE (1 << 0) @@ -728,6 +740,40 @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt) val = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / gt_cntfrq_period_ns(arm_cpu); break; + case SYSREG_PMCR_EL0: + val = env->cp15.c9_pmcr; + break; + case SYSREG_PMCCNTR_EL0: + pmu_op_start(env); + val = env->cp15.c15_ccnt; + pmu_op_finish(env); + break; + case SYSREG_PMCNTENCLR_EL0: + val = env->cp15.c9_pmcnten; + break; + case SYSREG_PMOVSCLR_EL0: + val = env->cp15.c9_pmovsr; + break; + case SYSREG_PMSELR_EL0: + val = env->cp15.c9_pmselr; + break; + case SYSREG_PMINTENCLR_EL1: + val = env->cp15.c9_pminten; + break; + case SYSREG_PMCCFILTR_EL0: + val = env->cp15.pmccfiltr_el0; + break; + case SYSREG_PMCNTENSET_EL0: + val = env->cp15.c9_pmcnten; + break; + case SYSREG_PMUSERENR_EL0: + val = env->cp15.c9_pmuserenr; + break; + case SYSREG_PMCEID0_EL0: + case SYSREG_PMCEID1_EL0: + /* We can't really count anything yet, declare all events invalid */ + val = 0; + break; case SYSREG_OSLSR_EL1: val = env->cp15.oslsr_el1; break; @@ -758,6 +804,82 @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt) return 0; } +static void pmu_update_irq(CPUARMState *env) +{ + ARMCPU *cpu = env_archcpu(env); + qemu_set_irq(cpu->pmu_interrupt, (env->cp15.c9_pmcr & PMCRE) && + (env->cp15.c9_pminten & env->cp15.c9_pmovsr)); +} + +static bool pmu_event_supported(uint16_t number) +{ + return false; +} + +/* Returns true if the counter (pass 31 for PMCCNTR) should count events using + * the current EL, security state, and register configuration. + */ +static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter) +{ + uint64_t filter; + bool enabled, filtered = true; + int el = arm_current_el(env); + + enabled = (env->cp15.c9_pmcr & PMCRE) && + (env->cp15.c9_pmcnten & (1 << counter)); + + if (counter == 31) { + filter = env->cp15.pmccfiltr_el0; + } else { + filter = env->cp15.c14_pmevtyper[counter]; + } + + if (el == 0) { + filtered = filter & PMXEVTYPER_U; + } else if (el == 1) { + filtered = filter & PMXEVTYPER_P; + } + + if (counter != 31) { + /* + * If not checking PMCCNTR, ensure the counter is setup to an event we + * support + */ + uint16_t event = filter & PMXEVTYPER_EVTCOUNT; + if (!pmu_event_supported(event)) { + return false; + } + } + + return enabled && !filtered; +} + +static void pmswinc_write(CPUARMState *env, uint64_t value) +{ + unsigned int i; + for (i = 0; i < pmu_num_counters(env); i++) { + /* Increment a counter's count iff: */ + if ((value & (1 << i)) && /* counter's bit is set */ + /* counter is enabled and not filtered */ + pmu_counter_enabled(env, i) && + /* counter is SW_INCR */ + (env->cp15.c14_pmevtyper[i] & PMXEVTYPER_EVTCOUNT) == 0x0) { + /* + * Detect if this write causes an overflow since we can't predict + * PMSWINC overflows like we can for other events + */ + uint32_t new_pmswinc = env->cp15.c14_pmevcntr[i] + 1; + + if (env->cp15.c14_pmevcntr[i] & ~new_pmswinc & INT32_MIN) { + env->cp15.c9_pmovsr |= (1 << i); + pmu_update_irq(env); + } + + env->cp15.c14_pmevcntr[i] = new_pmswinc; + } + } +} + static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val) { ARMCPU *arm_cpu = ARM_CPU(cpu); @@ -772,6 +894,63 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val) val); switch (reg) { + case SYSREG_PMCCNTR_EL0: + pmu_op_start(env); + env->cp15.c15_ccnt = val; + pmu_op_finish(env); + break; + case SYSREG_PMCR_EL0: + pmu_op_start(env); + + if (val & PMCRC) { + /* The counter has been reset */ + env->cp15.c15_ccnt = 0; + } + + if (val & PMCRP) { + unsigned int i; + for (i = 0; i < pmu_num_counters(env); i++) { + env->cp15.c14_pmevcntr[i] = 0; + } + } + + env->cp15.c9_pmcr &= ~PMCR_WRITEABLE_MASK; + env->cp15.c9_pmcr |= (val & PMCR_WRITEABLE_MASK); + + pmu_op_finish(env); + break; + case SYSREG_PMUSERENR_EL0: + env->cp15.c9_pmuserenr = val & 0xf; + break; + case SYSREG_PMCNTENSET_EL0: + env->cp15.c9_pmcnten |= (val & pmu_counter_mask(env)); + break; + case SYSREG_PMCNTENCLR_EL0: + env->cp15.c9_pmcnten &= ~(val & pmu_counter_mask(env)); + break; + case SYSREG_PMINTENCLR_EL1: + pmu_op_start(env); + env->cp15.c9_pminten |= val; + pmu_op_finish(env); + break; + case SYSREG_PMOVSCLR_EL0: + pmu_op_start(env); + env->cp15.c9_pmovsr &= ~val; + pmu_op_finish(env); + break; + case SYSREG_PMSWINC_EL0: + pmu_op_start(env); + pmswinc_write(env, val); + pmu_op_finish(env); + break; + case SYSREG_PMSELR_EL0: + env->cp15.c9_pmselr = val & 0x1f; + break; + case SYSREG_PMCCFILTR_EL0: + pmu_op_start(env); + env->cp15.pmccfiltr_el0 = val & PMCCFILTR_EL0; + pmu_op_finish(env); + break; case SYSREG_OSLAR_EL1: env->cp15.oslsr_el1 = val & 1; break; From patchwork Mon Sep 20 14:19:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 12505541 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 248AFC433F5 for ; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n17sm16229693wrp.17.2021.09.20.07.20.01 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Sep 2021 07:20:01 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 16/27] target/arm: Avoid goto_tb if we're trying to exit to the main loop Date: Mon, 20 Sep 2021 15:19:36 +0100 Message-Id: <20210920141947.5537-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210920141947.5537-1-peter.maydell@linaro.org> References: <20210920141947.5537-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Currently gen_jmp_tb() assumes that if it is called then the jump it is handling is the only reason that we might be trying to end the TB, so it will use goto_tb if it can. This is usually the case: mostly "we did something that means we must end the TB" happens on a non-branch instruction. However, there are cases where we decide early in handling an instruction that we need to end the TB and return to the main loop, and then the insn is a complex one that involves gen_jmp_tb(). For instance, for M-profile FP instructions, in gen_preserve_fp_state() which is called from vfp_access_check() we want to force an exit to the main loop if lazy state preservation is active and we are in icount mode. Make gen_jmp_tb() look at the current value of is_jmp, and only use goto_tb if the previous is_jmp was DISAS_NEXT or DISAS_TOO_MANY. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20210913095440.13462-2-peter.maydell@linaro.org --- target/arm/translate.c | 34 +++++++++++++++++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index caefb1e1a17..cf31e0237da 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -2610,8 +2610,40 @@ static inline void gen_jmp_tb(DisasContext *s, uint32_t dest, int tbno) /* An indirect jump so that we still trigger the debug exception. */ gen_set_pc_im(s, dest); s->base.is_jmp = DISAS_JUMP; - } else { + return; + } + switch (s->base.is_jmp) { + case DISAS_NEXT: + case DISAS_TOO_MANY: + case DISAS_NORETURN: + /* + * The normal case: just go to the destination TB. + * NB: NORETURN happens if we generate code like + * gen_brcondi(l); + * gen_jmp(); + * gen_set_label(l); + * gen_jmp(); + * on the second call to gen_jmp(). + */ gen_goto_tb(s, tbno, dest); + break; + case DISAS_UPDATE_NOCHAIN: + case DISAS_UPDATE_EXIT: + /* + * We already decided we're leaving the TB for some other reason. + * Avoid using goto_tb so we really do exit back to the main loop + * and don't chain to another TB. + */ + gen_set_pc_im(s, dest); + gen_goto_ptr(); + s->base.is_jmp = DISAS_NORETURN; + break; + default: + /* + * We shouldn't be emitting code for a jump and also have + * is_jmp set to one of the special cases like DISAS_SWI. + */ + g_assert_not_reached(); } } From patchwork Mon Sep 20 14:19:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 12505609 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2D263C433EF for ; Mon, 20 Sep 2021 14:55:52 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BCC6C60F46 for ; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n17sm16229693wrp.17.2021.09.20.07.20.02 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Sep 2021 07:20:02 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/27] target/arm: Enforce that FPDSCR.LTPSIZE is 4 on inbound migration Date: Mon, 20 Sep 2021 15:19:37 +0100 Message-Id: <20210920141947.5537-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210920141947.5537-1-peter.maydell@linaro.org> References: <20210920141947.5537-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Architecturally, for an M-profile CPU with the LOB feature the LTPSIZE field in FPDSCR is always constant 4. QEMU's implementation enforces this everywhere, except that we don't check that it is true in incoming migration data. We're going to add come in gen_update_fp_context() which relies on the "always 4" property. Since this is TCG-only, we don't actually need to be robust to bogus incoming migration data, and the effect of it being wrong would be wrong code generation rather than a QEMU crash; but if it did ever happen somehow it would be very difficult to track down the cause. Add a check so that we fail the inbound migration if the FPDSCR.LTPSIZE value is incorrect. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20210913095440.13462-3-peter.maydell@linaro.org --- target/arm/machine.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/target/arm/machine.c b/target/arm/machine.c index 81e30de8243..c74d8c3f4b3 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -781,6 +781,19 @@ static int cpu_post_load(void *opaque, int version_id) hw_breakpoint_update_all(cpu); hw_watchpoint_update_all(cpu); + /* + * TCG gen_update_fp_context() relies on the invariant that + * FPDSCR.LTPSIZE is constant 4 for M-profile with the LOB extension; + * forbid bogus incoming data with some other value. + */ + if (arm_feature(env, ARM_FEATURE_M) && cpu_isar_feature(aa32_lob, cpu)) { + if (extract32(env->v7m.fpdscr[M_REG_NS], + FPCR_LTPSIZE_SHIFT, FPCR_LTPSIZE_LENGTH) != 4 || + extract32(env->v7m.fpdscr[M_REG_S], + FPCR_LTPSIZE_SHIFT, FPCR_LTPSIZE_LENGTH) != 4) { + return -1; + } + } if (!kvm_enabled()) { pmu_op_finish(&cpu->env); } From patchwork Mon Sep 20 14:19:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 12505525 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 87E29C433F5 for ; Mon, 20 Sep 2021 14:33:51 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2F445610A0 for ; Mon, 20 Sep 2021 14:33:51 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 2F445610A0 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:45922 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mSKMg-0005Rc-51 for qemu-devel@archiver.kernel.org; Mon, 20 Sep 2021 10:33:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37276) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mSK9n-0002th-Df for qemu-devel@nongnu.org; Mon, 20 Sep 2021 10:20:33 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]:43838) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mSK9O-0000u8-Fb for qemu-devel@nongnu.org; Mon, 20 Sep 2021 10:20:30 -0400 Received: by mail-wr1-x434.google.com with SMTP id w17so22055097wrv.10 for ; Mon, 20 Sep 2021 07:20:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=o5PulC3UfG2fXZMjoQaIDpmO3fx5HN63LPJa8IhBcgk=; b=f/KWzlGaHJXlRY81BFBOINeuurgUY3rVcXKu7nZeMM1ipelIX1n6um3vyPsHWcpJhP g+PnagznFqOfbgFQtFoq8KJ0MtWi9k1+UfNAapzgtSuDyPdpH//5yEz0v5c6vIU1h1eD JWP8rir40h5AYLb82nEDJfrs574wf4mW0cJCxtURni9GDw45U0/bU7CXdcXFWg/K+f2Y KonDJcPivB3iq+hgDTA3ALmtJIaaxIjgcXnQgFJbvDe54vSSza4TkC/t/OaYRptZkX+Y pHjbiNtcv/MhoLz4Pw1aRdy9YUkCgfRlJkY1bN0APMj64etNXxyhiFMG78Odfs6In7sR xffg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=o5PulC3UfG2fXZMjoQaIDpmO3fx5HN63LPJa8IhBcgk=; b=0Iq7pWzOBC2YzlKNz7RwUHMIlqJ4K078aeYgzvNCPEsMBfgA3jGX19EoHrDKJ/J83S ej5vlKEB/WPUQ1xFLw1adx/8vgcbxmTWLqn7tyfEqeCrocld0Vdh1QEyKlSFr94LqHuH zd6ZNOjY3leXWw2YRIYldt88j0EmJ4y+bolDyok2A05i6kocsEpCElLmiC/wxsWWlZnu jirLs90Ts8MD5jTDnS5CiEpj6naoqQMyFgJUOV0HP5BOK2845dX7yFrjQ0spbJ8YUYX/ x+s80HRq3WvdG+XcuTXKgqgoP1EmR2ssPfzlIMNPUO0fC4m7kx2Zw+0NGuhS4QNOSz0u bQSg== X-Gm-Message-State: AOAM5307zDOR1G84oVw2oGm0gkP2HwUY+XWEAMoaW+AAkfNRs6o4/GOS RyvYQO7/3EkVGU+wXY+CRUJFwZnkonYkqw== X-Google-Smtp-Source: ABdhPJzbCejNQSb3vU9/3UmSDQrGzsUqQfOpnKMi5V/4qSlhBmDow7wW/MU0jdmgTmOaDGcoVaQ4/w== X-Received: by 2002:a5d:4608:: with SMTP id t8mr28826698wrq.136.1632147603325; Mon, 20 Sep 2021 07:20:03 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id n17sm16229693wrp.17.2021.09.20.07.20.02 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Sep 2021 07:20:03 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/27] target/arm: Add TB flag for "MVE insns not predicated" Date: Mon, 20 Sep 2021 15:19:38 +0100 Message-Id: <20210920141947.5537-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210920141947.5537-1-peter.maydell@linaro.org> References: <20210920141947.5537-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Our current codegen for MVE always calls out to helper functions, because some byte lanes might be predicated. The common case is that in fact there is no predication active and all lanes should be updated together, so we can produce better code by detecting that and using the TCG generic vector infrastructure. Add a TB flag that is set when we can guarantee that there is no active MVE predication, and a bool in the DisasContext. Subsequent patches will use this flag to generate improved code for some instructions. In most cases when the predication state changes we simply end the TB after that instruction. For the code called from vfp_access_check() that handles lazy state preservation and creating a new FP context, we can usually avoid having to try to end the TB because luckily the new value of the flag following the register changes in those sequences doesn't depend on any runtime decisions. We do have to end the TB if the guest has enabled lazy FP state preservation but not automatic state preservation, but this is an odd corner case that is not going to be common in real-world code. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20210913095440.13462-4-peter.maydell@linaro.org --- target/arm/cpu.h | 4 +++- target/arm/translate.h | 2 ++ target/arm/helper.c | 33 +++++++++++++++++++++++++++++++++ target/arm/translate-m-nocp.c | 8 +++++++- target/arm/translate-mve.c | 13 ++++++++++++- target/arm/translate-vfp.c | 33 +++++++++++++++++++++++++++------ target/arm/translate.c | 8 ++++++++ 7 files changed, 92 insertions(+), 9 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 3ed03391a83..87235dae631 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3441,7 +3441,7 @@ typedef ARMCPU ArchCPU; * | TBFLAG_AM32 | +-----+----------+ * | | |TBFLAG_M32| * +-------------+----------------+----------+ - * 31 23 5 4 0 + * 31 23 6 5 0 * * Unless otherwise noted, these bits are cached in env->hflags. */ @@ -3499,6 +3499,8 @@ FIELD(TBFLAG_M32, LSPACT, 2, 1) /* Not cached. */ FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 3, 1) /* Not cached. */ /* Set if FPCCR.S does not match current security state */ FIELD(TBFLAG_M32, FPCCR_S_WRONG, 4, 1) /* Not cached. */ +/* Set if MVE insns are definitely not predicated by VPR or LTPSIZE */ +FIELD(TBFLAG_M32, MVE_NO_PRED, 5, 1) /* Not cached. */ /* * Bit usage when in AArch64 state diff --git a/target/arm/translate.h b/target/arm/translate.h index 605d1f2e33d..3a0db801d3b 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -100,6 +100,8 @@ typedef struct DisasContext { bool align_mem; /* True if PSTATE.IL is set */ bool pstate_il; + /* True if MVE insns are definitely not predicated by VPR or LTPSIZE */ + bool mve_no_pred; /* * >= 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI. * < 0, set by the current instruction. diff --git a/target/arm/helper.c b/target/arm/helper.c index 21ee94ec2e7..62742214473 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -13637,6 +13637,35 @@ static inline void assert_hflags_rebuild_correctly(CPUARMState *env) #endif } +static bool mve_no_pred(CPUARMState *env) +{ + /* + * Return true if there is definitely no predication of MVE + * instructions by VPR or LTPSIZE. (Returning false even if there + * isn't any predication is OK; generated code will just be + * a little worse.) + * If the CPU does not implement MVE then this TB flag is always 0. + * + * NOTE: if you change this logic, the "recalculate s->mve_no_pred" + * logic in gen_update_fp_context() needs to be updated to match. + * + * We do not include the effect of the ECI bits here -- they are + * tracked in other TB flags. This simplifies the logic for + * "when did we emit code that changes the MVE_NO_PRED TB flag + * and thus need to end the TB?". + */ + if (cpu_isar_feature(aa32_mve, env_archcpu(env))) { + return false; + } + if (env->v7m.vpr) { + return false; + } + if (env->v7m.ltpsize < 4) { + return false; + } + return true; +} + void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *pflags) { @@ -13676,6 +13705,10 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, if (env->v7m.fpccr[is_secure] & R_V7M_FPCCR_LSPACT_MASK) { DP_TBFLAG_M32(flags, LSPACT, 1); } + + if (mve_no_pred(env)) { + DP_TBFLAG_M32(flags, MVE_NO_PRED, 1); + } } else { /* * Note that XSCALE_CPAR shares bits with VECSTRIDE. diff --git a/target/arm/translate-m-nocp.c b/target/arm/translate-m-nocp.c index 5eab04832cd..d9e144e8eb3 100644 --- a/target/arm/translate-m-nocp.c +++ b/target/arm/translate-m-nocp.c @@ -95,7 +95,10 @@ static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM_VLSTM *a) clear_eci_state(s); - /* End the TB, because we have updated FP control bits */ + /* + * End the TB, because we have updated FP control bits, + * and possibly VPR or LTPSIZE. + */ s->base.is_jmp = DISAS_UPDATE_EXIT; return true; } @@ -397,6 +400,7 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno, store_cpu_field(control, v7m.control[M_REG_S]); tcg_gen_andi_i32(tmp, tmp, ~FPCR_NZCV_MASK); gen_helper_vfp_set_fpscr(cpu_env, tmp); + s->base.is_jmp = DISAS_UPDATE_NOCHAIN; tcg_temp_free_i32(tmp); tcg_temp_free_i32(sfpa); break; @@ -409,6 +413,7 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno, } tmp = loadfn(s, opaque, true); store_cpu_field(tmp, v7m.vpr); + s->base.is_jmp = DISAS_UPDATE_NOCHAIN; break; case ARM_VFP_P0: { @@ -418,6 +423,7 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno, tcg_gen_deposit_i32(vpr, vpr, tmp, R_V7M_VPR_P0_SHIFT, R_V7M_VPR_P0_LENGTH); store_cpu_field(vpr, v7m.vpr); + s->base.is_jmp = DISAS_UPDATE_NOCHAIN; tcg_temp_free_i32(tmp); break; } diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 2ed91577ec8..0eca96e29cf 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -810,7 +810,12 @@ DO_LOGIC(VORR, gen_helper_mve_vorr) DO_LOGIC(VORN, gen_helper_mve_vorn) DO_LOGIC(VEOR, gen_helper_mve_veor) -DO_LOGIC(VPSEL, gen_helper_mve_vpsel) +static bool trans_VPSEL(DisasContext *s, arg_2op *a) +{ + /* This insn updates predication bits */ + s->base.is_jmp = DISAS_UPDATE_NOCHAIN; + return do_2op(s, a, gen_helper_mve_vpsel); +} #define DO_2OP(INSN, FN) \ static bool trans_##INSN(DisasContext *s, arg_2op *a) \ @@ -1366,6 +1371,8 @@ static bool trans_VPNOT(DisasContext *s, arg_VPNOT *a) } gen_helper_mve_vpnot(cpu_env); + /* This insn updates predication bits */ + s->base.is_jmp = DISAS_UPDATE_NOCHAIN; mve_update_eci(s); return true; } @@ -1852,6 +1859,8 @@ static bool do_vcmp(DisasContext *s, arg_vcmp *a, MVEGenCmpFn *fn) /* VPT */ gen_vpst(s, a->mask); } + /* This insn updates predication bits */ + s->base.is_jmp = DISAS_UPDATE_NOCHAIN; mve_update_eci(s); return true; } @@ -1883,6 +1892,8 @@ static bool do_vcmp_scalar(DisasContext *s, arg_vcmp_scalar *a, /* VPT */ gen_vpst(s, a->mask); } + /* This insn updates predication bits */ + s->base.is_jmp = DISAS_UPDATE_NOCHAIN; mve_update_eci(s); return true; } diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c index e2eb797c829..59bcaec5beb 100644 --- a/target/arm/translate-vfp.c +++ b/target/arm/translate-vfp.c @@ -109,7 +109,7 @@ static inline long vfp_f16_offset(unsigned reg, bool top) * Generate code for M-profile lazy FP state preservation if needed; * this corresponds to the pseudocode PreserveFPState() function. */ -static void gen_preserve_fp_state(DisasContext *s) +static void gen_preserve_fp_state(DisasContext *s, bool skip_context_update) { if (s->v7m_lspact) { /* @@ -128,6 +128,20 @@ static void gen_preserve_fp_state(DisasContext *s) * any further FP insns in this TB. */ s->v7m_lspact = false; + /* + * The helper might have zeroed VPR, so we do not know the + * correct value for the MVE_NO_PRED TB flag any more. + * If we're about to create a new fp context then that + * will precisely determine the MVE_NO_PRED value (see + * gen_update_fp_context()). Otherwise, we must: + * - set s->mve_no_pred to false, so this instruction + * is generated to use helper functions + * - end the TB now, without chaining to the next TB + */ + if (skip_context_update || !s->v7m_new_fp_ctxt_needed) { + s->mve_no_pred = false; + s->base.is_jmp = DISAS_UPDATE_NOCHAIN; + } } } @@ -169,12 +183,19 @@ static void gen_update_fp_context(DisasContext *s) TCGv_i32 z32 = tcg_const_i32(0); store_cpu_field(z32, v7m.vpr); } - /* - * We don't need to arrange to end the TB, because the only - * parts of FPSCR which we cache in the TB flags are the VECLEN - * and VECSTRIDE, and those don't exist for M-profile. + * We just updated the FPSCR and VPR. Some of this state is cached + * in the MVE_NO_PRED TB flag. We want to avoid having to end the + * TB here, which means we need the new value of the MVE_NO_PRED + * flag to be exactly known here and the same for all executions. + * Luckily FPDSCR.LTPSIZE is always constant 4 and the VPR is + * always set to 0, so the new MVE_NO_PRED flag is always 1 + * if and only if we have MVE. + * + * (The other FPSCR state cached in TB flags is VECLEN and VECSTRIDE, + * but those do not exist for M-profile, so are not relevant here.) */ + s->mve_no_pred = dc_isar_feature(aa32_mve, s); if (s->v8m_secure) { bits |= R_V7M_CONTROL_SFPA_MASK; @@ -238,7 +259,7 @@ bool vfp_access_check_m(DisasContext *s, bool skip_context_update) /* Handle M-profile lazy FP state mechanics */ /* Trigger lazy-state preservation if necessary */ - gen_preserve_fp_state(s); + gen_preserve_fp_state(s, skip_context_update); if (!skip_context_update) { /* Update ownership of FP context and create new FP context if needed */ diff --git a/target/arm/translate.c b/target/arm/translate.c index cf31e0237da..f7086c66a59 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8496,6 +8496,7 @@ static bool trans_DLS(DisasContext *s, arg_DLS *a) /* DLSTP: set FPSCR.LTPSIZE */ tmp = tcg_const_i32(a->size); store_cpu_field(tmp, v7m.ltpsize); + s->base.is_jmp = DISAS_UPDATE_NOCHAIN; } return true; } @@ -8561,6 +8562,10 @@ static bool trans_WLS(DisasContext *s, arg_WLS *a) assert(ok); tmp = tcg_const_i32(a->size); store_cpu_field(tmp, v7m.ltpsize); + /* + * LTPSIZE updated, but MVE_NO_PRED will always be the same thing (0) + * when we take this upcoming exit from this TB, so gen_jmp_tb() is OK. + */ } gen_jmp_tb(s, s->base.pc_next, 1); @@ -8743,6 +8748,8 @@ static bool trans_VCTP(DisasContext *s, arg_VCTP *a) gen_helper_mve_vctp(cpu_env, masklen); tcg_temp_free_i32(masklen); tcg_temp_free_i32(rn_shifted); + /* This insn updates predication bits */ + s->base.is_jmp = DISAS_UPDATE_NOCHAIN; mve_update_eci(s); return true; } @@ -9413,6 +9420,7 @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) dc->v7m_new_fp_ctxt_needed = EX_TBFLAG_M32(tb_flags, NEW_FP_CTXT_NEEDED); dc->v7m_lspact = EX_TBFLAG_M32(tb_flags, LSPACT); + dc->mve_no_pred = EX_TBFLAG_M32(tb_flags, MVE_NO_PRED); } else { dc->debug_target_el = EX_TBFLAG_ANY(tb_flags, DEBUG_TARGET_EL); dc->sctlr_b = EX_TBFLAG_A32(tb_flags, SCTLR__B); From patchwork Mon Sep 20 14:19:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 12505583 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4DD8CC433EF for ; Mon, 20 Sep 2021 14:52:43 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D015C60F21 for ; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n17sm16229693wrp.17.2021.09.20.07.20.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Sep 2021 07:20:03 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/27] target/arm: Optimize MVE logic ops Date: Mon, 20 Sep 2021 15:19:39 +0100 Message-Id: <20210920141947.5537-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210920141947.5537-1-peter.maydell@linaro.org> References: <20210920141947.5537-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" When not predicating, implement the MVE bitwise logical insns directly using TCG vector operations. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20210913095440.13462-5-peter.maydell@linaro.org --- target/arm/translate-mve.c | 51 +++++++++++++++++++++++++++----------- 1 file changed, 36 insertions(+), 15 deletions(-) diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 0eca96e29cf..77b9f0db334 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -64,6 +64,16 @@ static TCGv_ptr mve_qreg_ptr(unsigned reg) return ret; } +static bool mve_no_predication(DisasContext *s) +{ + /* + * Return true if we are executing the entire MVE instruction + * with no predication or partial-execution, and so we can safely + * use an inline TCG vector implementation. + */ + return s->eci == 0 && s->mve_no_pred; +} + static bool mve_check_qreg_bank(DisasContext *s, int qmask) { /* @@ -774,7 +784,8 @@ static bool trans_VNEG_fp(DisasContext *s, arg_1op *a) return do_1op(s, a, fns[a->size]); } -static bool do_2op(DisasContext *s, arg_2op *a, MVEGenTwoOpFn fn) +static bool do_2op_vec(DisasContext *s, arg_2op *a, MVEGenTwoOpFn fn, + GVecGen3Fn *vecfn) { TCGv_ptr qd, qn, qm; @@ -787,28 +798,38 @@ static bool do_2op(DisasContext *s, arg_2op *a, MVEGenTwoOpFn fn) return true; } - qd = mve_qreg_ptr(a->qd); - qn = mve_qreg_ptr(a->qn); - qm = mve_qreg_ptr(a->qm); - fn(cpu_env, qd, qn, qm); - tcg_temp_free_ptr(qd); - tcg_temp_free_ptr(qn); - tcg_temp_free_ptr(qm); + if (vecfn && mve_no_predication(s)) { + vecfn(a->size, mve_qreg_offset(a->qd), mve_qreg_offset(a->qn), + mve_qreg_offset(a->qm), 16, 16); + } else { + qd = mve_qreg_ptr(a->qd); + qn = mve_qreg_ptr(a->qn); + qm = mve_qreg_ptr(a->qm); + fn(cpu_env, qd, qn, qm); + tcg_temp_free_ptr(qd); + tcg_temp_free_ptr(qn); + tcg_temp_free_ptr(qm); + } mve_update_eci(s); return true; } -#define DO_LOGIC(INSN, HELPER) \ +static bool do_2op(DisasContext *s, arg_2op *a, MVEGenTwoOpFn *fn) +{ + return do_2op_vec(s, a, fn, NULL); +} + +#define DO_LOGIC(INSN, HELPER, VECFN) \ static bool trans_##INSN(DisasContext *s, arg_2op *a) \ { \ - return do_2op(s, a, HELPER); \ + return do_2op_vec(s, a, HELPER, VECFN); \ } -DO_LOGIC(VAND, gen_helper_mve_vand) -DO_LOGIC(VBIC, gen_helper_mve_vbic) -DO_LOGIC(VORR, gen_helper_mve_vorr) -DO_LOGIC(VORN, gen_helper_mve_vorn) -DO_LOGIC(VEOR, gen_helper_mve_veor) +DO_LOGIC(VAND, gen_helper_mve_vand, tcg_gen_gvec_and) +DO_LOGIC(VBIC, gen_helper_mve_vbic, tcg_gen_gvec_andc) +DO_LOGIC(VORR, gen_helper_mve_vorr, tcg_gen_gvec_or) +DO_LOGIC(VORN, gen_helper_mve_vorn, tcg_gen_gvec_orc) +DO_LOGIC(VEOR, gen_helper_mve_veor, tcg_gen_gvec_xor) static bool trans_VPSEL(DisasContext *s, arg_2op *a) { From patchwork Mon Sep 20 14:19:40 2021 Content-Type: text/plain; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n17sm16229693wrp.17.2021.09.20.07.20.04 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Sep 2021 07:20:04 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/27] target/arm: Optimize MVE arithmetic ops Date: Mon, 20 Sep 2021 15:19:40 +0100 Message-Id: <20210920141947.5537-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210920141947.5537-1-peter.maydell@linaro.org> References: <20210920141947.5537-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Optimize MVE arithmetic ops when we have a TCG vector operation we can use. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20210913095440.13462-6-peter.maydell@linaro.org --- target/arm/translate-mve.c | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 77b9f0db334..255cb860fec 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -838,7 +838,7 @@ static bool trans_VPSEL(DisasContext *s, arg_2op *a) return do_2op(s, a, gen_helper_mve_vpsel); } -#define DO_2OP(INSN, FN) \ +#define DO_2OP_VEC(INSN, FN, VECFN) \ static bool trans_##INSN(DisasContext *s, arg_2op *a) \ { \ static MVEGenTwoOpFn * const fns[] = { \ @@ -847,20 +847,22 @@ static bool trans_VPSEL(DisasContext *s, arg_2op *a) gen_helper_mve_##FN##w, \ NULL, \ }; \ - return do_2op(s, a, fns[a->size]); \ + return do_2op_vec(s, a, fns[a->size], VECFN); \ } -DO_2OP(VADD, vadd) -DO_2OP(VSUB, vsub) -DO_2OP(VMUL, vmul) +#define DO_2OP(INSN, FN) DO_2OP_VEC(INSN, FN, NULL) + +DO_2OP_VEC(VADD, vadd, tcg_gen_gvec_add) +DO_2OP_VEC(VSUB, vsub, tcg_gen_gvec_sub) +DO_2OP_VEC(VMUL, vmul, tcg_gen_gvec_mul) DO_2OP(VMULH_S, vmulhs) DO_2OP(VMULH_U, vmulhu) DO_2OP(VRMULH_S, vrmulhs) DO_2OP(VRMULH_U, vrmulhu) -DO_2OP(VMAX_S, vmaxs) -DO_2OP(VMAX_U, vmaxu) -DO_2OP(VMIN_S, vmins) -DO_2OP(VMIN_U, vminu) +DO_2OP_VEC(VMAX_S, vmaxs, tcg_gen_gvec_smax) +DO_2OP_VEC(VMAX_U, vmaxu, tcg_gen_gvec_umax) +DO_2OP_VEC(VMIN_S, vmins, tcg_gen_gvec_smin) +DO_2OP_VEC(VMIN_U, vminu, tcg_gen_gvec_umin) DO_2OP(VABD_S, vabds) DO_2OP(VABD_U, vabdu) DO_2OP(VHADD_S, vhadds) From patchwork Mon Sep 20 14:19:41 2021 Content-Type: text/plain; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n17sm16229693wrp.17.2021.09.20.07.20.04 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Sep 2021 07:20:05 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 21/27] target/arm: Optimize MVE VNEG, VABS Date: Mon, 20 Sep 2021 15:19:41 +0100 Message-Id: <20210920141947.5537-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210920141947.5537-1-peter.maydell@linaro.org> References: <20210920141947.5537-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Optimize the MVE VNEG and VABS insns by using TCG vector ops when possible. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20210913095440.13462-7-peter.maydell@linaro.org --- target/arm/translate-mve.c | 32 ++++++++++++++++++++++---------- 1 file changed, 22 insertions(+), 10 deletions(-) diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 255cb860fec..d30c7e57ea3 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -510,7 +510,8 @@ static bool trans_VDUP(DisasContext *s, arg_VDUP *a) return true; } -static bool do_1op(DisasContext *s, arg_1op *a, MVEGenOneOpFn fn) +static bool do_1op_vec(DisasContext *s, arg_1op *a, MVEGenOneOpFn fn, + GVecGen2Fn vecfn) { TCGv_ptr qd, qm; @@ -524,16 +525,25 @@ static bool do_1op(DisasContext *s, arg_1op *a, MVEGenOneOpFn fn) return true; } - qd = mve_qreg_ptr(a->qd); - qm = mve_qreg_ptr(a->qm); - fn(cpu_env, qd, qm); - tcg_temp_free_ptr(qd); - tcg_temp_free_ptr(qm); + if (vecfn && mve_no_predication(s)) { + vecfn(a->size, mve_qreg_offset(a->qd), mve_qreg_offset(a->qm), 16, 16); + } else { + qd = mve_qreg_ptr(a->qd); + qm = mve_qreg_ptr(a->qm); + fn(cpu_env, qd, qm); + tcg_temp_free_ptr(qd); + tcg_temp_free_ptr(qm); + } mve_update_eci(s); return true; } -#define DO_1OP(INSN, FN) \ +static bool do_1op(DisasContext *s, arg_1op *a, MVEGenOneOpFn fn) +{ + return do_1op_vec(s, a, fn, NULL); +} + +#define DO_1OP_VEC(INSN, FN, VECFN) \ static bool trans_##INSN(DisasContext *s, arg_1op *a) \ { \ static MVEGenOneOpFn * const fns[] = { \ @@ -542,13 +552,15 @@ static bool do_1op(DisasContext *s, arg_1op *a, MVEGenOneOpFn fn) gen_helper_mve_##FN##w, \ NULL, \ }; \ - return do_1op(s, a, fns[a->size]); \ + return do_1op_vec(s, a, fns[a->size], VECFN); \ } +#define DO_1OP(INSN, FN) DO_1OP_VEC(INSN, FN, NULL) + DO_1OP(VCLZ, vclz) DO_1OP(VCLS, vcls) -DO_1OP(VABS, vabs) -DO_1OP(VNEG, vneg) +DO_1OP_VEC(VABS, vabs, tcg_gen_gvec_abs) +DO_1OP_VEC(VNEG, vneg, tcg_gen_gvec_neg) DO_1OP(VQABS, vqabs) DO_1OP(VQNEG, vqneg) DO_1OP(VMAXA, vmaxa) From patchwork Mon Sep 20 14:19:42 2021 Content-Type: text/plain; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n17sm16229693wrp.17.2021.09.20.07.20.05 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Sep 2021 07:20:05 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 22/27] target/arm: Optimize MVE VDUP Date: Mon, 20 Sep 2021 15:19:42 +0100 Message-Id: <20210920141947.5537-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210920141947.5537-1-peter.maydell@linaro.org> References: <20210920141947.5537-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Optimize the MVE VDUP insns by using TCG vector ops when possible. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20210913095440.13462-8-peter.maydell@linaro.org --- target/arm/translate-mve.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index d30c7e57ea3..13de55242e2 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -500,11 +500,15 @@ static bool trans_VDUP(DisasContext *s, arg_VDUP *a) return true; } - qd = mve_qreg_ptr(a->qd); rt = load_reg(s, a->rt); - tcg_gen_dup_i32(a->size, rt, rt); - gen_helper_mve_vdup(cpu_env, qd, rt); - tcg_temp_free_ptr(qd); + if (mve_no_predication(s)) { + tcg_gen_gvec_dup_i32(a->size, mve_qreg_offset(a->qd), 16, 16, rt); + } else { + qd = mve_qreg_ptr(a->qd); + tcg_gen_dup_i32(a->size, rt, rt); + gen_helper_mve_vdup(cpu_env, qd, rt); + tcg_temp_free_ptr(qd); + } tcg_temp_free_i32(rt); mve_update_eci(s); return true; From patchwork Mon Sep 20 14:19:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 12505635 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CA390C433F5 for ; Mon, 20 Sep 2021 15:07:10 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7413360F93 for ; Mon, 20 Sep 2021 15:07:10 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 7413360F93 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:60266 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mSKsv-0002nt-IC for qemu-devel@archiver.kernel.org; Mon, 20 Sep 2021 11:07:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37294) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mSK9q-0002uj-Og for qemu-devel@nongnu.org; Mon, 20 Sep 2021 10:20:42 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:43840) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mSK9R-0000wk-20 for qemu-devel@nongnu.org; Mon, 20 Sep 2021 10:20:33 -0400 Received: by mail-wr1-x435.google.com with SMTP id w17so22055610wrv.10 for ; Mon, 20 Sep 2021 07:20:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=AXBRy08pEErOH7eruwxlYtrLmWIxeuV4R3OA3Hcv0S0=; b=fKFaVQ+6i7yMalr6wjxXk4L/aEVgX6ui383zrt5wRQhSFxIfsN0FqEofNz18183e0j ShWVqyS2+O0/j5UGtI9psTeUdHslxjv4jTbq3LPNEFDQmSCh3+KGkVp4JL0dOpsacgyv UNpRQj6Gy3c1BktxdS6HPiv1VUZB3JL0gANMqygeG1wwSCWRbFZdFzk+NhfmB+Zeesmp RRARnRUEtra/CX2T2ejlbpJ4qn94qeX0Rn+UALf+DRq1kuU3cuH4cVQ0OkwiEtKbzvgb VRohoDkiFIWZK88FsgRDMKa0meZNHj6UqjVVU7enTQdAaL0veIuzxHXau8o0aHdHwH1T xi7g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AXBRy08pEErOH7eruwxlYtrLmWIxeuV4R3OA3Hcv0S0=; b=iB9GsOQKOLc3lm0+i978KbEFdSSHgPiBWkBCpfD05Lt66z1vRIWzFgdVJVm/TcqQwT zl2JPeXL/EvbjR+cdPqiL9IUHkfsA3Aehtiq+QDtP1m7p4s4OD63g9zIZsdYHHDtNHg6 EKskKq2jPzGJ9ZcXs/ZCYkcE+XnAQUj47hNlNMHvr9p0Nyyo3CqcplXNEgfluyBYw++g Tqr+coqGtGg1Hx0jgwc7g9mZRX4WNL6q8rg1VvtNo2OcZPcoBJ4xmN2G0OG/U0JYKJ5w 3cmD4xdVpl5/Ev62i0ZCuHmeJHWP5nBsk0BV1z4mgBwxqLwSBbgWFEuhc/N/EmIBSTmw REag== X-Gm-Message-State: AOAM531kw2YBERAlU3A1aGVxDgVtaUKX3CnndsCVpzdrGnGl/TILiZfa Uw2ur9OSrc0IeNpUYjI9u4rMMCKwEMuxNA== X-Google-Smtp-Source: ABdhPJzNRbb3qngJIsK4t84/ohj+WDqT/GoxYDdMsqx99tGBWkt47S0PlkHlj/KIoNitg9bKZMH3SA== X-Received: by 2002:adf:e88e:: with SMTP id d14mr29476553wrm.207.1632147606534; Mon, 20 Sep 2021 07:20:06 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id n17sm16229693wrp.17.2021.09.20.07.20.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Sep 2021 07:20:06 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 23/27] target/arm: Optimize MVE VMVN Date: Mon, 20 Sep 2021 15:19:43 +0100 Message-Id: <20210920141947.5537-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210920141947.5537-1-peter.maydell@linaro.org> References: <20210920141947.5537-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Optimize the MVE VMVN insn by using TCG vector ops when possible. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20210913095440.13462-9-peter.maydell@linaro.org --- target/arm/translate-mve.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 13de55242e2..4583e22f21c 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -769,7 +769,7 @@ static bool trans_VREV64(DisasContext *s, arg_1op *a) static bool trans_VMVN(DisasContext *s, arg_1op *a) { - return do_1op(s, a, gen_helper_mve_vmvn); + return do_1op_vec(s, a, gen_helper_mve_vmvn, tcg_gen_gvec_not); } static bool trans_VABS_fp(DisasContext *s, arg_1op *a) From patchwork Mon Sep 20 14:19:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 12505491 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 88DEAC433EF for ; Mon, 20 Sep 2021 14:27:57 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3208561077 for ; Mon, 20 Sep 2021 14:27:57 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 3208561077 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:57314 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mSKGy-0002cp-AJ for qemu-devel@archiver.kernel.org; Mon, 20 Sep 2021 10:27:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37250) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mSK9l-0002sU-J1 for qemu-devel@nongnu.org; Mon, 20 Sep 2021 10:20:29 -0400 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]:34366) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mSK9Q-0000xD-M4 for qemu-devel@nongnu.org; Mon, 20 Sep 2021 10:20:26 -0400 Received: by mail-wr1-x42c.google.com with SMTP id t8so23199511wri.1 for ; Mon, 20 Sep 2021 07:20:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=2kQXJvsGgZieDZeANleNNFDtrgmioKh0HnKcjwchoi4=; b=xce5iJFxD1Vbzfp9LJWivRdLP6TXj0DaSEfElM5LAsRCAAlO6tzT0QehTtl6SoZGy6 9NoMkHtg3TV5qVcuGSUM7+TjJs7pzgp5WwSyMZ1i4w4M/Im69RDtgrgboBX+jQuAJry6 aj2DXi0zpGGCR6DSB8l1zTYeddKFheVzgz+IMygqgyTdG6eo5juOh040cX+PVEMRbU0L JN5OCBpXCPYTqbqAtNtZeJapUVgHBKReeaSnE51nVSiDOwjI23rhKW02gvv6sN2eYCNh /eHAB52a5b3D42gyw3zHhOW48phoXV33kNehrEPReXXaEwvSC7Bl5BBpGYNpZ8e2lEkO oygA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2kQXJvsGgZieDZeANleNNFDtrgmioKh0HnKcjwchoi4=; b=WYB7SmdYGoA8RBeUnxMiU9bA+Q4V9WWSQhH4AWXZwXfvdx50tAoEWlfD07JVqoju7A HqSQga+UKKq+MIZH+//9AbgMD4XpkbEGMUGzuulNgAh6eQFyGEkG7rEZLzWpH25+jPfk aH7DdfbC9GOHsNr+PROJ/wq8lQ5BXpYKI8Ab6RxVLPScxcjm/xHCasF2ZOUWjhFfujeE w10XTQagPMSb4v5wuPxLeSny08EBVxy28/ltfADpi9eV6KZzVxUnd9FIuVYepJ6hiNah 7tC9HrVO7HDxjCXl/qLt9cKBE0hYA1sS06iGsnagmAEIpnItqNXg6dzBud2Fm7Ek3Aa9 zT6w== X-Gm-Message-State: AOAM531FC2+t2TjDAnVURkXO5GPZRr4sAcWVJJslAaGbFMNCnlCtzSH3 QKeyYgBjkaoGTKLdTcxNZa8rfTHITMs27A== X-Google-Smtp-Source: ABdhPJwq4l3o89v1P16V/Dv/rA+uQzfTJutdfbmkIgOyFUVRaw3tUhSrX09NnG/JY+NvFsnYkYAaQQ== X-Received: by 2002:a7b:c745:: with SMTP id w5mr22286664wmk.192.1632147607271; Mon, 20 Sep 2021 07:20:07 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id n17sm16229693wrp.17.2021.09.20.07.20.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Sep 2021 07:20:06 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 24/27] target/arm: Optimize MVE VSHL, VSHR immediate forms Date: Mon, 20 Sep 2021 15:19:44 +0100 Message-Id: <20210920141947.5537-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210920141947.5537-1-peter.maydell@linaro.org> References: <20210920141947.5537-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Optimize the MVE VSHL and VSHR immediate forms by using TCG vector ops when possible. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20210913095440.13462-10-peter.maydell@linaro.org --- target/arm/translate-mve.c | 83 +++++++++++++++++++++++++++++--------- 1 file changed, 63 insertions(+), 20 deletions(-) diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 4583e22f21c..00fa4379a74 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -1570,8 +1570,8 @@ static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a) return do_1imm(s, a, fn); } -static bool do_2shift(DisasContext *s, arg_2shift *a, MVEGenTwoOpShiftFn fn, - bool negateshift) +static bool do_2shift_vec(DisasContext *s, arg_2shift *a, MVEGenTwoOpShiftFn fn, + bool negateshift, GVecGen2iFn vecfn) { TCGv_ptr qd, qm; int shift = a->shift; @@ -1594,34 +1594,77 @@ static bool do_2shift(DisasContext *s, arg_2shift *a, MVEGenTwoOpShiftFn fn, shift = -shift; } - qd = mve_qreg_ptr(a->qd); - qm = mve_qreg_ptr(a->qm); - fn(cpu_env, qd, qm, tcg_constant_i32(shift)); - tcg_temp_free_ptr(qd); - tcg_temp_free_ptr(qm); + if (vecfn && mve_no_predication(s)) { + vecfn(a->size, mve_qreg_offset(a->qd), mve_qreg_offset(a->qm), + shift, 16, 16); + } else { + qd = mve_qreg_ptr(a->qd); + qm = mve_qreg_ptr(a->qm); + fn(cpu_env, qd, qm, tcg_constant_i32(shift)); + tcg_temp_free_ptr(qd); + tcg_temp_free_ptr(qm); + } mve_update_eci(s); return true; } -#define DO_2SHIFT(INSN, FN, NEGATESHIFT) \ - static bool trans_##INSN(DisasContext *s, arg_2shift *a) \ - { \ - static MVEGenTwoOpShiftFn * const fns[] = { \ - gen_helper_mve_##FN##b, \ - gen_helper_mve_##FN##h, \ - gen_helper_mve_##FN##w, \ - NULL, \ - }; \ - return do_2shift(s, a, fns[a->size], NEGATESHIFT); \ +static bool do_2shift(DisasContext *s, arg_2shift *a, MVEGenTwoOpShiftFn fn, + bool negateshift) +{ + return do_2shift_vec(s, a, fn, negateshift, NULL); +} + +#define DO_2SHIFT_VEC(INSN, FN, NEGATESHIFT, VECFN) \ + static bool trans_##INSN(DisasContext *s, arg_2shift *a) \ + { \ + static MVEGenTwoOpShiftFn * const fns[] = { \ + gen_helper_mve_##FN##b, \ + gen_helper_mve_##FN##h, \ + gen_helper_mve_##FN##w, \ + NULL, \ + }; \ + return do_2shift_vec(s, a, fns[a->size], NEGATESHIFT, VECFN); \ } -DO_2SHIFT(VSHLI, vshli_u, false) +#define DO_2SHIFT(INSN, FN, NEGATESHIFT) \ + DO_2SHIFT_VEC(INSN, FN, NEGATESHIFT, NULL) + +static void do_gvec_shri_s(unsigned vece, uint32_t dofs, uint32_t aofs, + int64_t shift, uint32_t oprsz, uint32_t maxsz) +{ + /* + * We get here with a negated shift count, and we must handle + * shifts by the element size, which tcg_gen_gvec_sari() does not do. + */ + shift = -shift; + if (shift == (8 << vece)) { + shift--; + } + tcg_gen_gvec_sari(vece, dofs, aofs, shift, oprsz, maxsz); +} + +static void do_gvec_shri_u(unsigned vece, uint32_t dofs, uint32_t aofs, + int64_t shift, uint32_t oprsz, uint32_t maxsz) +{ + /* + * We get here with a negated shift count, and we must handle + * shifts by the element size, which tcg_gen_gvec_shri() does not do. + */ + shift = -shift; + if (shift == (8 << vece)) { + tcg_gen_gvec_dup_imm(vece, dofs, oprsz, maxsz, 0); + } else { + tcg_gen_gvec_shri(vece, dofs, aofs, shift, oprsz, maxsz); + } +} + +DO_2SHIFT_VEC(VSHLI, vshli_u, false, tcg_gen_gvec_shli) DO_2SHIFT(VQSHLI_S, vqshli_s, false) DO_2SHIFT(VQSHLI_U, vqshli_u, false) DO_2SHIFT(VQSHLUI, vqshlui_s, false) /* These right shifts use a left-shift helper with negated shift count */ -DO_2SHIFT(VSHRI_S, vshli_s, true) -DO_2SHIFT(VSHRI_U, vshli_u, true) +DO_2SHIFT_VEC(VSHRI_S, vshli_s, true, do_gvec_shri_s) +DO_2SHIFT_VEC(VSHRI_U, vshli_u, true, do_gvec_shri_u) DO_2SHIFT(VRSHRI_S, vrshli_s, true) DO_2SHIFT(VRSHRI_U, vrshli_u, true) From patchwork Mon Sep 20 14:19:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 12505571 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6C615C433F5 for ; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n17sm16229693wrp.17.2021.09.20.07.20.07 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Sep 2021 07:20:07 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 25/27] target/arm: Optimize MVE VSHLL and VMOVL Date: Mon, 20 Sep 2021 15:19:45 +0100 Message-Id: <20210920141947.5537-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210920141947.5537-1-peter.maydell@linaro.org> References: <20210920141947.5537-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Optimize the MVE VSHLL insns by using TCG vector ops when possible. This includes the VMOVL insn, which we handle in mve.decode as "VSHLL with zero shift count". Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20210913095440.13462-11-peter.maydell@linaro.org --- target/arm/translate-mve.c | 67 +++++++++++++++++++++++++++++++++----- 1 file changed, 59 insertions(+), 8 deletions(-) diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 00fa4379a74..5d66f70657e 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -1735,16 +1735,67 @@ DO_2SHIFT_SCALAR(VQSHL_U_scalar, vqshli_u) DO_2SHIFT_SCALAR(VQRSHL_S_scalar, vqrshli_s) DO_2SHIFT_SCALAR(VQRSHL_U_scalar, vqrshli_u) -#define DO_VSHLL(INSN, FN) \ - static bool trans_##INSN(DisasContext *s, arg_2shift *a) \ - { \ - static MVEGenTwoOpShiftFn * const fns[] = { \ - gen_helper_mve_##FN##b, \ - gen_helper_mve_##FN##h, \ - }; \ - return do_2shift(s, a, fns[a->size], false); \ +#define DO_VSHLL(INSN, FN) \ + static bool trans_##INSN(DisasContext *s, arg_2shift *a) \ + { \ + static MVEGenTwoOpShiftFn * const fns[] = { \ + gen_helper_mve_##FN##b, \ + gen_helper_mve_##FN##h, \ + }; \ + return do_2shift_vec(s, a, fns[a->size], false, do_gvec_##FN); \ } +/* + * For the VSHLL vector helpers, the vece is the size of the input + * (ie MO_8 or MO_16); the helpers want to work in the output size. + * The shift count can be 0.., inclusive. (0 is VMOVL.) + */ +static void do_gvec_vshllbs(unsigned vece, uint32_t dofs, uint32_t aofs, + int64_t shift, uint32_t oprsz, uint32_t maxsz) +{ + unsigned ovece = vece + 1; + unsigned ibits = vece == MO_8 ? 8 : 16; + tcg_gen_gvec_shli(ovece, dofs, aofs, ibits, oprsz, maxsz); + tcg_gen_gvec_sari(ovece, dofs, dofs, ibits - shift, oprsz, maxsz); +} + +static void do_gvec_vshllbu(unsigned vece, uint32_t dofs, uint32_t aofs, + int64_t shift, uint32_t oprsz, uint32_t maxsz) +{ + unsigned ovece = vece + 1; + tcg_gen_gvec_andi(ovece, dofs, aofs, + ovece == MO_16 ? 0xff : 0xffff, oprsz, maxsz); + tcg_gen_gvec_shli(ovece, dofs, dofs, shift, oprsz, maxsz); +} + +static void do_gvec_vshllts(unsigned vece, uint32_t dofs, uint32_t aofs, + int64_t shift, uint32_t oprsz, uint32_t maxsz) +{ + unsigned ovece = vece + 1; + unsigned ibits = vece == MO_8 ? 8 : 16; + if (shift == 0) { + tcg_gen_gvec_sari(ovece, dofs, aofs, ibits, oprsz, maxsz); + } else { + tcg_gen_gvec_andi(ovece, dofs, aofs, + ovece == MO_16 ? 0xff00 : 0xffff0000, oprsz, maxsz); + tcg_gen_gvec_sari(ovece, dofs, dofs, ibits - shift, oprsz, maxsz); + } +} + +static void do_gvec_vshlltu(unsigned vece, uint32_t dofs, uint32_t aofs, + int64_t shift, uint32_t oprsz, uint32_t maxsz) +{ + unsigned ovece = vece + 1; + unsigned ibits = vece == MO_8 ? 8 : 16; + if (shift == 0) { + tcg_gen_gvec_shri(ovece, dofs, aofs, ibits, oprsz, maxsz); + } else { + tcg_gen_gvec_andi(ovece, dofs, aofs, + ovece == MO_16 ? 0xff00 : 0xffff0000, oprsz, maxsz); + tcg_gen_gvec_shri(ovece, dofs, dofs, ibits - shift, oprsz, maxsz); + } +} + DO_VSHLL(VSHLL_BS, vshllbs) DO_VSHLL(VSHLL_BU, vshllbu) DO_VSHLL(VSHLL_TS, vshllts) From patchwork Mon Sep 20 14:19:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 12505631 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.9 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, UNWANTED_LANGUAGE_BODY,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DACF2C433EF for ; Mon, 20 Sep 2021 15:04:43 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5284260F93 for ; Mon, 20 Sep 2021 15:04:43 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 5284260F93 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:54230 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mSKqY-00078g-HX for qemu-devel@archiver.kernel.org; Mon, 20 Sep 2021 11:04:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37296) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mSK9q-0002uk-PH for qemu-devel@nongnu.org; Mon, 20 Sep 2021 10:20:42 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]:44579) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mSK9U-0000zZ-3h for qemu-devel@nongnu.org; Mon, 20 Sep 2021 10:20:34 -0400 Received: by mail-wr1-x42f.google.com with SMTP id d6so30067616wrc.11 for ; Mon, 20 Sep 2021 07:20:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=PNDmDu+RPJM3tZRuKDTq3viSs87Ynb/Gdsx0iNShQxk=; b=E+kGMDNan9MJoW9YVki2w2V86xLq3CDhrbL+fG2TvIrlPiwHzAPBVz6om6vIKXWg+K jue4GnSh62UmODcohDMfmsG5j0QMWa4BlrLE8Svx28kk54zn5f4XvovLVLACivFhnz4Q 8Yc+38ZuX78eeWe5YNsvHf08EzYK2dcNsl9amvuYzubc8TG2prKyTmkctgWzyeZZIicg yCWtY6o3uoWH6MoRezHHYgyySEECV2eEk5u7XIYrVI2gzRkzAn0CcM3pdud3zFHgHgui nX62v7RTB5eCNmV47m906qunkN7DcpSNn19HzjbvSd3MiFfn6jqXJvFMTyGKtCZ/wKKL EB3g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PNDmDu+RPJM3tZRuKDTq3viSs87Ynb/Gdsx0iNShQxk=; b=4FwC2qn12TdbsD0ElZ36oXrxDkGGH7hvqgZU/RkfsUhqaHUm7XAVfuJ748x/CgDxJR uWZcczEMf39OKrvszIBeYma1b+zNzpaNc+nW159okjNkotGiqGWjDYXqrt0hLT7iMen8 Bd8IU/74AbfV7x1RGM85xTNx1pgWDIvhX84jir0UiTD3AeK1hG8gkXcYAQJqZBw2Aenw TeOvCyqYBMyl7c1EqOBY+1G17Zzc7ett6H4UuDWSP0Cous4kOTe+9dxXvu6a0KsJzHhL uF7ow6TiVXkMaK3BsZpFTt6aoFnTdGLPK1U4Tl3tCKviqqdHvuODzVrk4Eiwi0tKHUDO TQSA== X-Gm-Message-State: AOAM533QhVJF5QOf3SUigr4/0aFJke95zi6xVFpk9wUBJbSre7Y5MqWw KwqL1Ff5ldQiyE9JmOPClHXQ/s+moYWukw== X-Google-Smtp-Source: ABdhPJxLcB6sQvK7gdgHB3BjxPTVcO82AZmEUqU8ioTmuYzpZ4rroplQ9YVGuzFQfL+1NY0SrJWPtg== X-Received: by 2002:a5d:6c67:: with SMTP id r7mr12572452wrz.29.1632147608836; Mon, 20 Sep 2021 07:20:08 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id n17sm16229693wrp.17.2021.09.20.07.20.08 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Sep 2021 07:20:08 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 26/27] target/arm: Optimize MVE VSLI and VSRI Date: Mon, 20 Sep 2021 15:19:46 +0100 Message-Id: <20210920141947.5537-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210920141947.5537-1-peter.maydell@linaro.org> References: <20210920141947.5537-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Optimize the MVE shift-and-insert insns by using TCG vector ops when possible. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20210913095440.13462-12-peter.maydell@linaro.org --- target/arm/translate-mve.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 5d66f70657e..1fd71c9a1ee 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -1668,8 +1668,8 @@ DO_2SHIFT_VEC(VSHRI_U, vshli_u, true, do_gvec_shri_u) DO_2SHIFT(VRSHRI_S, vrshli_s, true) DO_2SHIFT(VRSHRI_U, vrshli_u, true) -DO_2SHIFT(VSRI, vsri, false) -DO_2SHIFT(VSLI, vsli, false) +DO_2SHIFT_VEC(VSRI, vsri, false, gen_gvec_sri) +DO_2SHIFT_VEC(VSLI, vsli, false, gen_gvec_sli) #define DO_2SHIFT_FP(INSN, FN) \ static bool trans_##INSN(DisasContext *s, arg_2shift *a) \ From patchwork Mon Sep 20 14:19:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 12505519 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 90268C433EF for ; Mon, 20 Sep 2021 14:30:34 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1906161077 for ; Mon, 20 Sep 2021 14:30:34 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 1906161077 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:37492 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mSKJU-0008Cb-8y for qemu-devel@archiver.kernel.org; Mon, 20 Sep 2021 10:30:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37274) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mSK9n-0002tg-DD for qemu-devel@nongnu.org; Mon, 20 Sep 2021 10:20:32 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]:41520) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mSK9T-0000zY-Sm for qemu-devel@nongnu.org; Mon, 20 Sep 2021 10:20:31 -0400 Received: by mail-wr1-x431.google.com with SMTP id w29so30196015wra.8 for ; Mon, 20 Sep 2021 07:20:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=UsAnWUJXXQdrCgl7MANvH4HB45xqev5qmNo8iG4qPs0=; b=eqqP+vXUzGeF4ghedD1z/XYmOF30EdX8OUijaBQYZwfZklkDKprD50UXTbpeRuS9PD agQu4OsqF+lnIzID3O2svLXNNwqRmE1ShyV2h8HmwPLJ8d3xCSlCUvc+BrqQkENSdEFo pHfULVsyoQl47GVuk/aZXiEkhnTvWGwZ3vesY1roNPeovbNiZ5D4jRB3DkRRgno8meV5 ujUkspgF15ziPwC/A/jyOhXUC9SxERNciuVtPdxC1V3G45QPX7iH+snEEsAJ1U/C1Hlj Q+Y5crVZKDTSInYvIVgB9cN8h/etrwEVWAbu2ZV0B5PVoPCDLuHHLHZ9Jd3+qDtKYYvO BgrQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UsAnWUJXXQdrCgl7MANvH4HB45xqev5qmNo8iG4qPs0=; b=BDpIzmvrahUj93k4z0jYCTVKRe+AsDQu1k7iPYyN9y5Xg7l5Tw9PK8iGHcMUQce7Oi aANS4eeG/xjJa8TWuu6kPnvqg/+jTvPUb6/Cl2BIg1KoNruyaMsSmbedfi1Oir5SCFIX hfQgNy4j0iLytTERRdjzJdc9q77+YXCSpHnyRZaSRj0xCGx++GPOQbMEtKBsDbExisF5 ufA1bMYZYfpRZVHvZzo1nFVlal+0+PezLvg4hcyzUECAUJmWNr9CiUA8cnaDLReyB5um dkMJ7Tu8SqZCDlwI1cjLwACnFhHLv7ISL+tZxnCFnhp1JI/Gw/ojj5J9iAF5cvhcedUA mJnw== X-Gm-Message-State: AOAM533jPwFiGupyqCk2kX9a1ThmZAirrjX0nzq6e+3pxbpBGnVts56r wvxzP2P4hhH2VGSZEwttKMR5WVqx/gwGiw== X-Google-Smtp-Source: ABdhPJzNjrLefDAtdOshVuxJVMQh4Uor3nueK5CHUR3KzjZkK9pLrh2L62HR40K3rW4D8VeNOVBBew== X-Received: by 2002:a05:600c:a08:: with SMTP id z8mr29906294wmp.165.1632147609584; Mon, 20 Sep 2021 07:20:09 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id n17sm16229693wrp.17.2021.09.20.07.20.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Sep 2021 07:20:09 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 27/27] target/arm: Optimize MVE 1op-immediate insns Date: Mon, 20 Sep 2021 15:19:47 +0100 Message-Id: <20210920141947.5537-28-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210920141947.5537-1-peter.maydell@linaro.org> References: <20210920141947.5537-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Optimize the MVE 1op-immediate insns (VORR, VBIC, VMOV) to use TCG vector ops when possible. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20210913095440.13462-13-peter.maydell@linaro.org --- target/arm/translate-mve.c | 26 +++++++++++++++++++++----- 1 file changed, 21 insertions(+), 5 deletions(-) diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 1fd71c9a1ee..4267d43cc7c 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -1521,7 +1521,8 @@ static bool trans_VADDLV(DisasContext *s, arg_VADDLV *a) return true; } -static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn) +static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn, + GVecGen2iFn *vecfn) { TCGv_ptr qd; uint64_t imm; @@ -1537,17 +1538,29 @@ static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn) imm = asimd_imm_const(a->imm, a->cmode, a->op); - qd = mve_qreg_ptr(a->qd); - fn(cpu_env, qd, tcg_constant_i64(imm)); - tcg_temp_free_ptr(qd); + if (vecfn && mve_no_predication(s)) { + vecfn(MO_64, mve_qreg_offset(a->qd), mve_qreg_offset(a->qd), + imm, 16, 16); + } else { + qd = mve_qreg_ptr(a->qd); + fn(cpu_env, qd, tcg_constant_i64(imm)); + tcg_temp_free_ptr(qd); + } mve_update_eci(s); return true; } +static void gen_gvec_vmovi(unsigned vece, uint32_t dofs, uint32_t aofs, + int64_t c, uint32_t oprsz, uint32_t maxsz) +{ + tcg_gen_gvec_dup_imm(vece, dofs, oprsz, maxsz, c); +} + static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a) { /* Handle decode of cmode/op here between VORR/VBIC/VMOV */ MVEGenOneOpImmFn *fn; + GVecGen2iFn *vecfn; if ((a->cmode & 1) && a->cmode < 12) { if (a->op) { @@ -1556,8 +1569,10 @@ static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a) * so the VBIC becomes a logical AND operation. */ fn = gen_helper_mve_vandi; + vecfn = tcg_gen_gvec_andi; } else { fn = gen_helper_mve_vorri; + vecfn = tcg_gen_gvec_ori; } } else { /* There is one unallocated cmode/op combination in this space */ @@ -1566,8 +1581,9 @@ static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a) } /* asimd_imm_const() sorts out VMVNI vs VMOVI for us */ fn = gen_helper_mve_vmovi; + vecfn = gen_gvec_vmovi; } - return do_1imm(s, a, fn); + return do_1imm(s, a, fn, vecfn); } static bool do_2shift_vec(DisasContext *s, arg_2shift *a, MVEGenTwoOpShiftFn fn,