From patchwork Wed Sep 22 21:30:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "David E. Box" X-Patchwork-Id: 12511473 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 997A1C4167E for ; Wed, 22 Sep 2021 21:30:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7E64360F44 for ; Wed, 22 Sep 2021 21:30:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238095AbhIVVbn (ORCPT ); Wed, 22 Sep 2021 17:31:43 -0400 Received: from mga05.intel.com ([192.55.52.43]:33405 "EHLO mga05.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238067AbhIVVbm (ORCPT ); Wed, 22 Sep 2021 17:31:42 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10115"; a="309261969" X-IronPort-AV: E=Sophos;i="5.85,315,1624345200"; d="scan'208";a="309261969" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Sep 2021 14:30:11 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.85,315,1624345200"; d="scan'208";a="518740347" Received: from linux.intel.com ([10.54.29.200]) by orsmga001.jf.intel.com with ESMTP; 22 Sep 2021 14:30:07 -0700 Received: from debox1-server.jf.intel.com (debox1-server.jf.intel.com [10.54.39.121]) by linux.intel.com (Postfix) with ESMTP id B2BF4580C6E; Wed, 22 Sep 2021 14:30:07 -0700 (PDT) From: "David E. Box" To: lee.jones@linaro.org, bhelgaas@google.com, andy.shevchenko@gmail.com Cc: "David E. Box" , mgross@linux.intel.com, srinivas.pandruvada@intel.com, linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v3 1/5] PCI: Add #defines for accessing PCIE DVSEC fields Date: Wed, 22 Sep 2021 14:30:03 -0700 Message-Id: <20210922213007.2738388-2-david.e.box@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210922213007.2738388-1-david.e.box@linux.intel.com> References: <20210922213007.2738388-1-david.e.box@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add #defines for accessing Vendor ID, Revision, Length, and ID offsets in the Designated Vendor Specific Extended Capability (DVSEC). Defined in PCIe r5.0, sec 7.9.6. Signed-off-by: David E. Box Acked-by: Bjorn Helgaas --- v3: No change include/uapi/linux/pci_regs.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index e709ae8235e7..57ee51f19283 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -1080,7 +1080,11 @@ /* Designated Vendor-Specific (DVSEC, PCI_EXT_CAP_ID_DVSEC) */ #define PCI_DVSEC_HEADER1 0x4 /* Designated Vendor-Specific Header1 */ +#define PCI_DVSEC_HEADER1_VID(x) ((x) & 0xffff) +#define PCI_DVSEC_HEADER1_REV(x) (((x) >> 16) & 0xf) +#define PCI_DVSEC_HEADER1_LEN(x) (((x) >> 20) & 0xfff) #define PCI_DVSEC_HEADER2 0x8 /* Designated Vendor-Specific Header2 */ +#define PCI_DVSEC_HEADER2_ID(x) ((x) & 0xffff) /* Data Link Feature */ #define PCI_DLF_CAP 0x04 /* Capabilities Register */ From patchwork Wed Sep 22 21:30:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "David E. Box" X-Patchwork-Id: 12511471 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 94388C433EF for ; Wed, 22 Sep 2021 21:30:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 81CA761211 for ; Wed, 22 Sep 2021 21:30:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237770AbhIVVbm (ORCPT ); Wed, 22 Sep 2021 17:31:42 -0400 Received: from mga06.intel.com ([134.134.136.31]:32504 "EHLO mga06.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237859AbhIVVbl (ORCPT ); Wed, 22 Sep 2021 17:31:41 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10115"; a="284717937" X-IronPort-AV: E=Sophos;i="5.85,315,1624345200"; d="scan'208";a="284717937" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Sep 2021 14:30:08 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.85,315,1624345200"; d="scan'208";a="484734579" Received: from linux.intel.com ([10.54.29.200]) by orsmga008.jf.intel.com with ESMTP; 22 Sep 2021 14:30:07 -0700 Received: from debox1-server.jf.intel.com (debox1-server.jf.intel.com [10.54.39.121]) by linux.intel.com (Postfix) with ESMTP id C084C580C73; Wed, 22 Sep 2021 14:30:07 -0700 (PDT) From: "David E. Box" To: lee.jones@linaro.org, bhelgaas@google.com, andy.shevchenko@gmail.com Cc: "David E. Box" , mgross@linux.intel.com, srinivas.pandruvada@intel.com, linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v3 2/5] MFD: intel_pmt: Support non-PMT capabilities Date: Wed, 22 Sep 2021 14:30:04 -0700 Message-Id: <20210922213007.2738388-3-david.e.box@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210922213007.2738388-1-david.e.box@linux.intel.com> References: <20210922213007.2738388-1-david.e.box@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Intel Platform Monitoring Technology (PMT) support is indicated by presence of an Intel defined PCIe DVSEC structure with a PMT ID. However DVSEC structures may also be used by Intel to indicate support for other capabilities unrelated to PMT. OOBMSM is a device that can have both PMT and non-PMT capabilities. In order to support these capabilities it is necessary to modify the intel_pmt driver to handle the creation of platform devices more generically. Currently PMT devices are named by their capability (e.g. pmt_telemetry). Instead, generically name them by their capability ID (e.g. intel-extended-cap-2). This allows the IDs to be created automatically, minimizing the code needed to support future capabilities. However, to ensure that unsupported devices aren't created, use an allow list to specify supported capabilities. Signed-off-by: David E. Box --- V3: No change V2: Drop new driver. Keep changes in intel_pmt.c drivers/mfd/intel_pmt.c | 95 ++++++++++++++-------- drivers/platform/x86/intel/pmt/crashlog.c | 2 +- drivers/platform/x86/intel/pmt/telemetry.c | 2 +- 3 files changed, 62 insertions(+), 37 deletions(-) diff --git a/drivers/mfd/intel_pmt.c b/drivers/mfd/intel_pmt.c index dd7eb614c28e..08cd3357577e 100644 --- a/drivers/mfd/intel_pmt.c +++ b/drivers/mfd/intel_pmt.c @@ -27,9 +27,18 @@ #define INTEL_DVSEC_ENTRY_SIZE 4 /* PMT capabilities */ -#define DVSEC_INTEL_ID_TELEMETRY 2 -#define DVSEC_INTEL_ID_WATCHER 3 -#define DVSEC_INTEL_ID_CRASHLOG 4 +#define INTEL_EXT_CAP_ID_TELEMETRY 2 +#define INTEL_EXT_CAP_ID_WATCHER 3 +#define INTEL_EXT_CAP_ID_CRASHLOG 4 + +#define INTEL_EXT_CAP_PREFIX "intel_extnd_cap" +#define FEATURE_ID_NAME_LENGTH 25 + +static int intel_ext_cap_allow_list[] = { + INTEL_EXT_CAP_ID_TELEMETRY, + INTEL_EXT_CAP_ID_WATCHER, + INTEL_EXT_CAP_ID_CRASHLOG, +}; struct intel_dvsec_header { u16 length; @@ -84,42 +93,58 @@ static const struct pmt_platform_info dg1_info = { .capabilities = dg1_capabilities, }; -static int pmt_add_dev(struct pci_dev *pdev, struct intel_dvsec_header *header, - unsigned long quirks) +static bool intel_ext_cap_allowed(u16 id) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(intel_ext_cap_allow_list); i++) + if (intel_ext_cap_allow_list[i] == id) + return true; + + return false; +} + +static bool intel_ext_cap_disabled(u16 id, unsigned long quirks) +{ + switch (id) { + case INTEL_EXT_CAP_ID_WATCHER: + return !!(quirks & PMT_QUIRK_NO_WATCHER); + + case INTEL_EXT_CAP_ID_CRASHLOG: + return !!(quirks & PMT_QUIRK_NO_CRASHLOG); + + default: + return false; + } +} + +static int intel_ext_cap_add_dev(struct pci_dev *pdev, struct intel_dvsec_header *header, + unsigned long quirks) { struct device *dev = &pdev->dev; struct resource *res, *tmp; struct mfd_cell *cell; - const char *name; + char feature_id_name[FEATURE_ID_NAME_LENGTH]; int count = header->num_entries; int size = header->entry_size; int id = header->id; int i; - switch (id) { - case DVSEC_INTEL_ID_TELEMETRY: - name = "pmt_telemetry"; - break; - case DVSEC_INTEL_ID_WATCHER: - if (quirks & PMT_QUIRK_NO_WATCHER) { - dev_info(dev, "Watcher not supported\n"); - return -EINVAL; - } - name = "pmt_watcher"; - break; - case DVSEC_INTEL_ID_CRASHLOG: - if (quirks & PMT_QUIRK_NO_CRASHLOG) { - dev_info(dev, "Crashlog not supported\n"); - return -EINVAL; - } - name = "pmt_crashlog"; - break; - default: + if (!intel_ext_cap_allowed(id)) + return -EINVAL; + + if (intel_ext_cap_disabled(id, quirks)) + return -EINVAL; + + snprintf(feature_id_name, sizeof(feature_id_name), "%s_%d", INTEL_EXT_CAP_PREFIX, id); + + if (!header->num_entries) { + dev_err(dev, "Invalid 0 entry count for %s header\n", feature_id_name); return -EINVAL; } - if (!header->num_entries || !header->entry_size) { - dev_err(dev, "Invalid count or size for %s header\n", name); + if (!header->entry_size) { + dev_err(dev, "Invalid 0 entry size for %s header\n", feature_id_name); return -EINVAL; } @@ -135,26 +160,26 @@ static int pmt_add_dev(struct pci_dev *pdev, struct intel_dvsec_header *header, header->offset >>= 3; /* - * The PMT DVSEC contains the starting offset and count for a block of + * The DVSEC contains the starting offset and count for a block of * discovery tables, each providing access to monitoring facilities for * a section of the device. Create a resource list of these tables to * provide to the driver. */ for (i = 0, tmp = res; i < count; i++, tmp++) { tmp->start = pdev->resource[header->tbir].start + - header->offset + i * (size << 2); - tmp->end = tmp->start + (size << 2) - 1; + header->offset + i * (size * sizeof(u32)); + tmp->end = tmp->start + (size * sizeof(u32)) - 1; tmp->flags = IORESOURCE_MEM; } cell->resources = res; cell->num_resources = count; - cell->name = name; + cell->name = feature_id_name; - return devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO, cell, 1, NULL, 0, - NULL); + return devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO, cell, 1, NULL, 0, NULL); } + static int pmt_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) { struct pmt_platform_info *info; @@ -176,7 +201,7 @@ static int pmt_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) header = info->capabilities; while (*header) { - ret = pmt_add_dev(pdev, *header, quirks); + ret = intel_ext_cap_add_dev(pdev, *header, quirks); if (ret) dev_warn(&pdev->dev, "Failed to add device for DVSEC id %d\n", @@ -212,7 +237,7 @@ static int pmt_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) header.tbir = INTEL_DVSEC_TABLE_BAR(table); header.offset = INTEL_DVSEC_TABLE_OFFSET(table); - ret = pmt_add_dev(pdev, &header, quirks); + ret = intel_ext_cap_add_dev(pdev, &header, quirks); if (ret) continue; diff --git a/drivers/platform/x86/intel/pmt/crashlog.c b/drivers/platform/x86/intel/pmt/crashlog.c index 1c1021f04d3c..86c4b016af59 100644 --- a/drivers/platform/x86/intel/pmt/crashlog.c +++ b/drivers/platform/x86/intel/pmt/crashlog.c @@ -17,7 +17,7 @@ #include "class.h" -#define DRV_NAME "pmt_crashlog" +#define DRV_NAME "intel_extnd_cap_4" /* Crashlog discovery header types */ #define CRASH_TYPE_OOBMSM 1 diff --git a/drivers/platform/x86/intel/pmt/telemetry.c b/drivers/platform/x86/intel/pmt/telemetry.c index 38d52651c572..d93d02672679 100644 --- a/drivers/platform/x86/intel/pmt/telemetry.c +++ b/drivers/platform/x86/intel/pmt/telemetry.c @@ -17,7 +17,7 @@ #include "class.h" -#define TELEM_DEV_NAME "pmt_telemetry" +#define TELEM_DEV_NAME "intel_extnd_cap_2" #define TELEM_SIZE_OFFSET 0x0 #define TELEM_GUID_OFFSET 0x4 From patchwork Wed Sep 22 21:30:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "David E. Box" X-Patchwork-Id: 12511469 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 666A6C43219 for ; Wed, 22 Sep 2021 21:30:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4F20B61168 for ; Wed, 22 Sep 2021 21:30:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238066AbhIVVbm (ORCPT ); Wed, 22 Sep 2021 17:31:42 -0400 Received: from mga17.intel.com ([192.55.52.151]:19042 "EHLO mga17.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237833AbhIVVbj (ORCPT ); Wed, 22 Sep 2021 17:31:39 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10115"; a="203860363" X-IronPort-AV: E=Sophos;i="5.85,315,1624345200"; d="scan'208";a="203860363" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Sep 2021 14:30:08 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.85,315,1624345200"; d="scan'208";a="513141626" Received: from linux.intel.com ([10.54.29.200]) by fmsmga008.fm.intel.com with ESMTP; 22 Sep 2021 14:30:07 -0700 Received: from debox1-server.jf.intel.com (debox1-server.jf.intel.com [10.54.39.121]) by linux.intel.com (Postfix) with ESMTP id CF621580C8A; Wed, 22 Sep 2021 14:30:07 -0700 (PDT) From: "David E. Box" To: lee.jones@linaro.org, bhelgaas@google.com, andy.shevchenko@gmail.com Cc: "David E. Box" , mgross@linux.intel.com, srinivas.pandruvada@intel.com, linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v3 3/5] MFD: intel_pmt: Add support for PCIe VSEC structures Date: Wed, 22 Sep 2021 14:30:05 -0700 Message-Id: <20210922213007.2738388-4-david.e.box@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210922213007.2738388-1-david.e.box@linux.intel.com> References: <20210922213007.2738388-1-david.e.box@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Adds support for discovering Intel extended capability features from Vendor Specific Extended Capability (VSEC) registers in PCIe config space. Signed-off-by: David E. Box --- V3: No changes V2: Drop new driver. Keep changes in intel_pmt.c drivers/mfd/intel_pmt.c | 158 +++++++++++++++++++++++++++++----------- 1 file changed, 115 insertions(+), 43 deletions(-) diff --git a/drivers/mfd/intel_pmt.c b/drivers/mfd/intel_pmt.c index 08cd3357577e..08e07b31aeec 100644 --- a/drivers/mfd/intel_pmt.c +++ b/drivers/mfd/intel_pmt.c @@ -40,7 +40,8 @@ static int intel_ext_cap_allow_list[] = { INTEL_EXT_CAP_ID_CRASHLOG, }; -struct intel_dvsec_header { +struct intel_ext_cap_header { + u8 rev; u16 length; u16 id; u8 num_entries; @@ -65,7 +66,7 @@ enum pmt_quirks { struct pmt_platform_info { unsigned long quirks; - struct intel_dvsec_header **capabilities; + struct intel_ext_cap_header **capabilities; }; static const struct pmt_platform_info tgl_info = { @@ -74,7 +75,7 @@ static const struct pmt_platform_info tgl_info = { }; /* DG1 Platform with DVSEC quirk*/ -static struct intel_dvsec_header dg1_telemetry = { +static struct intel_ext_cap_header dg1_telemetry = { .length = 0x10, .id = 2, .num_entries = 1, @@ -83,7 +84,7 @@ static struct intel_dvsec_header dg1_telemetry = { .offset = 0x466000, }; -static struct intel_dvsec_header *dg1_capabilities[] = { +static struct intel_ext_cap_header *dg1_capabilities[] = { &dg1_telemetry, NULL }; @@ -118,7 +119,7 @@ static bool intel_ext_cap_disabled(u16 id, unsigned long quirks) } } -static int intel_ext_cap_add_dev(struct pci_dev *pdev, struct intel_dvsec_header *header, +static int intel_ext_cap_add_dev(struct pci_dev *pdev, struct intel_ext_cap_header *header, unsigned long quirks) { struct device *dev = &pdev->dev; @@ -160,7 +161,7 @@ static int intel_ext_cap_add_dev(struct pci_dev *pdev, struct intel_dvsec_header header->offset >>= 3; /* - * The DVSEC contains the starting offset and count for a block of + * The DVSEC/VSEC contains the starting offset and count for a block of * discovery tables, each providing access to monitoring facilities for * a section of the device. Create a resource list of these tables to * provide to the driver. @@ -179,13 +180,113 @@ static int intel_ext_cap_add_dev(struct pci_dev *pdev, struct intel_dvsec_header return devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO, cell, 1, NULL, 0, NULL); } +static bool intel_ext_cap_walk_dvsec(struct pci_dev *pdev, unsigned long quirks) +{ + int count = 0; + int pos = 0; + + do { + struct intel_ext_cap_header header; + u32 table, hdr; + u16 vid; + int ret; + + pos = pci_find_next_ext_capability(pdev, pos, PCI_EXT_CAP_ID_DVSEC); + if (!pos) + break; + + pci_read_config_dword(pdev, pos + PCI_DVSEC_HEADER1, &hdr); + vid = PCI_DVSEC_HEADER1_VID(hdr); + if (vid != PCI_VENDOR_ID_INTEL) + continue; + + /* Support only revision 1 */ + header.rev = PCI_DVSEC_HEADER1_REV(hdr); + if (header.rev != 1) { + dev_warn(&pdev->dev, "Unsupported DVSEC revision %d\n", + header.rev); + continue; + } + + header.length = PCI_DVSEC_HEADER1_LEN(hdr); + + pci_read_config_byte(pdev, pos + INTEL_DVSEC_ENTRIES, + &header.num_entries); + pci_read_config_byte(pdev, pos + INTEL_DVSEC_SIZE, + &header.entry_size); + pci_read_config_dword(pdev, pos + INTEL_DVSEC_TABLE, + &table); + + header.tbir = INTEL_DVSEC_TABLE_BAR(table); + header.offset = INTEL_DVSEC_TABLE_OFFSET(table); + + pci_read_config_dword(pdev, pos + PCI_DVSEC_HEADER2, &hdr); + header.id = PCI_DVSEC_HEADER2_ID(hdr); + + ret = intel_ext_cap_add_dev(pdev, &header, quirks); + if (ret) + continue; + + count++; + } while (true); + + return count; +} + +static bool intel_ext_cap_walk_vsec(struct pci_dev *pdev, unsigned long quirks) +{ + int count = 0; + int pos = 0; + + do { + struct intel_ext_cap_header header; + u32 table, hdr; + int ret; + + pos = pci_find_next_ext_capability(pdev, pos, PCI_EXT_CAP_ID_VNDR); + if (!pos) + break; + + pci_read_config_dword(pdev, pos + PCI_VNDR_HEADER, &hdr); + + /* Support only revision 1 */ + header.rev = PCI_VNDR_HEADER_REV(hdr); + if (header.rev != 1) { + dev_warn(&pdev->dev, "Unsupported VSEC revision %d\n", + header.rev); + continue; + } + + header.id = PCI_VNDR_HEADER_ID(hdr); + header.length = PCI_VNDR_HEADER_LEN(hdr); + + /* entry, size, and table offset are the same as DVSEC */ + pci_read_config_byte(pdev, pos + INTEL_DVSEC_ENTRIES, + &header.num_entries); + pci_read_config_byte(pdev, pos + INTEL_DVSEC_SIZE, + &header.entry_size); + pci_read_config_dword(pdev, pos + INTEL_DVSEC_TABLE, + &table); + + header.tbir = INTEL_DVSEC_TABLE_BAR(table); + header.offset = INTEL_DVSEC_TABLE_OFFSET(table); + + ret = intel_ext_cap_add_dev(pdev, &header, quirks); + if (ret) + continue; + + count++; + } while (true); + + return count; +} static int pmt_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) { struct pmt_platform_info *info; unsigned long quirks = 0; - bool found_devices = false; - int ret, pos = 0; + int device_count = 0; + int ret; ret = pcim_enable_device(pdev); if (ret) @@ -196,8 +297,11 @@ static int pmt_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) if (info) quirks = info->quirks; + device_count += intel_ext_cap_walk_dvsec(pdev, quirks); + device_count += intel_ext_cap_walk_vsec(pdev, quirks); + if (info && (info->quirks & PMT_QUIRK_NO_DVSEC)) { - struct intel_dvsec_header **header; + struct intel_ext_cap_header **header; header = info->capabilities; while (*header) { @@ -207,45 +311,13 @@ static int pmt_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) "Failed to add device for DVSEC id %d\n", (*header)->id); else - found_devices = true; + device_count++; ++header; } - } else { - do { - struct intel_dvsec_header header; - u32 table; - u16 vid; - - pos = pci_find_next_ext_capability(pdev, pos, PCI_EXT_CAP_ID_DVSEC); - if (!pos) - break; - - pci_read_config_word(pdev, pos + PCI_DVSEC_HEADER1, &vid); - if (vid != PCI_VENDOR_ID_INTEL) - continue; - - pci_read_config_word(pdev, pos + PCI_DVSEC_HEADER2, - &header.id); - pci_read_config_byte(pdev, pos + INTEL_DVSEC_ENTRIES, - &header.num_entries); - pci_read_config_byte(pdev, pos + INTEL_DVSEC_SIZE, - &header.entry_size); - pci_read_config_dword(pdev, pos + INTEL_DVSEC_TABLE, - &table); - - header.tbir = INTEL_DVSEC_TABLE_BAR(table); - header.offset = INTEL_DVSEC_TABLE_OFFSET(table); - - ret = intel_ext_cap_add_dev(pdev, &header, quirks); - if (ret) - continue; - - found_devices = true; - } while (true); } - if (!found_devices) + if (!device_count) return -ENODEV; pm_runtime_put(&pdev->dev); From patchwork Wed Sep 22 21:30:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "David E. Box" X-Patchwork-Id: 12511475 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 48FCCC433FE for ; Wed, 22 Sep 2021 21:30:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 37C84611C6 for ; Wed, 22 Sep 2021 21:30:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238135AbhIVVbq (ORCPT ); Wed, 22 Sep 2021 17:31:46 -0400 Received: from mga06.intel.com ([134.134.136.31]:32504 "EHLO mga06.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238035AbhIVVbl (ORCPT ); Wed, 22 Sep 2021 17:31:41 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10115"; a="284717939" X-IronPort-AV: E=Sophos;i="5.85,315,1624345200"; d="scan'208";a="284717939" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Sep 2021 14:30:08 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.85,315,1624345200"; d="scan'208";a="484734583" Received: from linux.intel.com ([10.54.29.200]) by orsmga008.jf.intel.com with ESMTP; 22 Sep 2021 14:30:07 -0700 Received: from debox1-server.jf.intel.com (debox1-server.jf.intel.com [10.54.39.121]) by linux.intel.com (Postfix) with ESMTP id DE386580C75; Wed, 22 Sep 2021 14:30:07 -0700 (PDT) From: "David E. Box" To: lee.jones@linaro.org, bhelgaas@google.com, andy.shevchenko@gmail.com Cc: "David E. Box" , mgross@linux.intel.com, srinivas.pandruvada@intel.com, linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v3 4/5] MFD: intel_pmt: Add DG2 support Date: Wed, 22 Sep 2021 14:30:06 -0700 Message-Id: <20210922213007.2738388-5-david.e.box@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210922213007.2738388-1-david.e.box@linux.intel.com> References: <20210922213007.2738388-1-david.e.box@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add Platform Monitoring Technology support for DG2 platforms. Signed-off-by: David E. Box --- V3: No change V2: New patch drivers/mfd/intel_pmt.c | 9 +++++++++ drivers/platform/x86/intel/pmt/class.c | 2 ++ 2 files changed, 11 insertions(+) diff --git a/drivers/mfd/intel_pmt.c b/drivers/mfd/intel_pmt.c index 08e07b31aeec..a6fe50f65479 100644 --- a/drivers/mfd/intel_pmt.c +++ b/drivers/mfd/intel_pmt.c @@ -94,6 +94,11 @@ static const struct pmt_platform_info dg1_info = { .capabilities = dg1_capabilities, }; +/* DG2 Platform */ +static const struct pmt_platform_info dg2_info = { + .quirks = PMT_QUIRK_TABLE_SHIFT +}; + static bool intel_ext_cap_allowed(u16 id) { int i; @@ -334,11 +339,15 @@ static void pmt_pci_remove(struct pci_dev *pdev) #define PCI_DEVICE_ID_INTEL_PMT_ADL 0x467d #define PCI_DEVICE_ID_INTEL_PMT_DG1 0x490e +#define PCI_DEVICE_ID_INTEL_PMT_DG2_G10 0x4f93 +#define PCI_DEVICE_ID_INTEL_PMT_DG2_G11 0x4f95 #define PCI_DEVICE_ID_INTEL_PMT_OOBMSM 0x09a7 #define PCI_DEVICE_ID_INTEL_PMT_TGL 0x9a0d static const struct pci_device_id pmt_pci_ids[] = { { PCI_DEVICE_DATA(INTEL, PMT_ADL, &tgl_info) }, { PCI_DEVICE_DATA(INTEL, PMT_DG1, &dg1_info) }, + { PCI_DEVICE_DATA(INTEL, PMT_DG2_G10, &dg2_info) }, + { PCI_DEVICE_DATA(INTEL, PMT_DG2_G11, &dg2_info) }, { PCI_DEVICE_DATA(INTEL, PMT_OOBMSM, NULL) }, { PCI_DEVICE_DATA(INTEL, PMT_TGL, &tgl_info) }, { } diff --git a/drivers/platform/x86/intel/pmt/class.c b/drivers/platform/x86/intel/pmt/class.c index 659b1073033c..f2a8e19a02e7 100644 --- a/drivers/platform/x86/intel/pmt/class.c +++ b/drivers/platform/x86/intel/pmt/class.c @@ -29,6 +29,8 @@ static const struct pci_device_id pmt_telem_early_client_pci_ids[] = { { PCI_VDEVICE(INTEL, 0x467d) }, /* ADL */ { PCI_VDEVICE(INTEL, 0x490e) }, /* DG1 */ + { PCI_VDEVICE(INTEL, 0x4f93) }, /* DG2_G10 */ + { PCI_VDEVICE(INTEL, 0x4f95) }, /* DG2_G11 */ { PCI_VDEVICE(INTEL, 0x9a0d) }, /* TGL */ { } }; From patchwork Wed Sep 22 21:30:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "David E. Box" X-Patchwork-Id: 12511467 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BD45BC43217 for ; Wed, 22 Sep 2021 21:30:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A565261211 for ; Wed, 22 Sep 2021 21:30:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238042AbhIVVbl (ORCPT ); Wed, 22 Sep 2021 17:31:41 -0400 Received: from mga12.intel.com ([192.55.52.136]:45002 "EHLO mga12.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237852AbhIVVbj (ORCPT ); Wed, 22 Sep 2021 17:31:39 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10115"; a="203202709" X-IronPort-AV: E=Sophos;i="5.85,315,1624345200"; d="scan'208";a="203202709" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Sep 2021 14:30:08 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.85,315,1624345200"; d="scan'208";a="435588456" Received: from linux.intel.com ([10.54.29.200]) by orsmga006.jf.intel.com with ESMTP; 22 Sep 2021 14:30:08 -0700 Received: from debox1-server.jf.intel.com (debox1-server.jf.intel.com [10.54.39.121]) by linux.intel.com (Postfix) with ESMTP id EBE1E580C8B; Wed, 22 Sep 2021 14:30:07 -0700 (PDT) From: "David E. Box" To: lee.jones@linaro.org, bhelgaas@google.com, andy.shevchenko@gmail.com Cc: "David E. Box" , mgross@linux.intel.com, srinivas.pandruvada@intel.com, linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v3 5/5] MFD: intel_extended_cap: Add support for Intel SDSi Date: Wed, 22 Sep 2021 14:30:07 -0700 Message-Id: <20210922213007.2738388-6-david.e.box@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210922213007.2738388-1-david.e.box@linux.intel.com> References: <20210922213007.2738388-1-david.e.box@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Adds platform device support for the Intel Software Defined Silicon (SDSi) device. Signed-off-by: David E. Box --- V3: New patch drivers/mfd/intel_pmt.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mfd/intel_pmt.c b/drivers/mfd/intel_pmt.c index a6fe50f65479..5d9adcfa67db 100644 --- a/drivers/mfd/intel_pmt.c +++ b/drivers/mfd/intel_pmt.c @@ -30,6 +30,7 @@ #define INTEL_EXT_CAP_ID_TELEMETRY 2 #define INTEL_EXT_CAP_ID_WATCHER 3 #define INTEL_EXT_CAP_ID_CRASHLOG 4 +#define INTEL_EXT_CAP_ID_SDSI 65 #define INTEL_EXT_CAP_PREFIX "intel_extnd_cap" #define FEATURE_ID_NAME_LENGTH 25 @@ -38,6 +39,7 @@ static int intel_ext_cap_allow_list[] = { INTEL_EXT_CAP_ID_TELEMETRY, INTEL_EXT_CAP_ID_WATCHER, INTEL_EXT_CAP_ID_CRASHLOG, + INTEL_EXT_CAP_ID_SDSI, }; struct intel_ext_cap_header {