From patchwork Thu Sep 23 13:20:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12512863 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 05171C433EF for ; Thu, 23 Sep 2021 13:21:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DBEB561211 for ; Thu, 23 Sep 2021 13:21:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241242AbhIWNWh (ORCPT ); Thu, 23 Sep 2021 09:22:37 -0400 Received: from esa.microchip.iphmx.com ([68.232.153.233]:42888 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241222AbhIWNWg (ORCPT ); Thu, 23 Sep 2021 09:22:36 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1632403264; x=1663939264; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=rdyYxX9kI9XRVOkHrnczUa3imNHEUgSsFG0/Pwlv9QA=; b=2EG2QVv9LXmwDqKJD+DYIT7Y1j1g6L10KokOuHSyFwRZATSc6obs5gKH RhSKaJSL40aXoWQcEQ6bnFOUszDD5HBIwEr5PZKRmAyOlfEtYF/cYzzpC SQvr4do2t/+1q8Sjgzcj6sxmc9Bq9rOC3plLi7LqDARQky2a8wUdsoz3j xHEo0nD0Muouc7KrQArRvLwOoqreB0hFLiQi5eoHpYXoU3LQSFsXDm23C nu9Frbs1hXmTMUnW7SK6LmDtNbM0NZ+aLdPucTOu8lEHV9f3ohEPoWX4c JxWi/xSQbU2EV9j3c7JGlhju8V1LqisA5QzSfNlKj3xNhAXoTMX+htBGK g==; IronPort-SDR: p/N1JG26CwquA9H3JMzV1Li0tWVh45YvUaRYgt+vO6MKbIZy73IGldvvZ/Cg6djyw9ZLYzA88E ovjDrwgsf/OGzLpdIdeSYs15yEryBKWPcIQ9BfZm13GTdFuWJCYtNixkZ5rhAhsWh+R4hoWXv8 3Ch2tQp56wMVNIb5AnXy/IfEnVCjcjFQCPce46Rn0d8d1TyeFau5C0/Gcc6NCY7xBNBscUh4mc tfsi1J5gn47EOSgSRLvwKcEP53umzhQGQxp8ttr5uVsJkpIhJPJZm8N4RJ46AVaaK8EfT8S5et 3D52bF0OMGPsye5XLq4ihXcA X-IronPort-AV: E=Sophos;i="5.85,316,1624345200"; d="scan'208";a="137664768" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 23 Sep 2021 06:21:04 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Thu, 23 Sep 2021 06:21:03 -0700 Received: from rob-dk-mpu01.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Thu, 23 Sep 2021 06:21:01 -0700 From: Claudiu Beznea To: , , , , CC: , , , Claudiu Beznea Subject: [PATCH v4 01/17] clk: at91: re-factor clocks suspend/resume Date: Thu, 23 Sep 2021 16:20:30 +0300 Message-ID: <20210923132046.1860549-2-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210923132046.1860549-1-claudiu.beznea@microchip.com> References: <20210923132046.1860549-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org SAMA5D2 and SAMA7G5 have a special power saving mode (backup mode) where most of the SoC's components are powered off (including PMC). Resuming from this mode is done with the help of bootloader. Peripherals are not aware of the power saving mode thus most of them are disabling clocks in proper suspend API and re-enable them in resume API without taking into account the previously setup rate. Moreover some of the peripherals are acting as wakeup sources and are not disabling the clocks in this scenario, when suspending. Since backup mode cuts the power for peripherals, in resume part these clocks needs to be re-configured. The initial PMC suspend/resume code was designed only for SAMA5D2's PMC (as it was the only one supporting backup mode). SAMA7G supports also backup mode and its PMC is different (few new functionalities, different registers offsets, different offsets in registers for each functionalities). To address both SAMA5D2 and SAMA7G5 PMC add .save_context()/.resume_context() support to each clocks driver and call this from PMC driver. Signed-off-by: Claudiu Beznea --- drivers/clk/at91/clk-generated.c | 46 +++++-- drivers/clk/at91/clk-main.c | 66 ++++++++++ drivers/clk/at91/clk-master.c | 194 ++++++++++++++++++++++++++-- drivers/clk/at91/clk-peripheral.c | 40 +++++- drivers/clk/at91/clk-pll.c | 39 ++++++ drivers/clk/at91/clk-programmable.c | 29 ++++- drivers/clk/at91/clk-sam9x60-pll.c | 68 +++++++++- drivers/clk/at91/clk-system.c | 20 +++ drivers/clk/at91/clk-usb.c | 27 ++++ drivers/clk/at91/clk-utmi.c | 39 ++++++ drivers/clk/at91/pmc.c | 147 +-------------------- drivers/clk/at91/pmc.h | 24 ++-- 12 files changed, 558 insertions(+), 181 deletions(-) diff --git a/drivers/clk/at91/clk-generated.c b/drivers/clk/at91/clk-generated.c index b656d25a9767..23cc8297ec4c 100644 --- a/drivers/clk/at91/clk-generated.c +++ b/drivers/clk/at91/clk-generated.c @@ -27,6 +27,7 @@ struct clk_generated { u32 id; u32 gckdiv; const struct clk_pcr_layout *layout; + struct at91_clk_pms pms; u8 parent_id; int chg_pid; }; @@ -34,25 +35,35 @@ struct clk_generated { #define to_clk_generated(hw) \ container_of(hw, struct clk_generated, hw) -static int clk_generated_enable(struct clk_hw *hw) +static int clk_generated_set(struct clk_generated *gck, int status) { - struct clk_generated *gck = to_clk_generated(hw); unsigned long flags; - - pr_debug("GCLK: %s, gckdiv = %d, parent id = %d\n", - __func__, gck->gckdiv, gck->parent_id); + unsigned int enable = status ? AT91_PMC_PCR_GCKEN : 0; spin_lock_irqsave(gck->lock, flags); regmap_write(gck->regmap, gck->layout->offset, (gck->id & gck->layout->pid_mask)); regmap_update_bits(gck->regmap, gck->layout->offset, AT91_PMC_PCR_GCKDIV_MASK | gck->layout->gckcss_mask | - gck->layout->cmd | AT91_PMC_PCR_GCKEN, + gck->layout->cmd | enable, field_prep(gck->layout->gckcss_mask, gck->parent_id) | gck->layout->cmd | FIELD_PREP(AT91_PMC_PCR_GCKDIV_MASK, gck->gckdiv) | - AT91_PMC_PCR_GCKEN); + enable); spin_unlock_irqrestore(gck->lock, flags); + + return 0; +} + +static int clk_generated_enable(struct clk_hw *hw) +{ + struct clk_generated *gck = to_clk_generated(hw); + + pr_debug("GCLK: %s, gckdiv = %d, parent id = %d\n", + __func__, gck->gckdiv, gck->parent_id); + + clk_generated_set(gck, 1); + return 0; } @@ -245,6 +256,23 @@ static int clk_generated_set_rate(struct clk_hw *hw, return 0; } +static int clk_generated_save_context(struct clk_hw *hw) +{ + struct clk_generated *gck = to_clk_generated(hw); + + gck->pms.status = clk_generated_is_enabled(&gck->hw); + + return 0; +} + +static void clk_generated_restore_context(struct clk_hw *hw) +{ + struct clk_generated *gck = to_clk_generated(hw); + + if (gck->pms.status) + clk_generated_set(gck, gck->pms.status); +} + static const struct clk_ops generated_ops = { .enable = clk_generated_enable, .disable = clk_generated_disable, @@ -254,6 +282,8 @@ static const struct clk_ops generated_ops = { .get_parent = clk_generated_get_parent, .set_parent = clk_generated_set_parent, .set_rate = clk_generated_set_rate, + .save_context = clk_generated_save_context, + .restore_context = clk_generated_restore_context, }; /** @@ -320,8 +350,6 @@ at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock, if (ret) { kfree(gck); hw = ERR_PTR(ret); - } else { - pmc_register_id(id); } return hw; diff --git a/drivers/clk/at91/clk-main.c b/drivers/clk/at91/clk-main.c index cfae2f59df66..8601b27c1ae0 100644 --- a/drivers/clk/at91/clk-main.c +++ b/drivers/clk/at91/clk-main.c @@ -28,6 +28,7 @@ struct clk_main_osc { struct clk_hw hw; struct regmap *regmap; + struct at91_clk_pms pms; }; #define to_clk_main_osc(hw) container_of(hw, struct clk_main_osc, hw) @@ -37,6 +38,7 @@ struct clk_main_rc_osc { struct regmap *regmap; unsigned long frequency; unsigned long accuracy; + struct at91_clk_pms pms; }; #define to_clk_main_rc_osc(hw) container_of(hw, struct clk_main_rc_osc, hw) @@ -51,6 +53,7 @@ struct clk_rm9200_main { struct clk_sam9x5_main { struct clk_hw hw; struct regmap *regmap; + struct at91_clk_pms pms; u8 parent; }; @@ -120,10 +123,29 @@ static int clk_main_osc_is_prepared(struct clk_hw *hw) return (status & AT91_PMC_MOSCS) && clk_main_parent_select(tmp); } +static int clk_main_osc_save_context(struct clk_hw *hw) +{ + struct clk_main_osc *osc = to_clk_main_osc(hw); + + osc->pms.status = clk_main_osc_is_prepared(hw); + + return 0; +} + +static void clk_main_osc_restore_context(struct clk_hw *hw) +{ + struct clk_main_osc *osc = to_clk_main_osc(hw); + + if (osc->pms.status) + clk_main_osc_prepare(hw); +} + static const struct clk_ops main_osc_ops = { .prepare = clk_main_osc_prepare, .unprepare = clk_main_osc_unprepare, .is_prepared = clk_main_osc_is_prepared, + .save_context = clk_main_osc_save_context, + .restore_context = clk_main_osc_restore_context, }; struct clk_hw * __init @@ -240,12 +262,31 @@ static unsigned long clk_main_rc_osc_recalc_accuracy(struct clk_hw *hw, return osc->accuracy; } +static int clk_main_rc_osc_save_context(struct clk_hw *hw) +{ + struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw); + + osc->pms.status = clk_main_rc_osc_is_prepared(hw); + + return 0; +} + +static void clk_main_rc_osc_restore_context(struct clk_hw *hw) +{ + struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw); + + if (osc->pms.status) + clk_main_rc_osc_prepare(hw); +} + static const struct clk_ops main_rc_osc_ops = { .prepare = clk_main_rc_osc_prepare, .unprepare = clk_main_rc_osc_unprepare, .is_prepared = clk_main_rc_osc_is_prepared, .recalc_rate = clk_main_rc_osc_recalc_rate, .recalc_accuracy = clk_main_rc_osc_recalc_accuracy, + .save_context = clk_main_rc_osc_save_context, + .restore_context = clk_main_rc_osc_restore_context, }; struct clk_hw * __init @@ -465,12 +506,37 @@ static u8 clk_sam9x5_main_get_parent(struct clk_hw *hw) return clk_main_parent_select(status); } +static int clk_sam9x5_main_save_context(struct clk_hw *hw) +{ + struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw); + + clkmain->pms.status = clk_main_rc_osc_is_prepared(&clkmain->hw); + clkmain->pms.parent = clk_sam9x5_main_get_parent(&clkmain->hw); + + return 0; +} + +static void clk_sam9x5_main_restore_context(struct clk_hw *hw) +{ + struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw); + int ret; + + ret = clk_sam9x5_main_set_parent(hw, clkmain->pms.parent); + if (ret) + return; + + if (clkmain->pms.status) + clk_sam9x5_main_prepare(hw); +} + static const struct clk_ops sam9x5_main_ops = { .prepare = clk_sam9x5_main_prepare, .is_prepared = clk_sam9x5_main_is_prepared, .recalc_rate = clk_sam9x5_main_recalc_rate, .set_parent = clk_sam9x5_main_set_parent, .get_parent = clk_sam9x5_main_get_parent, + .save_context = clk_sam9x5_main_save_context, + .restore_context = clk_sam9x5_main_restore_context, }; struct clk_hw * __init diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c index a80427980bf7..f75549fff023 100644 --- a/drivers/clk/at91/clk-master.c +++ b/drivers/clk/at91/clk-master.c @@ -37,6 +37,7 @@ struct clk_master { spinlock_t *lock; const struct clk_master_layout *layout; const struct clk_master_characteristics *characteristics; + struct at91_clk_pms pms; u32 *mux_table; u32 mckr; int chg_pid; @@ -112,10 +113,52 @@ static unsigned long clk_master_div_recalc_rate(struct clk_hw *hw, return rate; } +static int clk_master_div_save_context(struct clk_hw *hw) +{ + struct clk_master *master = to_clk_master(hw); + struct clk_hw *parent_hw = clk_hw_get_parent(hw); + unsigned long flags; + unsigned int mckr, div; + + spin_lock_irqsave(master->lock, flags); + regmap_read(master->regmap, master->layout->offset, &mckr); + spin_unlock_irqrestore(master->lock, flags); + + mckr &= master->layout->mask; + div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; + div = master->characteristics->divisors[div]; + + master->pms.parent_rate = clk_hw_get_rate(parent_hw); + master->pms.rate = DIV_ROUND_CLOSEST(master->pms.parent_rate, div); + + return 0; +} + +static void clk_master_div_restore_context(struct clk_hw *hw) +{ + struct clk_master *master = to_clk_master(hw); + unsigned long flags; + unsigned int mckr; + u8 div; + + spin_lock_irqsave(master->lock, flags); + regmap_read(master->regmap, master->layout->offset, &mckr); + spin_unlock_irqrestore(master->lock, flags); + + mckr &= master->layout->mask; + div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; + div = master->characteristics->divisors[div]; + + if (div != DIV_ROUND_CLOSEST(master->pms.parent_rate, master->pms.rate)) + pr_warn("MCKR DIV not configured properly by firmware!\n"); +} + static const struct clk_ops master_div_ops = { .prepare = clk_master_prepare, .is_prepared = clk_master_is_prepared, .recalc_rate = clk_master_div_recalc_rate, + .save_context = clk_master_div_save_context, + .restore_context = clk_master_div_restore_context, }; static int clk_master_div_set_rate(struct clk_hw *hw, unsigned long rate, @@ -125,7 +168,9 @@ static int clk_master_div_set_rate(struct clk_hw *hw, unsigned long rate, const struct clk_master_characteristics *characteristics = master->characteristics; unsigned long flags; + unsigned int mckr, tmp; int div, i; + int ret; div = DIV_ROUND_CLOSEST(parent_rate, rate); if (div > ARRAY_SIZE(characteristics->divisors)) @@ -145,11 +190,24 @@ static int clk_master_div_set_rate(struct clk_hw *hw, unsigned long rate, return -EINVAL; spin_lock_irqsave(master->lock, flags); - regmap_update_bits(master->regmap, master->layout->offset, - (MASTER_DIV_MASK << MASTER_DIV_SHIFT), - (div << MASTER_DIV_SHIFT)); + ret = regmap_read(master->regmap, master->layout->offset, &mckr); + if (ret) + goto unlock; + + tmp = mckr & master->layout->mask; + tmp = (tmp >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; + if (tmp == div) + goto unlock; + + mckr &= ~(MASTER_DIV_MASK << MASTER_DIV_SHIFT); + mckr |= (div << MASTER_DIV_SHIFT); + ret = regmap_write(master->regmap, master->layout->offset, mckr); + if (ret) + goto unlock; + while (!clk_master_ready(master)) cpu_relax(); +unlock: spin_unlock_irqrestore(master->lock, flags); return 0; @@ -197,12 +255,25 @@ static int clk_master_div_determine_rate(struct clk_hw *hw, return 0; } +static void clk_master_div_restore_context_chg(struct clk_hw *hw) +{ + struct clk_master *master = to_clk_master(hw); + int ret; + + ret = clk_master_div_set_rate(hw, master->pms.rate, + master->pms.parent_rate); + if (ret) + pr_warn("Failed to restore MCK DIV clock\n"); +} + static const struct clk_ops master_div_ops_chg = { .prepare = clk_master_prepare, .is_prepared = clk_master_is_prepared, .recalc_rate = clk_master_div_recalc_rate, .determine_rate = clk_master_div_determine_rate, .set_rate = clk_master_div_set_rate, + .save_context = clk_master_div_save_context, + .restore_context = clk_master_div_restore_context_chg, }; static void clk_sama7g5_master_best_diff(struct clk_rate_request *req, @@ -272,7 +343,8 @@ static int clk_master_pres_set_rate(struct clk_hw *hw, unsigned long rate, { struct clk_master *master = to_clk_master(hw); unsigned long flags; - unsigned int pres; + unsigned int pres, mckr, tmp; + int ret; pres = DIV_ROUND_CLOSEST(parent_rate, rate); if (pres > MASTER_PRES_MAX) @@ -284,15 +356,27 @@ static int clk_master_pres_set_rate(struct clk_hw *hw, unsigned long rate, pres = ffs(pres) - 1; spin_lock_irqsave(master->lock, flags); - regmap_update_bits(master->regmap, master->layout->offset, - (MASTER_PRES_MASK << master->layout->pres_shift), - (pres << master->layout->pres_shift)); + ret = regmap_read(master->regmap, master->layout->offset, &mckr); + if (ret) + goto unlock; + + mckr &= master->layout->mask; + tmp = (mckr >> master->layout->pres_shift) & MASTER_PRES_MASK; + if (pres == tmp) + goto unlock; + + mckr &= ~(MASTER_PRES_MASK << master->layout->pres_shift); + mckr |= (pres << master->layout->pres_shift); + ret = regmap_write(master->regmap, master->layout->offset, mckr); + if (ret) + goto unlock; while (!clk_master_ready(master)) cpu_relax(); +unlock: spin_unlock_irqrestore(master->lock, flags); - return 0; + return ret; } static unsigned long clk_master_pres_recalc_rate(struct clk_hw *hw, @@ -330,11 +414,68 @@ static u8 clk_master_pres_get_parent(struct clk_hw *hw) return mckr & AT91_PMC_CSS; } +static int clk_master_pres_save_context(struct clk_hw *hw) +{ + struct clk_master *master = to_clk_master(hw); + struct clk_hw *parent_hw = clk_hw_get_parent(hw); + unsigned long flags; + unsigned int val, pres; + + spin_lock_irqsave(master->lock, flags); + regmap_read(master->regmap, master->layout->offset, &val); + spin_unlock_irqrestore(master->lock, flags); + + val &= master->layout->mask; + pres = (val >> master->layout->pres_shift) & MASTER_PRES_MASK; + if (pres == MASTER_PRES_MAX && master->characteristics->have_div3_pres) + pres = 3; + else + pres = (1 << pres); + + master->pms.parent = val & AT91_PMC_CSS; + master->pms.parent_rate = clk_hw_get_rate(parent_hw); + master->pms.rate = DIV_ROUND_CLOSEST_ULL(master->pms.parent_rate, pres); + + return 0; +} + +static void clk_master_pres_restore_context(struct clk_hw *hw) +{ + struct clk_master *master = to_clk_master(hw); + unsigned long flags; + unsigned int val, pres; + + spin_lock_irqsave(master->lock, flags); + regmap_read(master->regmap, master->layout->offset, &val); + spin_unlock_irqrestore(master->lock, flags); + + val &= master->layout->mask; + pres = (val >> master->layout->pres_shift) & MASTER_PRES_MASK; + if (pres == MASTER_PRES_MAX && master->characteristics->have_div3_pres) + pres = 3; + else + pres = (1 << pres); + + if (master->pms.rate != + DIV_ROUND_CLOSEST_ULL(master->pms.parent_rate, pres) || + (master->pms.parent != (val & AT91_PMC_CSS))) + pr_warn("MCKR PRES was not configured properly by firmware!\n"); +} + +static void clk_master_pres_restore_context_chg(struct clk_hw *hw) +{ + struct clk_master *master = to_clk_master(hw); + + clk_master_pres_set_rate(hw, master->pms.rate, master->pms.parent_rate); +} + static const struct clk_ops master_pres_ops = { .prepare = clk_master_prepare, .is_prepared = clk_master_is_prepared, .recalc_rate = clk_master_pres_recalc_rate, .get_parent = clk_master_pres_get_parent, + .save_context = clk_master_pres_save_context, + .restore_context = clk_master_pres_restore_context, }; static const struct clk_ops master_pres_ops_chg = { @@ -344,6 +485,8 @@ static const struct clk_ops master_pres_ops_chg = { .recalc_rate = clk_master_pres_recalc_rate, .get_parent = clk_master_pres_get_parent, .set_rate = clk_master_pres_set_rate, + .save_context = clk_master_pres_save_context, + .restore_context = clk_master_pres_restore_context_chg, }; static struct clk_hw * __init @@ -539,20 +682,21 @@ static int clk_sama7g5_master_set_parent(struct clk_hw *hw, u8 index) return 0; } -static int clk_sama7g5_master_enable(struct clk_hw *hw) +static void clk_sama7g5_master_set(struct clk_master *master, + unsigned int status) { - struct clk_master *master = to_clk_master(hw); unsigned long flags; unsigned int val, cparent; + unsigned int enable = status ? PMC_MCR_EN : 0; spin_lock_irqsave(master->lock, flags); regmap_write(master->regmap, PMC_MCR, PMC_MCR_ID(master->id)); regmap_read(master->regmap, PMC_MCR, &val); regmap_update_bits(master->regmap, PMC_MCR, - PMC_MCR_EN | PMC_MCR_CSS | PMC_MCR_DIV | + enable | PMC_MCR_CSS | PMC_MCR_DIV | PMC_MCR_CMD | PMC_MCR_ID_MSK, - PMC_MCR_EN | (master->parent << PMC_MCR_CSS_SHIFT) | + enable | (master->parent << PMC_MCR_CSS_SHIFT) | (master->div << MASTER_DIV_SHIFT) | PMC_MCR_CMD | PMC_MCR_ID(master->id)); @@ -563,6 +707,13 @@ static int clk_sama7g5_master_enable(struct clk_hw *hw) cpu_relax(); spin_unlock_irqrestore(master->lock, flags); +} + +static int clk_sama7g5_master_enable(struct clk_hw *hw) +{ + struct clk_master *master = to_clk_master(hw); + + clk_sama7g5_master_set(master, 1); return 0; } @@ -620,6 +771,23 @@ static int clk_sama7g5_master_set_rate(struct clk_hw *hw, unsigned long rate, return 0; } +static int clk_sama7g5_master_save_context(struct clk_hw *hw) +{ + struct clk_master *master = to_clk_master(hw); + + master->pms.status = clk_sama7g5_master_is_enabled(hw); + + return 0; +} + +static void clk_sama7g5_master_restore_context(struct clk_hw *hw) +{ + struct clk_master *master = to_clk_master(hw); + + if (master->pms.status) + clk_sama7g5_master_set(master, master->pms.status); +} + static const struct clk_ops sama7g5_master_ops = { .enable = clk_sama7g5_master_enable, .disable = clk_sama7g5_master_disable, @@ -629,6 +797,8 @@ static const struct clk_ops sama7g5_master_ops = { .set_rate = clk_sama7g5_master_set_rate, .get_parent = clk_sama7g5_master_get_parent, .set_parent = clk_sama7g5_master_set_parent, + .save_context = clk_sama7g5_master_save_context, + .restore_context = clk_sama7g5_master_restore_context, }; struct clk_hw * __init diff --git a/drivers/clk/at91/clk-peripheral.c b/drivers/clk/at91/clk-peripheral.c index 7a27ba8e0577..e14fa5ac734c 100644 --- a/drivers/clk/at91/clk-peripheral.c +++ b/drivers/clk/at91/clk-peripheral.c @@ -37,6 +37,7 @@ struct clk_sam9x5_peripheral { u32 id; u32 div; const struct clk_pcr_layout *layout; + struct at91_clk_pms pms; bool auto_div; int chg_pid; }; @@ -155,10 +156,11 @@ static void clk_sam9x5_peripheral_autodiv(struct clk_sam9x5_peripheral *periph) periph->div = shift; } -static int clk_sam9x5_peripheral_enable(struct clk_hw *hw) +static int clk_sam9x5_peripheral_set(struct clk_sam9x5_peripheral *periph, + unsigned int status) { - struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw); unsigned long flags; + unsigned int enable = status ? AT91_PMC_PCR_EN : 0; if (periph->id < PERIPHERAL_ID_MIN) return 0; @@ -168,15 +170,21 @@ static int clk_sam9x5_peripheral_enable(struct clk_hw *hw) (periph->id & periph->layout->pid_mask)); regmap_update_bits(periph->regmap, periph->layout->offset, periph->layout->div_mask | periph->layout->cmd | - AT91_PMC_PCR_EN, + enable, field_prep(periph->layout->div_mask, periph->div) | - periph->layout->cmd | - AT91_PMC_PCR_EN); + periph->layout->cmd | enable); spin_unlock_irqrestore(periph->lock, flags); return 0; } +static int clk_sam9x5_peripheral_enable(struct clk_hw *hw) +{ + struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw); + + return clk_sam9x5_peripheral_set(periph, 1); +} + static void clk_sam9x5_peripheral_disable(struct clk_hw *hw) { struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw); @@ -393,6 +401,23 @@ static int clk_sam9x5_peripheral_set_rate(struct clk_hw *hw, return -EINVAL; } +static int clk_sam9x5_peripheral_save_context(struct clk_hw *hw) +{ + struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw); + + periph->pms.status = clk_sam9x5_peripheral_is_enabled(hw); + + return 0; +} + +static void clk_sam9x5_peripheral_restore_context(struct clk_hw *hw) +{ + struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw); + + if (periph->pms.status) + clk_sam9x5_peripheral_set(periph, periph->pms.status); +} + static const struct clk_ops sam9x5_peripheral_ops = { .enable = clk_sam9x5_peripheral_enable, .disable = clk_sam9x5_peripheral_disable, @@ -400,6 +425,8 @@ static const struct clk_ops sam9x5_peripheral_ops = { .recalc_rate = clk_sam9x5_peripheral_recalc_rate, .round_rate = clk_sam9x5_peripheral_round_rate, .set_rate = clk_sam9x5_peripheral_set_rate, + .save_context = clk_sam9x5_peripheral_save_context, + .restore_context = clk_sam9x5_peripheral_restore_context, }; static const struct clk_ops sam9x5_peripheral_chg_ops = { @@ -409,6 +436,8 @@ static const struct clk_ops sam9x5_peripheral_chg_ops = { .recalc_rate = clk_sam9x5_peripheral_recalc_rate, .determine_rate = clk_sam9x5_peripheral_determine_rate, .set_rate = clk_sam9x5_peripheral_set_rate, + .save_context = clk_sam9x5_peripheral_save_context, + .restore_context = clk_sam9x5_peripheral_restore_context, }; struct clk_hw * __init @@ -460,7 +489,6 @@ at91_clk_register_sam9x5_peripheral(struct regmap *regmap, spinlock_t *lock, hw = ERR_PTR(ret); } else { clk_sam9x5_peripheral_autodiv(periph); - pmc_register_id(id); } return hw; diff --git a/drivers/clk/at91/clk-pll.c b/drivers/clk/at91/clk-pll.c index 6ed986d3eee0..249d6a53cedf 100644 --- a/drivers/clk/at91/clk-pll.c +++ b/drivers/clk/at91/clk-pll.c @@ -40,6 +40,7 @@ struct clk_pll { u16 mul; const struct clk_pll_layout *layout; const struct clk_pll_characteristics *characteristics; + struct at91_clk_pms pms; }; static inline bool clk_pll_ready(struct regmap *regmap, int id) @@ -260,6 +261,42 @@ static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, return 0; } +static int clk_pll_save_context(struct clk_hw *hw) +{ + struct clk_pll *pll = to_clk_pll(hw); + struct clk_hw *parent_hw = clk_hw_get_parent(hw); + + pll->pms.parent_rate = clk_hw_get_rate(parent_hw); + pll->pms.rate = clk_pll_recalc_rate(&pll->hw, pll->pms.parent_rate); + pll->pms.status = clk_pll_ready(pll->regmap, PLL_REG(pll->id)); + + return 0; +} + +static void clk_pll_restore_context(struct clk_hw *hw) +{ + struct clk_pll *pll = to_clk_pll(hw); + unsigned long calc_rate; + unsigned int pllr, pllr_out, pllr_count; + u8 out = 0; + + if (pll->characteristics->out) + out = pll->characteristics->out[pll->range]; + + regmap_read(pll->regmap, PLL_REG(pll->id), &pllr); + + calc_rate = (pll->pms.parent_rate / PLL_DIV(pllr)) * + (PLL_MUL(pllr, pll->layout) + 1); + pllr_count = (pllr >> PLL_COUNT_SHIFT) & PLL_MAX_COUNT; + pllr_out = (pllr >> PLL_OUT_SHIFT) & out; + + if (pll->pms.rate != calc_rate || + pll->pms.status != clk_pll_ready(pll->regmap, PLL_REG(pll->id)) || + pllr_count != PLL_MAX_COUNT || + (out && pllr_out != out)) + pr_warn("PLLAR was not configured properly by firmware\n"); +} + static const struct clk_ops pll_ops = { .prepare = clk_pll_prepare, .unprepare = clk_pll_unprepare, @@ -267,6 +304,8 @@ static const struct clk_ops pll_ops = { .recalc_rate = clk_pll_recalc_rate, .round_rate = clk_pll_round_rate, .set_rate = clk_pll_set_rate, + .save_context = clk_pll_save_context, + .restore_context = clk_pll_restore_context, }; struct clk_hw * __init diff --git a/drivers/clk/at91/clk-programmable.c b/drivers/clk/at91/clk-programmable.c index fcf8f6a1c2c6..6c4b259d31d3 100644 --- a/drivers/clk/at91/clk-programmable.c +++ b/drivers/clk/at91/clk-programmable.c @@ -24,6 +24,7 @@ struct clk_programmable { u32 *mux_table; u8 id; const struct clk_programmable_layout *layout; + struct at91_clk_pms pms; }; #define to_clk_programmable(hw) container_of(hw, struct clk_programmable, hw) @@ -177,12 +178,38 @@ static int clk_programmable_set_rate(struct clk_hw *hw, unsigned long rate, return 0; } +static int clk_programmable_save_context(struct clk_hw *hw) +{ + struct clk_programmable *prog = to_clk_programmable(hw); + struct clk_hw *parent_hw = clk_hw_get_parent(hw); + + prog->pms.parent = clk_programmable_get_parent(hw); + prog->pms.parent_rate = clk_hw_get_rate(parent_hw); + prog->pms.rate = clk_programmable_recalc_rate(hw, prog->pms.parent_rate); + + return 0; +} + +static void clk_programmable_restore_context(struct clk_hw *hw) +{ + struct clk_programmable *prog = to_clk_programmable(hw); + int ret; + + ret = clk_programmable_set_parent(hw, prog->pms.parent); + if (ret) + return; + + clk_programmable_set_rate(hw, prog->pms.rate, prog->pms.parent_rate); +} + static const struct clk_ops programmable_ops = { .recalc_rate = clk_programmable_recalc_rate, .determine_rate = clk_programmable_determine_rate, .get_parent = clk_programmable_get_parent, .set_parent = clk_programmable_set_parent, .set_rate = clk_programmable_set_rate, + .save_context = clk_programmable_save_context, + .restore_context = clk_programmable_restore_context, }; struct clk_hw * __init @@ -221,8 +248,6 @@ at91_clk_register_programmable(struct regmap *regmap, if (ret) { kfree(prog); hw = ERR_PTR(ret); - } else { - pmc_register_pck(id); } return hw; diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c index 34e3ab13741a..7020d3bf6e13 100644 --- a/drivers/clk/at91/clk-sam9x60-pll.c +++ b/drivers/clk/at91/clk-sam9x60-pll.c @@ -38,12 +38,14 @@ struct sam9x60_pll_core { struct sam9x60_frac { struct sam9x60_pll_core core; + struct at91_clk_pms pms; u32 frac; u16 mul; }; struct sam9x60_div { struct sam9x60_pll_core core; + struct at91_clk_pms pms; u8 div; }; @@ -75,9 +77,8 @@ static unsigned long sam9x60_frac_pll_recalc_rate(struct clk_hw *hw, ((u64)parent_rate * frac->frac >> 22)); } -static int sam9x60_frac_pll_prepare(struct clk_hw *hw) +static int sam9x60_frac_pll_set(struct sam9x60_pll_core *core) { - struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); struct sam9x60_frac *frac = to_sam9x60_frac(core); struct regmap *regmap = core->regmap; unsigned int val, cfrac, cmul; @@ -141,6 +142,13 @@ static int sam9x60_frac_pll_prepare(struct clk_hw *hw) return 0; } +static int sam9x60_frac_pll_prepare(struct clk_hw *hw) +{ + struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); + + return sam9x60_frac_pll_set(core); +} + static void sam9x60_frac_pll_unprepare(struct clk_hw *hw) { struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); @@ -280,6 +288,25 @@ static int sam9x60_frac_pll_set_rate_chg(struct clk_hw *hw, unsigned long rate, return ret; } +static int sam9x60_frac_pll_save_context(struct clk_hw *hw) +{ + struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); + struct sam9x60_frac *frac = to_sam9x60_frac(core); + + frac->pms.status = sam9x60_pll_ready(core->regmap, core->id); + + return 0; +} + +static void sam9x60_frac_pll_restore_context(struct clk_hw *hw) +{ + struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); + struct sam9x60_frac *frac = to_sam9x60_frac(core); + + if (frac->pms.status) + sam9x60_frac_pll_set(core); +} + static const struct clk_ops sam9x60_frac_pll_ops = { .prepare = sam9x60_frac_pll_prepare, .unprepare = sam9x60_frac_pll_unprepare, @@ -287,6 +314,8 @@ static const struct clk_ops sam9x60_frac_pll_ops = { .recalc_rate = sam9x60_frac_pll_recalc_rate, .round_rate = sam9x60_frac_pll_round_rate, .set_rate = sam9x60_frac_pll_set_rate, + .save_context = sam9x60_frac_pll_save_context, + .restore_context = sam9x60_frac_pll_restore_context, }; static const struct clk_ops sam9x60_frac_pll_ops_chg = { @@ -296,11 +325,12 @@ static const struct clk_ops sam9x60_frac_pll_ops_chg = { .recalc_rate = sam9x60_frac_pll_recalc_rate, .round_rate = sam9x60_frac_pll_round_rate, .set_rate = sam9x60_frac_pll_set_rate_chg, + .save_context = sam9x60_frac_pll_save_context, + .restore_context = sam9x60_frac_pll_restore_context, }; -static int sam9x60_div_pll_prepare(struct clk_hw *hw) +static int sam9x60_div_pll_set(struct sam9x60_pll_core *core) { - struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); struct sam9x60_div *div = to_sam9x60_div(core); struct regmap *regmap = core->regmap; unsigned long flags; @@ -334,6 +364,13 @@ static int sam9x60_div_pll_prepare(struct clk_hw *hw) return 0; } +static int sam9x60_div_pll_prepare(struct clk_hw *hw) +{ + struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); + + return sam9x60_div_pll_set(core); +} + static void sam9x60_div_pll_unprepare(struct clk_hw *hw) { struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); @@ -482,6 +519,25 @@ static int sam9x60_div_pll_set_rate_chg(struct clk_hw *hw, unsigned long rate, return 0; } +static int sam9x60_div_pll_save_context(struct clk_hw *hw) +{ + struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); + struct sam9x60_div *div = to_sam9x60_div(core); + + div->pms.status = sam9x60_div_pll_is_prepared(hw); + + return 0; +} + +static void sam9x60_div_pll_restore_context(struct clk_hw *hw) +{ + struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); + struct sam9x60_div *div = to_sam9x60_div(core); + + if (div->pms.status) + sam9x60_div_pll_set(core); +} + static const struct clk_ops sam9x60_div_pll_ops = { .prepare = sam9x60_div_pll_prepare, .unprepare = sam9x60_div_pll_unprepare, @@ -489,6 +545,8 @@ static const struct clk_ops sam9x60_div_pll_ops = { .recalc_rate = sam9x60_div_pll_recalc_rate, .round_rate = sam9x60_div_pll_round_rate, .set_rate = sam9x60_div_pll_set_rate, + .save_context = sam9x60_div_pll_save_context, + .restore_context = sam9x60_div_pll_restore_context, }; static const struct clk_ops sam9x60_div_pll_ops_chg = { @@ -498,6 +556,8 @@ static const struct clk_ops sam9x60_div_pll_ops_chg = { .recalc_rate = sam9x60_div_pll_recalc_rate, .round_rate = sam9x60_div_pll_round_rate, .set_rate = sam9x60_div_pll_set_rate_chg, + .save_context = sam9x60_div_pll_save_context, + .restore_context = sam9x60_div_pll_restore_context, }; struct clk_hw * __init diff --git a/drivers/clk/at91/clk-system.c b/drivers/clk/at91/clk-system.c index f83ec0de86c3..80720fd1a9cf 100644 --- a/drivers/clk/at91/clk-system.c +++ b/drivers/clk/at91/clk-system.c @@ -20,6 +20,7 @@ struct clk_system { struct clk_hw hw; struct regmap *regmap; + struct at91_clk_pms pms; u8 id; }; @@ -77,10 +78,29 @@ static int clk_system_is_prepared(struct clk_hw *hw) return !!(status & (1 << sys->id)); } +static int clk_system_save_context(struct clk_hw *hw) +{ + struct clk_system *sys = to_clk_system(hw); + + sys->pms.status = clk_system_is_prepared(hw); + + return 0; +} + +static void clk_system_restore_context(struct clk_hw *hw) +{ + struct clk_system *sys = to_clk_system(hw); + + if (sys->pms.status) + clk_system_prepare(&sys->hw); +} + static const struct clk_ops system_ops = { .prepare = clk_system_prepare, .unprepare = clk_system_unprepare, .is_prepared = clk_system_is_prepared, + .save_context = clk_system_save_context, + .restore_context = clk_system_restore_context, }; struct clk_hw * __init diff --git a/drivers/clk/at91/clk-usb.c b/drivers/clk/at91/clk-usb.c index 31d5c45e30d7..b0696a928aa9 100644 --- a/drivers/clk/at91/clk-usb.c +++ b/drivers/clk/at91/clk-usb.c @@ -24,6 +24,7 @@ struct at91sam9x5_clk_usb { struct clk_hw hw; struct regmap *regmap; + struct at91_clk_pms pms; u32 usbs_mask; u8 num_parents; }; @@ -148,12 +149,38 @@ static int at91sam9x5_clk_usb_set_rate(struct clk_hw *hw, unsigned long rate, return 0; } +static int at91sam9x5_usb_save_context(struct clk_hw *hw) +{ + struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw); + struct clk_hw *parent_hw = clk_hw_get_parent(hw); + + usb->pms.parent = at91sam9x5_clk_usb_get_parent(hw); + usb->pms.parent_rate = clk_hw_get_rate(parent_hw); + usb->pms.rate = at91sam9x5_clk_usb_recalc_rate(hw, usb->pms.parent_rate); + + return 0; +} + +static void at91sam9x5_usb_restore_context(struct clk_hw *hw) +{ + struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw); + int ret; + + ret = at91sam9x5_clk_usb_set_parent(hw, usb->pms.parent); + if (ret) + return; + + at91sam9x5_clk_usb_set_rate(hw, usb->pms.rate, usb->pms.parent_rate); +} + static const struct clk_ops at91sam9x5_usb_ops = { .recalc_rate = at91sam9x5_clk_usb_recalc_rate, .determine_rate = at91sam9x5_clk_usb_determine_rate, .get_parent = at91sam9x5_clk_usb_get_parent, .set_parent = at91sam9x5_clk_usb_set_parent, .set_rate = at91sam9x5_clk_usb_set_rate, + .save_context = at91sam9x5_usb_save_context, + .restore_context = at91sam9x5_usb_restore_context, }; static int at91sam9n12_clk_usb_enable(struct clk_hw *hw) diff --git a/drivers/clk/at91/clk-utmi.c b/drivers/clk/at91/clk-utmi.c index df9f3fc3b6a6..a22c10d9a1b9 100644 --- a/drivers/clk/at91/clk-utmi.c +++ b/drivers/clk/at91/clk-utmi.c @@ -23,6 +23,7 @@ struct clk_utmi { struct clk_hw hw; struct regmap *regmap_pmc; struct regmap *regmap_sfr; + struct at91_clk_pms pms; }; #define to_clk_utmi(hw) container_of(hw, struct clk_utmi, hw) @@ -113,11 +114,30 @@ static unsigned long clk_utmi_recalc_rate(struct clk_hw *hw, return UTMI_RATE; } +static int clk_utmi_save_context(struct clk_hw *hw) +{ + struct clk_utmi *utmi = to_clk_utmi(hw); + + utmi->pms.status = clk_utmi_is_prepared(hw); + + return 0; +} + +static void clk_utmi_restore_context(struct clk_hw *hw) +{ + struct clk_utmi *utmi = to_clk_utmi(hw); + + if (utmi->pms.status) + clk_utmi_prepare(hw); +} + static const struct clk_ops utmi_ops = { .prepare = clk_utmi_prepare, .unprepare = clk_utmi_unprepare, .is_prepared = clk_utmi_is_prepared, .recalc_rate = clk_utmi_recalc_rate, + .save_context = clk_utmi_save_context, + .restore_context = clk_utmi_restore_context, }; static struct clk_hw * __init @@ -232,10 +252,29 @@ static int clk_utmi_sama7g5_is_prepared(struct clk_hw *hw) return 0; } +static int clk_utmi_sama7g5_save_context(struct clk_hw *hw) +{ + struct clk_utmi *utmi = to_clk_utmi(hw); + + utmi->pms.status = clk_utmi_sama7g5_is_prepared(hw); + + return 0; +} + +static void clk_utmi_sama7g5_restore_context(struct clk_hw *hw) +{ + struct clk_utmi *utmi = to_clk_utmi(hw); + + if (utmi->pms.status) + clk_utmi_sama7g5_prepare(hw); +} + static const struct clk_ops sama7g5_utmi_ops = { .prepare = clk_utmi_sama7g5_prepare, .is_prepared = clk_utmi_sama7g5_is_prepared, .recalc_rate = clk_utmi_recalc_rate, + .save_context = clk_utmi_sama7g5_save_context, + .restore_context = clk_utmi_sama7g5_restore_context, }; struct clk_hw * __init diff --git a/drivers/clk/at91/pmc.c b/drivers/clk/at91/pmc.c index b40035b011d0..b2806946a77a 100644 --- a/drivers/clk/at91/pmc.c +++ b/drivers/clk/at91/pmc.c @@ -3,6 +3,7 @@ * Copyright (C) 2013 Boris BREZILLON */ +#include #include #include #include @@ -14,8 +15,6 @@ #include -#include - #include "pmc.h" #define PMC_MAX_IDS 128 @@ -111,147 +110,19 @@ struct pmc_data *pmc_data_allocate(unsigned int ncore, unsigned int nsystem, } #ifdef CONFIG_PM -static struct regmap *pmcreg; - -static u8 registered_ids[PMC_MAX_IDS]; -static u8 registered_pcks[PMC_MAX_PCKS]; - -static struct -{ - u32 scsr; - u32 pcsr0; - u32 uckr; - u32 mor; - u32 mcfr; - u32 pllar; - u32 mckr; - u32 usb; - u32 imr; - u32 pcsr1; - u32 pcr[PMC_MAX_IDS]; - u32 audio_pll0; - u32 audio_pll1; - u32 pckr[PMC_MAX_PCKS]; -} pmc_cache; - -/* - * As Peripheral ID 0 is invalid on AT91 chips, the identifier is stored - * without alteration in the table, and 0 is for unused clocks. - */ -void pmc_register_id(u8 id) -{ - int i; - - for (i = 0; i < PMC_MAX_IDS; i++) { - if (registered_ids[i] == 0) { - registered_ids[i] = id; - break; - } - if (registered_ids[i] == id) - break; - } -} - -/* - * As Programmable Clock 0 is valid on AT91 chips, there is an offset - * of 1 between the stored value and the real clock ID. - */ -void pmc_register_pck(u8 pck) -{ - int i; - - for (i = 0; i < PMC_MAX_PCKS; i++) { - if (registered_pcks[i] == 0) { - registered_pcks[i] = pck + 1; - break; - } - if (registered_pcks[i] == (pck + 1)) - break; - } -} - -static int pmc_suspend(void) +static int at91_pmc_suspend(void) { - int i; - u8 num; - - regmap_read(pmcreg, AT91_PMC_SCSR, &pmc_cache.scsr); - regmap_read(pmcreg, AT91_PMC_PCSR, &pmc_cache.pcsr0); - regmap_read(pmcreg, AT91_CKGR_UCKR, &pmc_cache.uckr); - regmap_read(pmcreg, AT91_CKGR_MOR, &pmc_cache.mor); - regmap_read(pmcreg, AT91_CKGR_MCFR, &pmc_cache.mcfr); - regmap_read(pmcreg, AT91_CKGR_PLLAR, &pmc_cache.pllar); - regmap_read(pmcreg, AT91_PMC_MCKR, &pmc_cache.mckr); - regmap_read(pmcreg, AT91_PMC_USB, &pmc_cache.usb); - regmap_read(pmcreg, AT91_PMC_IMR, &pmc_cache.imr); - regmap_read(pmcreg, AT91_PMC_PCSR1, &pmc_cache.pcsr1); - - for (i = 0; registered_ids[i]; i++) { - regmap_write(pmcreg, AT91_PMC_PCR, - (registered_ids[i] & AT91_PMC_PCR_PID_MASK)); - regmap_read(pmcreg, AT91_PMC_PCR, - &pmc_cache.pcr[registered_ids[i]]); - } - for (i = 0; registered_pcks[i]; i++) { - num = registered_pcks[i] - 1; - regmap_read(pmcreg, AT91_PMC_PCKR(num), &pmc_cache.pckr[num]); - } - - return 0; + return clk_save_context(); } -static bool pmc_ready(unsigned int mask) +static void at91_pmc_resume(void) { - unsigned int status; - - regmap_read(pmcreg, AT91_PMC_SR, &status); - - return ((status & mask) == mask) ? 1 : 0; -} - -static void pmc_resume(void) -{ - int i; - u8 num; - u32 tmp; - u32 mask = AT91_PMC_MCKRDY | AT91_PMC_LOCKA; - - regmap_read(pmcreg, AT91_PMC_MCKR, &tmp); - if (pmc_cache.mckr != tmp) - pr_warn("MCKR was not configured properly by the firmware\n"); - regmap_read(pmcreg, AT91_CKGR_PLLAR, &tmp); - if (pmc_cache.pllar != tmp) - pr_warn("PLLAR was not configured properly by the firmware\n"); - - regmap_write(pmcreg, AT91_PMC_SCER, pmc_cache.scsr); - regmap_write(pmcreg, AT91_PMC_PCER, pmc_cache.pcsr0); - regmap_write(pmcreg, AT91_CKGR_UCKR, pmc_cache.uckr); - regmap_write(pmcreg, AT91_CKGR_MOR, pmc_cache.mor); - regmap_write(pmcreg, AT91_CKGR_MCFR, pmc_cache.mcfr); - regmap_write(pmcreg, AT91_PMC_USB, pmc_cache.usb); - regmap_write(pmcreg, AT91_PMC_IMR, pmc_cache.imr); - regmap_write(pmcreg, AT91_PMC_PCER1, pmc_cache.pcsr1); - - for (i = 0; registered_ids[i]; i++) { - regmap_write(pmcreg, AT91_PMC_PCR, - pmc_cache.pcr[registered_ids[i]] | - AT91_PMC_PCR_CMD); - } - for (i = 0; registered_pcks[i]; i++) { - num = registered_pcks[i] - 1; - regmap_write(pmcreg, AT91_PMC_PCKR(num), pmc_cache.pckr[num]); - } - - if (pmc_cache.uckr & AT91_PMC_UPLLEN) - mask |= AT91_PMC_LOCKU; - - while (!pmc_ready(mask)) - cpu_relax(); + clk_restore_context(); } static struct syscore_ops pmc_syscore_ops = { - .suspend = pmc_suspend, - .resume = pmc_resume, + .suspend = at91_pmc_suspend, + .resume = at91_pmc_resume, }; static const struct of_device_id sama5d2_pmc_dt_ids[] = { @@ -271,11 +142,7 @@ static int __init pmc_register_ops(void) of_node_put(np); return -ENODEV; } - - pmcreg = device_node_to_regmap(np); of_node_put(np); - if (IS_ERR(pmcreg)) - return PTR_ERR(pmcreg); register_syscore_ops(&pmc_syscore_ops); diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index a49076c804a9..45df094498ce 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -13,6 +13,8 @@ #include #include +#include + extern spinlock_t pmc_pcr_lock; struct pmc_data { @@ -98,6 +100,20 @@ struct clk_pcr_layout { u32 pid_mask; }; +/** + * struct at91_clk_pms - Power management state for AT91 clock + * @rate: clock rate + * @parent_rate: clock parent rate + * @status: clock status (enabled or disabled) + * @parent: clock parent index + */ +struct at91_clk_pms { + unsigned long rate; + unsigned long parent_rate; + unsigned int status; + unsigned int parent; +}; + #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) #define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) @@ -248,12 +264,4 @@ struct clk_hw * __init at91_clk_sama7g5_register_utmi(struct regmap *regmap, const char *name, const char *parent_name); -#ifdef CONFIG_PM -void pmc_register_id(u8 id); -void pmc_register_pck(u8 pck); -#else -static inline void pmc_register_id(u8 id) {} -static inline void pmc_register_pck(u8 pck) {} -#endif - #endif /* __PMC_H_ */ From patchwork Thu Sep 23 13:20:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12512867 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,TVD_PH_BODY_ACCOUNTS_PRE, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E956AC433FE for ; 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IronPort-SDR: 5cz/a+by3UACqSP0rYaRiJJsWe+xA9nqtrjzUwmHGBXhug0t6JWeoO17xxF0IlO3gpJ/dLHI2y /oa+RBSRWHHwoZBbKePR0j+YekUZD6G8cercJZO5To/ZUi+F2re8bRUOWqfB1i0T5adPbhT2Wx b4AzMVOa+iuU7TmxV9jPe5eaWPzc3jI8vXYsA/A0Yei7Wnye+p4tmqQQngfsIRdL3ZH6YEJcm0 pcLipp/ZNw++1e8zKTrz8aMXdj3Pctb8bg4X6TqysjwvRLrUj5jDsLJ9Rx16KqqxPopEpo+xhQ KqzrFMLyREBLOhjBSmtERWYS X-IronPort-AV: E=Sophos;i="5.85,316,1624345200"; d="scan'208";a="137664785" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 23 Sep 2021 06:21:10 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Thu, 23 Sep 2021 06:21:06 -0700 Received: from rob-dk-mpu01.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Thu, 23 Sep 2021 06:21:04 -0700 From: Claudiu Beznea To: , , , , CC: , , , Claudiu Beznea Subject: [PATCH v4 02/17] clk: at91: pmc: execute suspend/resume only for backup mode Date: Thu, 23 Sep 2021 16:20:31 +0300 Message-ID: <20210923132046.1860549-3-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210923132046.1860549-1-claudiu.beznea@microchip.com> References: <20210923132046.1860549-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Before going to backup mode architecture specific PM code sets the first word in securam (file arch/arm/mach-at91/pm.c, function at91_pm_begin()). Thus take this into account when suspending/resuming clocks. This will avoid executing unnecessary instructions when suspending to non backup modes. Also this commit changed the postcore_initcall() with subsys_initcall() to be able to execute of_find_compatible_node() since this was not available at the moment of postcore_initcall(). This should not alter the tcb_clksrc since the changes are related to clocks suspend/resume procedure that will be executed at the user space request, thus long ago after subsys_initcall(). Signed-off-by: Claudiu Beznea --- drivers/clk/at91/pmc.c | 49 ++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 47 insertions(+), 2 deletions(-) diff --git a/drivers/clk/at91/pmc.c b/drivers/clk/at91/pmc.c index b2806946a77a..58e9c088cb22 100644 --- a/drivers/clk/at91/pmc.c +++ b/drivers/clk/at91/pmc.c @@ -8,6 +8,8 @@ #include #include #include +#include +#include #include #include #include @@ -110,13 +112,35 @@ struct pmc_data *pmc_data_allocate(unsigned int ncore, unsigned int nsystem, } #ifdef CONFIG_PM + +/* Address in SECURAM that say if we suspend to backup mode. */ +static void __iomem *at91_pmc_backup_suspend; + static int at91_pmc_suspend(void) { + unsigned int backup; + + if (!at91_pmc_backup_suspend) + return 0; + + backup = *(unsigned int *)at91_pmc_backup_suspend; + if (!backup) + return 0; + return clk_save_context(); } static void at91_pmc_resume(void) { + unsigned int backup; + + if (!at91_pmc_backup_suspend) + return; + + backup = *(unsigned int *)at91_pmc_backup_suspend; + if (!backup) + return; + clk_restore_context(); } @@ -132,6 +156,7 @@ static const struct of_device_id sama5d2_pmc_dt_ids[] = { static int __init pmc_register_ops(void) { + struct platform_device *pdev; struct device_node *np; np = of_find_matching_node(NULL, sama5d2_pmc_dt_ids); @@ -144,10 +169,30 @@ static int __init pmc_register_ops(void) } of_node_put(np); + np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-securam"); + if (!np) + return -ENODEV; + + if (!of_device_is_available(np)) { + of_node_put(np); + return -ENODEV; + } + + pdev = of_find_device_by_node(np); + of_node_put(np); + if (!pdev) + return -ENODEV; + + at91_pmc_backup_suspend = of_iomap(np, 0); + if (!at91_pmc_backup_suspend) { + pr_warn("%s(): unable to map securam\n", __func__); + return -ENOMEM; + } + register_syscore_ops(&pmc_syscore_ops); return 0; } -/* This has to happen before arch_initcall because of the tcb_clksrc driver */ -postcore_initcall(pmc_register_ops); + +subsys_initcall(pmc_register_ops); #endif From patchwork Thu Sep 23 13:20:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12512865 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AD28AC433F5 for ; Thu, 23 Sep 2021 13:21:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9425C61050 for ; Thu, 23 Sep 2021 13:21:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241249AbhIWNWq (ORCPT ); Thu, 23 Sep 2021 09:22:46 -0400 Received: from esa.microchip.iphmx.com ([68.232.153.233]:50307 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241255AbhIWNWk (ORCPT ); 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d="scan'208";a="137071457" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 23 Sep 2021 06:21:10 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Thu, 23 Sep 2021 06:21:08 -0700 Received: from rob-dk-mpu01.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Thu, 23 Sep 2021 06:21:06 -0700 From: Claudiu Beznea To: , , , , CC: , , , Claudiu Beznea Subject: [PATCH v4 03/17] clk: at91: sama7g5: add securam's peripheral clock Date: Thu, 23 Sep 2021 16:20:32 +0300 Message-ID: <20210923132046.1860549-4-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210923132046.1860549-1-claudiu.beznea@microchip.com> References: <20210923132046.1860549-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add SECURAM's peripheral clock. Signed-off-by: Claudiu Beznea Acked-by: Nicolas Ferre --- drivers/clk/at91/sama7g5.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c index cf8c079aa086..970135e19a75 100644 --- a/drivers/clk/at91/sama7g5.c +++ b/drivers/clk/at91/sama7g5.c @@ -377,6 +377,7 @@ static const struct { u8 id; } sama7g5_periphck[] = { { .n = "pioA_clk", .p = "mck0", .id = 11, }, + { .n = "securam_clk", .p = "mck0", .id = 18, }, { .n = "sfr_clk", .p = "mck1", .id = 19, }, { .n = "hsmc_clk", .p = "mck1", .id = 21, }, { .n = "xdmac0_clk", .p = "mck1", .id = 22, }, From patchwork Thu Sep 23 13:20:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12512869 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D65A3C4332F for ; Thu, 23 Sep 2021 13:21:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BA5BD6126A for ; Thu, 23 Sep 2021 13:21:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241263AbhIWNWs (ORCPT ); Thu, 23 Sep 2021 09:22:48 -0400 Received: from esa.microchip.iphmx.com ([68.232.153.233]:64381 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241208AbhIWNWn (ORCPT ); Thu, 23 Sep 2021 09:22:43 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1632403272; x=1663939272; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=JMAJzlLQWHfPLEYAqNjpQbE6NgSO2QK2F0a5gUvdtUs=; b=yLFwxYOwk8kttOMr8DhhnxEh4MJxn+c8+/G7M0e60T391kduDMWm3MVU Hg6Ooiq+euSEJ1+THYVl/5Vq9/oHvqGA14NnN5sE32rAuBhiXvkgiRXvQ pJTs0abGMHehpsHpQVagpmjFlZnGaigXhzjQ7Ls9GrKnxN80O5yZpuA7V snl4oPMNeH7j7bt6Se6m/PcfCkDWmXe/pRCRGDYSMYQw3jNieJ5FHGTXF s3+UyAQzhBbDOVMoUVp42eM3gBY5pu6BLERpLK01Vzgm96XtJimGkXkka is9zG2esi6w9/cOsAylwAZ01ngPD25c5fF6Wfytebsyv4HS6EJZa6YNGp w==; IronPort-SDR: jsCdpUg3sx+d9S9F8UyH1kdC/eqiAT7HZKPIcEB4TvEX40LaoV85Db1bODNbnjp91pYUy3gI/8 Z0qYf8YnOcVGX+EsDExtUL3rdZI7e0NGRy4Ua0q0SCaDNnuNFxnQVgMBSGLLRILLveg78J+TM6 sy1YjJfYGyJbOFCMjfNA7WB14hVtJfe01gdzRXoCqNBDySWoYbHjzCX1GSycUBrlOP6FgQSkYR cXY9LQjaVw+duO1uwh+RaJeYAWAGjgLjh5rEtZ3bqg82OvSIQ7s4ZxrfUkVeCvwAZdoTnKengS u7jUVbjKVpTWPfsZnvl+bv7L X-IronPort-AV: E=Sophos;i="5.85,316,1624345200"; d="scan'208";a="145305401" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 23 Sep 2021 06:21:11 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Thu, 23 Sep 2021 06:21:11 -0700 Received: from rob-dk-mpu01.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Thu, 23 Sep 2021 06:21:09 -0700 From: Claudiu Beznea To: , , , , CC: , , , Claudiu Beznea Subject: [PATCH v4 04/17] clk: at91: clk-master: add register definition for sama7g5's master clock Date: Thu, 23 Sep 2021 16:20:33 +0300 Message-ID: <20210923132046.1860549-5-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210923132046.1860549-1-claudiu.beznea@microchip.com> References: <20210923132046.1860549-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org SAMA7G5 has 4 master clocks (MCK1..4) which are controlled though the register at offset 0x30 (relative to PMC). In the last/first phase of suspend/resume procedure (which is architecture specific) the parent of master clocks are changed (via assembly code) for more power saving (see file arch/arm/mach-at91/pm_suspend.S, macros at91_mckx_ps_enable and at91_mckx_ps_restore). Thus the macros corresponding to register at offset 0x30 need to be shared b/w clk-master.c and pm_suspend.S. commit ec03f18cc222 ("clk: at91: add register definition for sama7g5's master clock") introduced the proper macros but didn't adapted the clk-master.c as well. Thus, this commit adapt the clk-master.c to use the macros introduced in commit ec03f18cc222 ("clk: at91: add register definition for sama7g5's master clock"). Signed-off-by: Claudiu Beznea --- drivers/clk/at91/clk-master.c | 50 ++++++++++++++++------------------- 1 file changed, 23 insertions(+), 27 deletions(-) diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c index f75549fff023..88f7af1bfff6 100644 --- a/drivers/clk/at91/clk-master.c +++ b/drivers/clk/at91/clk-master.c @@ -17,15 +17,7 @@ #define MASTER_DIV_SHIFT 8 #define MASTER_DIV_MASK 0x7 -#define PMC_MCR 0x30 -#define PMC_MCR_ID_MSK GENMASK(3, 0) -#define PMC_MCR_CMD BIT(7) -#define PMC_MCR_DIV GENMASK(10, 8) -#define PMC_MCR_CSS GENMASK(20, 16) #define PMC_MCR_CSS_SHIFT (16) -#define PMC_MCR_EN BIT(28) - -#define PMC_MCR_ID(x) ((x) & PMC_MCR_ID_MSK) #define MASTER_MAX_ID 4 @@ -687,20 +679,22 @@ static void clk_sama7g5_master_set(struct clk_master *master, { unsigned long flags; unsigned int val, cparent; - unsigned int enable = status ? PMC_MCR_EN : 0; + unsigned int enable = status ? AT91_PMC_MCR_V2_EN : 0; spin_lock_irqsave(master->lock, flags); - regmap_write(master->regmap, PMC_MCR, PMC_MCR_ID(master->id)); - regmap_read(master->regmap, PMC_MCR, &val); - regmap_update_bits(master->regmap, PMC_MCR, - enable | PMC_MCR_CSS | PMC_MCR_DIV | - PMC_MCR_CMD | PMC_MCR_ID_MSK, + regmap_write(master->regmap, AT91_PMC_MCR_V2, + AT91_PMC_MCR_V2_ID(master->id)); + regmap_read(master->regmap, AT91_PMC_MCR_V2, &val); + regmap_update_bits(master->regmap, AT91_PMC_MCR_V2, + enable | AT91_PMC_MCR_V2_CSS | AT91_PMC_MCR_V2_DIV | + AT91_PMC_MCR_V2_CMD | AT91_PMC_MCR_V2_ID_MSK, enable | (master->parent << PMC_MCR_CSS_SHIFT) | (master->div << MASTER_DIV_SHIFT) | - PMC_MCR_CMD | PMC_MCR_ID(master->id)); + AT91_PMC_MCR_V2_CMD | + AT91_PMC_MCR_V2_ID(master->id)); - cparent = (val & PMC_MCR_CSS) >> PMC_MCR_CSS_SHIFT; + cparent = (val & AT91_PMC_MCR_V2_CSS) >> PMC_MCR_CSS_SHIFT; /* Wait here only if parent is being changed. */ while ((cparent != master->parent) && !clk_master_ready(master)) @@ -725,10 +719,12 @@ static void clk_sama7g5_master_disable(struct clk_hw *hw) spin_lock_irqsave(master->lock, flags); - regmap_write(master->regmap, PMC_MCR, master->id); - regmap_update_bits(master->regmap, PMC_MCR, - PMC_MCR_EN | PMC_MCR_CMD | PMC_MCR_ID_MSK, - PMC_MCR_CMD | PMC_MCR_ID(master->id)); + regmap_write(master->regmap, AT91_PMC_MCR_V2, master->id); + regmap_update_bits(master->regmap, AT91_PMC_MCR_V2, + AT91_PMC_MCR_V2_EN | AT91_PMC_MCR_V2_CMD | + AT91_PMC_MCR_V2_ID_MSK, + AT91_PMC_MCR_V2_CMD | + AT91_PMC_MCR_V2_ID(master->id)); spin_unlock_irqrestore(master->lock, flags); } @@ -741,12 +737,12 @@ static int clk_sama7g5_master_is_enabled(struct clk_hw *hw) spin_lock_irqsave(master->lock, flags); - regmap_write(master->regmap, PMC_MCR, master->id); - regmap_read(master->regmap, PMC_MCR, &val); + regmap_write(master->regmap, AT91_PMC_MCR_V2, master->id); + regmap_read(master->regmap, AT91_PMC_MCR_V2, &val); spin_unlock_irqrestore(master->lock, flags); - return !!(val & PMC_MCR_EN); + return !!(val & AT91_PMC_MCR_V2_EN); } static int clk_sama7g5_master_set_rate(struct clk_hw *hw, unsigned long rate, @@ -842,10 +838,10 @@ at91_clk_sama7g5_register_master(struct regmap *regmap, master->mux_table = mux_table; spin_lock_irqsave(master->lock, flags); - regmap_write(master->regmap, PMC_MCR, master->id); - regmap_read(master->regmap, PMC_MCR, &val); - master->parent = (val & PMC_MCR_CSS) >> PMC_MCR_CSS_SHIFT; - master->div = (val & PMC_MCR_DIV) >> MASTER_DIV_SHIFT; + regmap_write(master->regmap, AT91_PMC_MCR_V2, master->id); + regmap_read(master->regmap, AT91_PMC_MCR_V2, &val); + master->parent = (val & AT91_PMC_MCR_V2_CSS) >> PMC_MCR_CSS_SHIFT; + master->div = (val & AT91_PMC_MCR_V2_DIV) >> MASTER_DIV_SHIFT; spin_unlock_irqrestore(master->lock, flags); hw = &master->hw; From patchwork Thu Sep 23 13:20:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12512873 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3FE26C4332F for ; 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IronPort-SDR: aUNIoPko/XvWxIRTuTOBZ3Hoc3z93fhoSZj4TdmpWCzuxP2xbJmYZtbBAskMvTuHWNc31uknAc wbym5S0CoblBAlYCiRofwL38vhNCASD59R9zcdunnhaQqLgnX4tYQ1Koyi8K+O7X2VJsHjjQNE 8v+W3XoUT/eMbalotcq17y4mzdU+t04Cy2BzIUdUUdIFhScZz4T2qj8kXTa6XNQzXS4+aImX8e iPs1P9bpmRLvYKLPsc4Pfy7odMfUf3ZdqKGOPNvfqwCa6S+m+hmu3mKzMVxP7CG4XoHUHXO/VD smrnnhdFCDDUheET1tz4spM5 X-IronPort-AV: E=Sophos;i="5.85,316,1624345200"; d="scan'208";a="137664810" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 23 Sep 2021 06:21:17 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Thu, 23 Sep 2021 06:21:13 -0700 Received: from rob-dk-mpu01.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Thu, 23 Sep 2021 06:21:11 -0700 From: Claudiu Beznea To: , , , , CC: , , , Claudiu Beznea Subject: [PATCH v4 05/17] clk: at91: clk-master: improve readability by using local variables Date: Thu, 23 Sep 2021 16:20:34 +0300 Message-ID: <20210923132046.1860549-6-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210923132046.1860549-1-claudiu.beznea@microchip.com> References: <20210923132046.1860549-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Improve readability in clk_sama7g5_master_set() by using local variables. Suggested-by: Nicolas Ferre Signed-off-by: Claudiu Beznea --- drivers/clk/at91/clk-master.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c index 88f7af1bfff6..9a2c8e64cacf 100644 --- a/drivers/clk/at91/clk-master.c +++ b/drivers/clk/at91/clk-master.c @@ -680,6 +680,8 @@ static void clk_sama7g5_master_set(struct clk_master *master, unsigned long flags; unsigned int val, cparent; unsigned int enable = status ? AT91_PMC_MCR_V2_EN : 0; + unsigned int parent = master->parent << PMC_MCR_CSS_SHIFT; + unsigned int div = master->div << MASTER_DIV_SHIFT; spin_lock_irqsave(master->lock, flags); @@ -689,9 +691,7 @@ static void clk_sama7g5_master_set(struct clk_master *master, regmap_update_bits(master->regmap, AT91_PMC_MCR_V2, enable | AT91_PMC_MCR_V2_CSS | AT91_PMC_MCR_V2_DIV | AT91_PMC_MCR_V2_CMD | AT91_PMC_MCR_V2_ID_MSK, - enable | (master->parent << PMC_MCR_CSS_SHIFT) | - (master->div << MASTER_DIV_SHIFT) | - AT91_PMC_MCR_V2_CMD | + enable | parent | div | AT91_PMC_MCR_V2_CMD | AT91_PMC_MCR_V2_ID(master->id)); cparent = (val & AT91_PMC_MCR_V2_CSS) >> PMC_MCR_CSS_SHIFT; From patchwork Thu Sep 23 13:20:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12512871 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E5978C433FE for ; Thu, 23 Sep 2021 13:21:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CC7016121F for ; Thu, 23 Sep 2021 13:21:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241255AbhIWNW6 (ORCPT ); Thu, 23 Sep 2021 09:22:58 -0400 Received: from esa.microchip.iphmx.com ([68.232.153.233]:64381 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241290AbhIWNWt (ORCPT ); Thu, 23 Sep 2021 09:22:49 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1632403277; x=1663939277; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=PAlQz9ImFlO7qIwbUzAgmC9YSfeXGWfelq6OxBy//Dk=; b=DJhos12kOwh3BBz8J/d1kaK31SOacmkY4+4CV9Hr7I4jo81VO1ZTKQgs wVvSIb9KBoDtIu++c5sW0KddPAXDgJ2sLsUAgASsTLaLeE3Nu+Z7fcD1B tEKKdBs0Cd+vHZc/FZoLRDO1ELDkuUg47RFZAA1gBT2/tOojEziETXevQ PS07fTsnhpdoHR2tw0h8hfplrauBqrU9L36F5gphBiY5FbhI/KCtuHOhF Xg414nkqHjoubbyQULmwqiBJbCrLBafInRlAsap0pN9HW46frz9pJtsuj fbU2ItF6TWukDCvVZdSb0dR835O7R4QL1kcNGGLlYeWZlc9V8HEKwD/nd g==; IronPort-SDR: rm2OP2I2Lx90qkPM0vKcdrIxUO2QnHbPF+EpCo5yI7lEcC/dq051Pq57A57vkFWsBsT/K22Jx+ 7mz13tEJJNO1zCAwSCJP7K71z0azuQexDvbMp6+FdMHQvlpDB4vPq94kmQwMMbr6jcq63Vyk+p 89bqwz9TcLRsEd+E9H32gEy8wokeRfw42MnFYQWl+fyoIHXlr9E8KSv2GGohCn+IhDpRy0m2J/ 4ueFo5s0D+D/A5dx3qQHLlSTz7D3qi/w45jQEw6zTkhW+rL0sHJ5FwMwIU6E3/hBeCzraMISsW TmEZHT5a2jbli769VovjFiuI X-IronPort-AV: E=Sophos;i="5.85,316,1624345200"; d="scan'208";a="145305432" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 23 Sep 2021 06:21:17 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Thu, 23 Sep 2021 06:21:16 -0700 Received: from rob-dk-mpu01.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Thu, 23 Sep 2021 06:21:14 -0700 From: Claudiu Beznea To: , , , , CC: , , , Claudiu Beznea Subject: [PATCH v4 06/17] clk: at91: pmc: add sama7g5 to the list of available pmcs Date: Thu, 23 Sep 2021 16:20:35 +0300 Message-ID: <20210923132046.1860549-7-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210923132046.1860549-1-claudiu.beznea@microchip.com> References: <20210923132046.1860549-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add SAMA7G5 to the list of available PMCs such that the suspend/resume code for clocks to be used on backup mode. Signed-off-by: Claudiu Beznea --- drivers/clk/at91/pmc.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/clk/at91/pmc.c b/drivers/clk/at91/pmc.c index 58e9c088cb22..2a9636edfe9d 100644 --- a/drivers/clk/at91/pmc.c +++ b/drivers/clk/at91/pmc.c @@ -149,8 +149,9 @@ static struct syscore_ops pmc_syscore_ops = { .resume = at91_pmc_resume, }; -static const struct of_device_id sama5d2_pmc_dt_ids[] = { +static const struct of_device_id pmc_dt_ids[] = { { .compatible = "atmel,sama5d2-pmc" }, + { .compatible = "microchip,sama7g5-pmc", }, { /* sentinel */ } }; @@ -159,7 +160,7 @@ static int __init pmc_register_ops(void) struct platform_device *pdev; struct device_node *np; - np = of_find_matching_node(NULL, sama5d2_pmc_dt_ids); + np = of_find_matching_node(NULL, pmc_dt_ids); if (!np) return -ENODEV; From patchwork Thu Sep 23 13:20:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12512875 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CFAC7C433EF for ; Thu, 23 Sep 2021 13:21:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BDEB861241 for ; Thu, 23 Sep 2021 13:21:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241278AbhIWNW7 (ORCPT ); Thu, 23 Sep 2021 09:22:59 -0400 Received: from esa.microchip.iphmx.com ([68.232.153.233]:64403 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241277AbhIWNWu (ORCPT ); Thu, 23 Sep 2021 09:22:50 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1632403279; x=1663939279; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=bbgvOX8odhhcgQRbsWErZdBKALu82PPpkMqqT+eQSGM=; b=Mr9cO3NKfaC2whcrrYPNnGNUsbTlVQ6+J+8IT1HrYrFpB6D7ZZq/d4IY ZUDQW2Xd++lxRnI0raCuMRufyQzxqCz57QkV8XFGJEw6ep860zB3n3cC7 n1SaiteISoBN0La5n5yEQzDUZblVjYGiPNDpaXrveDS3DRqgieuzt+AB7 T/WeIlLiU2ZTNfLe5S0k2+I0Ns8EtzLQgpnZZ0HjDHsFC6wZQzWrgUyGN PJoLD9J8R+rdC4GW5KkczOleyz7GSLdUC3pTxzwFoLOCZTLMSKTmTLi1W LuZGZXXu+MIfJDGwCAolPP0WZmOEejz9+C7JKDqtbrM9JVDNIb6O2ZHLG g==; IronPort-SDR: o+trM+tlELZt7qoaLRH51vpi3MyEJppw7qodEHiu3lzjCCzLoRvbOlryYXAnPXZx79JR//fjzZ ia2CwFaVReOPa00H4Q9pEbSgK6bIprJ40+7pt50NYW3LGZLH8owsjWYQmG/xChyPU7eZY6F+iP r5oT0vNiM33o2EGsqKhztRcDYRqepdcEe0x74YZblDYX0lsGtnwv33JpGTVa5U+Oh5j7OrG20N pqA9vGtXq/MEBLh6I7u/E2To4AZu6a5n9/9e0qonZUu5LgjeGPdN/If3u8Kkjmgbw8g5YBvZ2h Yf6GGg781tl9FfeL2ITAkwun X-IronPort-AV: E=Sophos;i="5.85,316,1624345200"; d="scan'208";a="145305443" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 23 Sep 2021 06:21:18 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Thu, 23 Sep 2021 06:21:18 -0700 Received: from rob-dk-mpu01.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Thu, 23 Sep 2021 06:21:16 -0700 From: Claudiu Beznea To: , , , , CC: , , , Claudiu Beznea Subject: [PATCH v4 07/17] clk: at91: sam9x60-pll: use DIV_ROUND_CLOSEST_ULL Date: Thu, 23 Sep 2021 16:20:36 +0300 Message-ID: <20210923132046.1860549-8-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210923132046.1860549-1-claudiu.beznea@microchip.com> References: <20210923132046.1860549-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Use DIV_ROUND_CLOSEST_ULL() to avoid any inconsistency b/w the rate computed in sam9x60_frac_pll_recalc_rate() and the one computed in sam9x60_frac_pll_compute_mul_frac(). Fixes: 43b1bb4a9b3e1 ("clk: at91: clk-sam9x60-pll: re-factor to support plls with multiple outputs") Signed-off-by: Claudiu Beznea --- drivers/clk/at91/clk-sam9x60-pll.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c index 7020d3bf6e13..a73d7c96ce1d 100644 --- a/drivers/clk/at91/clk-sam9x60-pll.c +++ b/drivers/clk/at91/clk-sam9x60-pll.c @@ -73,8 +73,8 @@ static unsigned long sam9x60_frac_pll_recalc_rate(struct clk_hw *hw, struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); struct sam9x60_frac *frac = to_sam9x60_frac(core); - return (parent_rate * (frac->mul + 1) + - ((u64)parent_rate * frac->frac >> 22)); + return parent_rate * (frac->mul + 1) + + DIV_ROUND_CLOSEST_ULL((u64)parent_rate * frac->frac, (1 << 22)); } static int sam9x60_frac_pll_set(struct sam9x60_pll_core *core) From patchwork Thu Sep 23 13:20:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12512877 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9E246C433EF for ; Thu, 23 Sep 2021 13:21:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8657261164 for ; Thu, 23 Sep 2021 13:21:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241307AbhIWNXC (ORCPT ); Thu, 23 Sep 2021 09:23:02 -0400 Received: from esa.microchip.iphmx.com ([68.232.153.233]:64407 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241308AbhIWNWy (ORCPT ); Thu, 23 Sep 2021 09:22:54 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1632403282; x=1663939282; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=S2pBzduVdLBand+IYegWgUWMNB29c7JB6jeWuWWNdV0=; b=ZFOymQpRgRo7zpj+gweuehxKyl+wcMvMnJBlyRMOZvYyfeucZmBlZhs3 mheQ1J5uzgFb+o/Dk96vh4zI3sDKXVJNPvd1k7p7qyEJwoxGOXbPiKqWY NiRB6WLsQ2KW56qQCPa6+HLyJOefwsiKUvKArNKA/7cM9Xx69XAlwf0N3 62tay28+5Dq1QR/4QlD19lxsxVyKPlPXwXwy/7SS73g5Ci+KBX0d2Sqyj kDy6AsHiRoy7cWTOitzcLOq4xB0BGJSfix3vlXceqbUXn/gnzEcAj84Gp 9N+iHl70Ho4rfMMKR5dg/7ERbncdQLRjSMKuQAS6+4NPkrVennGYEPWxR Q==; IronPort-SDR: MeMq844Z+1AL9vQAX+/l/4fhk+E2EMbP0lQfYIJvVF/eFI0UUgt2s97BjD5ygigJG/kQKsWYyn 2D2/AkVxrXSBC2tAcjSX0PgAHOhDxRVCOVUYKhCvuq6f5qyRYDLlfeOqy9hx4A+dzvCCR48SBu h7N+5BUsWpGonKzMfa4tBFTkfwy5oJ8eHqQr1jFVwsXl3Nfjr9FzdozSWN8ERvyP0D4FpI9dvb 2LLom9kFkH3ocvoe0wfCF/MblTDtGh3yXqF7DFnaQHGYpzcyJ73MqBcaR57FZC2BxwLoe/KrIw 99EjZcYz3qHJ++CoaayZhf8Y X-IronPort-AV: E=Sophos;i="5.85,316,1624345200"; d="scan'208";a="145305449" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 23 Sep 2021 06:21:22 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Thu, 23 Sep 2021 06:21:21 -0700 Received: from rob-dk-mpu01.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Thu, 23 Sep 2021 06:21:19 -0700 From: Claudiu Beznea To: , , , , CC: , , , Claudiu Beznea Subject: [PATCH v4 08/17] clk: at91: clk-master: check if div or pres is zero Date: Thu, 23 Sep 2021 16:20:37 +0300 Message-ID: <20210923132046.1860549-9-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210923132046.1860549-1-claudiu.beznea@microchip.com> References: <20210923132046.1860549-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Check if div or pres is zero before using it as argument for ffs(). In case div is zero ffs() will return 0 and thus substracting from zero will lead to invalid values to be setup in registers. Fixes: 7a110b9107ed8 ("clk: at91: clk-master: re-factor master clock") Fixes: 75c88143f3b87 ("clk: at91: clk-master: add master clock support for SAMA7G5") Signed-off-by: Claudiu Beznea --- drivers/clk/at91/clk-master.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c index 9a2c8e64cacf..2093e13b5068 100644 --- a/drivers/clk/at91/clk-master.c +++ b/drivers/clk/at91/clk-master.c @@ -344,7 +344,7 @@ static int clk_master_pres_set_rate(struct clk_hw *hw, unsigned long rate, else if (pres == 3) pres = MASTER_PRES_MAX; - else + else if (pres) pres = ffs(pres) - 1; spin_lock_irqsave(master->lock, flags); @@ -757,7 +757,7 @@ static int clk_sama7g5_master_set_rate(struct clk_hw *hw, unsigned long rate, if (div == 3) div = MASTER_PRES_MAX; - else + else if (div) div = ffs(div) - 1; spin_lock_irqsave(master->lock, flags); From patchwork Thu Sep 23 13:20:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12512879 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2656DC433F5 for ; Thu, 23 Sep 2021 13:21:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 04C5E6103D for ; Thu, 23 Sep 2021 13:21:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241104AbhIWNXP (ORCPT ); Thu, 23 Sep 2021 09:23:15 -0400 Received: from esa.microchip.iphmx.com ([68.232.153.233]:42910 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241329AbhIWNXA (ORCPT ); Thu, 23 Sep 2021 09:23:00 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1632403289; x=1663939289; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ClMLzX2uOK3w3CaP5eMh1OuzGjwkLzpd+EABVYi3mwo=; b=Rj1zz9IpiK7IrU5nhMJ1VlPz9wp2u1H1qwZpl7G//rdPu+MLyOPXkjgF YJEmqHqUQiPO6J+2o4xXc1peG8LNFjj9L+HQ9id+rkv3x/X8YCjo2qjVw 3zVxLY6dXOTY7Syg1i8gLkMoW/PXD6FZ5Zl90vFxMykYJfrza8yuTf0t7 0kBV5sGFCpYcCPWiolZrbY4da/SG0e8e8oL/AhbmxVIUM21S29Ab8UNii +lm6qNu9iAM7M3CK+W+ExVzEVGWR+DT5X4S75TxRUTDbk4HI6bieEtyew e6G1r6amba2KbVokk5jVHhVxdjRNI+91gam1HMonQ5dzlPLNegoiudK9+ g==; IronPort-SDR: d9dOfSi97uQWiiFADTB3c/pqluyi+jEFRCdRanda+hrt5KE/l/Fi3WX4fPsT3T5efAD2riKwCO bZiHf8jm2zIBDvvrBTuNg3ujJXhFha8/OKXWo4UD6oOwlGHuc3toeE9aXLoeEvi+CcHablJE/b 1r/4Q0xmJvt4xfP3AUNg+3qbeATFLDYk4Mb6pmU43E/nt6e3KJigk12laSmlmJtSFfmvBVOMde 5Q3r5pVgtCV4NcxjlOhbYxMjQmWM3XVXpEGcS0/EoBUgIeUlyVswudaBYZeambFjw8WBJCMBZp V8pzyhPwxtwTAHjv2Al73cMC X-IronPort-AV: E=Sophos;i="5.85,316,1624345200"; d="scan'208";a="137664846" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 23 Sep 2021 06:21:28 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Thu, 23 Sep 2021 06:21:23 -0700 Received: from rob-dk-mpu01.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Thu, 23 Sep 2021 06:21:21 -0700 From: Claudiu Beznea To: , , , , CC: , , , Claudiu Beznea Subject: [PATCH v4 09/17] clk: at91: clk-master: mask mckr against layout->mask Date: Thu, 23 Sep 2021 16:20:38 +0300 Message-ID: <20210923132046.1860549-10-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210923132046.1860549-1-claudiu.beznea@microchip.com> References: <20210923132046.1860549-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Mask values read/written from/to MCKR against layout->mask as this mask may be different b/w PMC versions. Signed-off-by: Claudiu Beznea --- drivers/clk/at91/clk-master.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c index 2093e13b5068..6da9ae34313a 100644 --- a/drivers/clk/at91/clk-master.c +++ b/drivers/clk/at91/clk-master.c @@ -186,8 +186,8 @@ static int clk_master_div_set_rate(struct clk_hw *hw, unsigned long rate, if (ret) goto unlock; - tmp = mckr & master->layout->mask; - tmp = (tmp >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; + mckr &= master->layout->mask; + tmp = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; if (tmp == div) goto unlock; @@ -384,6 +384,7 @@ static unsigned long clk_master_pres_recalc_rate(struct clk_hw *hw, regmap_read(master->regmap, master->layout->offset, &val); spin_unlock_irqrestore(master->lock, flags); + val &= master->layout->mask; pres = (val >> master->layout->pres_shift) & MASTER_PRES_MASK; if (pres == 3 && characteristics->have_div3_pres) pres = 3; @@ -403,6 +404,8 @@ static u8 clk_master_pres_get_parent(struct clk_hw *hw) regmap_read(master->regmap, master->layout->offset, &mckr); spin_unlock_irqrestore(master->lock, flags); + mckr &= master->layout->mask; + return mckr & AT91_PMC_CSS; } From patchwork Thu Sep 23 13:20:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12512883 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 935CCC433FE for ; Thu, 23 Sep 2021 13:21:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7A90F61050 for ; Thu, 23 Sep 2021 13:21:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241299AbhIWNXQ (ORCPT ); Thu, 23 Sep 2021 09:23:16 -0400 Received: from esa.microchip.iphmx.com ([68.232.153.233]:42952 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241338AbhIWNXC (ORCPT ); Thu, 23 Sep 2021 09:23:02 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1632403290; x=1663939290; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=tJKSBuOTBiBd8Y63je4r0LFxJcPueVYGL0ehIQ+Ul8U=; b=hKUim/Ox00tL4BXvCHCnX3Z2X2zI1xFhd+kAclFNlfK/62dT9FV/8n8B aoBbA2vSB1fjjOO8J+cCG74hyu9LThVQwTEN78eeinqGovnU4IqyaPvrr gvRMd36Ks0qhwf6PO+TsKbiSyqmYPvQuQXVydyamnKg37YC8eFFGJDaDP okBb0LbLTbayv04+rgMmLbxVBXQMc/01nXGOlgn52PvoCKO08LEcug8p6 mFbWXr3byp3cgFPuk7zlqVHyBfQUkbzteOveGqnK3QE4seYHufPaX9va+ 8qdLwzPe/rhVqJthA6oNT858z5vIrNgmuNXcHGir8aF6JpdKsuFbOJ5aT g==; IronPort-SDR: C7OZdUQTBHRDKdMYMD+2y1R2lcUNrOtvE7q4IyuotbHtgBg7AZ+DHGm1r3IeYp4FzJg2ZD3knQ uqIMZ/i635nILhzW9KFNuurk651DX33HVu+rhpYHDnlifIPPGmkX8N+uO4uOKPpy9dG/6IQO0i G8vDttM53uHttlnpbzDE35f2sjrdZT2LrxDeOP5NF1J9wC8oc6dVRyEZ24Ft2ei0rAkQOvFF2H 9XS7W2nRt8Nn8UCcjK97Jooa9sVseZdVdl90r6KM9wyrpCLh5vpZvAD+ODdoBDWqtrh7F3Qr8h x81ZVqbZbBJgnaXOPyEW7nAc X-IronPort-AV: E=Sophos;i="5.85,316,1624345200"; d="scan'208";a="137664851" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 23 Sep 2021 06:21:30 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Thu, 23 Sep 2021 06:21:26 -0700 Received: from rob-dk-mpu01.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Thu, 23 Sep 2021 06:21:24 -0700 From: Claudiu Beznea To: , , , , CC: , , , Claudiu Beznea Subject: [PATCH v4 10/17] clk: at91: clk-master: fix prescaler logic Date: Thu, 23 Sep 2021 16:20:39 +0300 Message-ID: <20210923132046.1860549-11-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210923132046.1860549-1-claudiu.beznea@microchip.com> References: <20210923132046.1860549-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org When prescaler value read from register is MASTER_PRES_MAX it means that the input clock will be divided by 3. Fix the code to reflect this. Fixes: 7a110b9107ed8 ("clk: at91: clk-master: re-factor master clock") Signed-off-by: Claudiu Beznea --- drivers/clk/at91/clk-master.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c index 6da9ae34313a..e67bcd03a827 100644 --- a/drivers/clk/at91/clk-master.c +++ b/drivers/clk/at91/clk-master.c @@ -386,7 +386,7 @@ static unsigned long clk_master_pres_recalc_rate(struct clk_hw *hw, val &= master->layout->mask; pres = (val >> master->layout->pres_shift) & MASTER_PRES_MASK; - if (pres == 3 && characteristics->have_div3_pres) + if (pres == MASTER_PRES_MAX && characteristics->have_div3_pres) pres = 3; else pres = (1 << pres); From patchwork Thu Sep 23 13:20:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12512881 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 399C0C433EF for ; Thu, 23 Sep 2021 13:21:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1C5566115A for ; Thu, 23 Sep 2021 13:21:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241331AbhIWNXP (ORCPT ); Thu, 23 Sep 2021 09:23:15 -0400 Received: from esa.microchip.iphmx.com ([68.232.154.123]:64506 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241334AbhIWNXC (ORCPT ); Thu, 23 Sep 2021 09:23:02 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1632403290; x=1663939290; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=rUNzk6TIFLs7zjG6DIsoWGoRiw6L4nhGSRHkTEIf6IY=; b=Oo03mk/a72oZbNKargoGhH57STHp1lS9VCtaBpso45oeL2i97lka74xo nxGPI0zUBCyY1U5cdlQbE1AXIYlAoN35g3ir16VAhAKSOJsj5B9CXPnAq jypZhC/FHCoRrH0qmpgqIyk0NINz8+Pr/OKsdDY8K9Df2fy6Hk7zJvPCi hxKCixP+TAInELvOwtfcpw12THDBxqwrQ46C1B14+mekkGoTfGnlfJ5iS RbX5723iBHgmzFmX2B7q01hZzkv1Ov8SKRsv3y5vHoElE2QPigXC/EOwm IPZzAQaH7sRiawc5FcdjzNwKh0UmD8MRblFqgPxNJg40pq2p+mNjTJro2 w==; IronPort-SDR: lBeZYSyqmJfGH+RgjI63IUtsi/hb9Ut7Flq5eJp9uxKelT2xTL3I3JhyeuDxu6HFSHxMG0YUJl y9EFJw7cK7Czr7jAT8RESFspkYoyrcAxFfFPA1spGhaif2b0PWR4k87jKIcuDVhHam+uQ2Utcm CBP+xRslmvs3S/rSP+h1ZOH7c9ZnoQCFsW3LfSbkJfpmzn8FQVDWzesHnX8ZWp72mdwx4GS0Ll qrchV5QiIJ5mxMZWCxrvb1WxapjrMsovjTLKhATxmJBZ+BX8mXZSdQmwY5Kys1JObzk8CwUCsZ 0bMwZqsSLq6zoRzr18xMfD05 X-IronPort-AV: E=Sophos;i="5.85,316,1624345200"; d="scan'208";a="132870956" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 23 Sep 2021 06:21:29 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Thu, 23 Sep 2021 06:21:29 -0700 Received: from rob-dk-mpu01.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Thu, 23 Sep 2021 06:21:26 -0700 From: Claudiu Beznea To: , , , , CC: , , , Claudiu Beznea Subject: [PATCH v4 11/17] clk: at91: clk-sam9x60-pll: add notifier for div part of PLL Date: Thu, 23 Sep 2021 16:20:40 +0300 Message-ID: <20210923132046.1860549-12-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210923132046.1860549-1-claudiu.beznea@microchip.com> References: <20210923132046.1860549-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org SAM9X60's PLL which is also part of SAMA7G5 is composed of 2 parts: one fractional part and one divider. On SAMA7G5 the CPU PLL could be changed at run-time to implement DVFS. The hardware clock tree on SAMA7G5 for CPU PLL is as follows: +---- div1 ----------------> cpuck | FRAC PLL ---> DIV PLL -+-> prescaler ---> div0 ---> mck0 The div1 block is not implemented in Linux; on prescaler block it has been discovered a bug on some scenarios and will be removed from Linux in next commits. Thus, the final clock tree that will be used in Linux will be as follows: +-----------> cpuck | FRAC PLL ---> DIV PLL -+-> div0 ---> mck0 It has been proposed in [1] to not introduce a new CPUFreq driver but to overload the proper clock drivers with proper operation such that cpufreq-dt to be used. To accomplish this DIV PLL and div0 implement clock notifiers which applies safe dividers before FRAC PLL is changed. The current commit treats only the DIV PLL by adding a notifier that sets a safe divider on PRE_RATE_CHANGE events. The safe divider is provided by initialization clock code (sama7g5.c). The div0 is treated in next commits (to keep the changes as clean as possible). [1] https://lore.kernel.org/lkml/20210105104426.4tmgc2l3vyicwedd@vireshk-i7/ Signed-off-by: Claudiu Beznea --- drivers/clk/at91/clk-sam9x60-pll.c | 102 ++++++++++++++++++++++------- drivers/clk/at91/pmc.h | 3 +- drivers/clk/at91/sam9x60.c | 6 +- drivers/clk/at91/sama7g5.c | 13 +++- 4 files changed, 95 insertions(+), 29 deletions(-) diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c index a73d7c96ce1d..d757003004cb 100644 --- a/drivers/clk/at91/clk-sam9x60-pll.c +++ b/drivers/clk/at91/clk-sam9x60-pll.c @@ -5,6 +5,7 @@ */ #include +#include #include #include #include @@ -47,12 +48,15 @@ struct sam9x60_div { struct sam9x60_pll_core core; struct at91_clk_pms pms; u8 div; + u8 safe_div; }; #define to_sam9x60_pll_core(hw) container_of(hw, struct sam9x60_pll_core, hw) #define to_sam9x60_frac(core) container_of(core, struct sam9x60_frac, core) #define to_sam9x60_div(core) container_of(core, struct sam9x60_div, core) +static struct sam9x60_div *notifier_div; + static inline bool sam9x60_pll_ready(struct regmap *regmap, int id) { unsigned int status; @@ -329,6 +333,26 @@ static const struct clk_ops sam9x60_frac_pll_ops_chg = { .restore_context = sam9x60_frac_pll_restore_context, }; +/* This function should be called with spinlock acquired. */ +static void sam9x60_div_pll_set_div(struct sam9x60_pll_core *core, u32 div, + bool enable) +{ + struct regmap *regmap = core->regmap; + u32 ena_msk = enable ? core->layout->endiv_mask : 0; + u32 ena_val = enable ? (1 << core->layout->endiv_shift) : 0; + + regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0, + core->layout->div_mask | ena_msk, + (div << core->layout->div_shift) | ena_val); + + regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, + AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK, + AT91_PMC_PLL_UPDT_UPDATE | core->id); + + while (!sam9x60_pll_ready(regmap, core->id)) + cpu_relax(); +} + static int sam9x60_div_pll_set(struct sam9x60_pll_core *core) { struct sam9x60_div *div = to_sam9x60_div(core); @@ -346,17 +370,7 @@ static int sam9x60_div_pll_set(struct sam9x60_pll_core *core) if (!!(val & core->layout->endiv_mask) && cdiv == div->div) goto unlock; - regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0, - core->layout->div_mask | core->layout->endiv_mask, - (div->div << core->layout->div_shift) | - (1 << core->layout->endiv_shift)); - - regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, - AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK, - AT91_PMC_PLL_UPDT_UPDATE | core->id); - - while (!sam9x60_pll_ready(regmap, core->id)) - cpu_relax(); + sam9x60_div_pll_set_div(core, div->div, 1); unlock: spin_unlock_irqrestore(core->lock, flags); @@ -502,16 +516,7 @@ static int sam9x60_div_pll_set_rate_chg(struct clk_hw *hw, unsigned long rate, if (cdiv == div->div) goto unlock; - regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0, - core->layout->div_mask, - (div->div << core->layout->div_shift)); - - regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, - AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK, - AT91_PMC_PLL_UPDT_UPDATE | core->id); - - while (!sam9x60_pll_ready(regmap, core->id)) - cpu_relax(); + sam9x60_div_pll_set_div(core, div->div, 0); unlock: spin_unlock_irqrestore(core->lock, irqflags); @@ -538,6 +543,48 @@ static void sam9x60_div_pll_restore_context(struct clk_hw *hw) sam9x60_div_pll_set(core); } +static int sam9x60_div_pll_notifier_fn(struct notifier_block *notifier, + unsigned long code, void *data) +{ + struct sam9x60_div *div = notifier_div; + struct sam9x60_pll_core core = div->core; + struct regmap *regmap = core.regmap; + unsigned long irqflags; + u32 val, cdiv; + int ret = NOTIFY_DONE; + + if (code != PRE_RATE_CHANGE) + return ret; + + /* + * We switch to safe divider to avoid overclocking of other domains + * feed by us while the frac PLL (our parent) is changed. + */ + div->div = div->safe_div; + + spin_lock_irqsave(core.lock, irqflags); + regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK, + core.id); + regmap_read(regmap, AT91_PMC_PLL_CTRL0, &val); + cdiv = (val & core.layout->div_mask) >> core.layout->div_shift; + + /* Stop if nothing changed. */ + if (cdiv == div->safe_div) + goto unlock; + + sam9x60_div_pll_set_div(&core, div->div, 0); + ret = NOTIFY_OK; + +unlock: + spin_unlock_irqrestore(core.lock, irqflags); + + return ret; +} + +static struct notifier_block sam9x60_div_pll_notifier = { + .notifier_call = sam9x60_div_pll_notifier_fn, +}; + static const struct clk_ops sam9x60_div_pll_ops = { .prepare = sam9x60_div_pll_prepare, .unprepare = sam9x60_div_pll_unprepare, @@ -647,7 +694,8 @@ struct clk_hw * __init sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock, const char *name, const char *parent_name, u8 id, const struct clk_pll_characteristics *characteristics, - const struct clk_pll_layout *layout, u32 flags) + const struct clk_pll_layout *layout, u32 flags, + u32 safe_div) { struct sam9x60_div *div; struct clk_hw *hw; @@ -656,9 +704,13 @@ sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock, unsigned int val; int ret; - if (id > PLL_MAX_ID || !lock) + /* We only support one changeable PLL. */ + if (id > PLL_MAX_ID || !lock || (safe_div && notifier_div)) return ERR_PTR(-EINVAL); + if (safe_div >= PLL_DIV_MAX) + safe_div = PLL_DIV_MAX - 1; + div = kzalloc(sizeof(*div), GFP_KERNEL); if (!div) return ERR_PTR(-ENOMEM); @@ -678,6 +730,7 @@ sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock, div->core.layout = layout; div->core.regmap = regmap; div->core.lock = lock; + div->safe_div = safe_div; spin_lock_irqsave(div->core.lock, irqflags); @@ -693,6 +746,9 @@ sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock, if (ret) { kfree(div); hw = ERR_PTR(ret); + } else if (div->safe_div) { + notifier_div = div; + clk_notifier_register(hw->clk, &sam9x60_div_pll_notifier); } return hw; diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index 45df094498ce..207ecccef29f 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -214,7 +214,8 @@ struct clk_hw * __init sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock, const char *name, const char *parent_name, u8 id, const struct clk_pll_characteristics *characteristics, - const struct clk_pll_layout *layout, u32 flags); + const struct clk_pll_layout *layout, u32 flags, + u32 safe_div); struct clk_hw * __init sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock, diff --git a/drivers/clk/at91/sam9x60.c b/drivers/clk/at91/sam9x60.c index 5f6fa89571b7..5c264185f261 100644 --- a/drivers/clk/at91/sam9x60.c +++ b/drivers/clk/at91/sam9x60.c @@ -242,7 +242,7 @@ static void __init sam9x60_pmc_setup(struct device_node *np) * This feeds CPU. It should not * be disabled. */ - CLK_IS_CRITICAL | CLK_SET_RATE_GATE); + CLK_IS_CRITICAL | CLK_SET_RATE_GATE, 0); if (IS_ERR(hw)) goto err_free; @@ -260,7 +260,7 @@ static void __init sam9x60_pmc_setup(struct device_node *np) &pll_div_layout, CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | - CLK_SET_RATE_PARENT); + CLK_SET_RATE_PARENT, 0); if (IS_ERR(hw)) goto err_free; @@ -279,7 +279,7 @@ static void __init sam9x60_pmc_setup(struct device_node *np) hw = at91_clk_register_master_div(regmap, "masterck_div", "masterck_pres", &sam9x60_master_layout, &mck_characteristics, &mck_lock, - CLK_SET_RATE_GATE); + CLK_SET_RATE_GATE, 0); if (IS_ERR(hw)) goto err_free; diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c index 970135e19a75..ae52c10af040 100644 --- a/drivers/clk/at91/sama7g5.c +++ b/drivers/clk/at91/sama7g5.c @@ -127,6 +127,8 @@ static const struct clk_pll_characteristics pll_characteristics = { * @t: clock type * @f: clock flags * @eid: export index in sama7g5->chws[] array + * @safe_div: intermediate divider need to be set on PRE_RATE_CHANGE + * notification */ static const struct { const char *n; @@ -136,6 +138,7 @@ static const struct { unsigned long f; u8 t; u8 eid; + u8 safe_div; } sama7g5_plls[][PLL_ID_MAX] = { [PLL_ID_CPU] = { { .n = "cpupll_fracck", @@ -156,7 +159,12 @@ static const struct { .t = PLL_TYPE_DIV, /* This feeds CPU. It should not be disabled. */ .f = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, - .eid = PMC_CPUPLL, }, + .eid = PMC_CPUPLL, + /* + * Safe div=15 should be safe even for switching b/w 1GHz and + * 90MHz (frac pll might go up to 1.2GHz). + */ + .safe_div = 15, }, }, [PLL_ID_SYS] = { @@ -967,7 +975,8 @@ static void __init sama7g5_pmc_setup(struct device_node *np) sama7g5_plls[i][j].p, i, sama7g5_plls[i][j].c, sama7g5_plls[i][j].l, - sama7g5_plls[i][j].f); + sama7g5_plls[i][j].f, + sama7g5_plls[i][j].safe_div); break; default: From patchwork Thu Sep 23 13:20:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12512885 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6521AC4332F for ; Thu, 23 Sep 2021 13:21:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4DD4E61090 for ; Thu, 23 Sep 2021 13:21:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241336AbhIWNXQ (ORCPT ); Thu, 23 Sep 2021 09:23:16 -0400 Received: from esa.microchip.iphmx.com ([68.232.154.123]:30280 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241344AbhIWNXE (ORCPT ); Thu, 23 Sep 2021 09:23:04 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1632403292; x=1663939292; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=lSKdiOrxbun8N+a4R4QbmxvwI0kObncGgHB7kuDzTE0=; b=lHBdsoNHa1gzGwm2tE/UwrHB4rc3x50Vgoy4NR4lgpC0kqfxSDh/YyZn rhYJAXfMqXrbdiOC3/GaAoZwX8vA/m62ZfC9gn/GRmhCTPFQ2/CIGRikm lgbVitBCgtgJS7PoPc43xzGnYKFEOplSdNTYx+kpxM9j8ipyA+j5imJCn 6KVwN1VKHxLtOzHrBGTZsMKLF1pAxDqK5FfEdXrSuVAFaqqg9v3T24a9D F/WcjYW4YQe5dd7XMwu5EIl/b/mRjglxAT06IRHUsg4XgWKtXKDovECwK jpaySLZbOn4hDRKIY7GTjil9CfV814AXupLszw5iTuwY7pHOs+iOadQkR A==; IronPort-SDR: Fg1yEcnV0C+x+Qdn7qoKmjJVkOodu0I1qXjbjhy3cV6vPTNBesJqJZeamh1peROfmqc+MmgKHs TkItOzbVDbt2JkGI1AJgbgck5dUQjnUfdnr19LUWA5waoQrpkVw1yMmVERt+iSJDvyVAi0/vLS svK38o8ZwZbM8EQ93ioPfVYwZdWxhfLWuDQy0hZ0TGnJ1feARl6lqjdTwnHKqfT/ecD1cKKju6 J2LlvoVgAjih7etKIFp6iYc5zIakMy1gA+3GHxchu0VbfG32UVaewHnedbHQgelAlKUfOTUJFf /437OlC0u1vQJhSG51+74ODk X-IronPort-AV: E=Sophos;i="5.85,316,1624345200"; d="scan'208";a="130352831" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 23 Sep 2021 06:21:31 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Thu, 23 Sep 2021 06:21:31 -0700 Received: from rob-dk-mpu01.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Thu, 23 Sep 2021 06:21:29 -0700 From: Claudiu Beznea To: , , , , CC: , , , Claudiu Beznea Subject: [PATCH v4 12/17] clk: at91: clk-master: add notifier for divider Date: Thu, 23 Sep 2021 16:20:41 +0300 Message-ID: <20210923132046.1860549-13-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210923132046.1860549-1-claudiu.beznea@microchip.com> References: <20210923132046.1860549-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org SAMA7G5 supports DVFS by changing cpuck. On SAMA7G5 mck0 shares the same parent with cpuck as seen in the following clock tree: +----------> cpuck | FRAC PLL ---> DIV PLL -+-> DIV ---> mck0 mck0 could go b/w 32KHz and 200MHz on SAMA7G5. To avoid mck0 overclocking while changing FRAC PLL or DIV PLL the commit implements a notifier for mck0 which applies a safe divider to register (maximum value of the divider which is 5) on PRE_RATE_CHANGE events (such that changes on PLL to not overclock mck0) and sets the maximum allowed rate on POST_RATE_CHANGE events. Signed-off-by: Claudiu Beznea --- drivers/clk/at91/at91rm9200.c | 2 +- drivers/clk/at91/at91sam9260.c | 2 +- drivers/clk/at91/at91sam9g45.c | 2 +- drivers/clk/at91/at91sam9n12.c | 2 +- drivers/clk/at91/at91sam9rl.c | 2 +- drivers/clk/at91/at91sam9x5.c | 2 +- drivers/clk/at91/clk-master.c | 244 +++++++++++++++++++++++---------- drivers/clk/at91/dt-compat.c | 2 +- drivers/clk/at91/pmc.h | 2 +- drivers/clk/at91/sama5d2.c | 2 +- drivers/clk/at91/sama5d3.c | 2 +- drivers/clk/at91/sama5d4.c | 2 +- drivers/clk/at91/sama7g5.c | 2 +- 13 files changed, 186 insertions(+), 82 deletions(-) diff --git a/drivers/clk/at91/at91rm9200.c b/drivers/clk/at91/at91rm9200.c index 428a6f4b9ebc..fff4fdda974f 100644 --- a/drivers/clk/at91/at91rm9200.c +++ b/drivers/clk/at91/at91rm9200.c @@ -152,7 +152,7 @@ static void __init at91rm9200_pmc_setup(struct device_node *np) "masterck_pres", &at91rm9200_master_layout, &rm9200_mck_characteristics, - &rm9200_mck_lock, CLK_SET_RATE_GATE); + &rm9200_mck_lock, CLK_SET_RATE_GATE, 0); if (IS_ERR(hw)) goto err_free; diff --git a/drivers/clk/at91/at91sam9260.c b/drivers/clk/at91/at91sam9260.c index b29843bea278..79802f864ee5 100644 --- a/drivers/clk/at91/at91sam9260.c +++ b/drivers/clk/at91/at91sam9260.c @@ -429,7 +429,7 @@ static void __init at91sam926x_pmc_setup(struct device_node *np, &at91rm9200_master_layout, data->mck_characteristics, &at91sam9260_mck_lock, - CLK_SET_RATE_GATE); + CLK_SET_RATE_GATE, 0); if (IS_ERR(hw)) goto err_free; diff --git a/drivers/clk/at91/at91sam9g45.c b/drivers/clk/at91/at91sam9g45.c index 15da0dfe3ef2..7ed984f8058c 100644 --- a/drivers/clk/at91/at91sam9g45.c +++ b/drivers/clk/at91/at91sam9g45.c @@ -164,7 +164,7 @@ static void __init at91sam9g45_pmc_setup(struct device_node *np) &at91rm9200_master_layout, &mck_characteristics, &at91sam9g45_mck_lock, - CLK_SET_RATE_GATE); + CLK_SET_RATE_GATE, 0); if (IS_ERR(hw)) goto err_free; diff --git a/drivers/clk/at91/at91sam9n12.c b/drivers/clk/at91/at91sam9n12.c index 7fe435f4b46b..63cc58944b00 100644 --- a/drivers/clk/at91/at91sam9n12.c +++ b/drivers/clk/at91/at91sam9n12.c @@ -191,7 +191,7 @@ static void __init at91sam9n12_pmc_setup(struct device_node *np) &at91sam9x5_master_layout, &mck_characteristics, &at91sam9n12_mck_lock, - CLK_SET_RATE_GATE); + CLK_SET_RATE_GATE, 0); if (IS_ERR(hw)) goto err_free; diff --git a/drivers/clk/at91/at91sam9rl.c b/drivers/clk/at91/at91sam9rl.c index ecbabf5162bd..4d4faf6c61d8 100644 --- a/drivers/clk/at91/at91sam9rl.c +++ b/drivers/clk/at91/at91sam9rl.c @@ -132,7 +132,7 @@ static void __init at91sam9rl_pmc_setup(struct device_node *np) "masterck_pres", &at91rm9200_master_layout, &sam9rl_mck_characteristics, - &sam9rl_mck_lock, CLK_SET_RATE_GATE); + &sam9rl_mck_lock, CLK_SET_RATE_GATE, 0); if (IS_ERR(hw)) goto err_free; diff --git a/drivers/clk/at91/at91sam9x5.c b/drivers/clk/at91/at91sam9x5.c index 5cce48c64ea2..bd8007b4f3e0 100644 --- a/drivers/clk/at91/at91sam9x5.c +++ b/drivers/clk/at91/at91sam9x5.c @@ -210,7 +210,7 @@ static void __init at91sam9x5_pmc_setup(struct device_node *np, "masterck_pres", &at91sam9x5_master_layout, &mck_characteristics, &mck_lock, - CLK_SET_RATE_GATE); + CLK_SET_RATE_GATE, 0); if (IS_ERR(hw)) goto err_free; diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c index e67bcd03a827..b2d0a7f4f7f9 100644 --- a/drivers/clk/at91/clk-master.c +++ b/drivers/clk/at91/clk-master.c @@ -5,6 +5,7 @@ #include #include +#include #include #include #include @@ -36,8 +37,12 @@ struct clk_master { u8 id; u8 parent; u8 div; + u32 safe_div; }; +/* MCK div reference to be used by notifier. */ +static struct clk_master *master_div; + static inline bool clk_master_ready(struct clk_master *master) { unsigned int bit = master->id ? AT91_PMC_MCKXRDY : AT91_PMC_MCKRDY; @@ -153,107 +158,81 @@ static const struct clk_ops master_div_ops = { .restore_context = clk_master_div_restore_context, }; -static int clk_master_div_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) +/* This function must be called with lock acquired. */ +static int clk_master_div_set(struct clk_master *master, + unsigned long parent_rate, int div) { - struct clk_master *master = to_clk_master(hw); const struct clk_master_characteristics *characteristics = master->characteristics; - unsigned long flags; - unsigned int mckr, tmp; - int div, i; + unsigned long rate = parent_rate; + unsigned int max_div = 0, div_index = 0, max_div_index = 0; + unsigned int i, mckr, tmp; int ret; - div = DIV_ROUND_CLOSEST(parent_rate, rate); - if (div > ARRAY_SIZE(characteristics->divisors)) - return -EINVAL; - for (i = 0; i < ARRAY_SIZE(characteristics->divisors); i++) { if (!characteristics->divisors[i]) break; - if (div == characteristics->divisors[i]) { - div = i; - break; + if (div == characteristics->divisors[i]) + div_index = i; + + if (max_div < characteristics->divisors[i]) { + max_div = characteristics->divisors[i]; + max_div_index = i; } } - if (i == ARRAY_SIZE(characteristics->divisors)) - return -EINVAL; + if (div > max_div) + div_index = max_div_index; - spin_lock_irqsave(master->lock, flags); ret = regmap_read(master->regmap, master->layout->offset, &mckr); if (ret) - goto unlock; + return ret; mckr &= master->layout->mask; tmp = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; - if (tmp == div) - goto unlock; + if (tmp == div_index) + return 0; + + rate /= characteristics->divisors[div_index]; + if (rate < characteristics->output.min) + pr_warn("master clk div is underclocked"); + else if (rate > characteristics->output.max) + pr_warn("master clk div is overclocked"); mckr &= ~(MASTER_DIV_MASK << MASTER_DIV_SHIFT); - mckr |= (div << MASTER_DIV_SHIFT); + mckr |= (div_index << MASTER_DIV_SHIFT); ret = regmap_write(master->regmap, master->layout->offset, mckr); if (ret) - goto unlock; + return ret; while (!clk_master_ready(master)) cpu_relax(); -unlock: - spin_unlock_irqrestore(master->lock, flags); + + master->div = characteristics->divisors[div_index]; return 0; } -static int clk_master_div_determine_rate(struct clk_hw *hw, - struct clk_rate_request *req) +static unsigned long clk_master_div_recalc_rate_chg(struct clk_hw *hw, + unsigned long parent_rate) { struct clk_master *master = to_clk_master(hw); - const struct clk_master_characteristics *characteristics = - master->characteristics; - struct clk_hw *parent; - unsigned long parent_rate, tmp_rate, best_rate = 0; - int i, best_diff = INT_MIN, tmp_diff; - - parent = clk_hw_get_parent(hw); - if (!parent) - return -EINVAL; - - parent_rate = clk_hw_get_rate(parent); - if (!parent_rate) - return -EINVAL; - - for (i = 0; i < ARRAY_SIZE(characteristics->divisors); i++) { - if (!characteristics->divisors[i]) - break; - tmp_rate = DIV_ROUND_CLOSEST_ULL(parent_rate, - characteristics->divisors[i]); - tmp_diff = abs(tmp_rate - req->rate); - - if (!best_rate || best_diff > tmp_diff) { - best_diff = tmp_diff; - best_rate = tmp_rate; - } - - if (!best_diff) - break; - } - - req->best_parent_rate = best_rate; - req->best_parent_hw = parent; - req->rate = best_rate; - - return 0; + return DIV_ROUND_CLOSEST_ULL(parent_rate, master->div); } static void clk_master_div_restore_context_chg(struct clk_hw *hw) { struct clk_master *master = to_clk_master(hw); + unsigned long flags; int ret; - ret = clk_master_div_set_rate(hw, master->pms.rate, - master->pms.parent_rate); + spin_lock_irqsave(master->lock, flags); + ret = clk_master_div_set(master, master->pms.parent_rate, + DIV_ROUND_CLOSEST(master->pms.parent_rate, + master->pms.rate)); + spin_unlock_irqrestore(master->lock, flags); if (ret) pr_warn("Failed to restore MCK DIV clock\n"); } @@ -261,13 +240,116 @@ static void clk_master_div_restore_context_chg(struct clk_hw *hw) static const struct clk_ops master_div_ops_chg = { .prepare = clk_master_prepare, .is_prepared = clk_master_is_prepared, - .recalc_rate = clk_master_div_recalc_rate, - .determine_rate = clk_master_div_determine_rate, - .set_rate = clk_master_div_set_rate, + .recalc_rate = clk_master_div_recalc_rate_chg, .save_context = clk_master_div_save_context, .restore_context = clk_master_div_restore_context_chg, }; +static int clk_master_div_notifier_fn(struct notifier_block *notifier, + unsigned long code, void *data) +{ + const struct clk_master_characteristics *characteristics = + master_div->characteristics; + struct clk_notifier_data *cnd = data; + unsigned long flags, new_parent_rate, new_rate; + unsigned int mckr, div, new_div = 0; + int ret, i; + long tmp_diff; + long best_diff = -1; + + spin_lock_irqsave(master_div->lock, flags); + switch (code) { + case PRE_RATE_CHANGE: + /* + * We want to avoid any overclocking of MCK DIV domain. To do + * this we set a safe divider (the underclocking is not of + * interest as we can go as low as 32KHz). The relation + * b/w this clock and its parents are as follows: + * + * FRAC PLL -> DIV PLL -> MCK DIV + * + * With the proper safe divider we should be good even with FRAC + * PLL at its maximum value. + */ + ret = regmap_read(master_div->regmap, master_div->layout->offset, + &mckr); + if (ret) { + ret = NOTIFY_STOP_MASK; + goto unlock; + } + + mckr &= master_div->layout->mask; + div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; + + /* Switch to safe divider. */ + clk_master_div_set(master_div, + cnd->old_rate * characteristics->divisors[div], + master_div->safe_div); + break; + + case POST_RATE_CHANGE: + /* + * At this point we want to restore MCK DIV domain to its maximum + * allowed rate. + */ + ret = regmap_read(master_div->regmap, master_div->layout->offset, + &mckr); + if (ret) { + ret = NOTIFY_STOP_MASK; + goto unlock; + } + + mckr &= master_div->layout->mask; + div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; + new_parent_rate = cnd->new_rate * characteristics->divisors[div]; + + for (i = 0; i < ARRAY_SIZE(characteristics->divisors); i++) { + if (!characteristics->divisors[i]) + break; + + new_rate = DIV_ROUND_CLOSEST_ULL(new_parent_rate, + characteristics->divisors[i]); + + tmp_diff = characteristics->output.max - new_rate; + if (tmp_diff < 0) + continue; + + if (best_diff < 0 || best_diff > tmp_diff) { + new_div = characteristics->divisors[i]; + best_diff = tmp_diff; + } + + if (!tmp_diff) + break; + } + + if (!new_div) { + ret = NOTIFY_STOP_MASK; + goto unlock; + } + + /* Update the div to preserve MCK DIV clock rate. */ + clk_master_div_set(master_div, new_parent_rate, + new_div); + + ret = NOTIFY_OK; + break; + + default: + ret = NOTIFY_DONE; + break; + } + +unlock: + spin_unlock_irqrestore(master_div->lock, flags); + + return ret; +} + +static struct notifier_block clk_master_div_notifier = { + .notifier_call = clk_master_div_notifier_fn, +}; + static void clk_sama7g5_master_best_diff(struct clk_rate_request *req, struct clk_hw *parent, unsigned long parent_rate, @@ -496,6 +578,8 @@ at91_clk_register_master_internal(struct regmap *regmap, struct clk_master *master; struct clk_init_data init; struct clk_hw *hw; + unsigned int mckr; + unsigned long irqflags; int ret; if (!name || !num_parents || !parent_names || !lock) @@ -518,6 +602,16 @@ at91_clk_register_master_internal(struct regmap *regmap, master->chg_pid = chg_pid; master->lock = lock; + if (ops == &master_div_ops_chg) { + spin_lock_irqsave(master->lock, irqflags); + regmap_read(master->regmap, master->layout->offset, &mckr); + spin_unlock_irqrestore(master->lock, irqflags); + + mckr &= layout->mask; + mckr = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; + master->div = characteristics->divisors[mckr]; + } + hw = &master->hw; ret = clk_hw_register(NULL, &master->hw); if (ret) { @@ -554,19 +648,29 @@ at91_clk_register_master_div(struct regmap *regmap, const char *name, const char *parent_name, const struct clk_master_layout *layout, const struct clk_master_characteristics *characteristics, - spinlock_t *lock, u32 flags) + spinlock_t *lock, u32 flags, u32 safe_div) { const struct clk_ops *ops; + struct clk_hw *hw; if (flags & CLK_SET_RATE_GATE) ops = &master_div_ops; else ops = &master_div_ops_chg; - return at91_clk_register_master_internal(regmap, name, 1, - &parent_name, layout, - characteristics, ops, - lock, flags, -EINVAL); + hw = at91_clk_register_master_internal(regmap, name, 1, + &parent_name, layout, + characteristics, ops, + lock, flags, -EINVAL); + + if (!IS_ERR(hw) && safe_div) { + master_div = to_clk_master(hw); + master_div->safe_div = safe_div; + clk_notifier_register(hw->clk, + &clk_master_div_notifier); + } + + return hw; } static unsigned long diff --git a/drivers/clk/at91/dt-compat.c b/drivers/clk/at91/dt-compat.c index a97b99c2dc12..ca2dbb65b9df 100644 --- a/drivers/clk/at91/dt-compat.c +++ b/drivers/clk/at91/dt-compat.c @@ -399,7 +399,7 @@ of_at91_clk_master_setup(struct device_node *np, hw = at91_clk_register_master_div(regmap, name, "masterck_pres", layout, characteristics, - &mck_lock, CLK_SET_RATE_GATE); + &mck_lock, CLK_SET_RATE_GATE, 0); if (IS_ERR(hw)) goto out_free_characteristics; diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index 207ecccef29f..3a1bf6194c28 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -182,7 +182,7 @@ at91_clk_register_master_div(struct regmap *regmap, const char *name, const char *parent_names, const struct clk_master_layout *layout, const struct clk_master_characteristics *characteristics, - spinlock_t *lock, u32 flags); + spinlock_t *lock, u32 flags, u32 safe_div); struct clk_hw * __init at91_clk_sama7g5_register_master(struct regmap *regmap, diff --git a/drivers/clk/at91/sama5d2.c b/drivers/clk/at91/sama5d2.c index 3d1f78176c3e..d027294a0089 100644 --- a/drivers/clk/at91/sama5d2.c +++ b/drivers/clk/at91/sama5d2.c @@ -249,7 +249,7 @@ static void __init sama5d2_pmc_setup(struct device_node *np) "masterck_pres", &at91sam9x5_master_layout, &mck_characteristics, &mck_lock, - CLK_SET_RATE_GATE); + CLK_SET_RATE_GATE, 0); if (IS_ERR(hw)) goto err_free; diff --git a/drivers/clk/at91/sama5d3.c b/drivers/clk/at91/sama5d3.c index d376257807d2..339d0f382ff0 100644 --- a/drivers/clk/at91/sama5d3.c +++ b/drivers/clk/at91/sama5d3.c @@ -184,7 +184,7 @@ static void __init sama5d3_pmc_setup(struct device_node *np) "masterck_pres", &at91sam9x5_master_layout, &mck_characteristics, &mck_lock, - CLK_SET_RATE_GATE); + CLK_SET_RATE_GATE, 0); if (IS_ERR(hw)) goto err_free; diff --git a/drivers/clk/at91/sama5d4.c b/drivers/clk/at91/sama5d4.c index 5cbaac68da44..4af75b1e39e9 100644 --- a/drivers/clk/at91/sama5d4.c +++ b/drivers/clk/at91/sama5d4.c @@ -199,7 +199,7 @@ static void __init sama5d4_pmc_setup(struct device_node *np) "masterck_pres", &at91sam9x5_master_layout, &mck_characteristics, &mck_lock, - CLK_SET_RATE_GATE); + CLK_SET_RATE_GATE, 0); if (IS_ERR(hw)) goto err_free; diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c index ae52c10af040..c66bde6f7b47 100644 --- a/drivers/clk/at91/sama7g5.c +++ b/drivers/clk/at91/sama7g5.c @@ -1003,7 +1003,7 @@ static void __init sama7g5_pmc_setup(struct device_node *np) hw = at91_clk_register_master_div(regmap, "mck0", "cpuck", &mck0_layout, &mck0_characteristics, - &pmc_mck0_lock, 0); + &pmc_mck0_lock, CLK_GET_RATE_NOCACHE, 5); if (IS_ERR(hw)) goto err_free; From patchwork Thu Sep 23 13:20:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12512887 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 607D2C43217 for ; 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IronPort-SDR: xtXOt4SAePchpCzBhiyY+3sVvmsy2/DsYgxyQNl9D2/gpdzQhMhST8SdWuEVPftQ61/hfZ303X yHR/t+NJgVJrWRt5z1hjxyOWP6HTSARuo0Buf/CnelY/hTnCcvoh3zH8t02fs7v+32pjbcojkS tSiHzZbcdCw8epFyBO1hSBzAgPTAZTjhWnrGeiQMjxW93ryCP3wifB222uxww8m9aSyv3OWPOo gjKIJq7FncfsjVh/sT8iSLntacnSpvqtC1TGefANyhLOl2o5ekdvEUhmWSzTRBlx0WbyLCEaZq e+HqXFiVYN4jvtg72kby5bFK X-IronPort-AV: E=Sophos;i="5.85,316,1624345200"; d="scan'208";a="70327428" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 23 Sep 2021 06:21:34 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Thu, 23 Sep 2021 06:21:34 -0700 Received: from rob-dk-mpu01.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Thu, 23 Sep 2021 06:21:32 -0700 From: Claudiu Beznea To: , , , , CC: , , , Claudiu Beznea Subject: [PATCH v4 13/17] clk: at91: sama7g5: remove prescaler part of master clock Date: Thu, 23 Sep 2021 16:20:42 +0300 Message-ID: <20210923132046.1860549-14-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210923132046.1860549-1-claudiu.beznea@microchip.com> References: <20210923132046.1860549-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org On SAMA7G5 the prescaler part of master clock has been implemented as a changeable one. Everytime the prescaler is changed the PMC_SR.MCKRDY bit must be polled. Value 1 for PMC_SR.MCKRDY means the prescaler update is done. Driver polls for this bit until it becomes 1. On SAMA7G5 it has been discovered that in some conditions the PMC_SR.MCKRDY is not rising but the rate it provides it's stable. The workaround is to add a timeout when polling for PMC_SR.MCKRDY. At the moment, for SAMA7G5, the prescaler will be removed from Linux clock tree as all the frequencies for CPU could be obtained from PLL and also there will be less overhead when changing frequency via DVFS. Signed-off-by: Claudiu Beznea --- drivers/clk/at91/sama7g5.c | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c index c66bde6f7b47..fd9d17eabf54 100644 --- a/drivers/clk/at91/sama7g5.c +++ b/drivers/clk/at91/sama7g5.c @@ -992,16 +992,7 @@ static void __init sama7g5_pmc_setup(struct device_node *np) } parent_names[0] = "cpupll_divpmcck"; - hw = at91_clk_register_master_pres(regmap, "cpuck", 1, parent_names, - &mck0_layout, &mck0_characteristics, - &pmc_mck0_lock, - CLK_SET_RATE_PARENT, 0); - if (IS_ERR(hw)) - goto err_free; - - sama7g5_pmc->chws[PMC_CPU] = hw; - - hw = at91_clk_register_master_div(regmap, "mck0", "cpuck", + hw = at91_clk_register_master_div(regmap, "mck0", "cpupll_divpmcck", &mck0_layout, &mck0_characteristics, &pmc_mck0_lock, CLK_GET_RATE_NOCACHE, 5); if (IS_ERR(hw)) From patchwork Thu Sep 23 13:20:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12512889 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4740BC433F5 for ; Thu, 23 Sep 2021 13:21:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2F4A761090 for ; Thu, 23 Sep 2021 13:21:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241403AbhIWNXY (ORCPT ); Thu, 23 Sep 2021 09:23:24 -0400 Received: from esa.microchip.iphmx.com ([68.232.154.123]:7781 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241369AbhIWNXJ (ORCPT ); Thu, 23 Sep 2021 09:23:09 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1632403297; x=1663939297; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=RusdYrZLESoncLe3TEsjpmisjj7q2vbuzL1nryePEes=; b=QjsoUDtB+5iTKqznlEJ1y5KSxfSX4ssN5Fm0jYBBFa8GAdtV1Pgzn5gL k7S8kC+yuz2UpZXbJrdJ1E6HQ2lkfdzqK+GXtyQE4fs6wMmwnfk/E3k7U PpodVKT5l6rSY660gmu6nAdnQYlDsMktrPnyh6ToYC8RQtchAlxh5gGnC cYthSp/Kd3emmwAh83Cel9ghp4tSrGZx4FoxUD7aEVIHdUVVWsux95E3X ofSTJB6X15F8nVDTqpmrKQnVUs/Evs7jfn8gDrsIcSrnacTohqmZ62xOn wrGUj6+z1/P/y1gdObTcuhY/lj4v21+gvJ2myfG5vfx73gRsouUI77Vio Q==; IronPort-SDR: F4dFaDTDuKuz3swH/YeixtG1v+zSAc3a7cixjbr/YutU43xRyH/GKL0gB0JzIPAcmFAb+B/WEU b24zsx88EHZiX+lWfSTPZs6nWaQ+OW/NyxYmkXIsl/Li8j+WQJOdBpd4D5/K7LAbkiInFq2LkD kOJrgLaR4s7c3hWJfDh3MZ8pY/WVZ3mDPzX1tjxoSqRGBCQUmhPyjSjnZD5ipFpVbrPQRzjRtK BGY7dBNlsnVIhTd/ayQ+vBnNMNcZrMRGy+nWlz3xWVmW8yATn4gr1mlEyEyWrmuHG72qya2qPT r5x/DEDswHGca6atJ3l9Ulv5 X-IronPort-AV: E=Sophos;i="5.85,316,1624345200"; d="scan'208";a="70327432" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 23 Sep 2021 06:21:37 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Thu, 23 Sep 2021 06:21:36 -0700 Received: from rob-dk-mpu01.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Thu, 23 Sep 2021 06:21:34 -0700 From: Claudiu Beznea To: , , , , CC: , , , Claudiu Beznea Subject: [PATCH v4 14/17] clk: at91: sama7g5: set low limit for mck0 at 32KHz Date: Thu, 23 Sep 2021 16:20:43 +0300 Message-ID: <20210923132046.1860549-15-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210923132046.1860549-1-claudiu.beznea@microchip.com> References: <20210923132046.1860549-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org MCK0 could go as low as 32KHz. Set this limit. Signed-off-by: Claudiu Beznea --- drivers/clk/at91/sama7g5.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c index fd9d17eabf54..369dfafabbca 100644 --- a/drivers/clk/at91/sama7g5.c +++ b/drivers/clk/at91/sama7g5.c @@ -850,7 +850,7 @@ static const struct { /* MCK0 characteristics. */ static const struct clk_master_characteristics mck0_characteristics = { - .output = { .min = 50000000, .max = 200000000 }, + .output = { .min = 32768, .max = 200000000 }, .divisors = { 1, 2, 4, 3, 5 }, .have_div3_pres = 1, }; From patchwork Thu Sep 23 13:20:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12512891 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0CC41C433EF for ; Thu, 23 Sep 2021 13:21:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E971E61090 for ; Thu, 23 Sep 2021 13:21:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241283AbhIWNX1 (ORCPT ); Thu, 23 Sep 2021 09:23:27 -0400 Received: from esa.microchip.iphmx.com ([68.232.154.123]:30296 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241379AbhIWNXM (ORCPT ); Thu, 23 Sep 2021 09:23:12 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1632403300; x=1663939300; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=bZMQb4xEm45MpshvWcAzyLo2pqQa5xUnhBFD0WqA9bk=; b=VUux1Co5X4U0nXwSlnvioJXkMgBkfM2MqRErPQQAJXBtZNo4QDXnt484 7awEJIwoPmVhKA1SxLsCc8BTDsKdpkDreiya1UHMVtJIg6SLI068ja8+n RBVZEkRAuKny5M6mX6n12AozCOWSQghGa9C+LS5pU0nU26s59JE/8xawq vJ8wwECskxTCd5YSUtfICUDyHAwrnDe5650J3l/9LR065TBzlqXlr8K/q E1N1Z0iFthgvNpcL/DO3uknw5xoD/fquzSabKfFiKhouyyNi4/xPqXrFN h12pWYJWNx3M3SNi0eVoXqUI9P7zW3Lg9LZqWMKnv7644vWsqTfeotICb g==; IronPort-SDR: 2No5aWUIa1YZwUWob8WMea0H0kVLSx80Ds2wGRQAY5TrF6QPWGReNQWdFP9onm0zq8j4MUq9Lm 1IBUzU9hgESPJcEP0cP5a6TWYq7V+VtskGSygFZxPplOEV8rzhd3WywVDJ/Gx9QZsk5VNR5V5D uXHmbuUVLLm/6j2VgbpEchPKqN0obHiiKayrs3Dm5TYEOqeV1xnKxRpErTRrUnCcXTlyKXsNt6 tBQR0SMbNuWO17483uqTbReSyU3h8M5BUUu+yRUQ9m90QGTqNS6UkfMkBDaDig4K5c1ee0r+4s AW89rryx5rluc/+lypRa8deh X-IronPort-AV: E=Sophos;i="5.85,316,1624345200"; d="scan'208";a="130352847" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 23 Sep 2021 06:21:40 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Thu, 23 Sep 2021 06:21:39 -0700 Received: from rob-dk-mpu01.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Thu, 23 Sep 2021 06:21:37 -0700 From: Claudiu Beznea To: , , , , CC: , , , Claudiu Beznea Subject: [PATCH v4 15/17] clk: use clk_core_get_rate_recalc() in clk_rate_get() Date: Thu, 23 Sep 2021 16:20:44 +0300 Message-ID: <20210923132046.1860549-16-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210923132046.1860549-1-claudiu.beznea@microchip.com> References: <20210923132046.1860549-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org In case clock flags contains CLK_GET_RATE_NOCACHE the clk_rate_get() will return the cached rate. Thus, use clk_core_get_rate_recalc() which takes proper action when clock flags contains CLK_GET_RATE_NOCACHE. Signed-off-by: Claudiu Beznea --- drivers/clk/clk.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index 65508eb89ec9..64838754cdef 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -3108,7 +3108,7 @@ static int clk_rate_get(void *data, u64 *val) { struct clk_core *core = data; - *val = core->rate; + *val = clk_core_get_rate_recalc(core); return 0; } From patchwork Thu Sep 23 13:20:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12512893 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4D919C433EF for ; Thu, 23 Sep 2021 13:22:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3D08361050 for ; Thu, 23 Sep 2021 13:22:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241260AbhIWNXb (ORCPT ); Thu, 23 Sep 2021 09:23:31 -0400 Received: from esa.microchip.iphmx.com ([68.232.154.123]:30303 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241267AbhIWNXP (ORCPT ); Thu, 23 Sep 2021 09:23:15 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1632403303; x=1663939303; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=R9dm/LZCckRk6wJfIOlCq9hs1HeKlKJFOmWdXSXIfm8=; b=loZMJ/KzcQXaYliAnKyhxAuvPhoE2RCx48QWgPnsV1SSC65+W2iiawnp EmKoQMPQ6QvULhuAbory/61ibrle/mTMKQUXSu7IK6o4MxV0eYnQpvPyJ w08KXdivX2U1rr53s3ntru/N9UBm7hCnEdZeJhd70Df3eQMhtUgxCuuol K/tsKCdvSWQPXIvg6BN/lsMeXDCNPbshNkJZV9VZwrQWC8ad6Xz7txRE5 hYPSDEbHzlMy4fLBjhMaz5eQdoc55quEOP8xRRxkEsIlW7VM1OW4rOG+f 2iKG4rHZEZ67uukg78FLgHMiR0RO4njytHu7vI/AA7aC+k6q6VPc+an3f A==; IronPort-SDR: bdLKG+K25wuZgXPyBll0W/GRK660j/EYOExmv/xpxV4aQIyGbaIJ5EFbRHhsp/LHmDLx158FIU uLSHh1OhGCcMEtsYpY1e0jhaSsofGz2wZKkO1FlyGAEUMIEKuOySIu9MkWq30eM5meLCkplYKY wtMT3N23rIuwYlLRgNlncyx8yEE4g4vA1QEmbYR/EEMJBDWk4D8A1MGmfYV8TxnHtVaBXhXhuH Ub7bfOHQMaUwDaCIV1DXC7fwwU+EuvK7RMUoR2pWiG4X65Qo2Ri3Icnik+8uLwP5wQs/brwE8r iQ//w5oINhN2H2Chdq3+RoaX X-IronPort-AV: E=Sophos;i="5.85,316,1624345200"; d="scan'208";a="130352861" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 23 Sep 2021 06:21:42 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Thu, 23 Sep 2021 06:21:41 -0700 Received: from rob-dk-mpu01.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Thu, 23 Sep 2021 06:21:39 -0700 From: Claudiu Beznea To: , , , , CC: , , , Claudiu Beznea Subject: [PATCH v4 16/17] clk: remove extra empty line Date: Thu, 23 Sep 2021 16:20:45 +0300 Message-ID: <20210923132046.1860549-17-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210923132046.1860549-1-claudiu.beznea@microchip.com> References: <20210923132046.1860549-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Remove extra empty line. Signed-off-by: Claudiu Beznea --- drivers/clk/clk.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index 64838754cdef..815fe5f6651e 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -3574,7 +3574,6 @@ static int __clk_core_init(struct clk_core *core) clk_core_reparent_orphans_nolock(); - kref_init(&core->ref); out: clk_pm_runtime_put(core); From patchwork Thu Sep 23 13:20:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12512895 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 35384C433FE for ; Thu, 23 Sep 2021 13:22:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2089D61050 for ; Thu, 23 Sep 2021 13:22:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241350AbhIWNXc (ORCPT ); Thu, 23 Sep 2021 09:23:32 -0400 Received: from esa.microchip.iphmx.com ([68.232.154.123]:7798 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241302AbhIWNXQ (ORCPT ); Thu, 23 Sep 2021 09:23:16 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1632403305; x=1663939305; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=QVpsGQacYBazRN4bjzMQ0GaU+hULlQ1/8bIf+zxYHAo=; b=vuoJYRmLG2fkXvnEIby5aiz9dAoCaUdfc9ww6la3p36pBP/W1HujVObM 54wWWO/MIoMSywbyVVufvOy6koS/bQrefngSEgMf1h2RZGP2rGQk4jp2b /CfXx6UNCFQT8V/Bo/UoyfNTjOWDHGAORnfYwKesPfvn2Ydkw+aKZK2zo kodhb9q64FvhHJmZM4KHls+W9fW2rOu/mwEAGZ4vEaMmfOcS34cSVITaw myLNnOgRvuyVfXgyxUjkm6GkFF3BFcTcXF/cp54PnLiSOeuddY0bx2AML kCg3OuyYPRa0tP6uhAzcv0WK2dUm/OwoKJDCZl3CowZT60e4rCl4YCixQ A==; IronPort-SDR: GQ4MQtfibrFgCkykZtbKAF3droCnjQBYTd4D0iqkWxCAnqwxDPX4MfLtdK6AMKxNll+AV0GnZu CrYmMYa+ZxvIXh6lbXynVlK2mOdtLULwTao2b5c3jXvukvhl90WmI6ZWJ7wzV4kbxKjcs65otV l7eRaa2k/4nHD+sms+4fG3dBBu2Nq2MyJNXhczT0mObgXmgxe0ZlYnU9ET9YbLle6zr4FSPoL6 E5eqEKLdpIB+23XuqXOSkiBERGiUS99ABAEjZnvwgrO5hKDL7scZKaRM6XvIxiTNzC5fkjnGwD erR4F6IeKtp+RajoRURZnl8z X-IronPort-AV: E=Sophos;i="5.85,316,1624345200"; d="scan'208";a="70327459" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 23 Sep 2021 06:21:44 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Thu, 23 Sep 2021 06:21:44 -0700 Received: from rob-dk-mpu01.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Thu, 23 Sep 2021 06:21:42 -0700 From: Claudiu Beznea To: , , , , CC: , , , Claudiu Beznea Subject: [PATCH v4 17/17] clk: do not initialize ret Date: Thu, 23 Sep 2021 16:20:46 +0300 Message-ID: <20210923132046.1860549-18-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210923132046.1860549-1-claudiu.beznea@microchip.com> References: <20210923132046.1860549-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org There is no need to initialize ret. Signed-off-by: Claudiu Beznea --- drivers/clk/clk.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index 815fe5f6651e..b854c18e73af 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -2175,7 +2175,7 @@ static int clk_core_set_rate_nolock(struct clk_core *core, { struct clk_core *top, *fail_clk; unsigned long rate; - int ret = 0; + int ret; if (!core) return 0;