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Sun, 26 Sep 2021 23:38:46 -0700 Received: from [172.23.66.193] (port=60102 helo=xhdsneeli40u.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1mUkHl-00073C-F9; Sun, 26 Sep 2021 23:38:45 -0700 From: Srinivas Neeli To: , , , , CC: , , , , Srinivas Neeli Subject: [PATCH V2] rtc: zynqmp: Add calibration set and get support Date: Mon, 27 Sep 2021 12:08:37 +0530 Message-ID: <20210927063837.38478-1-srinivas.neeli@xilinx.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: c2491918-ef46-47db-384b-08d98181828e X-MS-TrafficTypeDiagnostic: SJ0PR02MB8768: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:7691; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: gzqfqZZjgC+QaFJRHicmsd+w9O+wLcTw4CfJQiLXHOQzJ/tMWb7HFAdVdzHBlgy3ALteSNwGMTySkgR8EIJOg05Y2ch0F9XL1tZjeYRXrjei6pPEsx+hKjooIZIBmXQFFpAgoJteQmHxqUto3a3hS6VlhRwLkDIuefwdhUo2E4k7MINuMbtFwZETxbFMxNXkfVQimPgr5cd04dgv/GsgfjL24GwOKMKonQxO5LjCxEREyvaTN2evYzJXARfJXdKS3Qy8p22/J0s9YFF5Nk9U1N+ImfOTKDKXOvvZNlId8u0yI8z8aFC9UsnAOqS7tL/9wnhBGu2SwWmZTp34O4yB9HkwrZj5N/fznqYU9VR3IwpCRx2IU17b8eEzlocCsasiGzlr3DWZ6otPa1U+Z915DhSyEdBm7hg8Dv6H5yE0V4pF7yfCxDr2x08VCpWOT7eceZn7WE7ErQ8h9J7XQILmvblrVuMNNNRisyRhli6EfNJChEEXpsr6hXnkEmnJqUXtARTMgYP5E8a7nIgVtOMaQAMxmyWany7hpau7cfwizWQ1xwoWqkqWjMBMWFlTPDBQYFHYI2HI7iEaUogoCMVgFD4CNtz7D+N2a4uPQfqF8Y1ddBbY2SAvPgiUSZmMHF1FwEu4YVxVXrkkHsM91TN5YBgygVQkL9bfcVJaIpI5+76aHUgXfI4r5hr464hoAPEIXedbc71lL/JCIxSuqdFQqOaMAF1y+P4kzGtlVm3eBwoXKN/MZefOeb92/mza3fs7 X-Forefront-Antispam-Report: CIP:149.199.62.198; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:xsj-pvapexch01.xlnx.xilinx.com; PTR:unknown-62-198.xilinx.com; CAT:NONE; SFS:(4636009)(36840700001)(46966006)(6666004)(36756003)(54906003)(110136005)(336012)(36860700001)(2616005)(186003)(44832011)(1076003)(47076005)(83380400001)(26005)(426003)(9786002)(8936002)(4326008)(316002)(70206006)(36906005)(107886003)(82310400003)(70586007)(6636002)(8676002)(2906002)(7696005)(508600001)(7636003)(356005)(5660300002)(102446001)(2101003); DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Sep 2021 06:39:08.9849 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c2491918-ef46-47db-384b-08d98181828e X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.62.198]; Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: DM3NAM02FT010.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR02MB8768 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210926_233912_935901_1CE1BD3F X-CRM114-Status: GOOD ( 19.93 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Zynqmp RTC controller has a calibration feature to compensate time deviation due to input clock inaccuracy. Set and get calibration API's are used for setting and getting calibration value from the controller calibration register. Signed-off-by: Srinivas Neeli --- Changes in V2: -Removed unused macro. -Updated code with review comments. --- drivers/rtc/rtc-zynqmp.c | 100 ++++++++++++++++++++++++++++++++------- 1 file changed, 83 insertions(+), 17 deletions(-) diff --git a/drivers/rtc/rtc-zynqmp.c b/drivers/rtc/rtc-zynqmp.c index f440bb52be92..3731ddfbd90f 100644 --- a/drivers/rtc/rtc-zynqmp.c +++ b/drivers/rtc/rtc-zynqmp.c @@ -36,10 +36,15 @@ #define RTC_OSC_EN BIT(24) #define RTC_BATT_EN BIT(31) -#define RTC_CALIB_DEF 0x198233 +#define RTC_CALIB_DEF 0x8000 #define RTC_CALIB_MASK 0x1FFFFF #define RTC_ALRM_MASK BIT(1) #define RTC_MSEC 1000 +#define RTC_FR_MASK 0xF0000 +#define RTC_FR_MAX_TICKS 16 +#define RTC_OFFSET_MAX 150000 +#define RTC_OFFSET_MIN -150000 +#define RTC_PPB 1000000000LL struct xlnx_rtc_dev { struct rtc_device *rtc; @@ -61,13 +66,6 @@ static int xlnx_rtc_set_time(struct device *dev, struct rtc_time *tm) */ new_time = rtc_tm_to_time64(tm) + 1; - /* - * Writing into calibration register will clear the Tick Counter and - * force the next second to be signaled exactly in 1 second period - */ - xrtcdev->calibval &= RTC_CALIB_MASK; - writel(xrtcdev->calibval, (xrtcdev->reg_base + RTC_CALIB_WR)); - writel(new_time, xrtcdev->reg_base + RTC_SET_TM_WR); /* @@ -174,14 +172,76 @@ static void xlnx_init_rtc(struct xlnx_rtc_dev *xrtcdev) rtc_ctrl |= RTC_BATT_EN; writel(rtc_ctrl, xrtcdev->reg_base + RTC_CTRL); - /* - * Based on crystal freq of 33.330 KHz - * set the seconds counter and enable, set fractions counter - * to default value suggested as per design spec - * to correct RTC delay in frequency over period of time. + /* Update calibvalue */ + xrtcdev->calibval = readl(xrtcdev->reg_base + RTC_CALIB_RD); +} + +static int xlnx_rtc_read_offset(struct device *dev, long *offset) +{ + struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev); + long offset_val = 0; + unsigned int tick_mult = RTC_PPB / (xrtcdev->calibval & RTC_TICK_MASK); + + /* Offset with seconds ticks */ + offset_val = xrtcdev->calibval & RTC_TICK_MASK; + offset_val = offset_val - RTC_CALIB_DEF; + offset_val = offset_val * tick_mult; + + /* Offset with fractional ticks */ + if (xrtcdev->calibval & RTC_FR_EN) + offset_val += ((xrtcdev->calibval & RTC_FR_MASK) >> RTC_FR_DATSHIFT) + * (tick_mult / RTC_FR_MAX_TICKS); + *offset = offset_val; + + return 0; +} + +static int xlnx_rtc_set_offset(struct device *dev, long offset) +{ + struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev); + short int max_tick; + unsigned char fract_tick = 0; + unsigned int calibval; + int fract_offset; + unsigned int tick_mult = RTC_PPB / (xrtcdev->calibval & RTC_TICK_MASK); + + /* Make sure offset value is within supported range */ + if (offset < RTC_OFFSET_MIN || offset > RTC_OFFSET_MAX) + return -ERANGE; + + /* Number ticks for given offset */ + max_tick = div_s64_rem(offset, tick_mult, &fract_offset); + + /* Number fractional ticks for given offset */ + if (fract_offset) { + if (fract_offset < 0) { + fract_offset = fract_offset + tick_mult; + max_tick--; + } + if (fract_offset > (tick_mult / RTC_FR_MAX_TICKS)) { + for (fract_tick = 1; fract_tick < 16; fract_tick++) { + if (fract_offset <= + (fract_tick * + (tick_mult / RTC_FR_MAX_TICKS))) + break; + } + } + } + + /* Zynqmp RTC uses second and fractional tick + * counters for compensation */ - xrtcdev->calibval &= RTC_CALIB_MASK; - writel(xrtcdev->calibval, (xrtcdev->reg_base + RTC_CALIB_WR)); + calibval = max_tick + RTC_CALIB_DEF; + + if (fract_tick) + calibval |= RTC_FR_EN; + + calibval |= (fract_tick << RTC_FR_DATSHIFT); + + writel(calibval, (xrtcdev->reg_base + RTC_CALIB_WR)); + xrtcdev->calibval = calibval; + + return 0; } static const struct rtc_class_ops xlnx_rtc_ops = { @@ -190,6 +250,8 @@ static const struct rtc_class_ops xlnx_rtc_ops = { .read_alarm = xlnx_rtc_read_alarm, .set_alarm = xlnx_rtc_set_alarm, .alarm_irq_enable = xlnx_rtc_alarm_irq_enable, + .read_offset = xlnx_rtc_read_offset, + .set_offset = xlnx_rtc_set_offset, }; static irqreturn_t xlnx_rtc_interrupt(int irq, void *id) @@ -215,6 +277,7 @@ static int xlnx_rtc_probe(struct platform_device *pdev) { struct xlnx_rtc_dev *xrtcdev; int ret; + unsigned int calibval; xrtcdev = devm_kzalloc(&pdev->dev, sizeof(*xrtcdev), GFP_KERNEL); if (!xrtcdev) @@ -256,9 +319,12 @@ static int xlnx_rtc_probe(struct platform_device *pdev) } ret = of_property_read_u32(pdev->dev.of_node, "calibration", - &xrtcdev->calibval); + &calibval); if (ret) - xrtcdev->calibval = RTC_CALIB_DEF; + calibval = RTC_CALIB_DEF; + ret = readl(xrtcdev->reg_base + RTC_CALIB_RD); + if (!ret) + writel(calibval, (xrtcdev->reg_base + RTC_CALIB_WR)); xlnx_init_rtc(xrtcdev);