From patchwork Tue Sep 28 01:49:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philip Chen X-Patchwork-Id: 12521413 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6935BC433EF for ; Tue, 28 Sep 2021 01:49:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3F8616120F for ; Tue, 28 Sep 2021 01:49:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238496AbhI1Bv0 (ORCPT ); Mon, 27 Sep 2021 21:51:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46092 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238443AbhI1BvZ (ORCPT ); Mon, 27 Sep 2021 21:51:25 -0400 Received: from mail-pl1-x630.google.com (mail-pl1-x630.google.com [IPv6:2607:f8b0:4864:20::630]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 03F32C061575 for ; Mon, 27 Sep 2021 18:49:47 -0700 (PDT) Received: by mail-pl1-x630.google.com with SMTP id c4so13082249pls.6 for ; Mon, 27 Sep 2021 18:49:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=DBB9PqXKAn7JtQopDAKE4raqjGwkNHbNRgTQPsWiL3c=; b=m/sLHK5M5r56kh/xekWvOHB003T89XyitfCHc4bhfZOZGs9hzR3qUE1Cqv8WDqpyab 5NtRbV5GSeVe0AxGLXznaHhgf/MxETYAnUPTpAbKD4ZhyhPNtFTaL2wYlSscgoZYx/qD yXxkJAf384J74xXg524GpkHr3G+83jO/3oO9c= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=DBB9PqXKAn7JtQopDAKE4raqjGwkNHbNRgTQPsWiL3c=; b=z5T+S+x+ddFCVac9eC99nqD/zp/3ytNEnXdtDIE3p7GQuJF06NKvmKTQO3HxYxz/ht mcakOmUWRJ1MpYIBNg1efLctxet4vRaOf9PG1HYs35f08CaFs49ETtOextOdPVaNA6qh wIq7kuv4kwPjDPZuXrfPISzYsHo2Ykn8drYZsf7gacEZwWVsqqHcbvX66MhqYLvUULvB HVy6dsGp6R493ytyGoSs5MVUGD7uOVnrQYXsUhuCsBElJXW4ct0QBzTFWNvFcv+iVtG9 Lq9dvsZc61bjXNwiXElXxka31ixALRjc5bgj/SWj8tyxv2ABoGvmKKyi03n6dLcQWIPa lPLw== X-Gm-Message-State: AOAM532t+7xAIwnUl/x8cAGB5ZuRGviRcl1TRquQGf96bNzWHjAS7gZ+ sgalIeWRtN76U9tVHRNCdRw22wPTmuNVJA== X-Google-Smtp-Source: ABdhPJx1mrpaEOexp4+9hCYNAayQ9lluQub+fVgerntdSlhmwqQYqw4lWi11WCoNSGprgT/cbc0grw== X-Received: by 2002:a17:90a:ec0b:: with SMTP id l11mr2442117pjy.30.1632793786461; Mon, 27 Sep 2021 18:49:46 -0700 (PDT) Received: from philipchen.mtv.corp.google.com ([2620:15c:202:201:8016:e67e:e320:7523]) by smtp.gmail.com with ESMTPSA id e15sm13013744pfc.134.2021.09.27.18.49.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Sep 2021 18:49:45 -0700 (PDT) From: Philip Chen To: LKML Cc: dianders@chromium.org, swboyd@chromium.org, Philip Chen , Andy Gross , Bjorn Andersson , Rob Herring , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH 1/2] arm64: dts: sc7180: Factor out ti-sn65dsi86 support Date: Mon, 27 Sep 2021 18:49:39 -0700 Message-Id: <20210927184858.1.Ib7e63ae17e827ce0636a09d5dec9796043e4f80a@changeid> X-Mailer: git-send-email 2.33.0.685.g46640cef36-goog MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Factor out ti-sn65dsi86 edp bridge as a separate dts fragment. This helps us introduce the second source edp bridge later. Signed-off-by: Philip Chen Reviewed-by: Stephen Boyd --- .../boot/dts/qcom/sc7180-trogdor-coachz.dtsi | 1 + .../boot/dts/qcom/sc7180-trogdor-lazor.dtsi | 1 + .../boot/dts/qcom/sc7180-trogdor-pompom.dtsi | 1 + .../arm64/boot/dts/qcom/sc7180-trogdor-r1.dts | 1 + .../dts/qcom/sc7180-trogdor-ti-sn65dsi86.dtsi | 87 +++++++++++++++++++ arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 81 ----------------- 6 files changed, 91 insertions(+), 81 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-ti-sn65dsi86.dtsi diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi index a758e4d22612..1d13fba3bd2f 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi @@ -11,6 +11,7 @@ ap_h1_spi: &spi0 {}; #include "sc7180-trogdor.dtsi" +#include "sc7180-trogdor-ti-sn65dsi86.dtsi" /* Deleted nodes from trogdor.dtsi */ diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi index 00535aaa43c9..27b26a782af9 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi @@ -11,6 +11,7 @@ ap_h1_spi: &spi0 {}; #include "sc7180-trogdor.dtsi" +#include "sc7180-trogdor-ti-sn65dsi86.dtsi" &ap_sar_sensor { semtech,cs0-ground; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi index a246dbd74cc1..e7c7cad14989 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi @@ -11,6 +11,7 @@ ap_h1_spi: &spi0 {}; #include "sc7180-trogdor.dtsi" +#include "sc7180-trogdor-ti-sn65dsi86.dtsi" / { thermal-zones { diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts index 2b522f9e0d8f..457c25499863 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts @@ -13,6 +13,7 @@ ap_h1_spi: &spi0 {}; #include "sc7180-trogdor.dtsi" +#include "sc7180-trogdor-ti-sn65dsi86.dtsi" / { model = "Google Trogdor (rev1+)"; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-ti-sn65dsi86.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-ti-sn65dsi86.dtsi new file mode 100644 index 000000000000..7b1034a5a8e9 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-ti-sn65dsi86.dtsi @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Trogdor dts fragment for the boards with TI sn65dsi86 edp bridge + * + * Copyright 2021 Google LLC. + */ + +&dsi0_out { + remote-endpoint = <&sn65dsi86_in>; + data-lanes = <0 1 2 3>; +}; + +&edp_brij_i2c { + sn65dsi86_bridge: bridge@2d { + compatible = "ti,sn65dsi86"; + reg = <0x2d>; + pinctrl-names = "default"; + pinctrl-0 = <&edp_brij_en>, <&edp_brij_irq>; + gpio-controller; + #gpio-cells = <2>; + + interrupt-parent = <&tlmm>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; + + enable-gpios = <&tlmm 104 GPIO_ACTIVE_HIGH>; + + vpll-supply = <&pp1800_edp_vpll>; + vccio-supply = <&pp1800_brij_vccio>; + vcca-supply = <&pp1200_brij>; + vcc-supply = <&pp1200_brij>; + + clocks = <&rpmhcc RPMH_LN_BB_CLK3>; + clock-names = "refclk"; + + no-hpd; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + sn65dsi86_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + sn65dsi86_out: endpoint { + data-lanes = <0 1>; + remote-endpoint = <&panel_in_edp>; + }; + }; + }; + + aux-bus { + panel: panel { + /* Compatible will be filled in per-board */ + power-supply = <&pp3300_dx_edp>; + backlight = <&backlight>; + hpd-gpios = <&sn65dsi86_bridge 2 GPIO_ACTIVE_HIGH>; + + port { + panel_in_edp: endpoint { + remote-endpoint = <&sn65dsi86_out>; + }; + }; + }; + }; + }; +}; + +&tlmm { + edp_brij_irq: edp-brij-irq { + pinmux { + pins = "gpio11"; + function = "gpio"; + }; + + pinconf { + pins = "gpio11"; + drive-strength = <2>; + bias-pull-down; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index 0f2b3c00e434..5ad3f15652d5 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -602,15 +602,6 @@ &camcc { &dsi0 { status = "okay"; vdda-supply = <&vdda_mipi_dsi0_1p2>; - - ports { - port@1 { - endpoint { - remote-endpoint = <&sn65dsi86_in>; - data-lanes = <0 1 2 3>; - }; - }; - }; }; &dsi_phy { @@ -621,65 +612,6 @@ &dsi_phy { edp_brij_i2c: &i2c2 { status = "okay"; clock-frequency = <400000>; - - sn65dsi86_bridge: bridge@2d { - compatible = "ti,sn65dsi86"; - reg = <0x2d>; - pinctrl-names = "default"; - pinctrl-0 = <&edp_brij_en>, <&edp_brij_irq>; - gpio-controller; - #gpio-cells = <2>; - - interrupt-parent = <&tlmm>; - interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; - - enable-gpios = <&tlmm 104 GPIO_ACTIVE_HIGH>; - - vpll-supply = <&pp1800_edp_vpll>; - vccio-supply = <&pp1800_brij_vccio>; - vcca-supply = <&pp1200_brij>; - vcc-supply = <&pp1200_brij>; - - clocks = <&rpmhcc RPMH_LN_BB_CLK3>; - clock-names = "refclk"; - - no-hpd; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - sn65dsi86_in: endpoint { - remote-endpoint = <&dsi0_out>; - }; - }; - - port@1 { - reg = <1>; - sn65dsi86_out: endpoint { - data-lanes = <0 1>; - remote-endpoint = <&panel_in_edp>; - }; - }; - }; - - aux-bus { - panel: panel { - /* Compatible will be filled in per-board */ - power-supply = <&pp3300_dx_edp>; - backlight = <&backlight>; - hpd-gpios = <&sn65dsi86_bridge 2 GPIO_ACTIVE_HIGH>; - - port { - panel_in_edp: endpoint { - remote-endpoint = <&sn65dsi86_out>; - }; - }; - }; - }; - }; }; ap_sar_sensor_i2c: &i2c5 { @@ -1245,19 +1177,6 @@ pinconf { }; }; - edp_brij_irq: edp-brij-irq { - pinmux { - pins = "gpio11"; - function = "gpio"; - }; - - pinconf { - pins = "gpio11"; - drive-strength = <2>; - bias-pull-down; - }; - }; - en_pp3300_codec: en-pp3300-codec { pinmux { pins = "gpio83"; From patchwork Tue Sep 28 01:49:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philip Chen X-Patchwork-Id: 12521415 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B669DC4332F for ; Tue, 28 Sep 2021 01:49:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 992736128A for ; Tue, 28 Sep 2021 01:49:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238583AbhI1Bvc (ORCPT ); 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Mon, 27 Sep 2021 18:49:48 -0700 (PDT) From: Philip Chen To: LKML Cc: dianders@chromium.org, swboyd@chromium.org, Philip Chen , Andy Gross , Bjorn Andersson , Rob Herring , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH 2/2] arm64: dts: sc7180: Support Parade ps8640 edp bridge Date: Mon, 27 Sep 2021 18:49:40 -0700 Message-Id: <20210927184858.2.I651eec59ce3cd1c4bdd64de31f9c3531f501b3a8@changeid> X-Mailer: git-send-email 2.33.0.685.g46640cef36-goog In-Reply-To: <20210927184858.1.Ib7e63ae17e827ce0636a09d5dec9796043e4f80a@changeid> References: <20210927184858.1.Ib7e63ae17e827ce0636a09d5dec9796043e4f80a@changeid> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add a dts fragment file to support the sc7180 boards with the second source edp bridge, Parade ps8640. Signed-off-by: Philip Chen --- .../qcom/sc7180-trogdor-parade-ps8640.dtsi | 105 ++++++++++++++++++ 1 file changed, 105 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-parade-ps8640.dtsi diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-parade-ps8640.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-parade-ps8640.dtsi new file mode 100644 index 000000000000..647afb3a7c6a --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-parade-ps8640.dtsi @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Trogdor dts fragment for the boards with Parade ps8640 edp bridge + * + * Copyright 2021 Google LLC. + */ + +/ { + pp3300_brij_ps8640: pp3300-brij-ps8640 { + compatible = "regulator-fixed"; + status = "okay"; + regulator-name = "pp3300_brij_ps8640"; + + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 32 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&en_pp3300_edp_brij_ps8640>; + + vin-supply = <&pp3300_a>; + }; +}; + +&dsi0_out { + remote-endpoint = <&ps8640_in>; +}; + +&i2c2 { + ps8640_bridge: edp-bridge@8 { + compatible = "parade,ps8640"; + reg = <0x8>; + + powerdown-gpios = <&tlmm 104 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 11 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&edp_brij_en>, <&edp_brij_ps8640_rst>; + + vdd12-supply = <&pp1200_brij>; + vdd33-supply = <&pp3300_brij_ps8640>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ps8640_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + ps8640_out: endpoint { + remote-endpoint = <&panel_in_edp>; + }; + }; + }; + + aux_bus: aux-bus { + panel: panel { + /* Compatible will be filled in per-board */ + power-supply = <&pp3300_dx_edp>; + backlight = <&backlight>; + + port { + panel_in_edp: endpoint { + remote-endpoint = <&ps8640_out>; + }; + }; + }; + }; + }; +}; + +&tlmm { + edp_brij_ps8640_rst: edp-brij-ps8640-rst { + pinmux { + pins = "gpio11"; + function = "gpio"; + }; + + pinconf { + pins = "gpio11"; + drive-strength = <2>; + bias-disable; + }; + }; + + en_pp3300_edp_brij_ps8640: en-pp3300-edp-brij-ps8640 { + pinmux { + pins = "gpio32"; + function = "gpio"; + }; + + pinconf { + pins = "gpio32"; + drive-strength = <2>; + bias-disable; + }; + }; +};