From patchwork Tue Sep 28 17:12:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephan Gerhold X-Patchwork-Id: 12523317 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 88EC6C433F5 for ; Tue, 28 Sep 2021 17:21:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 764576124A for ; Tue, 28 Sep 2021 17:21:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241997AbhI1RXU (ORCPT ); Tue, 28 Sep 2021 13:23:20 -0400 Received: from mo4-p01-ob.smtp.rzone.de ([85.215.255.52]:23162 "EHLO mo4-p01-ob.smtp.rzone.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242000AbhI1RXS (ORCPT ); Tue, 28 Sep 2021 13:23:18 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1632849687; s=strato-dkim-0002; d=gerhold.net; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Cc:Date: From:Subject:Sender; bh=UQcUTtYLE5XTLYEeJvf8m7Vgpj6UESAhcqPxJaTQEvQ=; b=TcYSdXZKMuNOJosUwXGfySV9hGAAZ0A8jF5ultZRQbp0/rEqXmqQreBSmmBip9WbYK cX1SWVcde0r1Md6Xi2QOYUaor4+/JrVAuJRJuvl4MbrqLFUjKR4K62ETD7dn5EgaAdW8 9Bzw1979G2fpsfOVM20PfmTlq7uw2Kqw5eTxXwhxlTrrg/6ykpspwGN9I2Qjjd1W1pwZ WxDBsqDzXdlHYkmY/s9FkjAw24393z0a5z6Ob8lNzqLoo/SoAbp+W3+taAuycLiRDCe4 Egg6S1qyNRxIM8zzZHMpZMdledGe/7V1jOKLPkKo0g08fLwQZ7QXLpWOXtki6pMGK02+ gllQ== Authentication-Results: strato.com; dkim=none X-RZG-AUTH: ":P3gBZUipdd93FF5ZZvYFPugejmSTVR2nRPhVORvLd4SsytBXTbAOHjRHIhr3eFSKSxc=" X-RZG-CLASS-ID: mo00 Received: from droid.. by smtp.strato.de (RZmta 47.33.8 DYNA|AUTH) with ESMTPSA id 301038x8SHLQoBH (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256 bits)) (Client did not present a certificate); Tue, 28 Sep 2021 19:21:26 +0200 (CEST) From: Stephan Gerhold To: Bjorn Andersson Cc: Andy Gross , linux-arm-msm@vger.kernel.org, Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, Stephan Gerhold Subject: [PATCH 01/15] arm64: dts: qcom: Add device tree for Samsung Galaxy S4 Mini Value Edition Date: Tue, 28 Sep 2021 19:12:17 +0200 Message-Id: <20210928171231.12766-2-stephan@gerhold.net> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210928171231.12766-1-stephan@gerhold.net> References: <20210928171231.12766-1-stephan@gerhold.net> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The Samsung Galaxy S4 Mini Value Edition is an updated version of the original S4 Mini based on MSM8916. It is similar to the other Samsung devices based on MSM8916 with only a few minor differences. The device tree contains initial support for the S4 Mini Value Edition with: - UART - eMMC/SD card (needs quirk for some reason) - Buttons - Vibrator - WiFi/Bluetooth (WCNSS) - USB Unfortunately, the S4 Mini VE was released with outdated 32-bit only firmware and never received any update from Samsung. Since the 32-bit TrustZone firmware is signed there seems to be no way currently to actually boot this device tree on arm64 Linux at the moment. :( However, it is possible to use this device tree by compiling an ARM32 kernel instead. The device tree can be easily built on ARM32 with an #include and it works really well there. To avoid confusion for others it is still better to add this device tree on arm64. Otherwise it's easy to forget to update this one when making some changes that affect all MSM8916 devices. Maybe someone finds a way to boot ARM64 Linux on this device at some point. In this case I expect that this device tree can be simply used as-is. Signed-off-by: Stephan Gerhold --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../dts/qcom/msm8916-samsung-serranove.dts | 301 ++++++++++++++++++ 2 files changed, 302 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 8398c0a2150f..6c6efa192a6e 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -15,6 +15,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8910.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a3u-eur.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a5u-eur.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-serranove.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-wingtech-wt88047.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8992-bullhead-rev-101.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8992-msft-lumia-octagon-talkman.dtb diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts new file mode 100644 index 000000000000..33613cbb4929 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts @@ -0,0 +1,301 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright (C) 2019 Stephan Gerhold + +/dts-v1/; + +#include "msm8916-pm8916.dtsi" +#include +#include +#include + +/* + * NOTE: The original firmware from Samsung can only boot ARM32 kernels. + * Unfortunately, the firmware is signed and cannot be replaced easily. + * There seems to be no way to boot ARM64 kernels on this device at the moment, + * even though the hardware would support it. + * + * However, it is possible to use this device tree by compiling an ARM32 kernel + * instead. For clarity and build testing this device tree is maintained next + * to the other MSM8916 device trees. However, it is actually used through + * arch/arm/boot/dts/qcom-msm8916-samsung-serranove.dts + */ + +/ { + model = "Samsung Galaxy S4 Mini Value Edition"; + compatible = "samsung,serranove", "qcom,msm8916"; + + aliases { + serial0 = &blsp1_uart2; + }; + + chosen { + stdout-path = "serial0"; + }; + + reserved-memory { + /* Additional memory used by Samsung firmware modifications */ + tz-apps@85500000 { + reg = <0x0 0x85500000 0x0 0xb00000>; + no-map; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_default>; + + label = "GPIO Buttons"; + + volume-up { + label = "Volume Up"; + gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + home { + label = "Home"; + gpios = <&msmgpio 109 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + gpio-hall-sensor { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_hall_sensor_default>; + + label = "GPIO Hall Effect Sensor"; + + hall-sensor { + label = "Hall Effect Sensor"; + gpios = <&msmgpio 52 GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + linux,can-disable; + }; + }; + + i2c-muic { + compatible = "i2c-gpio"; + sda-gpios = <&msmgpio 105 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&msmgpio 106 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + + pinctrl-names = "default"; + pinctrl-0 = <&muic_i2c_default>; + + #address-cells = <1>; + #size-cells = <0>; + + muic: extcon@14 { + compatible = "siliconmitus,sm5504-muic"; + reg = <0x14>; + + interrupt-parent = <&msmgpio>; + interrupts = <12 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-names = "default"; + pinctrl-0 = <&muic_irq_default>; + }; + }; +}; + +&blsp1_uart2 { + status = "okay"; +}; + +&pm8916_resin { + status = "okay"; + linux,code = ; +}; + +&pm8916_vib { + status = "okay"; +}; + +&pronto { + status = "okay"; + + iris { + compatible = "qcom,wcn3660b"; + }; +}; + +&sdhc_1 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; + pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; +}; + +&sdhc_2 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; + + non-removable; + + /* + * FIXME: Disable UHS-I modes since tuning fails with: + * + * sdhci_msm 7864900.sdhci: mmc1: No tuning point found + * mmc1: tuning execution failed: -5 + * mmc1: error -5 whilst initialising SD card + * + * This is the quirk used on downstream, which suggests this is + * a hardware limitation. However, probing a card using DDR50 + * (without tuning), so maybe only tuning is broken? + */ + no-1-8-v; +}; + +&usb { + status = "okay"; + extcon = <&muic>, <&muic>; +}; + +&usb_hs_phy { + extcon = <&muic>; +}; + +&smd_rpm_regulators { + vdd_l1_l2_l3-supply = <&pm8916_s3>; + vdd_l4_l5_l6-supply = <&pm8916_s4>; + vdd_l7-supply = <&pm8916_s4>; + + s3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1300000>; + }; + + s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2100000>; + }; + + l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + l4 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l8 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2900000>; + }; + + l9 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + l10 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2800000>; + }; + + l11 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + regulator-allow-set-load; + regulator-system-load = <200000>; + }; + + l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + l13 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + }; + + l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + l16 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + l18 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; +}; + +&msmgpio { + gpio_keys_default: gpio-keys-default { + pins = "gpio107", "gpio109"; + function = "gpio"; + + drive-strength = <2>; + bias-pull-up; + }; + + gpio_hall_sensor_default: gpio-hall-sensor-default { + pins = "gpio52"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + muic_i2c_default: muic-i2c-default { + pins = "gpio105", "gpio106"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + muic_irq_default: muic-irq-default { + pins = "gpio12"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; +}; From patchwork Tue Sep 28 17:12:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephan Gerhold X-Patchwork-Id: 12523309 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C432DC4332F for ; Tue, 28 Sep 2021 17:21:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AA40F61246 for ; Tue, 28 Sep 2021 17:21:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242022AbhI1RXT (ORCPT ); Tue, 28 Sep 2021 13:23:19 -0400 Received: from mo4-p02-ob.smtp.rzone.de ([85.215.255.83]:32774 "EHLO mo4-p02-ob.smtp.rzone.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241998AbhI1RXS (ORCPT ); Tue, 28 Sep 2021 13:23:18 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1632849687; s=strato-dkim-0002; d=gerhold.net; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Cc:Date: From:Subject:Sender; bh=A31zal12Ktk/Z33oNiiBVZbgIbmCKDXhW8R1vz9+q2A=; b=KGCqzoNaz57uwXgNplmg2rrNsT1K4LMSJAu+Bw+sUU8GMadjZyju0VsGpyQ2FYaQtF 4Mv25ASXC6NkSryK/9Db1VCnDluqEJXm2yn9ouBOr9t1h3+sIsMM5PoeMmdH5Tb/8SMh aFTNcuZ78S3fHcI1MMWNz0RmTAQhXAt+VTQ3GZGmSKlilRZe6Ug15I3pCnl+shuaj1BK dM2Tyrb/AIeriofEZMOuffxkfek0sgtbGpRpYaqKDcCQEKb8lmroChVmDKa5FsnB9emu rki/QPx41gvPgt7yAOw0gSml6Cq7nKHWETlGidKrIhDHxaA/EoikANJJ4wS0zoe1xIyd 43Dg== Authentication-Results: strato.com; dkim=none X-RZG-AUTH: ":P3gBZUipdd93FF5ZZvYFPugejmSTVR2nRPhVORvLd4SsytBXTbAOHjRHIhr3eFSKSxc=" X-RZG-CLASS-ID: mo00 Received: from droid.. by smtp.strato.de (RZmta 47.33.8 DYNA|AUTH) with ESMTPSA id 301038x8SHLRoBI (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256 bits)) (Client did not present a certificate); Tue, 28 Sep 2021 19:21:27 +0200 (CEST) From: Stephan Gerhold To: Bjorn Andersson Cc: Andy Gross , linux-arm-msm@vger.kernel.org, Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, Stephan Gerhold Subject: [PATCH 02/15] arm64: dts: qcom: msm8916-samsung-serranove: Add touch screen Date: Tue, 28 Sep 2021 19:12:18 +0200 Message-Id: <20210928171231.12766-3-stephan@gerhold.net> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210928171231.12766-1-stephan@gerhold.net> References: <20210928171231.12766-1-stephan@gerhold.net> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Like msm8916-samsung-a3u-eur, the S4 Mini VE uses a Zinitix BT541 touch screen. Add it together with the necessary fixed-regulator to the device tree. Signed-off-by: Stephan Gerhold --- .../dts/qcom/msm8916-samsung-serranove.dts | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts index 33613cbb4929..214a863eedbf 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts @@ -78,6 +78,19 @@ hall-sensor { }; }; + reg_vdd_tsp: regulator-vdd-tsp { + compatible = "regulator-fixed"; + regulator-name = "vdd_tsp"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&msmgpio 73 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&tsp_en_default>; + }; + i2c-muic { compatible = "i2c-gpio"; sda-gpios = <&msmgpio 105 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; @@ -102,6 +115,27 @@ muic: extcon@14 { }; }; +&blsp_i2c5 { + status = "okay"; + + touchscreen@20 { + compatible = "zinitix,bt541"; + reg = <0x20>; + + interrupt-parent = <&msmgpio>; + interrupts = <13 IRQ_TYPE_EDGE_FALLING>; + + touchscreen-size-x = <540>; + touchscreen-size-y = <960>; + + vdd-supply = <®_vdd_tsp>; + vddo-supply = <&pm8916_l6>; + + pinctrl-names = "default"; + pinctrl-0 = <&tsp_irq_default>; + }; +}; + &blsp1_uart2 { status = "okay"; }; @@ -298,4 +332,20 @@ muic_irq_default: muic-irq-default { drive-strength = <2>; bias-disable; }; + + tsp_en_default: tsp-en-default { + pins = "gpio73"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + tsp_irq_default: tsp-irq-default { + pins = "gpio13"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; }; From patchwork Tue Sep 28 17:12:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephan Gerhold X-Patchwork-Id: 12523321 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B296AC4321E for ; Tue, 28 Sep 2021 17:21:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 993156127C for ; Tue, 28 Sep 2021 17:21:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242051AbhI1RXW (ORCPT ); Tue, 28 Sep 2021 13:23:22 -0400 Received: from mo4-p02-ob.smtp.rzone.de ([81.169.146.170]:13682 "EHLO mo4-p02-ob.smtp.rzone.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242014AbhI1RXV (ORCPT ); Tue, 28 Sep 2021 13:23:21 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1632849688; s=strato-dkim-0002; d=gerhold.net; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Cc:Date: From:Subject:Sender; bh=Vt28A8btSKr+qswJd0U4CAoaAGGfqbbYx3A/RZjLeJY=; b=fJHWfS6iFnoy2NnnEmyGghTIRsITPwDjRPE8mM+ltjtwTAggECEWYzLlXW5KXDNMCW bswomA2p2nlUwdNPAbUDlx/YYPpdPJjtp4fUrCzAEl7fl8Fk8fiGb5CvuZkf/xzC+wdc ckuc9BuxpVJPMr1R5HeGZjLcjfDjz55oYYf2f0Y55hoiDAma3Y85AL5lwaJwpp0q/VVC Vw7k6AHXx/JZk6T4CMRmkhROT/yo9CAIf4qvdTPAgoc7XhobFrVjYnnQ6g7yFbfS2fO8 FoXVL90B6/3iW/p0dTGV8vQV9qX9LzrmPrEp5nwd0YnKmEEskh1zEfn2J95bRqtNgb/1 moDg== Authentication-Results: strato.com; dkim=none X-RZG-AUTH: ":P3gBZUipdd93FF5ZZvYFPugejmSTVR2nRPhVORvLd4SsytBXTbAOHjRHIhr3eFSKSxc=" X-RZG-CLASS-ID: mo00 Received: from droid.. by smtp.strato.de (RZmta 47.33.8 DYNA|AUTH) with ESMTPSA id 301038x8SHLRoBJ (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256 bits)) (Client did not present a certificate); Tue, 28 Sep 2021 19:21:27 +0200 (CEST) From: Stephan Gerhold To: Bjorn Andersson Cc: Andy Gross , linux-arm-msm@vger.kernel.org, Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, Stephan Gerhold Subject: [PATCH 03/15] arm64: dts: qcom: msm8916-samsung-serranove: Add touch key Date: Tue, 28 Sep 2021 19:12:19 +0200 Message-Id: <20210928171231.12766-4-stephan@gerhold.net> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210928171231.12766-1-stephan@gerhold.net> References: <20210928171231.12766-1-stephan@gerhold.net> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the CORERIVER TC360 touch key together with the two necessary fixed regulators for it. Note that for some reason Samsung decided to connect this to GPIOs where no hardware I2C bus is available, so we need to fall back to software bit-banging using i2c-gpio. Signed-off-by: Stephan Gerhold --- .../dts/qcom/msm8916-samsung-serranove.dts | 87 +++++++++++++++++++ 1 file changed, 87 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts index 214a863eedbf..6689687f544f 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts @@ -91,6 +91,32 @@ reg_vdd_tsp: regulator-vdd-tsp { pinctrl-0 = <&tsp_en_default>; }; + reg_touch_key: regulator-touch-key { + compatible = "regulator-fixed"; + regulator-name = "touch_key"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + gpio = <&msmgpio 86 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&tkey_en_default>; + }; + + reg_key_led: regulator-key-led { + compatible = "regulator-fixed"; + regulator-name = "key_led"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&msmgpio 60 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&tkey_led_en_default>; + }; + i2c-muic { compatible = "i2c-gpio"; sda-gpios = <&msmgpio 105 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; @@ -113,6 +139,35 @@ muic: extcon@14 { pinctrl-0 = <&muic_irq_default>; }; }; + + i2c-tkey { + compatible = "i2c-gpio"; + sda-gpios = <&msmgpio 16 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&msmgpio 17 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + + pinctrl-names = "default"; + pinctrl-0 = <&tkey_i2c_default>; + + #address-cells = <1>; + #size-cells = <0>; + + touchkey@20 { + compatible = "coreriver,tc360-touchkey"; + reg = <0x20>; + + interrupt-parent = <&msmgpio>; + interrupts = <98 IRQ_TYPE_EDGE_FALLING>; + + vcc-supply = <®_touch_key>; + vdd-supply = <®_key_led>; + vddio-supply = <&pm8916_l6>; + + linux,keycodes = ; + + pinctrl-names = "default"; + pinctrl-0 = <&tkey_default>; + }; + }; }; &blsp_i2c5 { @@ -333,6 +388,38 @@ muic_irq_default: muic-irq-default { bias-disable; }; + tkey_default: tkey-default { + pins = "gpio98"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + tkey_en_default: tkey-en-default { + pins = "gpio86"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + tkey_i2c_default: tkey-i2c-default { + pins = "gpio16", "gpio17"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + tkey_led_en_default: tkey-led-en-default { + pins = "gpio60"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + tsp_en_default: tsp-en-default { pins = "gpio73"; function = "gpio"; From patchwork Tue Sep 28 17:12:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephan Gerhold X-Patchwork-Id: 12523315 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B3975C4167E for ; Tue, 28 Sep 2021 17:21:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 98BF961246 for ; Tue, 28 Sep 2021 17:21:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241999AbhI1RXU (ORCPT ); Tue, 28 Sep 2021 13:23:20 -0400 Received: from mo4-p02-ob.smtp.rzone.de ([85.215.255.80]:20876 "EHLO mo4-p02-ob.smtp.rzone.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242001AbhI1RXU (ORCPT ); Tue, 28 Sep 2021 13:23:20 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1632849688; s=strato-dkim-0002; d=gerhold.net; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Cc:Date: From:Subject:Sender; bh=3pdZCJIS63omtWAExu94U6iabIKqzus595nFbkYuqE4=; b=jGkVY3bYtXtC6HY8h+xb0PQRMTbzZAC2BbRcCEvmBqIr28PkDbMLh6KjL9lrGpa6go rpmzHofWtvLbme9QhkoZ6ol2TZP7S17s0w8co5X1wyU+rzWDrPPd8szaQn+yts7PfPuq SLVB71tc1suGY0edacSUqalKxTpfFbSCLfYktlm56fMMvlCYM8ESdxxkTD6FjsSqeEaP QZJcB8+01x2U3MRKQar27CHrQKjuID67VZJ9hfpeorkCBFbu+Xw8JdTM4WthnttDRrb+ A5LGtWXk1UyRAGzchWukLxkNw2n8OX117OaL34NRlTwHHgO6k6nEW/NiZVGYxLXb5wIk IC3w== Authentication-Results: strato.com; dkim=none X-RZG-AUTH: ":P3gBZUipdd93FF5ZZvYFPugejmSTVR2nRPhVORvLd4SsytBXTbAOHjRHIhr3eFSKSxc=" X-RZG-CLASS-ID: mo00 Received: from droid.. by smtp.strato.de (RZmta 47.33.8 DYNA|AUTH) with ESMTPSA id 301038x8SHLSoBK (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256 bits)) (Client did not present a certificate); Tue, 28 Sep 2021 19:21:28 +0200 (CEST) From: Stephan Gerhold To: Bjorn Andersson Cc: Andy Gross , linux-arm-msm@vger.kernel.org, Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, Stephan Gerhold Subject: [PATCH 04/15] arm64: dts: qcom: msm8916-samsung-serranove: Add IMU Date: Tue, 28 Sep 2021 19:12:20 +0200 Message-Id: <20210928171231.12766-5-stephan@gerhold.net> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210928171231.12766-1-stephan@gerhold.net> References: <20210928171231.12766-1-stephan@gerhold.net> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the STMicroelectronics LSM6DS3 IMU that is used in the S4 Mini VE to the device tree. Signed-off-by: Stephan Gerhold --- .../dts/qcom/msm8916-samsung-serranove.dts | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts index 6689687f544f..73fe7b2a5b66 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts @@ -170,6 +170,21 @@ touchkey@20 { }; }; +&blsp_i2c2 { + status = "okay"; + + imu@6b { + compatible = "st,lsm6ds3"; + reg = <0x6b>; + + interrupt-parent = <&msmgpio>; + interrupts = <115 IRQ_TYPE_EDGE_RISING>; + + pinctrl-names = "default"; + pinctrl-0 = <&imu_irq_default>; + }; +}; + &blsp_i2c5 { status = "okay"; @@ -372,6 +387,14 @@ gpio_hall_sensor_default: gpio-hall-sensor-default { bias-disable; }; + imu_irq_default: imu-irq-default { + pins = "gpio115"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + muic_i2c_default: muic-i2c-default { pins = "gpio105", "gpio106"; function = "gpio"; From patchwork Tue Sep 28 17:12:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephan Gerhold X-Patchwork-Id: 12523307 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 87E3BC433EF for ; Tue, 28 Sep 2021 17:21:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6AC9A611C6 for ; Tue, 28 Sep 2021 17:21:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242004AbhI1RXS (ORCPT ); Tue, 28 Sep 2021 13:23:18 -0400 Received: from mo4-p02-ob.smtp.rzone.de ([85.215.255.80]:32115 "EHLO mo4-p02-ob.smtp.rzone.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241944AbhI1RXS (ORCPT ); Tue, 28 Sep 2021 13:23:18 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1632849689; s=strato-dkim-0002; d=gerhold.net; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Cc:Date: From:Subject:Sender; bh=KKL6fs65nkhZyVQ8iCMkQHWgC9qX0YJFvu3jOqVLaGs=; b=eoP+qb2py9xxPe6TXKMpKLAyM8LRa8nXhf8jtiHVIJ6MgDTLsszygcxgNME469ZnVO Gd/GikZGjviPmqczJX/amWbGCyVDGAky9eqDbCFu0vh5LjmpvdGO1ExaUEYz3QZ/kjsv Q0zMXrsz3neRSLoZkXHh22oDbKRDIZKoLSuHOoqFIRhn1f6qi9aacYBwsEBF/a0YhRKw DKeZHSE6boHvgTP2tmax8pwLM92uizfS7iYPK+5K3/l1udpIaAkvXKKsJ9YpOFemqv0c PPaeGtGs1J5GKlO/yeifSz6h/JEuBfF1eEhrnRzuE0ce0tpBThj2wFFgwzDTsNJV9yXY Hptw== Authentication-Results: strato.com; dkim=none X-RZG-AUTH: ":P3gBZUipdd93FF5ZZvYFPugejmSTVR2nRPhVORvLd4SsytBXTbAOHjRHIhr3eFSKSxc=" X-RZG-CLASS-ID: mo00 Received: from droid.. by smtp.strato.de (RZmta 47.33.8 DYNA|AUTH) with ESMTPSA id 301038x8SHLSoBL (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256 bits)) (Client did not present a certificate); Tue, 28 Sep 2021 19:21:28 +0200 (CEST) From: Stephan Gerhold To: Bjorn Andersson Cc: Andy Gross , linux-arm-msm@vger.kernel.org, Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, Stephan Gerhold Subject: [PATCH 05/15] arm64: dts: qcom: msm8916-samsung-serranove: Add rt5033 battery Date: Tue, 28 Sep 2021 19:12:21 +0200 Message-Id: <20210928171231.12766-6-stephan@gerhold.net> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210928171231.12766-1-stephan@gerhold.net> References: <20210928171231.12766-1-stephan@gerhold.net> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Like the Samsung Galaxy A3/A5, the S4 Mini VE uses a Richtek RT5033 PMIC as battery fuel gauge, charger, flash LED and for some regulators. For now, only add the fuel gauge/battery device to the device tree, so we can check the remaining battery percentage. The other RT5033 drivers need some more work first before they can be used properly. Signed-off-by: Stephan Gerhold --- .../dts/qcom/msm8916-samsung-serranove.dts | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts index 73fe7b2a5b66..4a94158e7624 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts @@ -185,6 +185,21 @@ imu@6b { }; }; +&blsp_i2c4 { + status = "okay"; + + battery@35 { + compatible = "richtek,rt5033-battery"; + reg = <0x35>; + + interrupt-parent = <&msmgpio>; + interrupts = <121 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-names = "default"; + pinctrl-0 = <&fg_alert_default>; + }; +}; + &blsp_i2c5 { status = "okay"; @@ -371,6 +386,14 @@ l18 { }; &msmgpio { + fg_alert_default: fg-alert-default { + pins = "gpio121"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + gpio_keys_default: gpio-keys-default { pins = "gpio107", "gpio109"; function = "gpio"; From patchwork Tue Sep 28 17:12:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephan Gerhold X-Patchwork-Id: 12523313 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 657DBC433EF for ; Tue, 28 Sep 2021 17:21:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4CAD56124A for ; Tue, 28 Sep 2021 17:21:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241952AbhI1RXU (ORCPT ); Tue, 28 Sep 2021 13:23:20 -0400 Received: from mo4-p02-ob.smtp.rzone.de ([85.215.255.81]:27835 "EHLO mo4-p02-ob.smtp.rzone.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241999AbhI1RXS (ORCPT ); Tue, 28 Sep 2021 13:23:18 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1632849690; s=strato-dkim-0002; d=gerhold.net; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Cc:Date: From:Subject:Sender; bh=s1FlzWcDA9eIJrOyiRw4JBchPVmZGKUUzVFj052hZhY=; b=IaB2aZ7mLbEY0bKzptvW8aixsRWfKnX3Dq3a4fWEPIkubu0OGbDirsweGGc9rm8cZ/ eZ/b3HxPvrLms2PO55qMnz51p1HP1ivcsf++O9jdrwtpUjCsaT9kHVTUw7Gtr6b9Xe1y 0dHRMJCkleugTaJc+2yGPUMx8ggmntVazKl60vkZaIZBRdfAkterIwhDDt4zLIOl7BxP AOkPjFW70ZaJDY2v8wWC92XHfLovDW0g+9AlxJtRRkL65rarTKh0RCPdYFrmATmstPEY AqfLP+j1ZHuIwEY0hU9aOZRDdWD6/crAJ6x7yaT/0Xo02ZHjXjslsQSTXwbATw3RT/Mu sCVg== Authentication-Results: strato.com; dkim=none X-RZG-AUTH: ":P3gBZUipdd93FF5ZZvYFPugejmSTVR2nRPhVORvLd4SsytBXTbAOHjRHIhr3eFSKSxc=" X-RZG-CLASS-ID: mo00 Received: from droid.. by smtp.strato.de (RZmta 47.33.8 DYNA|AUTH) with ESMTPSA id 301038x8SHLToBM (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256 bits)) (Client did not present a certificate); Tue, 28 Sep 2021 19:21:29 +0200 (CEST) From: Stephan Gerhold To: Bjorn Andersson Cc: Andy Gross , linux-arm-msm@vger.kernel.org, Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, Stephan Gerhold Subject: [PATCH 06/15] arm64: dts: qcom: msm8916-samsung-serranove: Add NFC Date: Tue, 28 Sep 2021 19:12:22 +0200 Message-Id: <20210928171231.12766-7-stephan@gerhold.net> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210928171231.12766-1-stephan@gerhold.net> References: <20210928171231.12766-1-stephan@gerhold.net> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The LTE version of the S4 Mini VE has a NXP PN547, which is supported by the nxp-nci-i2c driver in mainline. It seems to detect NFC tags using "nfctool" just fine, although more testing is difficult given there seem to be very few useful applications making use of the Linux NFC subsystem. :( Note that for some reason Samsung decided to connect the I2C pins to GPIOs where no hardware I2C bus is available, so we need to fall back to software bit-banging with i2c-gpio. Signed-off-by: Stephan Gerhold --- .../dts/qcom/msm8916-samsung-serranove.dts | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts index 4a94158e7624..caeed942a4c5 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts @@ -168,6 +168,32 @@ touchkey@20 { pinctrl-0 = <&tkey_default>; }; }; + + i2c-nfc { + compatible = "i2c-gpio"; + sda-gpios = <&msmgpio 0 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&msmgpio 1 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + + pinctrl-names = "default"; + pinctrl-0 = <&nfc_i2c_default>; + + #address-cells = <1>; + #size-cells = <0>; + + nfc@2b { + compatible = "nxp,pn547", "nxp,nxp-nci-i2c"; + reg = <0x2b>; + + interrupt-parent = <&msmgpio>; + interrupts = <21 IRQ_TYPE_EDGE_RISING>; + + enable-gpios = <&msmgpio 20 GPIO_ACTIVE_HIGH>; + firmware-gpios = <&msmgpio 49 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&nfc_default>; + }; + }; }; &blsp_i2c2 { @@ -434,6 +460,30 @@ muic_irq_default: muic-irq-default { bias-disable; }; + nfc_default: nfc-default { + pins = "gpio20", "gpio49"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + + irq { + pins = "gpio21"; + function = "gpio"; + + drive-strength = <2>; + bias-pull-down; + }; + }; + + nfc_i2c_default: nfc-i2c-default { + pins = "gpio0", "gpio1"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + tkey_default: tkey-default { pins = "gpio98"; function = "gpio"; From patchwork Tue Sep 28 17:12:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephan Gerhold X-Patchwork-Id: 12523311 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4ACBEC43219 for ; Tue, 28 Sep 2021 17:21:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3693361372 for ; Tue, 28 Sep 2021 17:21:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242029AbhI1RXT (ORCPT ); Tue, 28 Sep 2021 13:23:19 -0400 Received: from mo4-p02-ob.smtp.rzone.de ([81.169.146.168]:9000 "EHLO mo4-p02-ob.smtp.rzone.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241997AbhI1RXS (ORCPT ); Tue, 28 Sep 2021 13:23:18 -0400 X-Greylist: delayed 21036 seconds by postgrey-1.27 at vger.kernel.org; Tue, 28 Sep 2021 13:23:17 EDT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1632849690; s=strato-dkim-0002; d=gerhold.net; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Cc:Date: From:Subject:Sender; bh=ahq0OJq7JAJNssL5upRLs89oI17gIphySqvW7pf3FXo=; b=G+oY7swVr3wmnFaSRpDlhe0CojjZK1gfCbejHpE5NLDMhY6BsqeoqwLD5BBR2gmmYP 8WqEPPNCFFGNOglLLNFJVK9jt/eOnE3sVTAD466dkmFLxwt7mYzI+H3hdzQUc3wkrs8y 9fW1x6qGv4PxjNtHJ1rA8dz4t8Dib0OzN8fRoiI4NBlH6fN2Gk4ByWOEHkVoVRmPajIC lmnwpbp6R+cSEOJagwz01HwkleT71Bx32dy4AkqgWk7BraKqOGp96IgzzpOeBWZ6lyYQ 1vcSrnRoKC8Pkn1O9drt7cdfjPHawlM/3/RSic7R6mwnNGEzDw0g7ixfY3v6shW5Gf0c QpRA== Authentication-Results: strato.com; dkim=none X-RZG-AUTH: ":P3gBZUipdd93FF5ZZvYFPugejmSTVR2nRPhVORvLd4SsytBXTbAOHjRHIhr3eFSKSxc=" X-RZG-CLASS-ID: mo00 Received: from droid.. by smtp.strato.de (RZmta 47.33.8 DYNA|AUTH) with ESMTPSA id 301038x8SHLUoBN (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256 bits)) (Client did not present a certificate); Tue, 28 Sep 2021 19:21:30 +0200 (CEST) From: Stephan Gerhold To: Bjorn Andersson Cc: Andy Gross , linux-arm-msm@vger.kernel.org, Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, Stephan Gerhold Subject: [PATCH 07/15] ARM: qcom: Add ARCH_MSM8916 for MSM8916 on ARM32 Date: Tue, 28 Sep 2021 19:12:23 +0200 Message-Id: <20210928171231.12766-8-stephan@gerhold.net> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210928171231.12766-1-stephan@gerhold.net> References: <20210928171231.12766-1-stephan@gerhold.net> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add a CONFIG_ARCH_MSM8916 option to enable building MSM8916 support on ARM32. Note that since ARM64 is the main supported architecture for MSM8916 this is only intended for testing and for devices where (signed) outdated firmware does not support booting ARM64 kernels. Signed-off-by: Stephan Gerhold --- arch/arm/mach-qcom/Kconfig | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/mach-qcom/Kconfig b/arch/arm/mach-qcom/Kconfig index 1772eccb5caf..4ef3acd2448c 100644 --- a/arch/arm/mach-qcom/Kconfig +++ b/arch/arm/mach-qcom/Kconfig @@ -21,6 +21,16 @@ config ARCH_MSM8X60 bool "Enable support for MSM8X60" select CLKSRC_QCOM +config ARCH_MSM8916 + bool "Enable support for MSM8916" + select HAVE_ARM_ARCH_TIMER + help + Enable support for the Qualcomm Snapdragon 410 (MSM8916/APQ8016). + + Note that ARM64 is the main supported architecture for MSM8916. + The ARM32 option is intended for a few devices with outdated (signed) + firmware that does not allow booting ARM64 kernels. + config ARCH_MSM8960 bool "Enable support for MSM8960" select CLKSRC_QCOM From patchwork Tue Sep 28 17:12:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephan Gerhold X-Patchwork-Id: 12523319 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6384FC4332F for ; Tue, 28 Sep 2021 17:21:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4B57F6128B for ; Tue, 28 Sep 2021 17:21:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242043AbhI1RXV (ORCPT ); Tue, 28 Sep 2021 13:23:21 -0400 Received: from mo4-p02-ob.smtp.rzone.de ([81.169.146.169]:19514 "EHLO mo4-p02-ob.smtp.rzone.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242008AbhI1RXU (ORCPT ); Tue, 28 Sep 2021 13:23:20 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1632849691; s=strato-dkim-0002; d=gerhold.net; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Cc:Date: From:Subject:Sender; bh=y4uOiDAp8t62rZRNRmbMQrHAwdutrhAvadGOkgVUDtw=; b=pRTrCqvEdkOi6IpvFoxV+NVs4P7tnTwLDyF1DaAqF5wuSRkG8sUIga8+fJcMdc/ZIQ 7A2RKdKlyI6da/++ZO3wKP6zCgZCAXkNYk0VEWO0n4PnggiTRKug1mm/5QF2K4kAo2bH Z0vTa7VoKBgxFl1rzGlq07j6Zt05l2y7u0Y5lpOmCzFCwSYx1olswlSrh4Q6R3SPPRIy yAVZEunMjKKbTKs9LTR5xEfijF2m49dOMFfAyOS2kZzMZBP8S7vvZpfDG7Zo46k2CK/i CHOyggo+z8MKPJXY4a5N7p/RsmKFSUfkb+MR9xy9N/yN53AyVDzRPWFYn5jtG0A90Jrh Nbqg== Authentication-Results: strato.com; dkim=none X-RZG-AUTH: ":P3gBZUipdd93FF5ZZvYFPugejmSTVR2nRPhVORvLd4SsytBXTbAOHjRHIhr3eFSKSxc=" X-RZG-CLASS-ID: mo00 Received: from droid.. by smtp.strato.de (RZmta 47.33.8 DYNA|AUTH) with ESMTPSA id 301038x8SHLUoBO (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256 bits)) (Client did not present a certificate); Tue, 28 Sep 2021 19:21:30 +0200 (CEST) From: Stephan Gerhold To: Bjorn Andersson Cc: Andy Gross , linux-arm-msm@vger.kernel.org, Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, Stephan Gerhold Subject: [PATCH 08/15] dt-bindings: arm: cpus: Document qcom,msm8916-smp enable-method Date: Tue, 28 Sep 2021 19:12:24 +0200 Message-Id: <20210928171231.12766-9-stephan@gerhold.net> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210928171231.12766-1-stephan@gerhold.net> References: <20210928171231.12766-1-stephan@gerhold.net> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Document the qcom,msm8916-smp enable method. It is actually just an alias for qcom,msm8226-smp since it should be implemented identically. Signed-off-by: Stephan Gerhold --- Documentation/devicetree/bindings/arm/cpus.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index 11e3e09da2e5..5602a8f3c513 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -211,6 +211,7 @@ properties: - qcom,kpss-acc-v1 - qcom,kpss-acc-v2 - qcom,msm8226-smp + - qcom,msm8916-smp - renesas,apmu - renesas,r9a06g032-smp - rockchip,rk3036-smp @@ -295,7 +296,8 @@ properties: Specifies the ACC* node associated with this CPU. Required for systems that have an "enable-method" property - value of "qcom,kpss-acc-v1", "qcom,kpss-acc-v2" or "qcom,msm8226-smp" + value of "qcom,kpss-acc-v1", "qcom,kpss-acc-v2", "qcom,msm8226-smp" + or "qcom,msm8916-smp". * arm/msm/qcom,kpss-acc.txt From patchwork Tue Sep 28 17:12:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephan Gerhold X-Patchwork-Id: 12523323 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C8460C433EF for ; Tue, 28 Sep 2021 17:21:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B1A7D611C6 for ; Tue, 28 Sep 2021 17:21:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242019AbhI1RXa (ORCPT ); Tue, 28 Sep 2021 13:23:30 -0400 Received: from mo4-p03-ob.smtp.rzone.de ([81.169.146.173]:25450 "EHLO mo4-p03-ob.smtp.rzone.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242000AbhI1RXa (ORCPT ); Tue, 28 Sep 2021 13:23:30 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1632849691; s=strato-dkim-0002; d=gerhold.net; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Cc:Date: From:Subject:Sender; bh=+lHs//hdp8drmhyzzqs+02GJRw3C/ibC5yhs46Irwmw=; b=aJTQri0Mi+41n3gBQvP34y/ARHAUpME5v+18gH/Ypvtph3LZ+ZpawRDxXy2qiC5sxt 2JP6Rgw538BG9lAjeXE9ZjwJuBokYJX1aDtm1eklmkLN28aHhBelEX/2xl3ZmxFyjl/q JSAtvVvGgNg1efddkupvMLR+hQM99Irkct4hrFhUxpp0UiRQ7t3zWEdkQVI5aq0bz6TB btCwnNvLgRF50AGjP6ju4bEQqRkIUXj2HYhAMY97d1c1rnnOExnwTgrPbsdRuayygcfI 3O2iNHr4yKFUK4SWTbOojEI0DVDJdc9J4F8q+sHEGrUNMck6HDX6YKA7P6ahTqXbEBAY cPFg== Authentication-Results: strato.com; dkim=none X-RZG-AUTH: ":P3gBZUipdd93FF5ZZvYFPugejmSTVR2nRPhVORvLd4SsytBXTbAOHjRHIhr3eFSKSxc=" X-RZG-CLASS-ID: mo00 Received: from droid.. by smtp.strato.de (RZmta 47.33.8 DYNA|AUTH) with ESMTPSA id 301038x8SHLVoBP (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256 bits)) (Client did not present a certificate); Tue, 28 Sep 2021 19:21:31 +0200 (CEST) From: Stephan Gerhold To: Bjorn Andersson Cc: Andy Gross , linux-arm-msm@vger.kernel.org, Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, Stephan Gerhold Subject: [PATCH 09/15] ARM: qcom: Add qcom,msm8916-smp enable-method identical to MSM8226 Date: Tue, 28 Sep 2021 19:12:25 +0200 Message-Id: <20210928171231.12766-10-stephan@gerhold.net> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210928171231.12766-1-stephan@gerhold.net> References: <20210928171231.12766-1-stephan@gerhold.net> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Some MSM8916 devices have outdated (signed) firmware without PSCI and ARM64 support and can therefore only boot ARM32 Linux. The ARM Cortex-A53 cores should be actually booted exactly like the Cortex-A7 cores on MSM8226, so just add an alias for the existing code. Signed-off-by: Stephan Gerhold --- arch/arm/mach-qcom/platsmp.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-qcom/platsmp.c b/arch/arm/mach-qcom/platsmp.c index 60496554c6dd..58a4228455ce 100644 --- a/arch/arm/mach-qcom/platsmp.c +++ b/arch/arm/mach-qcom/platsmp.c @@ -385,6 +385,7 @@ static const struct smp_operations qcom_smp_cortex_a7_ops __initconst = { #endif }; CPU_METHOD_OF_DECLARE(qcom_smp_msm8226, "qcom,msm8226-smp", &qcom_smp_cortex_a7_ops); +CPU_METHOD_OF_DECLARE(qcom_smp_msm8916, "qcom,msm8916-smp", &qcom_smp_cortex_a7_ops); static const struct smp_operations qcom_smp_kpssv1_ops __initconst = { .smp_prepare_cpus = qcom_smp_prepare_cpus, From patchwork Tue Sep 28 17:12:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephan Gerhold X-Patchwork-Id: 12523325 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 37BBAC433FE for ; Tue, 28 Sep 2021 17:21:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2251C611C6 for ; Tue, 28 Sep 2021 17:21:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242034AbhI1RXa (ORCPT ); Tue, 28 Sep 2021 13:23:30 -0400 Received: from mo4-p03-ob.smtp.rzone.de ([85.215.255.104]:22026 "EHLO mo4-p03-ob.smtp.rzone.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242015AbhI1RXa (ORCPT ); Tue, 28 Sep 2021 13:23:30 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1632849692; s=strato-dkim-0002; d=gerhold.net; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Cc:Date: From:Subject:Sender; bh=SVUrBCI7UYa2hA+1oVubm58FINBZ1hT8WY6HZHT9k8I=; b=VlEMZBfdcoExr+1qWRjrXd74JVTNIQvH2Cz9NgaURTuIVP1+c7+50ba+33vOga3Sdz LDicNQ0e3JEglvOvR+amk6x1h9lXGpmWr9XerVMYqiRqG9lAmF4yJsnQuU6R3RtW9//m llnuqkd/57ayIXeyvq+wTUp9Ovo/ap71rrlkMFj4+cUkiix5tYmsXfmfKjcWPfyq4/KK OXyCpS2agY8tl/UEzyuD/utX75eWN13VhMCD3CS4ckJtN61jTTcwW1nM6HR6dd+JtA+h ef6qVCROUcNHsOi81cWXHbuF8nD3SIfYqlJHLG5D1NHLbXuZ4R/u9pW1rbx+sqARUOWU N0Ew== Authentication-Results: strato.com; dkim=none X-RZG-AUTH: ":P3gBZUipdd93FF5ZZvYFPugejmSTVR2nRPhVORvLd4SsytBXTbAOHjRHIhr3eFSKSxc=" X-RZG-CLASS-ID: mo00 Received: from droid.. by smtp.strato.de (RZmta 47.33.8 DYNA|AUTH) with ESMTPSA id 301038x8SHLVoBQ (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256 bits)) (Client did not present a certificate); Tue, 28 Sep 2021 19:21:31 +0200 (CEST) From: Stephan Gerhold To: Bjorn Andersson Cc: Andy Gross , linux-arm-msm@vger.kernel.org, Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, Stephan Gerhold Subject: [PATCH 10/15] dt-bindings: soc: qcom: spm: Document qcom,msm8916-saw2-v3.0-cpu Date: Tue, 28 Sep 2021 19:12:26 +0200 Message-Id: <20210928171231.12766-11-stephan@gerhold.net> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210928171231.12766-1-stephan@gerhold.net> References: <20210928171231.12766-1-stephan@gerhold.net> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Document the qcom,msm8916-saw2-v3.0-cpu compatible that is needed for cpuidle for MSM8916 on some devices with outdated (signed) firmware which is only capable of booting ARM32 kernels without PSCI. Signed-off-by: Stephan Gerhold Acked-by: Rob Herring --- Documentation/devicetree/bindings/soc/qcom/qcom,spm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,spm.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,spm.yaml index d68c002527fa..07d2d5398345 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,spm.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,spm.yaml @@ -22,6 +22,7 @@ properties: - qcom,sdm660-silver-saw2-v4.1-l2 - qcom,msm8998-gold-saw2-v4.1-l2 - qcom,msm8998-silver-saw2-v4.1-l2 + - qcom,msm8916-saw2-v3.0-cpu - qcom,msm8226-saw2-v2.1-cpu - qcom,msm8974-saw2-v2.1-cpu - qcom,apq8084-saw2-v2.1-cpu From patchwork Tue Sep 28 17:12:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephan Gerhold X-Patchwork-Id: 12523329 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CEFFAC4167B for ; Tue, 28 Sep 2021 17:21:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AEB4B6135F for ; Tue, 28 Sep 2021 17:21:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242036AbhI1RXb (ORCPT ); Tue, 28 Sep 2021 13:23:31 -0400 Received: from mo4-p03-ob.smtp.rzone.de ([85.215.255.100]:35553 "EHLO mo4-p03-ob.smtp.rzone.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242018AbhI1RXa (ORCPT ); Tue, 28 Sep 2021 13:23:30 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1632849692; s=strato-dkim-0002; d=gerhold.net; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Cc:Date: From:Subject:Sender; bh=G71mCTmQCHMhCU8D4JXvI4Tc2hKHBlUFMgU3lkDk7oA=; b=JFiWW5780Qe2X1KIcOLdfUHYEI3uW9LF8uNVzYt5JYRz89B0rRQO/UTilwGZPhBvgt VdRD7EMcxhLr5lix3+QtUarNvW+oe61KUHvNKY4MACbS3C05Jo33A/ViOI3G6mwLw+/0 ZzPbNYY7e/zOVd9EqDDMj8xY3NESVGStS0Wvqny+YGEmBNsdG5Snlx4jL1tdjsBV+tUC NlJi6WODAHi8epASjCmqgCUot1YnuihYX/tIyX3zU35g8f53xFlI1qHIcTGGRwLwgpsB XMU9rQgjoemhsbO5uaGvh0UOvUexKnX8VIkwcyjGg5j/TPB9Kc8VWfq19nUC82MJT2qC Q5lA== Authentication-Results: strato.com; dkim=none X-RZG-AUTH: ":P3gBZUipdd93FF5ZZvYFPugejmSTVR2nRPhVORvLd4SsytBXTbAOHjRHIhr3eFSKSxc=" X-RZG-CLASS-ID: mo00 Received: from droid.. by smtp.strato.de (RZmta 47.33.8 DYNA|AUTH) with ESMTPSA id 301038x8SHLWoBR (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256 bits)) (Client did not present a certificate); Tue, 28 Sep 2021 19:21:32 +0200 (CEST) From: Stephan Gerhold To: Bjorn Andersson Cc: Andy Gross , linux-arm-msm@vger.kernel.org, Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, Stephan Gerhold Subject: [PATCH 11/15] soc: qcom: spm: Add 8916 SPM register data Date: Tue, 28 Sep 2021 19:12:27 +0200 Message-Id: <20210928171231.12766-12-stephan@gerhold.net> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210928171231.12766-1-stephan@gerhold.net> References: <20210928171231.12766-1-stephan@gerhold.net> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Lina Iyer Add SPM register information and initialization values for QCOM 8916 SoC. Link: https://lore.kernel.org/linux-arm-msm/1429314549-6730-5-git-send-email-lina.iyer@linaro.org/ Signed-off-by: Lina Iyer [stephan: rebase patch and fix conflicts] Signed-off-by: Stephan Gerhold --- Like for qcom,msm8916-smp and qcom,msm8226-smp, this is actually pretty much identical to the MSM8226 configuration except for the new v3.0 register offsets. --- drivers/soc/qcom/spm.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/soc/qcom/spm.c b/drivers/soc/qcom/spm.c index 2961a89d929c..f831420b7fd4 100644 --- a/drivers/soc/qcom/spm.c +++ b/drivers/soc/qcom/spm.c @@ -67,6 +67,25 @@ static const struct spm_reg_data spm_reg_8998_silver_l2 = { .avs_limit = 0x4200420, }; +static const u16 spm_reg_offset_v3_0[SPM_REG_NR] = { + [SPM_REG_CFG] = 0x08, + [SPM_REG_SPM_CTL] = 0x30, + [SPM_REG_DLY] = 0x34, + [SPM_REG_SEQ_ENTRY] = 0x400, +}; + +/* SPM register data for 8916 */ +static const struct spm_reg_data spm_reg_8916_cpu = { + .reg_offset = spm_reg_offset_v3_0, + .spm_cfg = 0x1, + .spm_dly = 0x3C102800, + .seq = { 0x60, 0x03, 0x60, 0x0B, 0x0F, 0x20, 0x10, 0x80, 0x30, 0x90, + 0x5B, 0x60, 0x03, 0x60, 0x3B, 0x76, 0x76, 0x0B, 0x94, 0x5B, + 0x80, 0x10, 0x26, 0x30, 0x0F }, + .start_index[PM_SLEEP_MODE_STBY] = 0, + .start_index[PM_SLEEP_MODE_SPC] = 5, +}; + static const u16 spm_reg_offset_v2_1[SPM_REG_NR] = { [SPM_REG_CFG] = 0x08, [SPM_REG_SPM_CTL] = 0x30, @@ -176,6 +195,8 @@ static const struct of_device_id spm_match_table[] = { .data = &spm_reg_660_silver_l2 }, { .compatible = "qcom,msm8226-saw2-v2.1-cpu", .data = &spm_reg_8226_cpu }, + { .compatible = "qcom,msm8916-saw2-v3.0-cpu", + .data = &spm_reg_8916_cpu }, { .compatible = "qcom,msm8974-saw2-v2.1-cpu", .data = &spm_reg_8974_8084_cpu }, { .compatible = "qcom,msm8998-gold-saw2-v4.1-l2", From patchwork Tue Sep 28 17:12:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephan Gerhold X-Patchwork-Id: 12523331 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 32F88C4167E for ; Tue, 28 Sep 2021 17:21:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1B4736124A for ; Tue, 28 Sep 2021 17:21:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242018AbhI1RXb (ORCPT ); Tue, 28 Sep 2021 13:23:31 -0400 Received: from mo4-p03-ob.smtp.rzone.de ([85.215.255.103]:11275 "EHLO mo4-p03-ob.smtp.rzone.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242038AbhI1RXa (ORCPT ); Tue, 28 Sep 2021 13:23:30 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1632849693; s=strato-dkim-0002; d=gerhold.net; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Cc:Date: From:Subject:Sender; bh=o4Q7h3nlJh+ewylmQwaOalfO3Z+o27th5G6cQThPmpY=; b=BiEwryFYQs/G+p4x8H6eQcAlAuqe5/b+rJbECoM16hoI5NSYlSB+n8C6A6a1YOyP2t 4rzI0srh2IMplX9KmFaPSMNut+qmnqkE0R1ENFFSaHp3/h67uHwhtPb55hsjgRJN7XwQ ttxkn2y2RXVypAQMP1j1KvutSCBOkhHRRPD5f0G2JsjiVZWP76Giueo9Bsqq/R9gV6As PjOjJ6E1Rz5UuZGVqaGR+/RIn8PANitpMKQyIzsaPK4B4YwOwvsVHgHBPrbbpp5KVi5o ZQ3XHIsQ/BbQNgvME+mRUWKb+ED6KHgkqd/lirCtNfmurR6T2Ppl3CPK9FSfkH11DuaC 48WA== Authentication-Results: strato.com; dkim=none X-RZG-AUTH: ":P3gBZUipdd93FF5ZZvYFPugejmSTVR2nRPhVORvLd4SsytBXTbAOHjRHIhr3eFSKSxc=" X-RZG-CLASS-ID: mo00 Received: from droid.. by smtp.strato.de (RZmta 47.33.8 DYNA|AUTH) with ESMTPSA id 301038x8SHLWoBS (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256 bits)) (Client did not present a certificate); Tue, 28 Sep 2021 19:21:32 +0200 (CEST) From: Stephan Gerhold To: Bjorn Andersson Cc: Andy Gross , linux-arm-msm@vger.kernel.org, Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, Stephan Gerhold Subject: [PATCH 12/15] firmware: qcom: scm: Add support for MC boot address API Date: Tue, 28 Sep 2021 19:12:28 +0200 Message-Id: <20210928171231.12766-13-stephan@gerhold.net> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210928171231.12766-1-stephan@gerhold.net> References: <20210928171231.12766-1-stephan@gerhold.net> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org It looks like the old QCOM_SCM_BOOT_SET_ADDR API is broken on some MSM8916 firmware versions that implement the newer SMC32 calling convention. It just returns -EINVAL no matter which arguments are being passed. This does not cause any problems downstream because it first tries to use the new multi-cluster API replacement which is working fine. Implement support for the multi-cluster variant of the SCM call by attempting it first but still fallback to the old call in case of an error. Also, to be absolutely sure only use the multi-cluster variant with the SMC calling convention since older platforms should not need this. Signed-off-by: Stephan Gerhold --- The diff generated by Git is a bit hard to read sadly, what I did essentially is: 1. Add __qcom_scm_set_boot_addr_mc() 2. Rename original qcom_scm_set_cold/warm_boot_addr() to static __qcom_scm_set_cold/warm_boot_addr() 3. Make new qcom_scm_set_cold/warm_boot_addr() call __qcom_scm_set_boot_addr_mc() first and then fall back to the old __qcom_scm_set_cold/warm_boot_addr() as before --- drivers/firmware/qcom_scm.c | 84 +++++++++++++++++++++++++++++-------- drivers/firmware/qcom_scm.h | 4 ++ 2 files changed, 71 insertions(+), 17 deletions(-) diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c index a861033616ee..75506a1bbcfc 100644 --- a/drivers/firmware/qcom_scm.c +++ b/drivers/firmware/qcom_scm.c @@ -17,6 +17,8 @@ #include #include +#include + #include "qcom_scm.h" static bool download_mode = IS_ENABLED(CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT); @@ -260,15 +262,36 @@ static bool __qcom_scm_is_call_available(struct device *dev, u32 svc_id, return ret ? false : !!res.result[0]; } -/** - * qcom_scm_set_warm_boot_addr() - Set the warm boot address for cpus - * @entry: Entry point function for the cpus - * @cpus: The cpumask of cpus that will use the entry point - * - * Set the Linux entry point for the SCM to transfer control to when coming - * out of a power down. CPU power down may be executed on cpuidle or hotplug. - */ -int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus) +static int __qcom_scm_set_boot_addr_mc(void *entry, const cpumask_t *cpus, + unsigned int flags) +{ + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_BOOT, + .cmd = QCOM_SCM_BOOT_SET_ADDR_MC, + .owner = ARM_SMCCC_OWNER_SIP, + .arginfo = QCOM_SCM_ARGS(6), + }; + unsigned int cpu; + u64 map; + + /* Need a device for DMA of the additional arguments */ + if (!__scm || __get_convention() == SMC_CONVENTION_LEGACY) + return -EOPNOTSUPP; + + desc.args[0] = virt_to_phys(entry); + for_each_cpu(cpu, cpus) { + map = cpu_logical_map(cpu); + desc.args[1] |= BIT(MPIDR_AFFINITY_LEVEL(map, 0)); + desc.args[2] |= BIT(MPIDR_AFFINITY_LEVEL(map, 1)); + desc.args[3] |= BIT(MPIDR_AFFINITY_LEVEL(map, 2)); + } + desc.args[4] = ~0ULL; /* Reserved for affinity level 3 */ + desc.args[5] = flags; + + return qcom_scm_call(__scm->dev, &desc, NULL); +} + +static int __qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus) { int ret; int flags = 0; @@ -304,17 +327,28 @@ int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus) return ret; } -EXPORT_SYMBOL(qcom_scm_set_warm_boot_addr); /** - * qcom_scm_set_cold_boot_addr() - Set the cold boot address for cpus + * qcom_scm_set_warm_boot_addr() - Set the warm boot address for cpus * @entry: Entry point function for the cpus * @cpus: The cpumask of cpus that will use the entry point * - * Set the cold boot address of the cpus. Any cpu outside the supported - * range would be removed from the cpu present mask. + * Set the Linux entry point for the SCM to transfer control to when coming + * out of a power down. CPU power down may be executed on cpuidle or hotplug. */ -int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus) +int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus) +{ + if (!cpus || cpumask_empty(cpus)) + return -EINVAL; + + if (__qcom_scm_set_boot_addr_mc(entry, cpus, QCOM_SCM_BOOT_MC_FLAG_WARMBOOT)) + /* Fallback to old SCM call */ + return __qcom_scm_set_warm_boot_addr(entry, cpus); + return 0; +} +EXPORT_SYMBOL(qcom_scm_set_warm_boot_addr); + +static int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus) { int flags = 0; int cpu; @@ -331,9 +365,6 @@ int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus) .owner = ARM_SMCCC_OWNER_SIP, }; - if (!cpus || cpumask_empty(cpus)) - return -EINVAL; - for_each_cpu(cpu, cpus) { if (cpu < ARRAY_SIZE(scm_cb_flags)) flags |= scm_cb_flags[cpu]; @@ -346,6 +377,25 @@ int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus) return qcom_scm_call_atomic(__scm ? __scm->dev : NULL, &desc, NULL); } + +/** + * qcom_scm_set_cold_boot_addr() - Set the cold boot address for cpus + * @entry: Entry point function for the cpus + * @cpus: The cpumask of cpus that will use the entry point + * + * Set the cold boot address of the cpus. Any cpu outside the supported + * range would be removed from the cpu present mask. + */ +int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus) +{ + if (!cpus || cpumask_empty(cpus)) + return -EINVAL; + + if (__qcom_scm_set_boot_addr_mc(entry, cpus, QCOM_SCM_BOOT_MC_FLAG_COLDBOOT)) + /* Fallback to old SCM call */ + return __qcom_scm_set_cold_boot_addr(entry, cpus); + return 0; +} EXPORT_SYMBOL(qcom_scm_set_cold_boot_addr); /** diff --git a/drivers/firmware/qcom_scm.h b/drivers/firmware/qcom_scm.h index d92156ceb3ac..2a6a87b75231 100644 --- a/drivers/firmware/qcom_scm.h +++ b/drivers/firmware/qcom_scm.h @@ -78,8 +78,12 @@ extern int scm_legacy_call(struct device *dev, const struct qcom_scm_desc *desc, #define QCOM_SCM_BOOT_SET_ADDR 0x01 #define QCOM_SCM_BOOT_TERMINATE_PC 0x02 #define QCOM_SCM_BOOT_SET_DLOAD_MODE 0x10 +#define QCOM_SCM_BOOT_SET_ADDR_MC 0x11 #define QCOM_SCM_BOOT_SET_REMOTE_STATE 0x0a #define QCOM_SCM_FLUSH_FLAG_MASK 0x3 +#define QCOM_SCM_BOOT_MC_FLAG_AARCH64 BIT(0) +#define QCOM_SCM_BOOT_MC_FLAG_COLDBOOT BIT(1) +#define QCOM_SCM_BOOT_MC_FLAG_WARMBOOT BIT(2) #define QCOM_SCM_SVC_PIL 0x02 #define QCOM_SCM_PIL_PAS_INIT_IMAGE 0x01 From patchwork Tue Sep 28 17:12:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephan Gerhold X-Patchwork-Id: 12523327 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9C818C43217 for ; Tue, 28 Sep 2021 17:21:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8460961246 for ; Tue, 28 Sep 2021 17:21:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242015AbhI1RXb (ORCPT ); Tue, 28 Sep 2021 13:23:31 -0400 Received: from mo4-p03-ob.smtp.rzone.de ([81.169.146.172]:20403 "EHLO mo4-p03-ob.smtp.rzone.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242037AbhI1RXa (ORCPT ); Tue, 28 Sep 2021 13:23:30 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1632849694; s=strato-dkim-0002; d=gerhold.net; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Cc:Date: From:Subject:Sender; bh=QIw47FLLOn+KBvt/FSo5366cnFJ0U/sATIyQvR+hj6A=; b=gHybHLPlfgeQOSeTFmeXuSovzAuGM70olxrksdve0r2dI8u7I6BpBZxOo2lXfWyF0k n7wWX9U5Y3SmkK53I5dUMxaSfQzoU2gJa2+NVC0y3kxxYATLp+YwwX5/JHiQcu2lFlMN Ige+Hl9xcfpdEXZP7p0OtuXXl4CDKsCLUjD56iOXHe+PIxOcl0eOdIbUiuF3r/0mPu7S pEKi66QMlFIKzfQMOjVavcSLYXcpidKuifYv6KwRbW/woijTn0UZqyedXkqs5i/fPhVz p5Ts+6jgq1xsqlFg2w/GpRb78VTFAh85zU4wBY2A2/C/pb/+gsK2PphyQSelvSyrlc8x BX/A== Authentication-Results: strato.com; dkim=none X-RZG-AUTH: ":P3gBZUipdd93FF5ZZvYFPugejmSTVR2nRPhVORvLd4SsytBXTbAOHjRHIhr3eFSKSxc=" X-RZG-CLASS-ID: mo00 Received: from droid.. by smtp.strato.de (RZmta 47.33.8 DYNA|AUTH) with ESMTPSA id 301038x8SHLXoBT (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256 bits)) (Client did not present a certificate); Tue, 28 Sep 2021 19:21:33 +0200 (CEST) From: Stephan Gerhold To: Bjorn Andersson Cc: Andy Gross , linux-arm-msm@vger.kernel.org, Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, Stephan Gerhold Subject: [PATCH 13/15] arm64: dts: qcom: msm8916: Add CPU ACC and SAW/SPM Date: Tue, 28 Sep 2021 19:12:29 +0200 Message-Id: <20210928171231.12766-14-stephan@gerhold.net> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210928171231.12766-1-stephan@gerhold.net> References: <20210928171231.12766-1-stephan@gerhold.net> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the device tree nodes necessary for SMP bring-up and cpuidle without PSCI on ARM32. The hardware is typically controlled by the PSCI implementation in the TrustZone firmware and is therefore marked as status = "reserved" by default (from the device tree specification): "Indicates that the device is operational, but should not be used. Typically this is used for devices that are controlled by another software component, such as platform firmware." Since this is part of the MSM8916 SoC it should be added to msm8916.dtsi but in practice these nodes should only get enabled via an extra include on ARM32. This is necessary for some devices with outdated (signed) firmware which is missing both PSCI and ARM64 support and can therefore only boot ARM32 kernels. Signed-off-by: Stephan Gerhold --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 56 +++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 6b06b387b021..3e7e5c9e6f1b 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -124,6 +124,8 @@ CPU0: cpu@0 { #cooling-cells = <2>; power-domains = <&CPU_PD0>; power-domain-names = "psci"; + qcom,acc = <&cpu0_acc>; + qcom,saw = <&cpu0_saw>; }; CPU1: cpu@1 { @@ -137,6 +139,8 @@ CPU1: cpu@1 { #cooling-cells = <2>; power-domains = <&CPU_PD1>; power-domain-names = "psci"; + qcom,acc = <&cpu1_acc>; + qcom,saw = <&cpu1_saw>; }; CPU2: cpu@2 { @@ -150,6 +154,8 @@ CPU2: cpu@2 { #cooling-cells = <2>; power-domains = <&CPU_PD2>; power-domain-names = "psci"; + qcom,acc = <&cpu2_acc>; + qcom,saw = <&cpu2_saw>; }; CPU3: cpu@3 { @@ -163,6 +169,8 @@ CPU3: cpu@3 { #cooling-cells = <2>; power-domains = <&CPU_PD3>; power-domain-names = "psci"; + qcom,acc = <&cpu3_acc>; + qcom,saw = <&cpu3_saw>; }; L2_0: l2-cache { @@ -1877,6 +1885,54 @@ frame@b028000 { status = "disabled"; }; }; + + cpu0_acc: power-manager@b088000 { + compatible = "qcom,msm8916-acc"; + reg = <0x0b088000 0x1000>; + status = "reserved"; /* Controlled by PSCI firmware */ + }; + + cpu0_saw: power-manager@b089000 { + compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2"; + reg = <0x0b089000 0x1000>; + status = "reserved"; /* Controlled by PSCI firmware */ + }; + + cpu1_acc: power-manager@b098000 { + compatible = "qcom,msm8916-acc"; + reg = <0x0b098000 0x1000>; + status = "reserved"; /* Controlled by PSCI firmware */ + }; + + cpu1_saw: power-manager@b099000 { + compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2"; + reg = <0x0b099000 0x1000>; + status = "reserved"; /* Controlled by PSCI firmware */ + }; + + cpu2_acc: power-manager@b0a8000 { + compatible = "qcom,msm8916-acc"; + reg = <0x0b0a8000 0x1000>; + status = "reserved"; /* Controlled by PSCI firmware */ + }; + + cpu2_saw: power-manager@b0a9000 { + compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2"; + reg = <0x0b0a9000 0x1000>; + status = "reserved"; /* Controlled by PSCI firmware */ + }; + + cpu3_acc: power-manager@b0b8000 { + compatible = "qcom,msm8916-acc"; + reg = <0x0b0b8000 0x1000>; + status = "reserved"; /* Controlled by PSCI firmware */ + }; + + cpu3_saw: power-manager@b0b9000 { + compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2"; + reg = <0x0b0b9000 0x1000>; + status = "reserved"; /* Controlled by PSCI firmware */ + }; }; thermal-zones { From patchwork Tue Sep 28 17:12:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephan Gerhold X-Patchwork-Id: 12523335 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BF099C433F5 for ; Tue, 28 Sep 2021 17:21:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A9B706127C for ; Tue, 28 Sep 2021 17:21:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234519AbhI1RXc (ORCPT ); Tue, 28 Sep 2021 13:23:32 -0400 Received: from mo4-p03-ob.smtp.rzone.de ([85.215.255.102]:15763 "EHLO mo4-p03-ob.smtp.rzone.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242041AbhI1RXa (ORCPT ); Tue, 28 Sep 2021 13:23:30 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1632849694; s=strato-dkim-0002; d=gerhold.net; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Cc:Date: From:Subject:Sender; bh=Ate8aNGD9Y3BCuk05fnC9BYkaLgxkyM/iTTiZ0A3sF0=; b=Mj2ss7D55SJa/TKkyGzT129/TJtQqKt/TjC+gkU9d8Mwig5/DrMAx2n9Qkqq1DpIyS zSVImmkPEbTwY/4XzlmQbwFQ6or7WaZI9R9ie3H40QGxe8bvJ/OSb8El5M96i3l+/THH i6sgJIb6IWBxg0GpmkVTcFG7g6RmnUrvTLTjS1g+IRfv7UTtG6OaYjkmacUJzmrcziQE 3o+LzCJMAjVvpA6T8ncOWwOcX0pwINz9NJrCgAWUMFIeSAirt+Xt7G8b4CdGcW8p5vvB FREZJizw3GY3i1lV8rhy7IcSLiwYv8rAJBLYukS4OXojCAZHsjytsIDCJ7HUmYm+qQx0 mHvA== Authentication-Results: strato.com; dkim=none X-RZG-AUTH: ":P3gBZUipdd93FF5ZZvYFPugejmSTVR2nRPhVORvLd4SsytBXTbAOHjRHIhr3eFSKSxc=" X-RZG-CLASS-ID: mo00 Received: from droid.. by smtp.strato.de (RZmta 47.33.8 DYNA|AUTH) with ESMTPSA id 301038x8SHLYoBU (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256 bits)) (Client did not present a certificate); Tue, 28 Sep 2021 19:21:34 +0200 (CEST) From: Stephan Gerhold To: Bjorn Andersson Cc: Andy Gross , linux-arm-msm@vger.kernel.org, Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, Stephan Gerhold Subject: [PATCH 14/15] ARM: dts: qcom: msm8916: Add include for SMP without PSCI on ARM32 Date: Tue, 28 Sep 2021 19:12:30 +0200 Message-Id: <20210928171231.12766-15-stephan@gerhold.net> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210928171231.12766-1-stephan@gerhold.net> References: <20210928171231.12766-1-stephan@gerhold.net> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add a special device tree include for MSM8916 on ARM32 that sets up SMP and cpuidle without PSCI. This is meant for devices with outdated (signed) firmware that does not support PSCI and only allows booting ARM32 kernels. Signed-off-by: Stephan Gerhold --- arch/arm/boot/dts/qcom-msm8916-smp.dtsi | 62 +++++++++++++++++++++++++ 1 file changed, 62 insertions(+) create mode 100644 arch/arm/boot/dts/qcom-msm8916-smp.dtsi diff --git a/arch/arm/boot/dts/qcom-msm8916-smp.dtsi b/arch/arm/boot/dts/qcom-msm8916-smp.dtsi new file mode 100644 index 000000000000..36328dbe4212 --- /dev/null +++ b/arch/arm/boot/dts/qcom-msm8916-smp.dtsi @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/ { + cpus { + cpu@0 { + enable-method = "qcom,msm8916-smp"; + }; + cpu@1 { + enable-method = "qcom,msm8916-smp"; + }; + cpu@2 { + enable-method = "qcom,msm8916-smp"; + }; + cpu@3 { + enable-method = "qcom,msm8916-smp"; + }; + + idle-states { + /delete-property/ entry-method; + }; + }; + + psci { + status = "disabled"; + }; +}; + +&CPU_SLEEP_0 { + compatible = "qcom,idle-state-spc"; +}; + +&cpu0_acc { + status = "okay"; +}; + +&cpu0_saw { + status = "okay"; +}; + +&cpu1_acc { + status = "okay"; +}; + +&cpu1_saw { + status = "okay"; +}; + +&cpu2_acc { + status = "okay"; +}; + +&cpu2_saw { + status = "okay"; +}; + +&cpu3_acc { + status = "okay"; +}; + +&cpu3_saw { + status = "okay"; +}; From patchwork Tue Sep 28 17:12:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephan Gerhold X-Patchwork-Id: 12523333 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7C801C433EF for ; Tue, 28 Sep 2021 17:21:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6027C61381 for ; Tue, 28 Sep 2021 17:21:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242038AbhI1RXc (ORCPT ); Tue, 28 Sep 2021 13:23:32 -0400 Received: from mo4-p03-ob.smtp.rzone.de ([81.169.146.174]:9000 "EHLO mo4-p03-ob.smtp.rzone.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242040AbhI1RXa (ORCPT ); Tue, 28 Sep 2021 13:23:30 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1632849695; s=strato-dkim-0002; d=gerhold.net; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Cc:Date: From:Subject:Sender; bh=S9w5GiKQ2oy3NSyTEw/qOS43AM2R39Tjvw3qTBO3Zj4=; b=be9uUQxmVeU8gYqHprkIP23lqdRMsBKz0LStw88fX1W5jg5bI+r5xvDsxMYHtuDmwj D08hnopCwRGwFzJyOGGfb8JXT7yKkjp18c1OlZo3UECID/nc3263q6H6iLxrN6u3Mzab KGLmrLTirnzlQjAep27OsaLl9Pl7FxHRE2a2fOOLxr+hsCxomhlGQux32IYEi+/VuuB9 6IKfsmdvXf7RMgYcRZ1uOiEcFpNwaeG//FQd8JxywLLkCYQb2J+L3nhdXjsxM5CP4LyK tmH6DYJZTvPSB5kbt+9kjNcKHm1vhPpUH2nwvFonxJ4xR2eH4oU5LFLWsOC8Bb21Pr0S QsOA== Authentication-Results: strato.com; dkim=none X-RZG-AUTH: ":P3gBZUipdd93FF5ZZvYFPugejmSTVR2nRPhVORvLd4SsytBXTbAOHjRHIhr3eFSKSxc=" X-RZG-CLASS-ID: mo00 Received: from droid.. by smtp.strato.de (RZmta 47.33.8 DYNA|AUTH) with ESMTPSA id 301038x8SHLYoBV (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256 bits)) (Client did not present a certificate); Tue, 28 Sep 2021 19:21:34 +0200 (CEST) From: Stephan Gerhold To: Bjorn Andersson Cc: Andy Gross , linux-arm-msm@vger.kernel.org, Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, Stephan Gerhold Subject: [PATCH 15/15] ARM: dts: qcom: msm8916-samsung-serranove: Include dts from arm64 Date: Tue, 28 Sep 2021 19:12:31 +0200 Message-Id: <20210928171231.12766-16-stephan@gerhold.net> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210928171231.12766-1-stephan@gerhold.net> References: <20210928171231.12766-1-stephan@gerhold.net> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org After adding all necessary support for MSM8916 SMP/cpuidle without PSCI on ARM32, build the Samsung Galaxy S4 Mini VE device tree from the arm64 tree together with the ARM32 include to allow booting this device on ARM32. The approach to include device tree files from other architectures is inspired from e.g. the Raspberry Pi (bcm2711-rpi-4-b.dts) where this is used to build the device tree for both ARM32 and ARM64. Signed-off-by: Stephan Gerhold --- I'm not sure what's the best way to apply this patch... It might be easiest to apply the two ARM32 dts patches to the arm64 branch. (It does not seem to cause any conflicts at the moment...) --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/qcom-msm8916-samsung-serranove.dts | 3 +++ 2 files changed, 4 insertions(+) create mode 100644 arch/arm/boot/dts/qcom-msm8916-samsung-serranove.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 8cb859728bd9..0a53bbd9d7b1 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -960,6 +960,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \ qcom-ipq8064-rb3011.dtb \ qcom-msm8226-samsung-s3ve3g.dtb \ qcom-msm8660-surf.dtb \ + qcom-msm8916-samsung-serranove.dtb \ qcom-msm8960-cdp.dtb \ qcom-msm8974-fairphone-fp2.dtb \ qcom-msm8974-lge-nexus5-hammerhead.dtb \ diff --git a/arch/arm/boot/dts/qcom-msm8916-samsung-serranove.dts b/arch/arm/boot/dts/qcom-msm8916-samsung-serranove.dts new file mode 100644 index 000000000000..dee2c20af355 --- /dev/null +++ b/arch/arm/boot/dts/qcom-msm8916-samsung-serranove.dts @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include "arm64/qcom/msm8916-samsung-serranove.dts" +#include "qcom-msm8916-smp.dtsi"