From patchwork Tue Sep 28 23:56:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William McVicker X-Patchwork-Id: 12524121 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E7F63C43217 for ; Tue, 28 Sep 2021 23:56:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CC98161157 for ; Tue, 28 Sep 2021 23:56:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243414AbhI1X6f (ORCPT ); Tue, 28 Sep 2021 19:58:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43100 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243400AbhI1X6e (ORCPT ); Tue, 28 Sep 2021 19:58:34 -0400 Received: from mail-pj1-x1049.google.com (mail-pj1-x1049.google.com [IPv6:2607:f8b0:4864:20::1049]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 73F39C06174E for ; Tue, 28 Sep 2021 16:56:54 -0700 (PDT) Received: by mail-pj1-x1049.google.com with SMTP id v3-20020a17090ac90300b0019f05c8b098so308113pjt.0 for ; Tue, 28 Sep 2021 16:56:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=WOfA7vqZaeoKU/e1lLNxRvQ3gUoOauPeXLamkl8PSGc=; b=KiEqOgIm3SGRYiytUWMvkiFilRMq4hcnoUjGZy2fugPVesXqH0cImCsb3qJue8v6bv 7Fx7Z6pokfjGwdqweU4uFrb8jyM2FQCE+yFFpD9+a1q64oEa+tk+OlF9pA4thqki5OXQ J2BflQ12t6BE31Vf1AiPHhDsaJjob8WjumAWDbYvOEWJMoFLRSomDpzXufIVo1Xu8e7M 62KIypn6Als+Q+iL1ifJKTJRiNUywEMTbV/c3Yimd6dK+zfjrdMHp74RRuj4HD6Wk695 ANwAAn/AxRb/X5L3FpEtvixO4HQKesydwsz7T+U6X/W87/hi4d9OZDzJ0qaaKfGxAlkI KyUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=WOfA7vqZaeoKU/e1lLNxRvQ3gUoOauPeXLamkl8PSGc=; b=6nBErjWK4Y2ZBJwUmtz15v19cIpjPijNArEBbpweG0O+2RrziYTtPSRlQErl09H2F4 3JoNsDrt89OIJk0Y77AOHyCzGQx5yy8DC+PLuB047bfoqz+O3xKYjKLoCaUEC+vDBmgm b2Siti+FBBynmI1KdN1VTfqBVIsXx+DEGBSgFlevYZZN7bMmqjxerwk4Ktn/oulSrMwg y5FdsXK6Zu/iM/ucZ4I2vCl9VICRQPY55P54D0xGRoZkAZWUiu06oQ2JVSdabHriU/dK lGKIbAhWMiJc9LFsB5Ec7iRcaLwlZrZOqY5kjX73lvXP1bXLDl19b1Hs2UpCOqwl+SXM 4Iyw== X-Gm-Message-State: AOAM531id4BQl56ijk/aZXZxQeGvW1wAuRtwS067JSFvJQrq4kGrCmmV utd4YDk97mJ6fhjgUFmtLQjXJVXOhJ+zO2UShIU= X-Google-Smtp-Source: ABdhPJyTX0ueGZRrc4pLQX2FyNwm8KLBrvGP099JJM4DTlk3tPSz5MIXRLHVcvqtvDkUGGw+nFFpupf7/tOk4GeOGUI= X-Received: from willmcvicker.c.googlers.com ([fda3:e722:ac3:cc00:24:72f4:c0a8:2dd0]) (user=willmcvicker job=sendgmr) by 2002:a62:1d4d:0:b0:443:eac2:8a1b with SMTP id d74-20020a621d4d000000b00443eac28a1bmr7873523pfd.2.1632873413309; Tue, 28 Sep 2021 16:56:53 -0700 (PDT) Date: Tue, 28 Sep 2021 23:56:18 +0000 In-Reply-To: <20210928235635.1348330-1-willmcvicker@google.com> Message-Id: <20210928235635.1348330-2-willmcvicker@google.com> Mime-Version: 1.0 References: <20210928235635.1348330-1-willmcvicker@google.com> X-Mailer: git-send-email 2.33.0.685.g46640cef36-goog Subject: [PATCH v2 01/12] arm64: don't have ARCH_EXYNOS select EXYNOS_CHIPID From: Will McVicker To: Russell King , Krzysztof Kozlowski , Catalin Marinas , Will Deacon , Michael Turquette , Stephen Boyd , Sylwester Nawrocki , Tomasz Figa , Chanwoo Choi , Linus Walleij , Alessandro Zummo , Alexandre Belloni , John Stultz , Thomas Gleixner Cc: Lee Jones , Geert Uytterhoeven , Saravana Kannan , Will McVicker , kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-rtc@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Now that EXYNOS_CHIPID can be a module and is enabled by default via ARCH_EXYNOS, we don't need to have ARCH_EXYNOS directly select it. So remove that. Signed-off-by: Will McVicker --- arch/arm64/Kconfig.platforms | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index b0ce18d4cc98..90c5cf4856e1 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -92,7 +92,6 @@ config ARCH_BRCMSTB config ARCH_EXYNOS bool "ARMv8 based Samsung Exynos SoC family" select COMMON_CLK_SAMSUNG - select EXYNOS_CHIPID select EXYNOS_PM_DOMAINS if PM_GENERIC_DOMAINS select EXYNOS_PMU select HAVE_S3C_RTC if RTC_CLASS From patchwork Tue Sep 28 23:56:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William McVicker X-Patchwork-Id: 12524123 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 546B2C4332F for ; Tue, 28 Sep 2021 23:56:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3FCE0610A0 for ; Tue, 28 Sep 2021 23:56:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243373AbhI1X6i (ORCPT ); Tue, 28 Sep 2021 19:58:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43106 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243377AbhI1X6g (ORCPT ); Tue, 28 Sep 2021 19:58:36 -0400 Received: from mail-qv1-xf49.google.com (mail-qv1-xf49.google.com [IPv6:2607:f8b0:4864:20::f49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2C67CC061749 for ; Tue, 28 Sep 2021 16:56:56 -0700 (PDT) Received: by mail-qv1-xf49.google.com with SMTP id z6-20020a056214060600b0037a3f6bd9abso2498577qvw.3 for ; Tue, 28 Sep 2021 16:56:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=FyJ369ORhnTpgfvJUNNRTX2KSF/fWPdPTlu0VC0PyLM=; b=PaaG/yNgQ5UlgBkmQMFEj8x5onJx3t43YX9/gnMIOkLb7hb/2GHCo2NiDGbztXWhU5 PfEZ+2dEaedybg8p1NuLLUGjjBsUjMjmQidENXeBsYaPdIxgl4NREIsuMiQ5ujBcKhAy e3DQhc8vYrDPZly86xqtzuaQ5jsETHOFRYEiQrMZ1HNZUgJNbiuZHQJMpQ8t2ZcBuo/s RhQ9Gm/FUQ99OUT1SsozOGpD2/jCyDK8nVab+7l8+wMDHLWJWlCwdiYntY8vl9o2VXJx DZabR5owhv031c4fsluZeHJvOXU7TyaOq7ESATZPsUeXaJjSQ9R/JHeWwVvRCNv3wiKk LLhg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=FyJ369ORhnTpgfvJUNNRTX2KSF/fWPdPTlu0VC0PyLM=; b=PKqIyzEDK3jwgCwiynAebSfVpO4XzvfVZYPChJpneWwALB00nTS1IBYsNz9GJrZ50X cXtj6I0mnHw7SvVTNfRVLSREQdkNhHw78VjpctE3E9l3zZHVIuiJ59hnN1mhpLQGa75T CMm9H45dIb8G34YYPZQp89lFU7FFDboUSOpfGvMri4EZDiaUGq+/fCaXJb20ycgn4ENP lNkLiyroJ3Dpz5R751AMhL+PsWUXjenwxD+i1+Vv+k9dT29XDNIVR5eBRQDXiVY2weZw zAijJ9SAwRvzLOxfXglFvzSoNv6VEGE4oRoYVKoE3Z1FzpWBC8dA29APfdu+/8AAHyGi jSdg== X-Gm-Message-State: AOAM530nKD5p5XdPl+8ccMExw79dA0ktTx9a8MRiv/jxy3bZcApRqZ8n dFAyjHVIN4VqquzOnjDnEMFA8/+ULtbVQNaHDbE= X-Google-Smtp-Source: ABdhPJzXdWyTY8J1BvgzEXbunMmQb+HgazP0ODFQ/qBWC8/QD6yR11ln+gAIGqxBn3FgWiikx/7A/5W0r9/iRUFdbdE= X-Received: from willmcvicker.c.googlers.com ([fda3:e722:ac3:cc00:24:72f4:c0a8:2dd0]) (user=willmcvicker job=sendgmr) by 2002:ad4:476a:: with SMTP id d10mr8228907qvx.59.1632873415332; Tue, 28 Sep 2021 16:56:55 -0700 (PDT) Date: Tue, 28 Sep 2021 23:56:19 +0000 In-Reply-To: <20210928235635.1348330-1-willmcvicker@google.com> Message-Id: <20210928235635.1348330-3-willmcvicker@google.com> Mime-Version: 1.0 References: <20210928235635.1348330-1-willmcvicker@google.com> X-Mailer: git-send-email 2.33.0.685.g46640cef36-goog Subject: [PATCH v2 02/12] timekeeping: add API for getting timekeeping_suspended From: Will McVicker To: Russell King , Krzysztof Kozlowski , Catalin Marinas , Will Deacon , Michael Turquette , Stephen Boyd , Sylwester Nawrocki , Tomasz Figa , Chanwoo Choi , Linus Walleij , Alessandro Zummo , Alexandre Belloni , John Stultz , Thomas Gleixner Cc: Lee Jones , Geert Uytterhoeven , Saravana Kannan , Will McVicker , kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-rtc@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org This allows modules to access the value of timekeeping_suspended without giving them write access to the variable. Signed-off-by: Will McVicker --- include/linux/timekeeping.h | 1 + kernel/time/timekeeping.c | 11 +++++++++++ 2 files changed, 12 insertions(+) diff --git a/include/linux/timekeeping.h b/include/linux/timekeeping.h index 78a98bdff76d..cdc84421d77b 100644 --- a/include/linux/timekeeping.h +++ b/include/linux/timekeeping.h @@ -8,6 +8,7 @@ /* Included from linux/ktime.h */ void timekeeping_init(void); +extern bool timekeeping_is_suspended(void); extern int timekeeping_suspended; /* Architecture timer tick functions: */ diff --git a/kernel/time/timekeeping.c b/kernel/time/timekeeping.c index b348749a9fc6..27873c052e57 100644 --- a/kernel/time/timekeeping.c +++ b/kernel/time/timekeeping.c @@ -57,6 +57,17 @@ static struct timekeeper shadow_timekeeper; /* flag for if timekeeping is suspended */ int __read_mostly timekeeping_suspended; +/** + * timekeeping_is_suspended - query for timekeeping_suspended + * + * Returns the true/false based on the value of timekeeping_suspened. + */ +bool timekeeping_is_suspended(void) +{ + return timekeeping_suspended ? true : false; +} +EXPORT_SYMBOL_GPL(timekeeping_is_suspended); + /** * struct tk_fast - NMI safe timekeeper * @seq: Sequence counter for protecting updates. The lowest bit From patchwork Tue Sep 28 23:56:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William McVicker X-Patchwork-Id: 12524125 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 38362C433EF for ; Tue, 28 Sep 2021 23:57:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 269C2610A0 for ; Tue, 28 Sep 2021 23:57:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243451AbhI1X6i (ORCPT ); Tue, 28 Sep 2021 19:58:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43102 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243433AbhI1X6i (ORCPT ); Tue, 28 Sep 2021 19:58:38 -0400 Received: from mail-pg1-x54a.google.com (mail-pg1-x54a.google.com [IPv6:2607:f8b0:4864:20::54a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 09962C06161C for ; Tue, 28 Sep 2021 16:56:58 -0700 (PDT) Received: by mail-pg1-x54a.google.com with SMTP id e5-20020a656885000000b0027e0068121fso608420pgt.16 for ; Tue, 28 Sep 2021 16:56:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=A8qNzCNapMxw2jtmX47pKK84lMS41znzFOgk5hTsT4g=; b=rEo7ZDk5e74TCZBbSEUciWvSKxRQt3AIRdoY/S4aknlZO6vJvuU71n003Fc6U8WYth 0kHrD/+d368nV17Q41I0GkP3xTCrlv8locgEp+y/zMuLznOMvYWEN+PPQznKHGoR1qwW 5ud0uIR1ymaCY67XvJWUyz4g6h/cV3RcVB5tL1z/9Fg24KaHkZ25ldxkUJcT2SmvXUY+ kZzVFsAcvtCEQAq6Vpjq5TdtIUyJh6TM6caJoAuvOJ7N2eOxGyi6a69qKunyA9Q98+EP pgCavuUeDMhoN70PAK08NwPgPm6cuBogJkWbzdO+vzmo9n3wqNgV7No4YROJsrnwFxYo O1Ig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=A8qNzCNapMxw2jtmX47pKK84lMS41znzFOgk5hTsT4g=; b=bHAOcdJOfB79NMydeuBbLiwcGbAzJUVUcXch/FhowUO/EgE1ndoIbHg0XZOmSv9uVa aWCBLT37+QFieS/rb5B55qvRVxIpmqArVaRfMEbym0OtKb9old9ZvyySVBmOVdWCRUxF naIhA+NEHkgA/KeltlKxg52lFYST/11ZLwS5mf0osPjmHHNWQbe1ElalsObUswWBe1bA pHoptlDHn/Sr3uufV7UFiDJeJ1qsfejbWCqdXnWrcWeAwGxo/X7dbNvcKw/+81izhjhg AUm0qq0nrEa46hIoiD3VcS0cQs5671l60CQJEJqrqVM0G+22DQMHdBTaGpMVOhzS2IsD yQDQ== X-Gm-Message-State: AOAM533IjHtWI6G29/McfAj8EdQvtFhw44RtQROOy1PSVBV/uP4TcMr2 BhDx16zWrUYdJ5w0lwEHCkJQ/fBY2UBpLKcFxO4= X-Google-Smtp-Source: ABdhPJwRgu3AvnXGjTVwA8JT01BkJv7hKMCFR0qy8+4P5LRuXfn4cDD3Trc0z1P2c4Oy7QYgSjVQOIaQWfZ46jPwhNE= X-Received: from willmcvicker.c.googlers.com ([fda3:e722:ac3:cc00:24:72f4:c0a8:2dd0]) (user=willmcvicker job=sendgmr) by 2002:a17:902:7e05:b0:13d:e01a:be5f with SMTP id b5-20020a1709027e0500b0013de01abe5fmr243419plm.56.1632873417456; Tue, 28 Sep 2021 16:56:57 -0700 (PDT) Date: Tue, 28 Sep 2021 23:56:20 +0000 In-Reply-To: <20210928235635.1348330-1-willmcvicker@google.com> Message-Id: <20210928235635.1348330-4-willmcvicker@google.com> Mime-Version: 1.0 References: <20210928235635.1348330-1-willmcvicker@google.com> X-Mailer: git-send-email 2.33.0.685.g46640cef36-goog Subject: [PATCH v2 03/12] clk: samsung: add support for CPU clocks From: Will McVicker To: Russell King , Krzysztof Kozlowski , Catalin Marinas , Will Deacon , Michael Turquette , Stephen Boyd , Sylwester Nawrocki , Tomasz Figa , Chanwoo Choi , Linus Walleij , Alessandro Zummo , Alexandre Belloni , John Stultz , Thomas Gleixner Cc: Lee Jones , Geert Uytterhoeven , Saravana Kannan , Will McVicker , kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-rtc@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Adds 'struct samsung_cpu_clock' and correpsonding code to the samsung common clk driver. This allows drivers to register their CPU clocks with the samsung_cmu_register_one() API. Signed-off-by: Will McVicker --- drivers/clk/samsung/clk-cpu.c | 26 ++++++++++++++++++++++++++ drivers/clk/samsung/clk.c | 2 ++ drivers/clk/samsung/clk.h | 26 ++++++++++++++++++++++++++ 3 files changed, 54 insertions(+) diff --git a/drivers/clk/samsung/clk-cpu.c b/drivers/clk/samsung/clk-cpu.c index 00ef4d1b0888..b5017934fc41 100644 --- a/drivers/clk/samsung/clk-cpu.c +++ b/drivers/clk/samsung/clk-cpu.c @@ -469,3 +469,29 @@ int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx, kfree(cpuclk); return ret; } + +void samsung_clk_register_cpu(struct samsung_clk_provider *ctx, + const struct samsung_cpu_clock *list, unsigned int nr_clk) +{ + unsigned int idx; + unsigned int num_cfgs; + struct clk *parent_clk, *alt_parent_clk; + const struct clk_hw *parent_clk_hw = NULL; + const struct clk_hw *alt_parent_clk_hw = NULL; + + for (idx = 0; idx < nr_clk; idx++, list++) { + /* find count of configuration rates in cfg */ + for (num_cfgs = 0; list->cfg[num_cfgs].prate != 0; ) + num_cfgs++; + + parent_clk = __clk_lookup(list->parent_name); + if (parent_clk) + parent_clk_hw = __clk_get_hw(parent_clk); + alt_parent_clk = __clk_lookup(list->alt_parent_name); + if (alt_parent_clk) + alt_parent_clk_hw = __clk_get_hw(alt_parent_clk); + + exynos_register_cpu_clock(ctx, list->id, list->name, parent_clk_hw, + alt_parent_clk_hw, list->offset, list->cfg, num_cfgs, list->flags); + } +} diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c index 1949ae7851b2..336243c6f120 100644 --- a/drivers/clk/samsung/clk.c +++ b/drivers/clk/samsung/clk.c @@ -378,6 +378,8 @@ struct samsung_clk_provider * __init samsung_cmu_register_one( samsung_clk_extended_sleep_init(reg_base, cmu->clk_regs, cmu->nr_clk_regs, cmu->suspend_regs, cmu->nr_suspend_regs); + if (cmu->cpu_clks) + samsung_clk_register_cpu(ctx, cmu->cpu_clks, cmu->nr_cpu_clks); samsung_clk_of_add_provider(np, ctx); diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h index c1e1a6b2f499..a52a38cc1740 100644 --- a/drivers/clk/samsung/clk.h +++ b/drivers/clk/samsung/clk.h @@ -271,6 +271,27 @@ struct samsung_pll_clock { __PLL(_typ, _id, _name, _pname, CLK_GET_RATE_NOCACHE, _lock, \ _con, _rtable) +struct samsung_cpu_clock { + unsigned int id; + const char *name; + const char *parent_name; + const char *alt_parent_name; + unsigned long flags; + int offset; + const struct exynos_cpuclk_cfg_data *cfg; +}; + +#define CPU_CLK(_id, _name, _pname, _apname, _flags, _offset, _cfg) \ + { \ + .id = _id, \ + .name = _name, \ + .parent_name = _pname, \ + .alt_parent_name = _apname, \ + .flags = _flags, \ + .offset = _offset, \ + .cfg = _cfg, \ + } + struct samsung_clock_reg_cache { struct list_head node; void __iomem *reg_base; @@ -301,6 +322,9 @@ struct samsung_cmu_info { unsigned int nr_fixed_factor_clks; /* total number of clocks with IDs assigned*/ unsigned int nr_clk_ids; + /* list of cpu clocks and respective count */ + const struct samsung_cpu_clock *cpu_clks; + unsigned int nr_cpu_clks; /* list and number of clocks registers */ const unsigned long *clk_regs; @@ -350,6 +374,8 @@ extern void __init samsung_clk_register_gate(struct samsung_clk_provider *ctx, extern void __init samsung_clk_register_pll(struct samsung_clk_provider *ctx, const struct samsung_pll_clock *pll_list, unsigned int nr_clk, void __iomem *base); +extern void __init samsung_clk_register_cpu(struct samsung_clk_provider *ctx, + const struct samsung_cpu_clock *list, unsigned int nr_clk); extern struct samsung_clk_provider __init *samsung_cmu_register_one( struct device_node *, From patchwork Tue Sep 28 23:56:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William McVicker X-Patchwork-Id: 12524127 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 07F37C433FE for ; Tue, 28 Sep 2021 23:57:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E6D856136F for ; Tue, 28 Sep 2021 23:57:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243450AbhI1X6w (ORCPT ); Tue, 28 Sep 2021 19:58:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43164 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243489AbhI1X6n (ORCPT ); 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d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=vr0wJpYVwT3Wf5W9z3LnDmKiASoPIRkm5Y4SX8T/B5k=; b=vKBftqIMCciZjvybcUACnrbQHkbqjLs+nfiI1df+IPzL/4tNPlgG2UbFk3zPf7kvkL CcPh8xW+fNOna3MRow7PRz1Lo2ASxuIg/C/I2YECf2pLnU5f7BMRe8jKkS4iPf2YHySD OLa4p5u/+K2xozYqY3Xm0whKkk2/4eI824eOAVo7VA7BU+1eBNO9c2TcDZc1LiGa5+PS pGIpaUdDWErwPlEqCZWjUVV+YGQ6NJLytkt4zEfYJn+/ZAF7ZqL4jwug8bAryT+r0Qwc c8aL0O/RZF3vQsZSrv5vtO245OOnHyfDb1h65hxVPJKaKIKmQNwyzAz3s6qgA6GpuBNt /8Dg== X-Gm-Message-State: AOAM53269+HHtuwg/TFBTLNZqlseYd53dVdU0mKVCs+Q5bMaEPsneJNa 6Mz79w9KO/ucymrjR/3gzpf6ZcOHYe0lR6ETGBk= X-Google-Smtp-Source: ABdhPJzVWvnFzcOenwV1KFMPgwyLHTY5xI3xxVNlgn4OW95Xjc374MNho/692ny5HZjJ8ThoLixN4aO9xsiIYMO9SYs= X-Received: from willmcvicker.c.googlers.com ([fda3:e722:ac3:cc00:24:72f4:c0a8:2dd0]) (user=willmcvicker job=sendgmr) by 2002:a05:6214:3ac:: with SMTP id m12mr8367504qvy.9.1632873419629; Tue, 28 Sep 2021 16:56:59 -0700 (PDT) Date: Tue, 28 Sep 2021 23:56:21 +0000 In-Reply-To: <20210928235635.1348330-1-willmcvicker@google.com> Message-Id: <20210928235635.1348330-5-willmcvicker@google.com> Mime-Version: 1.0 References: <20210928235635.1348330-1-willmcvicker@google.com> X-Mailer: git-send-email 2.33.0.685.g46640cef36-goog Subject: [PATCH v2 04/12] clk: samsung: exynos5433: update apollo and atlas clock probing From: Will McVicker To: Russell King , Krzysztof Kozlowski , Catalin Marinas , Will Deacon , Michael Turquette , Stephen Boyd , Sylwester Nawrocki , Tomasz Figa , Chanwoo Choi , Linus Walleij , Alessandro Zummo , Alexandre Belloni , John Stultz , Thomas Gleixner Cc: Lee Jones , Geert Uytterhoeven , Saravana Kannan , Will McVicker , kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-rtc@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Use the samsung common clk driver to initialize and probe the apollo and atlas clocks. This removes their dedicated init functions and uses the platform driver to handle the probing. Signed-off-by: Will McVicker --- drivers/clk/samsung/clk-exynos5433.c | 130 ++++++++++----------------- 1 file changed, 49 insertions(+), 81 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c index f203074d858b..b45f6a65ba64 100644 --- a/drivers/clk/samsung/clk-exynos5433.c +++ b/drivers/clk/samsung/clk-exynos5433.c @@ -3675,47 +3675,28 @@ static const struct exynos_cpuclk_cfg_data exynos5433_apolloclk_d[] __initconst { 0 }, }; -static void __init exynos5433_cmu_apollo_init(struct device_node *np) -{ - void __iomem *reg_base; - struct samsung_clk_provider *ctx; - struct clk_hw **hws; - - reg_base = of_iomap(np, 0); - if (!reg_base) { - panic("%s: failed to map registers\n", __func__); - return; - } - - ctx = samsung_clk_init(np, reg_base, APOLLO_NR_CLK); - if (!ctx) { - panic("%s: unable to allocate ctx\n", __func__); - return; - } - - samsung_clk_register_pll(ctx, apollo_pll_clks, - ARRAY_SIZE(apollo_pll_clks), reg_base); - samsung_clk_register_mux(ctx, apollo_mux_clks, - ARRAY_SIZE(apollo_mux_clks)); - samsung_clk_register_div(ctx, apollo_div_clks, - ARRAY_SIZE(apollo_div_clks)); - samsung_clk_register_gate(ctx, apollo_gate_clks, - ARRAY_SIZE(apollo_gate_clks)); - - hws = ctx->clk_data.hws; - - exynos_register_cpu_clock(ctx, CLK_SCLK_APOLLO, "apolloclk", - hws[CLK_MOUT_APOLLO_PLL], hws[CLK_MOUT_BUS_PLL_APOLLO_USER], 0x200, - exynos5433_apolloclk_d, ARRAY_SIZE(exynos5433_apolloclk_d), - CLK_CPU_HAS_E5433_REGS_LAYOUT); - - samsung_clk_sleep_init(reg_base, apollo_clk_regs, - ARRAY_SIZE(apollo_clk_regs)); - - samsung_clk_of_add_provider(np, ctx); -} -CLK_OF_DECLARE(exynos5433_cmu_apollo, "samsung,exynos5433-cmu-apollo", - exynos5433_cmu_apollo_init); +static const struct samsung_cpu_clock apollo_cpu_clks[] __initconst = { + CPU_CLK(CLK_SCLK_APOLLO, "apolloclk", "mout_apollo_pll", + "mout_bus_pll_apollo_user", + CLK_CPU_HAS_E5433_REGS_LAYOUT, 0x200, + exynos5433_apolloclk_d), +}; + +static const struct samsung_cmu_info apollo_cmu_info __initconst = { + .pll_clks = apollo_pll_clks, + .nr_pll_clks = ARRAY_SIZE(apollo_pll_clks), + .mux_clks = apollo_mux_clks, + .nr_mux_clks = ARRAY_SIZE(apollo_mux_clks), + .div_clks = apollo_div_clks, + .nr_div_clks = ARRAY_SIZE(apollo_div_clks), + .gate_clks = apollo_gate_clks, + .nr_gate_clks = ARRAY_SIZE(apollo_gate_clks), + .cpu_clks = apollo_cpu_clks, + .nr_cpu_clks = ARRAY_SIZE(apollo_cpu_clks), + .nr_clk_ids = APOLLO_NR_CLK, + .clk_regs = apollo_clk_regs, + .nr_clk_regs = ARRAY_SIZE(apollo_clk_regs), +}; /* * Register offset definitions for CMU_ATLAS @@ -3932,47 +3913,28 @@ static const struct exynos_cpuclk_cfg_data exynos5433_atlasclk_d[] __initconst = { 0 }, }; -static void __init exynos5433_cmu_atlas_init(struct device_node *np) -{ - void __iomem *reg_base; - struct samsung_clk_provider *ctx; - struct clk_hw **hws; - - reg_base = of_iomap(np, 0); - if (!reg_base) { - panic("%s: failed to map registers\n", __func__); - return; - } - - ctx = samsung_clk_init(np, reg_base, ATLAS_NR_CLK); - if (!ctx) { - panic("%s: unable to allocate ctx\n", __func__); - return; - } - - samsung_clk_register_pll(ctx, atlas_pll_clks, - ARRAY_SIZE(atlas_pll_clks), reg_base); - samsung_clk_register_mux(ctx, atlas_mux_clks, - ARRAY_SIZE(atlas_mux_clks)); - samsung_clk_register_div(ctx, atlas_div_clks, - ARRAY_SIZE(atlas_div_clks)); - samsung_clk_register_gate(ctx, atlas_gate_clks, - ARRAY_SIZE(atlas_gate_clks)); - - hws = ctx->clk_data.hws; - - exynos_register_cpu_clock(ctx, CLK_SCLK_ATLAS, "atlasclk", - hws[CLK_MOUT_ATLAS_PLL], hws[CLK_MOUT_BUS_PLL_ATLAS_USER], 0x200, - exynos5433_atlasclk_d, ARRAY_SIZE(exynos5433_atlasclk_d), - CLK_CPU_HAS_E5433_REGS_LAYOUT); - - samsung_clk_sleep_init(reg_base, atlas_clk_regs, - ARRAY_SIZE(atlas_clk_regs)); +static const struct samsung_cpu_clock atlas_cpu_clks[] __initconst = { + CPU_CLK(CLK_SCLK_ATLAS, "atlasclk", "mout_atlas_pll", + "mout_bus_pll_atlas_user", + CLK_CPU_HAS_E5433_REGS_LAYOUT, 0x200, + exynos5433_atlasclk_d), +}; - samsung_clk_of_add_provider(np, ctx); -} -CLK_OF_DECLARE(exynos5433_cmu_atlas, "samsung,exynos5433-cmu-atlas", - exynos5433_cmu_atlas_init); +static const struct samsung_cmu_info atlas_cmu_info __initconst = { + .pll_clks = atlas_pll_clks, + .nr_pll_clks = ARRAY_SIZE(atlas_pll_clks), + .mux_clks = atlas_mux_clks, + .nr_mux_clks = ARRAY_SIZE(atlas_mux_clks), + .div_clks = atlas_div_clks, + .nr_div_clks = ARRAY_SIZE(atlas_div_clks), + .gate_clks = atlas_gate_clks, + .nr_gate_clks = ARRAY_SIZE(atlas_gate_clks), + .cpu_clks = atlas_cpu_clks, + .nr_cpu_clks = ARRAY_SIZE(atlas_cpu_clks), + .nr_clk_ids = ATLAS_NR_CLK, + .clk_regs = atlas_clk_regs, + .nr_clk_regs = ARRAY_SIZE(atlas_clk_regs), +}; /* * Register offset definitions for CMU_MSCL @@ -5700,6 +5662,12 @@ static const struct of_device_id exynos5433_cmu_of_match[] = { }, { .compatible = "samsung,exynos5433-cmu-imem", .data = &imem_cmu_info, + }, { + .compatible = "samsung,exynos5433-cmu-atlas", + .data = &atlas_cmu_info, + }, { + .compatible = "samsung,exynos5433-cmu-apollo", + .data = &apollo_cmu_info, }, { }, }; From patchwork Tue Sep 28 23:56:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William McVicker X-Patchwork-Id: 12524129 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E995CC433F5 for ; Tue, 28 Sep 2021 23:57:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C9EAC610A0 for ; Tue, 28 Sep 2021 23:57:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243498AbhI1X6z (ORCPT ); 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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=0xU4rMhQf+Tsh4aGgPmL2VLP+qQMedKrbqJYsYtJvB8=; b=mztaOvl0ptrFepyEwiyOWPFpRcg+LBZGoxPL5ghVPCt5SPBA/ZoFRan7ui/wu/PDZo s9P328ztbq3TmMk9T+lYiDqUv2gM88du6hX3Wk3NwdSH+LzadpNREc0ObGeD9OBBGysE BfGptWM2rckz/2nyoxMGBtcFMNPdSDt2LmSz24FXbR/hAfemhHC4UJBKkJiokThNgM/L 2dYiWaKgNZhTf7FoibioY/dp7rJBXrXgdnDtPcCBC2RLimDdPC9Ljf3f8A7a3jRS5mdH z4Kp+gs8xYkNMSQ3OJ93QCo42yAaYc8oL12sykWd3osnWFxiN4SO1tKnD54FepZTy4PB HM2Q== X-Gm-Message-State: AOAM533txKrzhVycRsDzhfeZEbPUTgbnVcMFAKeMXrTvSslXMriPjIw3 EOFx8jzTdmiF7w2NvyTeTGqOhsRUnJgA31U2+6s= X-Google-Smtp-Source: ABdhPJxXnGbQVYIKPCX7yNjY7ijrlFpSIGUian9jiU0yLqRqfT6gSGW3vVD1t8tBVnpZPavgKlT5Hlw9NDYqIMPa9/k= X-Received: from willmcvicker.c.googlers.com ([fda3:e722:ac3:cc00:24:72f4:c0a8:2dd0]) (user=willmcvicker job=sendgmr) by 2002:a05:6214:98d:: with SMTP id dt13mr8482075qvb.13.1632873421401; Tue, 28 Sep 2021 16:57:01 -0700 (PDT) Date: Tue, 28 Sep 2021 23:56:22 +0000 In-Reply-To: <20210928235635.1348330-1-willmcvicker@google.com> Message-Id: <20210928235635.1348330-6-willmcvicker@google.com> Mime-Version: 1.0 References: <20210928235635.1348330-1-willmcvicker@google.com> X-Mailer: git-send-email 2.33.0.685.g46640cef36-goog Subject: [PATCH v2 05/12] clk: export __clk_lookup From: Will McVicker To: Russell King , Krzysztof Kozlowski , Catalin Marinas , Will Deacon , Michael Turquette , Stephen Boyd , Sylwester Nawrocki , Tomasz Figa , Chanwoo Choi , Linus Walleij , Alessandro Zummo , Alexandre Belloni , John Stultz , Thomas Gleixner Cc: Lee Jones , Geert Uytterhoeven , Saravana Kannan , Will McVicker , kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-rtc@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org This symbol is needed to modularize the samsung clk drivers. It's used to get the clock using the clock name. Signed-off-by: Will McVicker --- drivers/clk/clk.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index 65508eb89ec9..f2aa4b49adfc 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -612,6 +612,7 @@ struct clk *__clk_lookup(const char *name) return !core ? NULL : core->hw->clk; } +EXPORT_SYMBOL_GPL(__clk_lookup); static void clk_core_get_boundaries(struct clk_core *core, unsigned long *min_rate, From patchwork Tue Sep 28 23:56:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William McVicker X-Patchwork-Id: 12524133 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 660B4C43219 for ; Tue, 28 Sep 2021 23:57:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4455C613C8 for ; Tue, 28 Sep 2021 23:57:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243561AbhI1X66 (ORCPT ); Tue, 28 Sep 2021 19:58:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43224 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243467AbhI1X6x (ORCPT ); Tue, 28 Sep 2021 19:58:53 -0400 Received: from mail-yb1-xb4a.google.com (mail-yb1-xb4a.google.com [IPv6:2607:f8b0:4864:20::b4a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CEDE5C06161C for ; Tue, 28 Sep 2021 16:57:05 -0700 (PDT) Received: by mail-yb1-xb4a.google.com with SMTP id s6-20020a254506000000b005b6b6434cd6so1092794yba.9 for ; Tue, 28 Sep 2021 16:57:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=QCRxrKLhXqOeSWL7ZKhPhASp9RJabJgFFXFn6xQJAW8=; b=R0bo3m5mJxFslYZV4SrHJOGzAcINrUOt5uRO0KPp5Jyag68ajDO39Qxa6AWTtj6gst T3bvF7FKyYbXSPWkPXyfUbk4zZdJj5bLBi4mwd4VOn62Z5SwqPi7NeYkZUmy7JptJ6SS JSWoRQjM18OhxHgKxPVhIrKl3q6ECiHZowliIcyXt047XQ8PzvMr4EAzB5zc0zlovK7Q BM5MYep2pVQbmOFdop2sknWb7Tygu3dCmboql71vRywlaF/7/6aEoAniCDa7/flEV8EI FOzRACeLjrR9cMdcQNF6BON/O6bY/E26k9NW7EibR+y0PO43c+9WYKtjioHP5DrGnaPS mUNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=QCRxrKLhXqOeSWL7ZKhPhASp9RJabJgFFXFn6xQJAW8=; b=OfGffhiipLk4pwolbxUhnRecmfeMHw013Z3WHEmv08M+iXHhdHGotPMNybe6wGm+lj fE8ptOS0EzHgV4hDfbMkCV9xUQCz5HiC/ejR3FzDUusIC01j7r1od2rihJQWIISG7d9y v+n/f6l+BiGBMB195mSAhEOkdY3qq95dxqzaRU5yikJ+Vn4a36/f/j5PvxtU6T0lmZhx nK1hAyJ3nVy+HEdeSb4XS1HFOjjMnPPqN1YJrpqUVdA64WECosy8P7s5utG+YL8pI92A 9yi0Hsnq3lERPIIr3J2gCBZRdBoYAPjf8BjSwYKZOWryz0zn5rNBdo5ASqtU4FPA+3Zk RA6Q== X-Gm-Message-State: AOAM532D/TJkjI+exvSLXtk+enMvS/OoThOQRUcuKQjmBRejyHkUekft V7ikH/jC9SWBTcDbm7KbrByItLTitXsZqcXsb0A= X-Google-Smtp-Source: ABdhPJw5Cl0QKvSqR1C6Kj5koYOvTNZW60AWo0EYWYte+u2y/IUxx6c+IZ+oM5GmssFgv89a8FBU7+QQSLhZM9WeQsc= X-Received: from willmcvicker.c.googlers.com ([fda3:e722:ac3:cc00:24:72f4:c0a8:2dd0]) (user=willmcvicker job=sendgmr) by 2002:a25:3f04:: with SMTP id m4mr8900577yba.123.1632873425007; Tue, 28 Sep 2021 16:57:05 -0700 (PDT) Date: Tue, 28 Sep 2021 23:56:23 +0000 In-Reply-To: <20210928235635.1348330-1-willmcvicker@google.com> Message-Id: <20210928235635.1348330-7-willmcvicker@google.com> Mime-Version: 1.0 References: <20210928235635.1348330-1-willmcvicker@google.com> X-Mailer: git-send-email 2.33.0.685.g46640cef36-goog Subject: [PATCH v2 06/12] clk: samsung: modularize exynos arm64 clk drivers From: Will McVicker To: Russell King , Krzysztof Kozlowski , Catalin Marinas , Will Deacon , Michael Turquette , Stephen Boyd , Sylwester Nawrocki , Tomasz Figa , Chanwoo Choi , Linus Walleij , Alessandro Zummo , Alexandre Belloni , John Stultz , Thomas Gleixner Cc: Lee Jones , Geert Uytterhoeven , Saravana Kannan , Will McVicker , kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-rtc@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org This modularizes the Exynos ARM64 clock drivers. The change consolidates the clock devices into the of match table so that the platform driver probes all the clocks (per driver) as well as exports the necessary functions for each driver. With this, we now have 3 separate kernel modules (pending Kconfig changes): 1) clk-common-exynos.ko: the common exynos clock driver 2) clk-exynos5433.ko: the Exynos5433 clock driver 3) clk-exynos7.ko: the Exynos7 clock driver Signed-off-by: Will McVicker --- drivers/clk/samsung/Makefile | 3 +- drivers/clk/samsung/clk-cpu.c | 2 +- drivers/clk/samsung/clk-cpu.h | 2 +- drivers/clk/samsung/clk-exynos5433.c | 349 +++++++++++++-------------- drivers/clk/samsung/clk-exynos7.c | 177 ++++++-------- drivers/clk/samsung/clk-pll.c | 6 +- drivers/clk/samsung/clk.c | 33 ++- drivers/clk/samsung/clk.h | 26 +- 8 files changed, 287 insertions(+), 311 deletions(-) diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile index 028b2e27a37e..33f07ee87d90 100644 --- a/drivers/clk/samsung/Makefile +++ b/drivers/clk/samsung/Makefile @@ -3,7 +3,8 @@ # Samsung Clock specific Makefile # -obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o clk-cpu.o +obj-$(CONFIG_COMMON_CLK_SAMSUNG) += clk-common-exynos.o +clk-common-exynos-y += clk.o clk-pll.o clk-cpu.o obj-$(CONFIG_EXYNOS_3250_COMMON_CLK) += clk-exynos3250.o obj-$(CONFIG_EXYNOS_4_COMMON_CLK) += clk-exynos4.o obj-$(CONFIG_EXYNOS_4_COMMON_CLK) += clk-exynos4412-isp.o diff --git a/drivers/clk/samsung/clk-cpu.c b/drivers/clk/samsung/clk-cpu.c index b5017934fc41..ab3d0c073031 100644 --- a/drivers/clk/samsung/clk-cpu.c +++ b/drivers/clk/samsung/clk-cpu.c @@ -400,7 +400,7 @@ static int exynos5433_cpuclk_notifier_cb(struct notifier_block *nb, } /* helper function to register a CPU clock */ -int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx, +int exynos_register_cpu_clock(struct samsung_clk_provider *ctx, unsigned int lookup_id, const char *name, const struct clk_hw *parent, const struct clk_hw *alt_parent, unsigned long offset, const struct exynos_cpuclk_cfg_data *cfg, diff --git a/drivers/clk/samsung/clk-cpu.h b/drivers/clk/samsung/clk-cpu.h index af74686db9ef..fd885d2bf74c 100644 --- a/drivers/clk/samsung/clk-cpu.h +++ b/drivers/clk/samsung/clk-cpu.h @@ -62,7 +62,7 @@ struct exynos_cpuclk { #define CLK_CPU_HAS_E5433_REGS_LAYOUT (1 << 2) }; -int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx, +int exynos_register_cpu_clock(struct samsung_clk_provider *ctx, unsigned int lookup_id, const char *name, const struct clk_hw *parent, const struct clk_hw *alt_parent, unsigned long offset, diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c index b45f6a65ba64..885e38c1d487 100644 --- a/drivers/clk/samsung/clk-exynos5433.c +++ b/drivers/clk/samsung/clk-exynos5433.c @@ -8,6 +8,7 @@ #include #include +#include #include #include #include @@ -112,7 +113,7 @@ #define ENABLE_CMU_TOP 0x0c00 #define ENABLE_CMU_TOP_DIV_STAT 0x0c04 -static const unsigned long top_clk_regs[] __initconst = { +static const unsigned long top_clk_regs[] = { ISP_PLL_LOCK, AUD_PLL_LOCK, ISP_PLL_CON0, @@ -233,11 +234,11 @@ PNAME(mout_sclk_audio0_p) = { "ioclk_audiocdclk0", "oscclk", PNAME(mout_sclk_hdmi_spdif_p) = { "sclk_audio1", "ioclk_spdif_extclk", }; -static const struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initconst = { +static const struct samsung_fixed_factor_clock top_fixed_factor_clks[] = { FFACTOR(0, "oscclk_efuse_common", "oscclk", 1, 1, 0), }; -static const struct samsung_fixed_rate_clock top_fixed_clks[] __initconst = { +static const struct samsung_fixed_rate_clock top_fixed_clks[] = { /* Xi2s{0|1}CDCLK input clock for I2S/PCM */ FRATE(0, "ioclk_audiocdclk1", NULL, 0, 100000000), FRATE(0, "ioclk_audiocdclk0", NULL, 0, 100000000), @@ -253,7 +254,7 @@ static const struct samsung_fixed_rate_clock top_fixed_clks[] __initconst = { FRATE(0, "ioclk_i2s1_bclk_in", NULL, 0, 12288000), }; -static const struct samsung_mux_clock top_mux_clks[] __initconst = { +static const struct samsung_mux_clock top_mux_clks[] = { /* MUX_SEL_TOP0 */ MUX(CLK_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p, MUX_SEL_TOP0, 4, 1), @@ -389,7 +390,7 @@ static const struct samsung_mux_clock top_mux_clks[] __initconst = { mout_sclk_hdmi_spdif_p, MUX_SEL_TOP_DISP, 0, 1), }; -static const struct samsung_div_clock top_div_clks[] __initconst = { +static const struct samsung_div_clock top_div_clks[] = { /* DIV_TOP0 */ DIV(CLK_DIV_ACLK_CAM1_333, "div_aclk_cam1_333", "mout_aclk_cam1_333", DIV_TOP0, 28, 3), @@ -553,7 +554,7 @@ static const struct samsung_div_clock top_div_clks[] __initconst = { DIV_TOP_PERIC4, 0, 4), }; -static const struct samsung_gate_clock top_gate_clks[] __initconst = { +static const struct samsung_gate_clock top_gate_clks[] = { /* ENABLE_ACLK_TOP */ GATE(CLK_ACLK_G3D_400, "aclk_g3d_400", "div_aclk_g3d_400", ENABLE_ACLK_TOP, 30, CLK_IS_CRITICAL, 0), @@ -711,7 +712,7 @@ static const struct samsung_gate_clock top_gate_clks[] __initconst = { * ATLAS_PLL & APOLLO_PLL & MEM0_PLL & MEM1_PLL & BUS_PLL & MFC_PLL * & MPHY_PLL & G3D_PLL & DISP_PLL & ISP_PLL */ -static const struct samsung_pll_rate_table exynos5433_pll_rates[] __initconst = { +static const struct samsung_pll_rate_table exynos5433_pll_rates[] = { PLL_35XX_RATE(24 * MHZ, 2500000000U, 625, 6, 0), PLL_35XX_RATE(24 * MHZ, 2400000000U, 500, 5, 0), PLL_35XX_RATE(24 * MHZ, 2300000000U, 575, 6, 0), @@ -764,7 +765,7 @@ static const struct samsung_pll_rate_table exynos5433_pll_rates[] __initconst = }; /* AUD_PLL */ -static const struct samsung_pll_rate_table exynos5433_aud_pll_rates[] __initconst = { +static const struct samsung_pll_rate_table exynos5433_aud_pll_rates[] = { PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0), PLL_36XX_RATE(24 * MHZ, 393216003U, 197, 3, 2, -25690), PLL_36XX_RATE(24 * MHZ, 384000000U, 128, 2, 2, 0), @@ -778,14 +779,14 @@ static const struct samsung_pll_rate_table exynos5433_aud_pll_rates[] __initcons { /* sentinel */ } }; -static const struct samsung_pll_clock top_pll_clks[] __initconst = { +static const struct samsung_pll_clock top_pll_clks[] = { PLL(pll_35xx, CLK_FOUT_ISP_PLL, "fout_isp_pll", "oscclk", ISP_PLL_LOCK, ISP_PLL_CON0, exynos5433_pll_rates), PLL(pll_36xx, CLK_FOUT_AUD_PLL, "fout_aud_pll", "oscclk", AUD_PLL_LOCK, AUD_PLL_CON0, exynos5433_aud_pll_rates), }; -static const struct samsung_cmu_info top_cmu_info __initconst = { +static const struct samsung_cmu_info top_cmu_info = { .pll_clks = top_pll_clks, .nr_pll_clks = ARRAY_SIZE(top_pll_clks), .mux_clks = top_mux_clks, @@ -805,13 +806,6 @@ static const struct samsung_cmu_info top_cmu_info __initconst = { .nr_suspend_regs = ARRAY_SIZE(top_suspend_regs), }; -static void __init exynos5433_cmu_top_init(struct device_node *np) -{ - samsung_cmu_register_one(np, &top_cmu_info); -} -CLK_OF_DECLARE(exynos5433_cmu_top, "samsung,exynos5433-cmu-top", - exynos5433_cmu_top_init); - /* * Register offset definitions for CMU_CPIF */ @@ -823,7 +817,7 @@ CLK_OF_DECLARE(exynos5433_cmu_top, "samsung,exynos5433-cmu-top", #define DIV_CPIF 0x0600 #define ENABLE_SCLK_CPIF 0x0a00 -static const unsigned long cpif_clk_regs[] __initconst = { +static const unsigned long cpif_clk_regs[] = { MPHY_PLL_LOCK, MPHY_PLL_CON0, MPHY_PLL_CON1, @@ -843,24 +837,24 @@ static const struct samsung_clk_reg_dump cpif_suspend_regs[] = { /* list of all parent clock list */ PNAME(mout_mphy_pll_p) = { "oscclk", "fout_mphy_pll", }; -static const struct samsung_pll_clock cpif_pll_clks[] __initconst = { +static const struct samsung_pll_clock cpif_pll_clks[] = { PLL(pll_35xx, CLK_FOUT_MPHY_PLL, "fout_mphy_pll", "oscclk", MPHY_PLL_LOCK, MPHY_PLL_CON0, exynos5433_pll_rates), }; -static const struct samsung_mux_clock cpif_mux_clks[] __initconst = { +static const struct samsung_mux_clock cpif_mux_clks[] = { /* MUX_SEL_CPIF0 */ MUX(CLK_MOUT_MPHY_PLL, "mout_mphy_pll", mout_mphy_pll_p, MUX_SEL_CPIF0, 0, 1), }; -static const struct samsung_div_clock cpif_div_clks[] __initconst = { +static const struct samsung_div_clock cpif_div_clks[] = { /* DIV_CPIF */ DIV(CLK_DIV_SCLK_MPHY, "div_sclk_mphy", "mout_mphy_pll", DIV_CPIF, 0, 6), }; -static const struct samsung_gate_clock cpif_gate_clks[] __initconst = { +static const struct samsung_gate_clock cpif_gate_clks[] = { /* ENABLE_SCLK_CPIF */ GATE(CLK_SCLK_MPHY_PLL, "sclk_mphy_pll", "mout_mphy_pll", ENABLE_SCLK_CPIF, 9, CLK_IGNORE_UNUSED, 0), @@ -868,7 +862,7 @@ static const struct samsung_gate_clock cpif_gate_clks[] __initconst = { ENABLE_SCLK_CPIF, 4, 0, 0), }; -static const struct samsung_cmu_info cpif_cmu_info __initconst = { +static const struct samsung_cmu_info cpif_cmu_info = { .pll_clks = cpif_pll_clks, .nr_pll_clks = ARRAY_SIZE(cpif_pll_clks), .mux_clks = cpif_mux_clks, @@ -884,13 +878,6 @@ static const struct samsung_cmu_info cpif_cmu_info __initconst = { .nr_suspend_regs = ARRAY_SIZE(cpif_suspend_regs), }; -static void __init exynos5433_cmu_cpif_init(struct device_node *np) -{ - samsung_cmu_register_one(np, &cpif_cmu_info); -} -CLK_OF_DECLARE(exynos5433_cmu_cpif, "samsung,exynos5433-cmu-cpif", - exynos5433_cmu_cpif_init); - /* * Register offset definitions for CMU_MIF */ @@ -971,7 +958,7 @@ CLK_OF_DECLARE(exynos5433_cmu_cpif, "samsung,exynos5433-cmu-cpif", #define PAUSE 0x1008 #define DDRPHY_LOCK_CTRL 0x100c -static const unsigned long mif_clk_regs[] __initconst = { +static const unsigned long mif_clk_regs[] = { MEM0_PLL_LOCK, MEM1_PLL_LOCK, BUS_PLL_LOCK, @@ -1036,7 +1023,7 @@ static const unsigned long mif_clk_regs[] __initconst = { DDRPHY_LOCK_CTRL, }; -static const struct samsung_pll_clock mif_pll_clks[] __initconst = { +static const struct samsung_pll_clock mif_pll_clks[] = { PLL(pll_35xx, CLK_FOUT_MEM0_PLL, "fout_mem0_pll", "oscclk", MEM0_PLL_LOCK, MEM0_PLL_CON0, exynos5433_pll_rates), PLL(pll_35xx, CLK_FOUT_MEM1_PLL, "fout_mem1_pll", "oscclk", @@ -1097,7 +1084,7 @@ PNAME(mout_sclk_decon_tv_vclk_b_p) = { "mout_sclk_decon_tv_vclk_a", PNAME(mout_sclk_dsim1_c_p) = { "mout_sclk_dsim1_b", "sclk_mphy_pll", }; PNAME(mout_sclk_dsim1_b_p) = { "mout_sclk_dsim1_a", "mout_mfc_pll_div2",}; -static const struct samsung_fixed_factor_clock mif_fixed_factor_clks[] __initconst = { +static const struct samsung_fixed_factor_clock mif_fixed_factor_clks[] = { /* dout_{mfc|bus|mem1|mem0}_pll is half fixed rate from parent mux */ FFACTOR(CLK_DOUT_MFC_PLL, "dout_mfc_pll", "mout_mfc_pll", 1, 1, 0), FFACTOR(CLK_DOUT_BUS_PLL, "dout_bus_pll", "mout_bus_pll", 1, 1, 0), @@ -1105,7 +1092,7 @@ static const struct samsung_fixed_factor_clock mif_fixed_factor_clks[] __initcon FFACTOR(CLK_DOUT_MEM0_PLL, "dout_mem0_pll", "mout_mem0_pll", 1, 1, 0), }; -static const struct samsung_mux_clock mif_mux_clks[] __initconst = { +static const struct samsung_mux_clock mif_mux_clks[] = { /* MUX_SEL_MIF0 */ MUX(CLK_MOUT_MFC_PLL_DIV2, "mout_mfc_pll_div2", mout_mfc_pll_div2_p, MUX_SEL_MIF0, 28, 1), @@ -1201,7 +1188,7 @@ static const struct samsung_mux_clock mif_mux_clks[] __initconst = { MUX_SEL_MIF7, 0, 1), }; -static const struct samsung_div_clock mif_div_clks[] __initconst = { +static const struct samsung_div_clock mif_div_clks[] = { /* DIV_MIF1 */ DIV(CLK_DIV_SCLK_HPM_MIF, "div_sclk_hpm_mif", "div_clk2x_phy", DIV_MIF1, 16, 2), @@ -1255,7 +1242,7 @@ static const struct samsung_div_clock mif_div_clks[] __initconst = { 0, 3), }; -static const struct samsung_gate_clock mif_gate_clks[] __initconst = { +static const struct samsung_gate_clock mif_gate_clks[] = { /* ENABLE_ACLK_MIF0 */ GATE(CLK_CLK2X_PHY1, "clk2k_phy1", "div_clk2x_phy", ENABLE_ACLK_MIF0, 19, CLK_IGNORE_UNUSED, 0), @@ -1520,7 +1507,7 @@ static const struct samsung_gate_clock mif_gate_clks[] __initconst = { ENABLE_SCLK_MIF, 0, CLK_IGNORE_UNUSED, 0), }; -static const struct samsung_cmu_info mif_cmu_info __initconst = { +static const struct samsung_cmu_info mif_cmu_info = { .pll_clks = mif_pll_clks, .nr_pll_clks = ARRAY_SIZE(mif_pll_clks), .mux_clks = mif_mux_clks, @@ -1536,13 +1523,6 @@ static const struct samsung_cmu_info mif_cmu_info __initconst = { .nr_clk_regs = ARRAY_SIZE(mif_clk_regs), }; -static void __init exynos5433_cmu_mif_init(struct device_node *np) -{ - samsung_cmu_register_one(np, &mif_cmu_info); -} -CLK_OF_DECLARE(exynos5433_cmu_mif, "samsung,exynos5433-cmu-mif", - exynos5433_cmu_mif_init); - /* * Register offset definitions for CMU_PERIC */ @@ -1556,7 +1536,7 @@ CLK_OF_DECLARE(exynos5433_cmu_mif, "samsung,exynos5433-cmu-mif", #define ENABLE_IP_PERIC1 0x0B04 #define ENABLE_IP_PERIC2 0x0B08 -static const unsigned long peric_clk_regs[] __initconst = { +static const unsigned long peric_clk_regs[] = { DIV_PERIC, ENABLE_ACLK_PERIC, ENABLE_PCLK_PERIC0, @@ -1574,13 +1554,13 @@ static const struct samsung_clk_reg_dump peric_suspend_regs[] = { { ENABLE_SCLK_PERIC, 0x7 }, }; -static const struct samsung_div_clock peric_div_clks[] __initconst = { +static const struct samsung_div_clock peric_div_clks[] = { /* DIV_PERIC */ DIV(CLK_DIV_SCLK_SCI, "div_sclk_sci", "oscclk", DIV_PERIC, 4, 4), DIV(CLK_DIV_SCLK_SC_IN, "div_sclk_sc_in", "oscclk", DIV_PERIC, 0, 4), }; -static const struct samsung_gate_clock peric_gate_clks[] __initconst = { +static const struct samsung_gate_clock peric_gate_clks[] = { /* ENABLE_ACLK_PERIC */ GATE(CLK_ACLK_AHB2APB_PERIC2P, "aclk_ahb2apb_peric2p", "aclk_peric_66", ENABLE_ACLK_PERIC, 3, CLK_IGNORE_UNUSED, 0), @@ -1725,7 +1705,7 @@ static const struct samsung_gate_clock peric_gate_clks[] __initconst = { CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), }; -static const struct samsung_cmu_info peric_cmu_info __initconst = { +static const struct samsung_cmu_info peric_cmu_info = { .div_clks = peric_div_clks, .nr_div_clks = ARRAY_SIZE(peric_div_clks), .gate_clks = peric_gate_clks, @@ -1737,14 +1717,6 @@ static const struct samsung_cmu_info peric_cmu_info __initconst = { .nr_suspend_regs = ARRAY_SIZE(peric_suspend_regs), }; -static void __init exynos5433_cmu_peric_init(struct device_node *np) -{ - samsung_cmu_register_one(np, &peric_cmu_info); -} - -CLK_OF_DECLARE(exynos5433_cmu_peric, "samsung,exynos5433-cmu-peric", - exynos5433_cmu_peric_init); - /* * Register offset definitions for CMU_PERIS */ @@ -1774,7 +1746,7 @@ CLK_OF_DECLARE(exynos5433_cmu_peric, "samsung,exynos5433-cmu-peric", #define ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT 0x0b1c #define ENABLE_IP_PERIS_SECURE_OTP_CON 0x0b20 -static const unsigned long peris_clk_regs[] __initconst = { +static const unsigned long peris_clk_regs[] = { ENABLE_ACLK_PERIS, ENABLE_PCLK_PERIS, ENABLE_PCLK_PERIS_SECURE_TZPC, @@ -1802,7 +1774,7 @@ static const unsigned long peris_clk_regs[] __initconst = { ENABLE_IP_PERIS_SECURE_OTP_CON, }; -static const struct samsung_gate_clock peris_gate_clks[] __initconst = { +static const struct samsung_gate_clock peris_gate_clks[] = { /* ENABLE_ACLK_PERIS */ GATE(CLK_ACLK_AHB2APB_PERIS1P, "aclk_ahb2apb_peris1p", "aclk_peris_66", ENABLE_ACLK_PERIS, 2, CLK_IGNORE_UNUSED, 0), @@ -1921,7 +1893,7 @@ static const struct samsung_gate_clock peris_gate_clks[] __initconst = { ENABLE_SCLK_PERIS_SECURE_OTP_CON, 0, 0, 0), }; -static const struct samsung_cmu_info peris_cmu_info __initconst = { +static const struct samsung_cmu_info peris_cmu_info = { .gate_clks = peris_gate_clks, .nr_gate_clks = ARRAY_SIZE(peris_gate_clks), .nr_clk_ids = PERIS_NR_CLK, @@ -1929,14 +1901,6 @@ static const struct samsung_cmu_info peris_cmu_info __initconst = { .nr_clk_regs = ARRAY_SIZE(peris_clk_regs), }; -static void __init exynos5433_cmu_peris_init(struct device_node *np) -{ - samsung_cmu_register_one(np, &peris_cmu_info); -} - -CLK_OF_DECLARE(exynos5433_cmu_peris, "samsung,exynos5433-cmu-peris", - exynos5433_cmu_peris_init); - /* * Register offset definitions for CMU_FSYS */ @@ -2005,7 +1969,7 @@ PNAME(mout_sclk_mphy_p) = { "mout_sclk_ufs_mphy_user", "mout_phyclk_lli_mphy_to_ufs_user", }; -static const unsigned long fsys_clk_regs[] __initconst = { +static const unsigned long fsys_clk_regs[] = { MUX_SEL_FSYS0, MUX_SEL_FSYS1, MUX_SEL_FSYS2, @@ -2034,7 +1998,7 @@ static const struct samsung_clk_reg_dump fsys_suspend_regs[] = { { MUX_SEL_FSYS4, 0 }, }; -static const struct samsung_fixed_rate_clock fsys_fixed_clks[] __initconst = { +static const struct samsung_fixed_rate_clock fsys_fixed_clks[] = { /* PHY clocks from USBDRD30_PHY */ FRATE(CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY, "phyclk_usbdrd30_udrd30_phyclock_phy", NULL, @@ -2074,7 +2038,7 @@ static const struct samsung_fixed_rate_clock fsys_fixed_clks[] __initconst = { NULL, 0, 26000000), }; -static const struct samsung_mux_clock fsys_mux_clks[] __initconst = { +static const struct samsung_mux_clock fsys_mux_clks[] = { /* MUX_SEL_FSYS0 */ MUX(CLK_MOUT_SCLK_UFS_MPHY_USER, "mout_sclk_ufs_mphy_user", mout_sclk_ufs_mphy_user_p, MUX_SEL_FSYS0, 4, 1), @@ -2158,7 +2122,7 @@ static const struct samsung_mux_clock fsys_mux_clks[] __initconst = { MUX_SEL_FSYS4, 0, 1), }; -static const struct samsung_gate_clock fsys_gate_clks[] __initconst = { +static const struct samsung_gate_clock fsys_gate_clks[] = { /* ENABLE_ACLK_FSYS0 */ GATE(CLK_ACLK_PCIE, "aclk_pcie", "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS0, 13, CLK_IGNORE_UNUSED, 0), @@ -2329,7 +2293,7 @@ static const struct samsung_gate_clock fsys_gate_clks[] __initconst = { GATE(CLK_PDMA0, "pdma0", "aclk_pdma0", ENABLE_IP_FSYS0, 0, 0, 0), }; -static const struct samsung_cmu_info fsys_cmu_info __initconst = { +static const struct samsung_cmu_info fsys_cmu_info = { .mux_clks = fsys_mux_clks, .nr_mux_clks = ARRAY_SIZE(fsys_mux_clks), .gate_clks = fsys_gate_clks, @@ -2360,7 +2324,7 @@ static const struct samsung_cmu_info fsys_cmu_info __initconst = { #define DIV_ENABLE_IP_G2D1 0x0b04 #define DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D 0x0b08 -static const unsigned long g2d_clk_regs[] __initconst = { +static const unsigned long g2d_clk_regs[] = { MUX_SEL_G2D0, MUX_SEL_ENABLE_G2D0, DIV_G2D, @@ -2381,7 +2345,7 @@ static const struct samsung_clk_reg_dump g2d_suspend_regs[] = { PNAME(mout_aclk_g2d_266_user_p) = { "oscclk", "aclk_g2d_266", }; PNAME(mout_aclk_g2d_400_user_p) = { "oscclk", "aclk_g2d_400", }; -static const struct samsung_mux_clock g2d_mux_clks[] __initconst = { +static const struct samsung_mux_clock g2d_mux_clks[] = { /* MUX_SEL_G2D0 */ MUX(CLK_MUX_ACLK_G2D_266_USER, "mout_aclk_g2d_266_user", mout_aclk_g2d_266_user_p, MUX_SEL_G2D0, 4, 1), @@ -2389,13 +2353,13 @@ static const struct samsung_mux_clock g2d_mux_clks[] __initconst = { mout_aclk_g2d_400_user_p, MUX_SEL_G2D0, 0, 1), }; -static const struct samsung_div_clock g2d_div_clks[] __initconst = { +static const struct samsung_div_clock g2d_div_clks[] = { /* DIV_G2D */ DIV(CLK_DIV_PCLK_G2D, "div_pclk_g2d", "mout_aclk_g2d_266_user", DIV_G2D, 0, 2), }; -static const struct samsung_gate_clock g2d_gate_clks[] __initconst = { +static const struct samsung_gate_clock g2d_gate_clks[] = { /* DIV_ENABLE_ACLK_G2D */ GATE(CLK_ACLK_SMMU_MDMA1, "aclk_smmu_mdma1", "mout_aclk_g2d_266_user", DIV_ENABLE_ACLK_G2D, 12, 0, 0), @@ -2452,7 +2416,7 @@ static const struct samsung_gate_clock g2d_gate_clks[] __initconst = { DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D, 0, 0, 0), }; -static const struct samsung_cmu_info g2d_cmu_info __initconst = { +static const struct samsung_cmu_info g2d_cmu_info = { .mux_clks = g2d_mux_clks, .nr_mux_clks = ARRAY_SIZE(g2d_mux_clks), .div_clks = g2d_div_clks, @@ -2503,7 +2467,7 @@ static const struct samsung_cmu_info g2d_cmu_info __initconst = { #define CLKOUT_CMU_DISP 0x0c00 #define CLKOUT_CMU_DISP_DIV_STAT 0x0c04 -static const unsigned long disp_clk_regs[] __initconst = { +static const unsigned long disp_clk_regs[] = { DISP_PLL_LOCK, DISP_PLL_CON0, DISP_PLL_CON1, @@ -2588,12 +2552,12 @@ PNAME(mout_sclk_decon_tv_vclk_c_disp_p) = { PNAME(mout_sclk_decon_tv_vclk_b_disp_p) = { "mout_sclk_decon_tv_vclk_a_disp", "mout_sclk_decon_tv_vclk_user", }; -static const struct samsung_pll_clock disp_pll_clks[] __initconst = { +static const struct samsung_pll_clock disp_pll_clks[] = { PLL(pll_35xx, CLK_FOUT_DISP_PLL, "fout_disp_pll", "oscclk", DISP_PLL_LOCK, DISP_PLL_CON0, exynos5433_pll_rates), }; -static const struct samsung_fixed_factor_clock disp_fixed_factor_clks[] __initconst = { +static const struct samsung_fixed_factor_clock disp_fixed_factor_clks[] = { /* * sclk_rgb_{vclk|tv_vclk} is half clock of sclk_decon_{vclk|tv_vclk}. * The divider has fixed value (2) between sclk_rgb_{vclk|tv_vclk} @@ -2605,7 +2569,7 @@ static const struct samsung_fixed_factor_clock disp_fixed_factor_clks[] __initco 1, 2, 0), }; -static const struct samsung_fixed_rate_clock disp_fixed_clks[] __initconst = { +static const struct samsung_fixed_rate_clock disp_fixed_clks[] = { /* PHY clocks from MIPI_DPHY1 */ FRATE(0, "phyclk_mipidphy1_bitclkdiv8_phy", NULL, 0, 188000000), FRATE(0, "phyclk_mipidphy1_rxclkesc0_phy", NULL, 0, 100000000), @@ -2621,7 +2585,7 @@ static const struct samsung_fixed_rate_clock disp_fixed_clks[] __initconst = { NULL, 0, 166000000), }; -static const struct samsung_mux_clock disp_mux_clks[] __initconst = { +static const struct samsung_mux_clock disp_mux_clks[] = { /* MUX_SEL_DISP0 */ MUX(CLK_MOUT_DISP_PLL, "mout_disp_pll", mout_disp_pll_p, MUX_SEL_DISP0, 0, 1), @@ -2696,7 +2660,7 @@ static const struct samsung_mux_clock disp_mux_clks[] __initconst = { mout_sclk_decon_vclk_p, MUX_SEL_DISP4, 0, 1), }; -static const struct samsung_div_clock disp_div_clks[] __initconst = { +static const struct samsung_div_clock disp_div_clks[] = { /* DIV_DISP */ DIV(CLK_DIV_SCLK_DSIM1_DISP, "div_sclk_dsim1_disp", "mout_sclk_dsim1_b_disp", DIV_DISP, 24, 3), @@ -2714,7 +2678,7 @@ static const struct samsung_div_clock disp_div_clks[] __initconst = { DIV_DISP, 0, 2), }; -static const struct samsung_gate_clock disp_gate_clks[] __initconst = { +static const struct samsung_gate_clock disp_gate_clks[] = { /* ENABLE_ACLK_DISP0 */ GATE(CLK_ACLK_DECON_TV, "aclk_decon_tv", "mout_aclk_disp_333_user", ENABLE_ACLK_DISP0, 2, 0, 0), @@ -2874,7 +2838,7 @@ static const struct samsung_gate_clock disp_gate_clks[] __initconst = { "div_sclk_decon_eclk_disp", ENABLE_SCLK_DISP, 2, 0, 0), }; -static const struct samsung_cmu_info disp_cmu_info __initconst = { +static const struct samsung_cmu_info disp_cmu_info = { .pll_clks = disp_pll_clks, .nr_pll_clks = ARRAY_SIZE(disp_pll_clks), .mux_clks = disp_mux_clks, @@ -2914,7 +2878,7 @@ static const struct samsung_cmu_info disp_cmu_info __initconst = { #define ENABLE_IP_AUD0 0x0b00 #define ENABLE_IP_AUD1 0x0b04 -static const unsigned long aud_clk_regs[] __initconst = { +static const unsigned long aud_clk_regs[] = { MUX_SEL_AUD0, MUX_SEL_AUD1, MUX_ENABLE_AUD0, @@ -2938,13 +2902,13 @@ static const struct samsung_clk_reg_dump aud_suspend_regs[] = { PNAME(mout_aud_pll_user_aud_p) = { "oscclk", "fout_aud_pll", }; PNAME(mout_sclk_aud_pcm_p) = { "mout_aud_pll_user", "ioclk_audiocdclk0",}; -static const struct samsung_fixed_rate_clock aud_fixed_clks[] __initconst = { +static const struct samsung_fixed_rate_clock aud_fixed_clks[] = { FRATE(0, "ioclk_jtag_tclk", NULL, 0, 33000000), FRATE(0, "ioclk_slimbus_clk", NULL, 0, 25000000), FRATE(0, "ioclk_i2s_bclk", NULL, 0, 50000000), }; -static const struct samsung_mux_clock aud_mux_clks[] __initconst = { +static const struct samsung_mux_clock aud_mux_clks[] = { /* MUX_SEL_AUD0 */ MUX(CLK_MOUT_AUD_PLL_USER, "mout_aud_pll_user", mout_aud_pll_user_aud_p, MUX_SEL_AUD0, 0, 1), @@ -2956,7 +2920,7 @@ static const struct samsung_mux_clock aud_mux_clks[] __initconst = { MUX_SEL_AUD1, 0, 1), }; -static const struct samsung_div_clock aud_div_clks[] __initconst = { +static const struct samsung_div_clock aud_div_clks[] = { /* DIV_AUD0 */ DIV(CLK_DIV_ATCLK_AUD, "div_atclk_aud", "div_aud_ca5", DIV_AUD0, 12, 4), @@ -2978,7 +2942,7 @@ static const struct samsung_div_clock aud_div_clks[] __initconst = { DIV_AUD1, 0, 4), }; -static const struct samsung_gate_clock aud_gate_clks[] __initconst = { +static const struct samsung_gate_clock aud_gate_clks[] = { /* ENABLE_ACLK_AUD */ GATE(CLK_ACLK_INTR_CTRL, "aclk_intr_ctrl", "div_aclk_aud", ENABLE_ACLK_AUD, 12, 0, 0), @@ -3048,7 +3012,7 @@ static const struct samsung_gate_clock aud_gate_clks[] __initconst = { ENABLE_SCLK_AUD1, 0, CLK_IGNORE_UNUSED, 0), }; -static const struct samsung_cmu_info aud_cmu_info __initconst = { +static const struct samsung_cmu_info aud_cmu_info = { .mux_clks = aud_mux_clks, .nr_mux_clks = ARRAY_SIZE(aud_mux_clks), .div_clks = aud_div_clks, @@ -3089,24 +3053,24 @@ PNAME(mout_aclk_bus2_400_p) = { "oscclk", "aclk_bus2_400", }; ENABLE_IP_BUS0, \ ENABLE_IP_BUS1 -static const unsigned long bus01_clk_regs[] __initconst = { +static const unsigned long bus01_clk_regs[] = { CMU_BUS_COMMON_CLK_REGS, }; -static const unsigned long bus2_clk_regs[] __initconst = { +static const unsigned long bus2_clk_regs[] = { MUX_SEL_BUS2, MUX_ENABLE_BUS2, CMU_BUS_COMMON_CLK_REGS, }; -static const struct samsung_div_clock bus0_div_clks[] __initconst = { +static const struct samsung_div_clock bus0_div_clks[] = { /* DIV_BUS0 */ DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus0_133", "aclk_bus0_400", DIV_BUS, 0, 3), }; /* CMU_BUS0 clocks */ -static const struct samsung_gate_clock bus0_gate_clks[] __initconst = { +static const struct samsung_gate_clock bus0_gate_clks[] = { /* ENABLE_ACLK_BUS0 */ GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus0p", "div_pclk_bus0_133", ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0), @@ -3125,13 +3089,13 @@ static const struct samsung_gate_clock bus0_gate_clks[] __initconst = { }; /* CMU_BUS1 clocks */ -static const struct samsung_div_clock bus1_div_clks[] __initconst = { +static const struct samsung_div_clock bus1_div_clks[] = { /* DIV_BUS1 */ DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus1_133", "aclk_bus1_400", DIV_BUS, 0, 3), }; -static const struct samsung_gate_clock bus1_gate_clks[] __initconst = { +static const struct samsung_gate_clock bus1_gate_clks[] = { /* ENABLE_ACLK_BUS1 */ GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus1p", "div_pclk_bus1_133", ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0), @@ -3150,19 +3114,19 @@ static const struct samsung_gate_clock bus1_gate_clks[] __initconst = { }; /* CMU_BUS2 clocks */ -static const struct samsung_mux_clock bus2_mux_clks[] __initconst = { +static const struct samsung_mux_clock bus2_mux_clks[] = { /* MUX_SEL_BUS2 */ MUX(CLK_MOUT_ACLK_BUS2_400_USER, "mout_aclk_bus2_400_user", mout_aclk_bus2_400_p, MUX_SEL_BUS2, 0, 1), }; -static const struct samsung_div_clock bus2_div_clks[] __initconst = { +static const struct samsung_div_clock bus2_div_clks[] = { /* DIV_BUS2 */ DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus2_133", "mout_aclk_bus2_400_user", DIV_BUS, 0, 3), }; -static const struct samsung_gate_clock bus2_gate_clks[] __initconst = { +static const struct samsung_gate_clock bus2_gate_clks[] = { /* ENABLE_ACLK_BUS2 */ GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus2p", "div_pclk_bus2_133", ENABLE_ACLK_BUS, 3, CLK_IGNORE_UNUSED, 0), @@ -3191,19 +3155,19 @@ static const struct samsung_gate_clock bus2_gate_clks[] __initconst = { .nr_gate_clks = ARRAY_SIZE(bus##id##_gate_clks), \ .nr_clk_ids = BUSx_NR_CLK -static const struct samsung_cmu_info bus0_cmu_info __initconst = { +static const struct samsung_cmu_info bus0_cmu_info = { CMU_BUS_INFO_CLKS(0), .clk_regs = bus01_clk_regs, .nr_clk_regs = ARRAY_SIZE(bus01_clk_regs), }; -static const struct samsung_cmu_info bus1_cmu_info __initconst = { +static const struct samsung_cmu_info bus1_cmu_info = { CMU_BUS_INFO_CLKS(1), .clk_regs = bus01_clk_regs, .nr_clk_regs = ARRAY_SIZE(bus01_clk_regs), }; -static const struct samsung_cmu_info bus2_cmu_info __initconst = { +static const struct samsung_cmu_info bus2_cmu_info = { CMU_BUS_INFO_CLKS(2), .mux_clks = bus2_mux_clks, .nr_mux_clks = ARRAY_SIZE(bus2_mux_clks), @@ -3211,19 +3175,6 @@ static const struct samsung_cmu_info bus2_cmu_info __initconst = { .nr_clk_regs = ARRAY_SIZE(bus2_clk_regs), }; -#define exynos5433_cmu_bus_init(id) \ -static void __init exynos5433_cmu_bus##id##_init(struct device_node *np)\ -{ \ - samsung_cmu_register_one(np, &bus##id##_cmu_info); \ -} \ -CLK_OF_DECLARE(exynos5433_cmu_bus##id, \ - "samsung,exynos5433-cmu-bus"#id, \ - exynos5433_cmu_bus##id##_init) - -exynos5433_cmu_bus_init(0); -exynos5433_cmu_bus_init(1); -exynos5433_cmu_bus_init(2); - /* * Register offset definitions for CMU_G3D */ @@ -3247,7 +3198,7 @@ exynos5433_cmu_bus_init(2); #define CLKOUT_CMU_G3D_DIV_STAT 0x0c04 #define CLK_STOPCTRL 0x1000 -static const unsigned long g3d_clk_regs[] __initconst = { +static const unsigned long g3d_clk_regs[] = { G3D_PLL_LOCK, G3D_PLL_CON0, G3D_PLL_CON1, @@ -3274,12 +3225,12 @@ static const struct samsung_clk_reg_dump g3d_suspend_regs[] = { PNAME(mout_aclk_g3d_400_p) = { "mout_g3d_pll", "aclk_g3d_400", }; PNAME(mout_g3d_pll_p) = { "oscclk", "fout_g3d_pll", }; -static const struct samsung_pll_clock g3d_pll_clks[] __initconst = { +static const struct samsung_pll_clock g3d_pll_clks[] = { PLL(pll_35xx, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "oscclk", G3D_PLL_LOCK, G3D_PLL_CON0, exynos5433_pll_rates), }; -static const struct samsung_mux_clock g3d_mux_clks[] __initconst = { +static const struct samsung_mux_clock g3d_mux_clks[] = { /* MUX_SEL_G3D */ MUX_F(CLK_MOUT_ACLK_G3D_400, "mout_aclk_g3d_400", mout_aclk_g3d_400_p, MUX_SEL_G3D, 8, 1, CLK_SET_RATE_PARENT, 0), @@ -3287,7 +3238,7 @@ static const struct samsung_mux_clock g3d_mux_clks[] __initconst = { MUX_SEL_G3D, 0, 1, CLK_SET_RATE_PARENT, 0), }; -static const struct samsung_div_clock g3d_div_clks[] __initconst = { +static const struct samsung_div_clock g3d_div_clks[] = { /* DIV_G3D */ DIV(CLK_DIV_SCLK_HPM_G3D, "div_sclk_hpm_g3d", "mout_g3d_pll", DIV_G3D, 8, 2), @@ -3297,7 +3248,7 @@ static const struct samsung_div_clock g3d_div_clks[] __initconst = { 0, 3, CLK_SET_RATE_PARENT, 0), }; -static const struct samsung_gate_clock g3d_gate_clks[] __initconst = { +static const struct samsung_gate_clock g3d_gate_clks[] = { /* ENABLE_ACLK_G3D */ GATE(CLK_ACLK_BTS_G3D1, "aclk_bts_g3d1", "div_aclk_g3d", ENABLE_ACLK_G3D, 7, 0, 0), @@ -3331,7 +3282,7 @@ static const struct samsung_gate_clock g3d_gate_clks[] __initconst = { ENABLE_SCLK_G3D, 0, 0, 0), }; -static const struct samsung_cmu_info g3d_cmu_info __initconst = { +static const struct samsung_cmu_info g3d_cmu_info = { .pll_clks = g3d_pll_clks, .nr_pll_clks = ARRAY_SIZE(g3d_pll_clks), .mux_clks = g3d_mux_clks, @@ -3368,7 +3319,7 @@ static const struct samsung_cmu_info g3d_cmu_info __initconst = { #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL1 0x0b0c #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL2 0x0b10 -static const unsigned long gscl_clk_regs[] __initconst = { +static const unsigned long gscl_clk_regs[] = { MUX_SEL_GSCL, MUX_ENABLE_GSCL, ENABLE_ACLK_GSCL, @@ -3396,7 +3347,7 @@ static const struct samsung_clk_reg_dump gscl_suspend_regs[] = { PNAME(aclk_gscl_111_user_p) = { "oscclk", "aclk_gscl_111", }; PNAME(aclk_gscl_333_user_p) = { "oscclk", "aclk_gscl_333", }; -static const struct samsung_mux_clock gscl_mux_clks[] __initconst = { +static const struct samsung_mux_clock gscl_mux_clks[] = { /* MUX_SEL_GSCL */ MUX(CLK_MOUT_ACLK_GSCL_111_USER, "mout_aclk_gscl_111_user", aclk_gscl_111_user_p, MUX_SEL_GSCL, 4, 1), @@ -3404,7 +3355,7 @@ static const struct samsung_mux_clock gscl_mux_clks[] __initconst = { aclk_gscl_333_user_p, MUX_SEL_GSCL, 0, 1), }; -static const struct samsung_gate_clock gscl_gate_clks[] __initconst = { +static const struct samsung_gate_clock gscl_gate_clks[] = { /* ENABLE_ACLK_GSCL */ GATE(CLK_ACLK_BTS_GSCL2, "aclk_bts_gscl2", "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 11, 0, 0), @@ -3478,7 +3429,7 @@ static const struct samsung_gate_clock gscl_gate_clks[] __initconst = { ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2, 0, 0, 0), }; -static const struct samsung_cmu_info gscl_cmu_info __initconst = { +static const struct samsung_cmu_info gscl_cmu_info = { .mux_clks = gscl_mux_clks, .nr_mux_clks = ARRAY_SIZE(gscl_mux_clks), .gate_clks = gscl_gate_clks, @@ -3527,7 +3478,7 @@ static const struct samsung_cmu_info gscl_cmu_info __initconst = { #define APOLLO_INTR_SPREAD_USE_STANDBYWFI 0x1084 #define APOLLO_INTR_SPREAD_BLOCKING_DURATION 0x1088 -static const unsigned long apollo_clk_regs[] __initconst = { +static const unsigned long apollo_clk_regs[] = { APOLLO_PLL_LOCK, APOLLO_PLL_CON0, APOLLO_PLL_CON1, @@ -3562,12 +3513,12 @@ PNAME(mout_bus_pll_apollo_user_p) = { "oscclk", "sclk_bus_pll_apollo", }; PNAME(mout_apollo_p) = { "mout_apollo_pll", "mout_bus_pll_apollo_user", }; -static const struct samsung_pll_clock apollo_pll_clks[] __initconst = { +static const struct samsung_pll_clock apollo_pll_clks[] = { PLL(pll_35xx, CLK_FOUT_APOLLO_PLL, "fout_apollo_pll", "oscclk", APOLLO_PLL_LOCK, APOLLO_PLL_CON0, exynos5433_pll_rates), }; -static const struct samsung_mux_clock apollo_mux_clks[] __initconst = { +static const struct samsung_mux_clock apollo_mux_clks[] = { /* MUX_SEL_APOLLO0 */ MUX_F(CLK_MOUT_APOLLO_PLL, "mout_apollo_pll", mout_apollo_pll_p, MUX_SEL_APOLLO0, 0, 1, CLK_SET_RATE_PARENT | @@ -3582,7 +3533,7 @@ static const struct samsung_mux_clock apollo_mux_clks[] __initconst = { 0, 1, CLK_SET_RATE_PARENT, 0), }; -static const struct samsung_div_clock apollo_div_clks[] __initconst = { +static const struct samsung_div_clock apollo_div_clks[] = { /* DIV_APOLLO0 */ DIV_F(CLK_DIV_CNTCLK_APOLLO, "div_cntclk_apollo", "div_apollo2", DIV_APOLLO0, 24, 3, CLK_GET_RATE_NOCACHE, @@ -3613,7 +3564,7 @@ static const struct samsung_div_clock apollo_div_clks[] __initconst = { CLK_DIVIDER_READ_ONLY), }; -static const struct samsung_gate_clock apollo_gate_clks[] __initconst = { +static const struct samsung_gate_clock apollo_gate_clks[] = { /* ENABLE_ACLK_APOLLO */ GATE(CLK_ACLK_ASATBSLV_APOLLO_3_CSSYS, "aclk_asatbslv_apollo_3_cssys", "div_atclk_apollo", ENABLE_ACLK_APOLLO, @@ -3661,7 +3612,7 @@ static const struct samsung_gate_clock apollo_gate_clks[] __initconst = { #define E5433_APOLLO_DIV1(hpm, copy) \ (((hpm) << 4) | ((copy) << 0)) -static const struct exynos_cpuclk_cfg_data exynos5433_apolloclk_d[] __initconst = { +static const struct exynos_cpuclk_cfg_data exynos5433_apolloclk_d[] = { { 1300000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), }, { 1200000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), }, { 1100000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), }, @@ -3672,17 +3623,17 @@ static const struct exynos_cpuclk_cfg_data exynos5433_apolloclk_d[] __initconst { 600000, E5433_APOLLO_DIV0(3, 7, 7, 7, 1), E5433_APOLLO_DIV1(7, 1), }, { 500000, E5433_APOLLO_DIV0(3, 7, 7, 7, 1), E5433_APOLLO_DIV1(7, 1), }, { 400000, E5433_APOLLO_DIV0(3, 7, 7, 7, 1), E5433_APOLLO_DIV1(7, 1), }, - { 0 }, + { /* sentinel */ }, }; -static const struct samsung_cpu_clock apollo_cpu_clks[] __initconst = { +static const struct samsung_cpu_clock apollo_cpu_clks[] = { CPU_CLK(CLK_SCLK_APOLLO, "apolloclk", "mout_apollo_pll", "mout_bus_pll_apollo_user", CLK_CPU_HAS_E5433_REGS_LAYOUT, 0x200, exynos5433_apolloclk_d), }; -static const struct samsung_cmu_info apollo_cmu_info __initconst = { +static const struct samsung_cmu_info apollo_cmu_info = { .pll_clks = apollo_pll_clks, .nr_pll_clks = ARRAY_SIZE(apollo_pll_clks), .mux_clks = apollo_mux_clks, @@ -3734,7 +3685,7 @@ static const struct samsung_cmu_info apollo_cmu_info __initconst = { #define ATLAS_INTR_SPREAD_USE_STANDBYWFI 0x1084 #define ATLAS_INTR_SPREAD_BLOCKING_DURATION 0x1088 -static const unsigned long atlas_clk_regs[] __initconst = { +static const unsigned long atlas_clk_regs[] = { ATLAS_PLL_LOCK, ATLAS_PLL_CON0, ATLAS_PLL_CON1, @@ -3769,12 +3720,12 @@ PNAME(mout_bus_pll_atlas_user_p) = { "oscclk", "sclk_bus_pll_atlas", }; PNAME(mout_atlas_p) = { "mout_atlas_pll", "mout_bus_pll_atlas_user", }; -static const struct samsung_pll_clock atlas_pll_clks[] __initconst = { +static const struct samsung_pll_clock atlas_pll_clks[] = { PLL(pll_35xx, CLK_FOUT_ATLAS_PLL, "fout_atlas_pll", "oscclk", ATLAS_PLL_LOCK, ATLAS_PLL_CON0, exynos5433_pll_rates), }; -static const struct samsung_mux_clock atlas_mux_clks[] __initconst = { +static const struct samsung_mux_clock atlas_mux_clks[] = { /* MUX_SEL_ATLAS0 */ MUX_F(CLK_MOUT_ATLAS_PLL, "mout_atlas_pll", mout_atlas_pll_p, MUX_SEL_ATLAS0, 0, 1, CLK_SET_RATE_PARENT | @@ -3789,7 +3740,7 @@ static const struct samsung_mux_clock atlas_mux_clks[] __initconst = { 0, 1, CLK_SET_RATE_PARENT, 0), }; -static const struct samsung_div_clock atlas_div_clks[] __initconst = { +static const struct samsung_div_clock atlas_div_clks[] = { /* DIV_ATLAS0 */ DIV_F(CLK_DIV_CNTCLK_ATLAS, "div_cntclk_atlas", "div_atlas2", DIV_ATLAS0, 24, 3, CLK_GET_RATE_NOCACHE, @@ -3820,7 +3771,7 @@ static const struct samsung_div_clock atlas_div_clks[] __initconst = { CLK_DIVIDER_READ_ONLY), }; -static const struct samsung_gate_clock atlas_gate_clks[] __initconst = { +static const struct samsung_gate_clock atlas_gate_clks[] = { /* ENABLE_ACLK_ATLAS */ GATE(CLK_ACLK_ATB_AUD_CSSYS, "aclk_atb_aud_cssys", "div_atclk_atlas", ENABLE_ACLK_ATLAS, @@ -3894,7 +3845,7 @@ static const struct samsung_gate_clock atlas_gate_clks[] __initconst = { #define E5433_ATLAS_DIV1(hpm, copy) \ (((hpm) << 4) | ((copy) << 0)) -static const struct exynos_cpuclk_cfg_data exynos5433_atlasclk_d[] __initconst = { +static const struct exynos_cpuclk_cfg_data exynos5433_atlasclk_d[] = { { 1900000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), }, { 1800000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), }, { 1700000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), }, @@ -3910,17 +3861,17 @@ static const struct exynos_cpuclk_cfg_data exynos5433_atlasclk_d[] __initconst = { 700000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), }, { 600000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), }, { 500000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), }, - { 0 }, + { /* sentinel */ }, }; -static const struct samsung_cpu_clock atlas_cpu_clks[] __initconst = { +static const struct samsung_cpu_clock atlas_cpu_clks[] = { CPU_CLK(CLK_SCLK_ATLAS, "atlasclk", "mout_atlas_pll", "mout_bus_pll_atlas_user", CLK_CPU_HAS_E5433_REGS_LAYOUT, 0x200, exynos5433_atlasclk_d), }; -static const struct samsung_cmu_info atlas_cmu_info __initconst = { +static const struct samsung_cmu_info atlas_cmu_info = { .pll_clks = atlas_pll_clks, .nr_pll_clks = ARRAY_SIZE(atlas_pll_clks), .mux_clks = atlas_mux_clks, @@ -3962,7 +3913,7 @@ static const struct samsung_cmu_info atlas_cmu_info __initconst = { #define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER1 0x0b0c #define ENABLE_IP_MSCL_SECURE_SMMU_JPEG 0x0b10 -static const unsigned long mscl_clk_regs[] __initconst = { +static const unsigned long mscl_clk_regs[] = { MUX_SEL_MSCL0, MUX_SEL_MSCL1, MUX_ENABLE_MSCL0, @@ -3995,7 +3946,7 @@ PNAME(mout_aclk_mscl_400_user_p) = { "oscclk", "aclk_mscl_400", }; PNAME(mout_sclk_jpeg_p) = { "mout_sclk_jpeg_user", "mout_aclk_mscl_400_user", }; -static const struct samsung_mux_clock mscl_mux_clks[] __initconst = { +static const struct samsung_mux_clock mscl_mux_clks[] = { /* MUX_SEL_MSCL0 */ MUX(CLK_MOUT_SCLK_JPEG_USER, "mout_sclk_jpeg_user", mout_sclk_jpeg_user_p, MUX_SEL_MSCL0, 4, 1), @@ -4007,13 +3958,13 @@ static const struct samsung_mux_clock mscl_mux_clks[] __initconst = { MUX_SEL_MSCL1, 0, 1), }; -static const struct samsung_div_clock mscl_div_clks[] __initconst = { +static const struct samsung_div_clock mscl_div_clks[] = { /* DIV_MSCL */ DIV(CLK_DIV_PCLK_MSCL, "div_pclk_mscl", "mout_aclk_mscl_400_user", DIV_MSCL, 0, 3), }; -static const struct samsung_gate_clock mscl_gate_clks[] __initconst = { +static const struct samsung_gate_clock mscl_gate_clks[] = { /* ENABLE_ACLK_MSCL */ GATE(CLK_ACLK_BTS_JPEG, "aclk_bts_jpeg", "mout_aclk_mscl_400_user", ENABLE_ACLK_MSCL, 9, 0, 0), @@ -4091,7 +4042,7 @@ static const struct samsung_gate_clock mscl_gate_clks[] __initconst = { CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), }; -static const struct samsung_cmu_info mscl_cmu_info __initconst = { +static const struct samsung_cmu_info mscl_cmu_info = { .mux_clks = mscl_mux_clks, .nr_mux_clks = ARRAY_SIZE(mscl_mux_clks), .div_clks = mscl_div_clks, @@ -4122,7 +4073,7 @@ static const struct samsung_cmu_info mscl_cmu_info __initconst = { #define ENABLE_IP_MFC1 0x0b04 #define ENABLE_IP_MFC_SECURE_SMMU_MFC 0x0b08 -static const unsigned long mfc_clk_regs[] __initconst = { +static const unsigned long mfc_clk_regs[] = { MUX_SEL_MFC, MUX_ENABLE_MFC, DIV_MFC, @@ -4141,19 +4092,19 @@ static const struct samsung_clk_reg_dump mfc_suspend_regs[] = { PNAME(mout_aclk_mfc_400_user_p) = { "oscclk", "aclk_mfc_400", }; -static const struct samsung_mux_clock mfc_mux_clks[] __initconst = { +static const struct samsung_mux_clock mfc_mux_clks[] = { /* MUX_SEL_MFC */ MUX(CLK_MOUT_ACLK_MFC_400_USER, "mout_aclk_mfc_400_user", mout_aclk_mfc_400_user_p, MUX_SEL_MFC, 0, 0), }; -static const struct samsung_div_clock mfc_div_clks[] __initconst = { +static const struct samsung_div_clock mfc_div_clks[] = { /* DIV_MFC */ DIV(CLK_DIV_PCLK_MFC, "div_pclk_mfc", "mout_aclk_mfc_400_user", DIV_MFC, 0, 2), }; -static const struct samsung_gate_clock mfc_gate_clks[] __initconst = { +static const struct samsung_gate_clock mfc_gate_clks[] = { /* ENABLE_ACLK_MFC */ GATE(CLK_ACLK_BTS_MFC_1, "aclk_bts_mfc_1", "mout_aclk_mfc_400_user", ENABLE_ACLK_MFC, 6, 0, 0), @@ -4199,7 +4150,7 @@ static const struct samsung_gate_clock mfc_gate_clks[] __initconst = { 0, CLK_IGNORE_UNUSED, 0), }; -static const struct samsung_cmu_info mfc_cmu_info __initconst = { +static const struct samsung_cmu_info mfc_cmu_info = { .mux_clks = mfc_mux_clks, .nr_mux_clks = ARRAY_SIZE(mfc_mux_clks), .div_clks = mfc_div_clks, @@ -4230,7 +4181,7 @@ static const struct samsung_cmu_info mfc_cmu_info __initconst = { #define ENABLE_IP_HEVC1 0x0b04 #define ENABLE_IP_HEVC_SECURE_SMMU_HEVC 0x0b08 -static const unsigned long hevc_clk_regs[] __initconst = { +static const unsigned long hevc_clk_regs[] = { MUX_SEL_HEVC, MUX_ENABLE_HEVC, DIV_HEVC, @@ -4249,19 +4200,19 @@ static const struct samsung_clk_reg_dump hevc_suspend_regs[] = { PNAME(mout_aclk_hevc_400_user_p) = { "oscclk", "aclk_hevc_400", }; -static const struct samsung_mux_clock hevc_mux_clks[] __initconst = { +static const struct samsung_mux_clock hevc_mux_clks[] = { /* MUX_SEL_HEVC */ MUX(CLK_MOUT_ACLK_HEVC_400_USER, "mout_aclk_hevc_400_user", mout_aclk_hevc_400_user_p, MUX_SEL_HEVC, 0, 0), }; -static const struct samsung_div_clock hevc_div_clks[] __initconst = { +static const struct samsung_div_clock hevc_div_clks[] = { /* DIV_HEVC */ DIV(CLK_DIV_PCLK_HEVC, "div_pclk_hevc", "mout_aclk_hevc_400_user", DIV_HEVC, 0, 2), }; -static const struct samsung_gate_clock hevc_gate_clks[] __initconst = { +static const struct samsung_gate_clock hevc_gate_clks[] = { /* ENABLE_ACLK_HEVC */ GATE(CLK_ACLK_BTS_HEVC_1, "aclk_bts_hevc_1", "mout_aclk_hevc_400_user", ENABLE_ACLK_HEVC, 6, 0, 0), @@ -4309,7 +4260,7 @@ static const struct samsung_gate_clock hevc_gate_clks[] __initconst = { 0, CLK_IGNORE_UNUSED, 0), }; -static const struct samsung_cmu_info hevc_cmu_info __initconst = { +static const struct samsung_cmu_info hevc_cmu_info = { .mux_clks = hevc_mux_clks, .nr_mux_clks = ARRAY_SIZE(hevc_mux_clks), .div_clks = hevc_div_clks, @@ -4342,7 +4293,7 @@ static const struct samsung_cmu_info hevc_cmu_info __initconst = { #define ENABLE_IP_ISP2 0x0b08 #define ENABLE_IP_ISP3 0x0b0c -static const unsigned long isp_clk_regs[] __initconst = { +static const unsigned long isp_clk_regs[] = { MUX_SEL_ISP, MUX_ENABLE_ISP, DIV_ISP, @@ -4364,7 +4315,7 @@ static const struct samsung_clk_reg_dump isp_suspend_regs[] = { PNAME(mout_aclk_isp_dis_400_user_p) = { "oscclk", "aclk_isp_dis_400", }; PNAME(mout_aclk_isp_400_user_p) = { "oscclk", "aclk_isp_400", }; -static const struct samsung_mux_clock isp_mux_clks[] __initconst = { +static const struct samsung_mux_clock isp_mux_clks[] = { /* MUX_SEL_ISP */ MUX(CLK_MOUT_ACLK_ISP_DIS_400_USER, "mout_aclk_isp_dis_400_user", mout_aclk_isp_dis_400_user_p, MUX_SEL_ISP, 4, 0), @@ -4372,7 +4323,7 @@ static const struct samsung_mux_clock isp_mux_clks[] __initconst = { mout_aclk_isp_400_user_p, MUX_SEL_ISP, 0, 0), }; -static const struct samsung_div_clock isp_div_clks[] __initconst = { +static const struct samsung_div_clock isp_div_clks[] = { /* DIV_ISP */ DIV(CLK_DIV_PCLK_ISP_DIS, "div_pclk_isp_dis", "mout_aclk_isp_dis_400_user", DIV_ISP, 12, 3), @@ -4384,7 +4335,7 @@ static const struct samsung_div_clock isp_div_clks[] __initconst = { "mout_aclk_isp_400_user", DIV_ISP, 0, 3), }; -static const struct samsung_gate_clock isp_gate_clks[] __initconst = { +static const struct samsung_gate_clock isp_gate_clks[] = { /* ENABLE_ACLK_ISP0 */ GATE(CLK_ACLK_ISP_D_GLUE, "aclk_isp_d_glue", "mout_aclk_isp_400_user", ENABLE_ACLK_ISP0, 6, CLK_IGNORE_UNUSED, 0), @@ -4562,7 +4513,7 @@ static const struct samsung_gate_clock isp_gate_clks[] __initconst = { 0, CLK_IGNORE_UNUSED, 0), }; -static const struct samsung_cmu_info isp_cmu_info __initconst = { +static const struct samsung_cmu_info isp_cmu_info = { .mux_clks = isp_mux_clks, .nr_mux_clks = ARRAY_SIZE(isp_mux_clks), .div_clks = isp_div_clks, @@ -4614,7 +4565,7 @@ static const struct samsung_cmu_info isp_cmu_info __initconst = { #define ENABLE_IP_CAM02 0X0b08 #define ENABLE_IP_CAM03 0X0b0C -static const unsigned long cam0_clk_regs[] __initconst = { +static const unsigned long cam0_clk_regs[] = { MUX_SEL_CAM00, MUX_SEL_CAM01, MUX_SEL_CAM02, @@ -4707,14 +4658,14 @@ PNAME(mout_sclk_pixelasync_lite_c_init_a_p) = { "mout_aclk_cam0_552_user", "mout_aclk_cam0_400_user", }; -static const struct samsung_fixed_rate_clock cam0_fixed_clks[] __initconst = { +static const struct samsung_fixed_rate_clock cam0_fixed_clks[] = { FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S4_PHY, "phyclk_rxbyteclkhs0_s4_phy", NULL, 0, 100000000), FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S2A_PHY, "phyclk_rxbyteclkhs0_s2a_phy", NULL, 0, 100000000), }; -static const struct samsung_mux_clock cam0_mux_clks[] __initconst = { +static const struct samsung_mux_clock cam0_mux_clks[] = { /* MUX_SEL_CAM00 */ MUX(CLK_MOUT_ACLK_CAM0_333_USER, "mout_aclk_cam0_333_user", mout_aclk_cam0_333_user_p, MUX_SEL_CAM00, 8, 1), @@ -4788,7 +4739,7 @@ static const struct samsung_mux_clock cam0_mux_clks[] __initconst = { MUX_SEL_CAM04, 0, 1), }; -static const struct samsung_div_clock cam0_div_clks[] __initconst = { +static const struct samsung_div_clock cam0_div_clks[] = { /* DIV_CAM00 */ DIV(CLK_DIV_PCLK_CAM0_50, "div_pclk_cam0_50", "div_aclk_cam0_200", DIV_CAM00, 8, 2), @@ -4835,7 +4786,7 @@ static const struct samsung_div_clock cam0_div_clks[] __initconst = { "mout_sclk_pixelasync_lite_c_init_b", DIV_CAM03, 0, 3), }; -static const struct samsung_gate_clock cam0_gate_clks[] __initconst = { +static const struct samsung_gate_clock cam0_gate_clks[] = { /* ENABLE_ACLK_CAM00 */ GATE(CLK_ACLK_CSIS1, "aclk_csis1", "div_aclk_csis1", ENABLE_ACLK_CAM00, 6, 0, 0), @@ -5042,7 +4993,7 @@ static const struct samsung_gate_clock cam0_gate_clks[] __initconst = { ENABLE_SCLK_CAM0, 0, 0, 0), }; -static const struct samsung_cmu_info cam0_cmu_info __initconst = { +static const struct samsung_cmu_info cam0_cmu_info = { .mux_clks = cam0_mux_clks, .nr_mux_clks = ARRAY_SIZE(cam0_mux_clks), .div_clks = cam0_div_clks, @@ -5085,7 +5036,7 @@ static const struct samsung_cmu_info cam0_cmu_info __initconst = { #define ENABLE_IP_CAM11 0X0b04 #define ENABLE_IP_CAM12 0X0b08 -static const unsigned long cam1_clk_regs[] __initconst = { +static const unsigned long cam1_clk_regs[] = { MUX_SEL_CAM10, MUX_SEL_CAM11, MUX_SEL_CAM12, @@ -5137,12 +5088,12 @@ PNAME(mout_aclk_lite_c_b_p) = { "mout_aclk_lite_c_a", PNAME(mout_aclk_lite_c_a_p) = { "mout_aclk_cam1_552_user", "mout_aclk_cam1_400_user", }; -static const struct samsung_fixed_rate_clock cam1_fixed_clks[] __initconst = { +static const struct samsung_fixed_rate_clock cam1_fixed_clks[] = { FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S2B, "phyclk_rxbyteclkhs0_s2b_phy", NULL, 0, 100000000), }; -static const struct samsung_mux_clock cam1_mux_clks[] __initconst = { +static const struct samsung_mux_clock cam1_mux_clks[] = { /* MUX_SEL_CAM10 */ MUX(CLK_MOUT_SCLK_ISP_UART_USER, "mout_sclk_isp_uart_user", mout_sclk_isp_uart_user_p, MUX_SEL_CAM10, 20, 1), @@ -5178,7 +5129,7 @@ static const struct samsung_mux_clock cam1_mux_clks[] __initconst = { MUX_SEL_CAM12, 0, 1), }; -static const struct samsung_div_clock cam1_div_clks[] __initconst = { +static const struct samsung_div_clock cam1_div_clks[] = { /* DIV_CAM10 */ DIV(CLK_DIV_SCLK_ISP_MPWM, "div_sclk_isp_mpwm", "div_pclk_cam1_83", DIV_CAM10, 16, 2), @@ -5202,7 +5153,7 @@ static const struct samsung_div_clock cam1_div_clks[] __initconst = { DIV_CAM11, 0, 3), }; -static const struct samsung_gate_clock cam1_gate_clks[] __initconst = { +static const struct samsung_gate_clock cam1_gate_clks[] = { /* ENABLE_ACLK_CAM10 */ GATE(CLK_ACLK_ISP_GIC, "aclk_isp_gic", "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM10, 4, 0, 0), @@ -5417,7 +5368,7 @@ static const struct samsung_gate_clock cam1_gate_clks[] __initconst = { ENABLE_SCLK_CAM1, 0, 0, 0), }; -static const struct samsung_cmu_info cam1_cmu_info __initconst = { +static const struct samsung_cmu_info cam1_cmu_info = { .mux_clks = cam1_mux_clks, .nr_mux_clks = ARRAY_SIZE(cam1_mux_clks), .div_clks = cam1_div_clks, @@ -5440,12 +5391,12 @@ static const struct samsung_cmu_info cam1_cmu_info __initconst = { #define ENABLE_ACLK_IMEM_SLIMSSS 0x080c #define ENABLE_PCLK_IMEM_SLIMSSS 0x0908 -static const unsigned long imem_clk_regs[] __initconst = { +static const unsigned long imem_clk_regs[] = { ENABLE_ACLK_IMEM_SLIMSSS, ENABLE_PCLK_IMEM_SLIMSSS, }; -static const struct samsung_gate_clock imem_gate_clks[] __initconst = { +static const struct samsung_gate_clock imem_gate_clks[] = { /* ENABLE_ACLK_IMEM_SLIMSSS */ GATE(CLK_ACLK_SLIMSSS, "aclk_slimsss", "aclk_imem_sssx_266", ENABLE_ACLK_IMEM_SLIMSSS, 0, CLK_IGNORE_UNUSED, 0), @@ -5455,7 +5406,7 @@ static const struct samsung_gate_clock imem_gate_clks[] __initconst = { ENABLE_PCLK_IMEM_SLIMSSS, 0, CLK_IGNORE_UNUSED, 0), }; -static const struct samsung_cmu_info imem_cmu_info __initconst = { +static const struct samsung_cmu_info imem_cmu_info = { .gate_clks = imem_gate_clks, .nr_gate_clks = ARRAY_SIZE(imem_gate_clks), .nr_clk_ids = IMEM_NR_CLK, @@ -5520,7 +5471,7 @@ static int __maybe_unused exynos5433_cmu_resume(struct device *dev) return 0; } -static int __init exynos5433_cmu_probe(struct platform_device *pdev) +static int exynos5433_cmu_probe(struct platform_device *pdev) { const struct samsung_cmu_info *info; struct exynos5433_cmu_data *data; @@ -5663,11 +5614,35 @@ static const struct of_device_id exynos5433_cmu_of_match[] = { .compatible = "samsung,exynos5433-cmu-imem", .data = &imem_cmu_info, }, { - .compatible = "samsung,exynos5433-cmu-atlas", - .data = &atlas_cmu_info, + .compatible = "samsung,exynos5433-cmu-top", + .data = &top_cmu_info + }, { + .compatible = "samsung,exynos5433-cmu-cpif", + .data = &cpif_cmu_info + }, { + .compatible = "samsung,exynos5433-cmu-mif", + .data = &mif_cmu_info + }, { + .compatible = "samsung,exynos5433-cmu-peric", + .data = &peric_cmu_info, + }, { + .compatible = "samsung,exynos5433-cmu-peris", + .data = &peris_cmu_info, + }, { + .compatible = "samsung,exynos5433-cmu-bus0", + .data = &bus0_cmu_info, + }, { + .compatible = "samsung,exynos5433-cmu-bus1", + .data = &bus1_cmu_info, + }, { + .compatible = "samsung,exynos5433-cmu-bus2", + .data = &bus2_cmu_info, }, { .compatible = "samsung,exynos5433-cmu-apollo", .data = &apollo_cmu_info, + }, { + .compatible = "samsung,exynos5433-cmu-atlas", + .data = &atlas_cmu_info, }, { }, }; @@ -5689,8 +5664,8 @@ static struct platform_driver exynos5433_cmu_driver __refdata = { .probe = exynos5433_cmu_probe, }; -static int __init exynos5433_cmu_init(void) -{ - return platform_driver_register(&exynos5433_cmu_driver); -} -core_initcall(exynos5433_cmu_init); +module_platform_driver(exynos5433_cmu_driver); + +MODULE_AUTHOR("Chanwoo Choi "); +MODULE_DESCRIPTION("Samsung Exynos5433 ARMv8-family clock driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c index 4a5d2a914bd6..d2cdd3eec190 100644 --- a/drivers/clk/samsung/clk-exynos7.c +++ b/drivers/clk/samsung/clk-exynos7.c @@ -6,6 +6,9 @@ #include #include +#include +#include +#include #include "clk.h" #include @@ -183,7 +186,7 @@ static const struct samsung_pll_clock topc_pll_clks[] __initconst = { AUD_PLL_CON0, pll1460x_24mhz_tbl), }; -static const struct samsung_cmu_info topc_cmu_info __initconst = { +static const struct samsung_cmu_info topc_cmu_info = { .pll_clks = topc_pll_clks, .nr_pll_clks = ARRAY_SIZE(topc_pll_clks), .mux_clks = topc_mux_clks, @@ -199,14 +202,6 @@ static const struct samsung_cmu_info topc_cmu_info __initconst = { .nr_clk_regs = ARRAY_SIZE(topc_clk_regs), }; -static void __init exynos7_clk_topc_init(struct device_node *np) -{ - samsung_cmu_register_one(np, &topc_cmu_info); -} - -CLK_OF_DECLARE(exynos7_clk_topc, "samsung,exynos7-clock-topc", - exynos7_clk_topc_init); - /* Register Offset definitions for CMU_TOP0 (0x105D0000) */ #define MUX_SEL_TOP00 0x0200 #define MUX_SEL_TOP01 0x0204 @@ -377,7 +372,7 @@ static const struct samsung_fixed_factor_clock top0_fixed_factor_clks[] __initco FFACTOR(0, "ffac_top0_mfc_pll_div2", "mout_top0_mfc_pll_user", 1, 2, 0), }; -static const struct samsung_cmu_info top0_cmu_info __initconst = { +static const struct samsung_cmu_info top0_cmu_info = { .mux_clks = top0_mux_clks, .nr_mux_clks = ARRAY_SIZE(top0_mux_clks), .div_clks = top0_div_clks, @@ -391,14 +386,6 @@ static const struct samsung_cmu_info top0_cmu_info __initconst = { .nr_clk_regs = ARRAY_SIZE(top0_clk_regs), }; -static void __init exynos7_clk_top0_init(struct device_node *np) -{ - samsung_cmu_register_one(np, &top0_cmu_info); -} - -CLK_OF_DECLARE(exynos7_clk_top0, "samsung,exynos7-clock-top0", - exynos7_clk_top0_init); - /* Register Offset definitions for CMU_TOP1 (0x105E0000) */ #define MUX_SEL_TOP10 0x0200 #define MUX_SEL_TOP11 0x0204 @@ -559,7 +546,7 @@ static const struct samsung_fixed_factor_clock top1_fixed_factor_clks[] __initco FFACTOR(0, "ffac_top1_mfc_pll_div2", "mout_top1_mfc_pll_user", 1, 2, 0), }; -static const struct samsung_cmu_info top1_cmu_info __initconst = { +static const struct samsung_cmu_info top1_cmu_info = { .mux_clks = top1_mux_clks, .nr_mux_clks = ARRAY_SIZE(top1_mux_clks), .div_clks = top1_div_clks, @@ -573,14 +560,6 @@ static const struct samsung_cmu_info top1_cmu_info __initconst = { .nr_clk_regs = ARRAY_SIZE(top1_clk_regs), }; -static void __init exynos7_clk_top1_init(struct device_node *np) -{ - samsung_cmu_register_one(np, &top1_cmu_info); -} - -CLK_OF_DECLARE(exynos7_clk_top1, "samsung,exynos7-clock-top1", - exynos7_clk_top1_init); - /* Register Offset definitions for CMU_CCORE (0x105B0000) */ #define MUX_SEL_CCORE 0x0200 #define DIV_CCORE 0x0600 @@ -608,7 +587,7 @@ static const struct samsung_gate_clock ccore_gate_clks[] __initconst = { ENABLE_PCLK_CCORE, 8, 0, 0), }; -static const struct samsung_cmu_info ccore_cmu_info __initconst = { +static const struct samsung_cmu_info ccore_cmu_info = { .mux_clks = ccore_mux_clks, .nr_mux_clks = ARRAY_SIZE(ccore_mux_clks), .gate_clks = ccore_gate_clks, @@ -618,14 +597,6 @@ static const struct samsung_cmu_info ccore_cmu_info __initconst = { .nr_clk_regs = ARRAY_SIZE(ccore_clk_regs), }; -static void __init exynos7_clk_ccore_init(struct device_node *np) -{ - samsung_cmu_register_one(np, &ccore_cmu_info); -} - -CLK_OF_DECLARE(exynos7_clk_ccore, "samsung,exynos7-clock-ccore", - exynos7_clk_ccore_init); - /* Register Offset definitions for CMU_PERIC0 (0x13610000) */ #define MUX_SEL_PERIC0 0x0200 #define ENABLE_PCLK_PERIC0 0x0900 @@ -675,7 +646,7 @@ static const struct samsung_gate_clock peric0_gate_clks[] __initconst = { GATE(SCLK_PWM, "sclk_pwm", "fin_pll", ENABLE_SCLK_PERIC0, 21, 0, 0), }; -static const struct samsung_cmu_info peric0_cmu_info __initconst = { +static const struct samsung_cmu_info peric0_cmu_info = { .mux_clks = peric0_mux_clks, .nr_mux_clks = ARRAY_SIZE(peric0_mux_clks), .gate_clks = peric0_gate_clks, @@ -685,11 +656,6 @@ static const struct samsung_cmu_info peric0_cmu_info __initconst = { .nr_clk_regs = ARRAY_SIZE(peric0_clk_regs), }; -static void __init exynos7_clk_peric0_init(struct device_node *np) -{ - samsung_cmu_register_one(np, &peric0_cmu_info); -} - /* Register Offset definitions for CMU_PERIC1 (0x14C80000) */ #define MUX_SEL_PERIC10 0x0200 #define MUX_SEL_PERIC11 0x0204 @@ -697,8 +663,6 @@ static void __init exynos7_clk_peric0_init(struct device_node *np) #define ENABLE_PCLK_PERIC1 0x0900 #define ENABLE_SCLK_PERIC10 0x0A00 -CLK_OF_DECLARE(exynos7_clk_peric0, "samsung,exynos7-clock-peric0", - exynos7_clk_peric0_init); /* List of parent clocks for Muxes in CMU_PERIC1 */ PNAME(mout_aclk_peric1_66_user_p) = { "fin_pll", "aclk_peric1_66" }; @@ -799,7 +763,7 @@ static const struct samsung_gate_clock peric1_gate_clks[] __initconst = { ENABLE_SCLK_PERIC10, 19, CLK_SET_RATE_PARENT, 0), }; -static const struct samsung_cmu_info peric1_cmu_info __initconst = { +static const struct samsung_cmu_info peric1_cmu_info = { .mux_clks = peric1_mux_clks, .nr_mux_clks = ARRAY_SIZE(peric1_mux_clks), .gate_clks = peric1_gate_clks, @@ -809,14 +773,6 @@ static const struct samsung_cmu_info peric1_cmu_info __initconst = { .nr_clk_regs = ARRAY_SIZE(peric1_clk_regs), }; -static void __init exynos7_clk_peric1_init(struct device_node *np) -{ - samsung_cmu_register_one(np, &peric1_cmu_info); -} - -CLK_OF_DECLARE(exynos7_clk_peric1, "samsung,exynos7-clock-peric1", - exynos7_clk_peric1_init); - /* Register Offset definitions for CMU_PERIS (0x10040000) */ #define MUX_SEL_PERIS 0x0200 #define ENABLE_PCLK_PERIS 0x0900 @@ -854,7 +810,7 @@ static const struct samsung_gate_clock peris_gate_clks[] __initconst = { GATE(SCLK_TMU, "sclk_tmu", "fin_pll", ENABLE_SCLK_PERIS, 10, 0, 0), }; -static const struct samsung_cmu_info peris_cmu_info __initconst = { +static const struct samsung_cmu_info peris_cmu_info = { .mux_clks = peris_mux_clks, .nr_mux_clks = ARRAY_SIZE(peris_mux_clks), .gate_clks = peris_gate_clks, @@ -864,14 +820,6 @@ static const struct samsung_cmu_info peris_cmu_info __initconst = { .nr_clk_regs = ARRAY_SIZE(peris_clk_regs), }; -static void __init exynos7_clk_peris_init(struct device_node *np) -{ - samsung_cmu_register_one(np, &peris_cmu_info); -} - -CLK_OF_DECLARE(exynos7_clk_peris, "samsung,exynos7-clock-peris", - exynos7_clk_peris_init); - /* Register Offset definitions for CMU_FSYS0 (0x10E90000) */ #define MUX_SEL_FSYS00 0x0200 #define MUX_SEL_FSYS01 0x0204 @@ -962,7 +910,7 @@ static const struct samsung_gate_clock fsys0_gate_clks[] __initconst = { ENABLE_SCLK_FSYS04, 28, 0, 0), }; -static const struct samsung_cmu_info fsys0_cmu_info __initconst = { +static const struct samsung_cmu_info fsys0_cmu_info = { .fixed_clks = fixed_rate_clks_fsys0, .nr_fixed_clks = ARRAY_SIZE(fixed_rate_clks_fsys0), .mux_clks = fsys0_mux_clks, @@ -974,14 +922,6 @@ static const struct samsung_cmu_info fsys0_cmu_info __initconst = { .nr_clk_regs = ARRAY_SIZE(fsys0_clk_regs), }; -static void __init exynos7_clk_fsys0_init(struct device_node *np) -{ - samsung_cmu_register_one(np, &fsys0_cmu_info); -} - -CLK_OF_DECLARE(exynos7_clk_fsys0, "samsung,exynos7-clock-fsys0", - exynos7_clk_fsys0_init); - /* Register Offset definitions for CMU_FSYS1 (0x156E0000) */ #define MUX_SEL_FSYS10 0x0200 #define MUX_SEL_FSYS11 0x0204 @@ -1091,7 +1031,7 @@ static const struct samsung_gate_clock fsys1_gate_clks[] __initconst = { ENABLE_SCLK_FSYS13, 24, CLK_IGNORE_UNUSED, 0), }; -static const struct samsung_cmu_info fsys1_cmu_info __initconst = { +static const struct samsung_cmu_info fsys1_cmu_info = { .fixed_clks = fixed_rate_clks_fsys1, .nr_fixed_clks = ARRAY_SIZE(fixed_rate_clks_fsys1), .mux_clks = fsys1_mux_clks, @@ -1105,14 +1045,6 @@ static const struct samsung_cmu_info fsys1_cmu_info __initconst = { .nr_clk_regs = ARRAY_SIZE(fsys1_clk_regs), }; -static void __init exynos7_clk_fsys1_init(struct device_node *np) -{ - samsung_cmu_register_one(np, &fsys1_cmu_info); -} - -CLK_OF_DECLARE(exynos7_clk_fsys1, "samsung,exynos7-clock-fsys1", - exynos7_clk_fsys1_init); - #define MUX_SEL_MSCL 0x0200 #define DIV_MSCL 0x0600 #define ENABLE_ACLK_MSCL 0x0800 @@ -1206,7 +1138,7 @@ static const struct samsung_gate_clock mscl_gate_clks[] __initconst = { ENABLE_PCLK_MSCL, 20, 0, 0), }; -static const struct samsung_cmu_info mscl_cmu_info __initconst = { +static const struct samsung_cmu_info mscl_cmu_info = { .mux_clks = mscl_mux_clks, .nr_mux_clks = ARRAY_SIZE(mscl_mux_clks), .div_clks = mscl_div_clks, @@ -1218,14 +1150,6 @@ static const struct samsung_cmu_info mscl_cmu_info __initconst = { .nr_clk_regs = ARRAY_SIZE(mscl_clk_regs), }; -static void __init exynos7_clk_mscl_init(struct device_node *np) -{ - samsung_cmu_register_one(np, &mscl_cmu_info); -} - -CLK_OF_DECLARE(exynos7_clk_mscl, "samsung,exynos7-clock-mscl", - exynos7_clk_mscl_init); - /* Register Offset definitions for CMU_AUD (0x114C0000) */ #define MUX_SEL_AUD 0x0200 #define DIV_AUD0 0x0600 @@ -1240,7 +1164,7 @@ CLK_OF_DECLARE(exynos7_clk_mscl, "samsung,exynos7-clock-mscl", PNAME(mout_aud_pll_user_p) = { "fin_pll", "fout_aud_pll" }; PNAME(mout_aud_group_p) = { "dout_aud_cdclk", "ioclk_audiocdclk0" }; -static const unsigned long aud_clk_regs[] __initconst = { +static const unsigned long aud_clk_regs[] = { MUX_SEL_AUD, DIV_AUD0, DIV_AUD1, @@ -1249,13 +1173,13 @@ static const unsigned long aud_clk_regs[] __initconst = { ENABLE_SCLK_AUD, }; -static const struct samsung_mux_clock aud_mux_clks[] __initconst = { +static const struct samsung_mux_clock aud_mux_clks[] = { MUX(0, "mout_sclk_i2s", mout_aud_group_p, MUX_SEL_AUD, 12, 1), MUX(0, "mout_sclk_pcm", mout_aud_group_p, MUX_SEL_AUD, 16, 1), MUX(0, "mout_aud_pll_user", mout_aud_pll_user_p, MUX_SEL_AUD, 20, 1), }; -static const struct samsung_div_clock aud_div_clks[] __initconst = { +static const struct samsung_div_clock aud_div_clks[] = { DIV(0, "dout_aud_ca5", "mout_aud_pll_user", DIV_AUD0, 0, 4), DIV(0, "dout_aclk_aud", "dout_aud_ca5", DIV_AUD0, 4, 4), DIV(0, "dout_aud_pclk_dbg", "dout_aud_ca5", DIV_AUD0, 8, 4), @@ -1267,7 +1191,7 @@ static const struct samsung_div_clock aud_div_clks[] __initconst = { DIV(0, "dout_aud_cdclk", "mout_aud_pll_user", DIV_AUD1, 24, 4), }; -static const struct samsung_gate_clock aud_gate_clks[] __initconst = { +static const struct samsung_gate_clock aud_gate_clks[] = { GATE(SCLK_PCM, "sclk_pcm", "dout_sclk_pcm", ENABLE_SCLK_AUD, 27, CLK_SET_RATE_PARENT, 0), GATE(SCLK_I2S, "sclk_i2s", "dout_sclk_i2s", @@ -1295,7 +1219,7 @@ static const struct samsung_gate_clock aud_gate_clks[] __initconst = { GATE(ACLK_ADMA, "aclk_dmac", "dout_aclk_aud", ENABLE_ACLK_AUD, 31, 0, 0), }; -static const struct samsung_cmu_info aud_cmu_info __initconst = { +static const struct samsung_cmu_info aud_cmu_info = { .mux_clks = aud_mux_clks, .nr_mux_clks = ARRAY_SIZE(aud_mux_clks), .div_clks = aud_div_clks, @@ -1307,10 +1231,67 @@ static const struct samsung_cmu_info aud_cmu_info __initconst = { .nr_clk_regs = ARRAY_SIZE(aud_clk_regs), }; -static void __init exynos7_clk_aud_init(struct device_node *np) +static int exynos7_cmu_probe(struct platform_device *pdev) { - samsung_cmu_register_one(np, &aud_cmu_info); + struct device *dev = &pdev->dev; + const struct samsung_cmu_info *info; + + info = of_device_get_match_data(dev); + if (info) + samsung_cmu_register_one(dev->of_node, info); + + return 0; } -CLK_OF_DECLARE(exynos7_clk_aud, "samsung,exynos7-clock-aud", - exynos7_clk_aud_init); +static const struct of_device_id exynos7_cmu_of_match[] = { + { + .compatible = "samsung,exynos7-clock-aud", + .data = &aud_cmu_info, + }, { + .compatible = "samsung,exynos7-clock-mscl", + .data = &mscl_cmu_info, + }, { + .compatible = "samsung,exynos7-clock-fsys1", + .data = &fsys1_cmu_info, + }, { + .compatible = "samsung,exynos7-clock-fsys0", + .data = &fsys0_cmu_info, + }, { + .compatible = "samsung,exynos7-clock-peris", + .data = &peris_cmu_info, + }, { + .compatible = "samsung,exynos7-clock-peric1", + .data = &peric1_cmu_info, + }, { + .compatible = "samsung,exynos7-clock-peric0", + .data = &peric0_cmu_info, + }, { + .compatible = "samsung,exynos7-clock-ccore", + .data = &ccore_cmu_info, + }, { + .compatible = "samsung,exynos7-clock-top1", + .data = &top1_cmu_info, + }, { + .compatible = "samsung,exynos7-clock-top0", + .data = &top0_cmu_info, + }, { + .compatible = "samsung,exynos7-clock-topc", + .data = &topc_cmu_info, + }, +}; + +static struct platform_driver exynos7_cmu_driver __refdata = { + .driver = { + .name = "exynos7-clock", + .of_match_table = exynos7_cmu_of_match, + .suppress_bind_attrs = true, + }, + .probe = exynos7_cmu_probe, +}; + +module_platform_driver(exynos7_cmu_driver); + +MODULE_DESCRIPTION("Samsung Exynos7 ARMv8-family clock driver"); +MODULE_AUTHOR("Naveen Krishna Ch "); +MODULE_AUTHOR("Alim Akhtar "); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index 5873a9354b50..7124d831d484 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -6,6 +6,7 @@ * This file contains the utility functions to register the pll clocks. */ +#include #include #include #include @@ -93,7 +94,7 @@ static int samsung_pll_lock_wait(struct samsung_clk_pll *pll, * Exynos SoC variants. Single register read time was usually in range * 0.4...1.5 us, never less than 0.4 us. */ - if (pll_early_timeout || timekeeping_suspended) { + if (pll_early_timeout || timekeeping_is_suspended()) { i = PLL_TIMEOUT_LOOPS; while (i-- > 0) { if (readl_relaxed(pll->con_reg) & reg_mask) @@ -1392,7 +1393,7 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, samsung_clk_add_lookup(ctx, &pll->hw, pll_clk->id); } -void __init samsung_clk_register_pll(struct samsung_clk_provider *ctx, +void samsung_clk_register_pll(struct samsung_clk_provider *ctx, const struct samsung_pll_clock *pll_list, unsigned int nr_pll, void __iomem *base) { @@ -1401,3 +1402,4 @@ void __init samsung_clk_register_pll(struct samsung_clk_provider *ctx, for (cnt = 0; cnt < nr_pll; cnt++) _samsung_clk_register_pll(ctx, &pll_list[cnt], base); } +EXPORT_SYMBOL_GPL(samsung_clk_register_pll); diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c index 336243c6f120..478a25ac763b 100644 --- a/drivers/clk/samsung/clk.c +++ b/drivers/clk/samsung/clk.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include @@ -27,6 +28,7 @@ void samsung_clk_save(void __iomem *base, for (; num_regs > 0; --num_regs, ++rd) rd->value = readl(base + rd->offset); } +EXPORT_SYMBOL_GPL(samsung_clk_save); void samsung_clk_restore(void __iomem *base, const struct samsung_clk_reg_dump *rd, @@ -35,6 +37,7 @@ void samsung_clk_restore(void __iomem *base, for (; num_regs > 0; --num_regs, ++rd) writel(rd->value, base + rd->offset); } +EXPORT_SYMBOL_GPL(samsung_clk_restore); struct samsung_clk_reg_dump *samsung_clk_alloc_reg_dump( const unsigned long *rdump, @@ -52,9 +55,10 @@ struct samsung_clk_reg_dump *samsung_clk_alloc_reg_dump( return rd; } +EXPORT_SYMBOL_GPL(samsung_clk_alloc_reg_dump); /* setup the essentials required to support clock lookup using ccf */ -struct samsung_clk_provider *__init samsung_clk_init(struct device_node *np, +struct samsung_clk_provider *samsung_clk_init(struct device_node *np, void __iomem *base, unsigned long nr_clks) { struct samsung_clk_provider *ctx; @@ -74,7 +78,7 @@ struct samsung_clk_provider *__init samsung_clk_init(struct device_node *np, return ctx; } -void __init samsung_clk_of_add_provider(struct device_node *np, +void samsung_clk_of_add_provider(struct device_node *np, struct samsung_clk_provider *ctx) { if (np) { @@ -83,6 +87,7 @@ void __init samsung_clk_of_add_provider(struct device_node *np, panic("could not register clk provider\n"); } } +EXPORT_SYMBOL_GPL(samsung_clk_of_add_provider); /* add a clock instance to the clock lookup table used for dt based lookup */ void samsung_clk_add_lookup(struct samsung_clk_provider *ctx, @@ -123,7 +128,7 @@ void __init samsung_clk_register_alias(struct samsung_clk_provider *ctx, } /* register a list of fixed clocks */ -void __init samsung_clk_register_fixed_rate(struct samsung_clk_provider *ctx, +void samsung_clk_register_fixed_rate(struct samsung_clk_provider *ctx, const struct samsung_fixed_rate_clock *list, unsigned int nr_clk) { @@ -151,9 +156,10 @@ void __init samsung_clk_register_fixed_rate(struct samsung_clk_provider *ctx, __func__, list->name); } } +EXPORT_SYMBOL_GPL(samsung_clk_register_fixed_rate); /* register a list of fixed factor clocks */ -void __init samsung_clk_register_fixed_factor(struct samsung_clk_provider *ctx, +void samsung_clk_register_fixed_factor(struct samsung_clk_provider *ctx, const struct samsung_fixed_factor_clock *list, unsigned int nr_clk) { struct clk_hw *clk_hw; @@ -171,9 +177,10 @@ void __init samsung_clk_register_fixed_factor(struct samsung_clk_provider *ctx, samsung_clk_add_lookup(ctx, clk_hw, list->id); } } +EXPORT_SYMBOL_GPL(samsung_clk_register_fixed_factor); /* register a list of mux clocks */ -void __init samsung_clk_register_mux(struct samsung_clk_provider *ctx, +void samsung_clk_register_mux(struct samsung_clk_provider *ctx, const struct samsung_mux_clock *list, unsigned int nr_clk) { @@ -194,9 +201,10 @@ void __init samsung_clk_register_mux(struct samsung_clk_provider *ctx, samsung_clk_add_lookup(ctx, clk_hw, list->id); } } +EXPORT_SYMBOL_GPL(samsung_clk_register_mux); /* register a list of div clocks */ -void __init samsung_clk_register_div(struct samsung_clk_provider *ctx, +void samsung_clk_register_div(struct samsung_clk_provider *ctx, const struct samsung_div_clock *list, unsigned int nr_clk) { @@ -224,9 +232,10 @@ void __init samsung_clk_register_div(struct samsung_clk_provider *ctx, samsung_clk_add_lookup(ctx, clk_hw, list->id); } } +EXPORT_SYMBOL_GPL(samsung_clk_register_div); /* register a list of gate clocks */ -void __init samsung_clk_register_gate(struct samsung_clk_provider *ctx, +void samsung_clk_register_gate(struct samsung_clk_provider *ctx, const struct samsung_gate_clock *list, unsigned int nr_clk) { @@ -246,6 +255,7 @@ void __init samsung_clk_register_gate(struct samsung_clk_provider *ctx, samsung_clk_add_lookup(ctx, clk_hw, list->id); } } +EXPORT_SYMBOL_GPL(samsung_clk_register_gate); /* * obtain the clock speed of all external fixed clock sources from device @@ -342,7 +352,7 @@ void samsung_clk_extended_sleep_init(void __iomem *reg_base, * Common function which registers plls, muxes, dividers and gates * for each CMU. It also add CMU register list to register cache. */ -struct samsung_clk_provider * __init samsung_cmu_register_one( +struct samsung_clk_provider *samsung_cmu_register_one( struct device_node *np, const struct samsung_cmu_info *cmu) { @@ -385,3 +395,10 @@ struct samsung_clk_provider * __init samsung_cmu_register_one( return ctx; } +EXPORT_SYMBOL_GPL(samsung_cmu_register_one); + +MODULE_DESCRIPTION("Samsung Exynos clock controller support"); +MODULE_AUTHOR("Thomas Abraham "); +MODULE_AUTHOR("Marek Szyprowski "); +MODULE_AUTHOR("Bartlomiej Zolnierkiewicz "); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h index a52a38cc1740..b82709696751 100644 --- a/drivers/clk/samsung/clk.h +++ b/drivers/clk/samsung/clk.h @@ -222,7 +222,7 @@ struct samsung_gate_clock { #define GATE(_id, cname, pname, o, b, f, gf) \ __GATE(_id, cname, pname, o, b, f, gf) -#define PNAME(x) static const char * const x[] __initconst +#define PNAME(x) static const char * const x[] /** * struct samsung_clk_reg_dump: register dump of clock controller registers. @@ -337,10 +337,10 @@ struct samsung_cmu_info { const char *clk_name; }; -extern struct samsung_clk_provider *__init samsung_clk_init( +extern struct samsung_clk_provider *samsung_clk_init( struct device_node *np, void __iomem *base, unsigned long nr_clks); -extern void __init samsung_clk_of_add_provider(struct device_node *np, +extern void samsung_clk_of_add_provider(struct device_node *np, struct samsung_clk_provider *ctx); extern void __init samsung_clk_of_register_fixed_ext( struct samsung_clk_provider *ctx, @@ -354,32 +354,32 @@ extern void samsung_clk_add_lookup(struct samsung_clk_provider *ctx, extern void __init samsung_clk_register_alias(struct samsung_clk_provider *ctx, const struct samsung_clock_alias *list, unsigned int nr_clk); -extern void __init samsung_clk_register_fixed_rate( +extern void samsung_clk_register_fixed_rate( struct samsung_clk_provider *ctx, const struct samsung_fixed_rate_clock *clk_list, unsigned int nr_clk); -extern void __init samsung_clk_register_fixed_factor( +extern void samsung_clk_register_fixed_factor( struct samsung_clk_provider *ctx, const struct samsung_fixed_factor_clock *list, unsigned int nr_clk); -extern void __init samsung_clk_register_mux(struct samsung_clk_provider *ctx, +extern void samsung_clk_register_mux(struct samsung_clk_provider *ctx, const struct samsung_mux_clock *clk_list, unsigned int nr_clk); -extern void __init samsung_clk_register_div(struct samsung_clk_provider *ctx, +extern void samsung_clk_register_div(struct samsung_clk_provider *ctx, const struct samsung_div_clock *clk_list, unsigned int nr_clk); -extern void __init samsung_clk_register_gate(struct samsung_clk_provider *ctx, +extern void samsung_clk_register_gate(struct samsung_clk_provider *ctx, const struct samsung_gate_clock *clk_list, unsigned int nr_clk); -extern void __init samsung_clk_register_pll(struct samsung_clk_provider *ctx, +extern void samsung_clk_register_pll(struct samsung_clk_provider *ctx, const struct samsung_pll_clock *pll_list, unsigned int nr_clk, void __iomem *base); -extern void __init samsung_clk_register_cpu(struct samsung_clk_provider *ctx, +extern void samsung_clk_register_cpu(struct samsung_clk_provider *ctx, const struct samsung_cpu_clock *list, unsigned int nr_clk); -extern struct samsung_clk_provider __init *samsung_cmu_register_one( - struct device_node *, - const struct samsung_cmu_info *); +extern struct samsung_clk_provider *samsung_cmu_register_one( + struct device_node *np, + const struct samsung_cmu_info *cmu); extern unsigned long _get_rate(const char *clk_name); From patchwork Tue Sep 28 23:56:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William McVicker X-Patchwork-Id: 12524131 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E2E80C433EF for ; Tue, 28 Sep 2021 23:57:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D09C0610A0 for ; Tue, 28 Sep 2021 23:57:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243399AbhI1X67 (ORCPT ); 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Tue, 28 Sep 2021 16:57:07 -0700 (PDT) Date: Tue, 28 Sep 2021 23:56:24 +0000 In-Reply-To: <20210928235635.1348330-1-willmcvicker@google.com> Message-Id: <20210928235635.1348330-8-willmcvicker@google.com> Mime-Version: 1.0 References: <20210928235635.1348330-1-willmcvicker@google.com> X-Mailer: git-send-email 2.33.0.685.g46640cef36-goog Subject: [PATCH v2 07/12] clk: samsung: set exynos arm64 clk driver as tristate From: Will McVicker To: Russell King , Krzysztof Kozlowski , Catalin Marinas , Will Deacon , Michael Turquette , Stephen Boyd , Sylwester Nawrocki , Tomasz Figa , Chanwoo Choi , Linus Walleij , Alessandro Zummo , Alexandre Belloni , John Stultz , Thomas Gleixner Cc: Lee Jones , Geert Uytterhoeven , Saravana Kannan , Will McVicker , kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-rtc@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org This sets the COMMON_CLK_SAMSUNG and EXYNOS_ARM64_COMMON_CLK drivers as tristate so that we can compile them as modules. Signed-off-by: Will McVicker --- arch/arm/mach-exynos/Kconfig | 1 - arch/arm/mach-s3c/Kconfig.s3c64xx | 1 - arch/arm/mach-s5pv210/Kconfig | 1 - arch/arm64/Kconfig.platforms | 1 - drivers/clk/samsung/Kconfig | 5 +++-- 5 files changed, 3 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 30f930e20599..01b8e8b8d95d 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -12,7 +12,6 @@ menuconfig ARCH_EXYNOS select ARM_AMBA select ARM_GIC select EXYNOS_IRQ_COMBINER - select COMMON_CLK_SAMSUNG select EXYNOS_THERMAL select EXYNOS_PMU select EXYNOS_SROM diff --git a/arch/arm/mach-s3c/Kconfig.s3c64xx b/arch/arm/mach-s3c/Kconfig.s3c64xx index f3fcb570edf5..f65117bb9f4c 100644 --- a/arch/arm/mach-s3c/Kconfig.s3c64xx +++ b/arch/arm/mach-s3c/Kconfig.s3c64xx @@ -9,7 +9,6 @@ menuconfig ARCH_S3C64XX select ARM_AMBA select ARM_VIC select CLKSRC_SAMSUNG_PWM - select COMMON_CLK_SAMSUNG select GPIO_SAMSUNG if ATAGS select GPIOLIB select HAVE_S3C2410_I2C if I2C diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig index d644b45bc29d..3d7e0b5739d8 100644 --- a/arch/arm/mach-s5pv210/Kconfig +++ b/arch/arm/mach-s5pv210/Kconfig @@ -10,7 +10,6 @@ config ARCH_S5PV210 depends on ARCH_MULTI_V7 select ARM_VIC select CLKSRC_SAMSUNG_PWM - select COMMON_CLK_SAMSUNG select GPIOLIB select HAVE_S3C2410_I2C if I2C select HAVE_S3C_RTC if RTC_CLASS diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 90c5cf4856e1..e6d4abadacd8 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -91,7 +91,6 @@ config ARCH_BRCMSTB config ARCH_EXYNOS bool "ARMv8 based Samsung Exynos SoC family" - select COMMON_CLK_SAMSUNG select EXYNOS_PM_DOMAINS if PM_GENERIC_DOMAINS select EXYNOS_PMU select HAVE_S3C_RTC if RTC_CLASS diff --git a/drivers/clk/samsung/Kconfig b/drivers/clk/samsung/Kconfig index 0441c4f73ac9..f987d386979d 100644 --- a/drivers/clk/samsung/Kconfig +++ b/drivers/clk/samsung/Kconfig @@ -1,7 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-only # Recent Exynos platforms should just select COMMON_CLK_SAMSUNG: config COMMON_CLK_SAMSUNG - bool "Samsung Exynos clock controller support" if COMPILE_TEST + tristate "Samsung Exynos clock controller support" + default y if ARCH_EXYNOS || ARCH_S5PV210 || ARCH_S3C64XX select S3C64XX_COMMON_CLK if ARM && ARCH_S3C64XX select S5PV210_COMMON_CLK if ARM && ARCH_S5PV210 select EXYNOS_3250_COMMON_CLK if ARM && SOC_EXYNOS3250 @@ -70,7 +71,7 @@ config EXYNOS_5420_COMMON_CLK Exynos5420 SoCs. Choose Y here only if you build for this SoC. config EXYNOS_ARM64_COMMON_CLK - bool "Samsung Exynos ARMv8-family clock controller support" if COMPILE_TEST + tristate "Samsung Exynos ARMv8-family clock controller support" depends on COMMON_CLK_SAMSUNG config EXYNOS_AUDSS_CLK_CON From patchwork Tue Sep 28 23:56:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William McVicker X-Patchwork-Id: 12524137 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0D6D8C433EF for ; Tue, 28 Sep 2021 23:57:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E85C061357 for ; Tue, 28 Sep 2021 23:57:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243621AbhI1X7M (ORCPT ); Tue, 28 Sep 2021 19:59:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43190 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243516AbhI1X65 (ORCPT ); Tue, 28 Sep 2021 19:58:57 -0400 Received: from mail-qt1-x84a.google.com (mail-qt1-x84a.google.com [IPv6:2607:f8b0:4864:20::84a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A92C1C0613E3 for ; Tue, 28 Sep 2021 16:57:10 -0700 (PDT) Received: by mail-qt1-x84a.google.com with SMTP id a18-20020aed2792000000b002a6d480aa95so2734399qtd.14 for ; Tue, 28 Sep 2021 16:57:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=h43D/RGXCRAHCvT6PHRIQgGhpZoIfzzJQ0XUHpA3FZ4=; b=Kfvq2JNsvB7vtKyUaDX4jqIiYB0c0k/ncTX72Jn0ep0oLkyNfDMqskUycmmcFaWh8W O9i9NTtxlP8xSvDnPYw2O1ADcJV5K3HzMPQ6Mi+aCvM+71xUx91y2CmDQCs630eNp2HG HiROZzIiqx9M/De8w6qGqbAmUaUghdeIb66EXZ2wRAeMlqa8A7AjmsvhosKVDtgRUS2O RmGKpXHLSfU1qQRwJ0Mv42csJyXE8zrUIdkaP3fpR+DwnMr8+FzDTVR5rbQAZjH9EzQ5 Xudn/NmNdT0ynKeGG+LTW3m45tZNlVB1za72d1hyaAzNLeh5HQQztowObP91nWzaFCP1 S9kQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=h43D/RGXCRAHCvT6PHRIQgGhpZoIfzzJQ0XUHpA3FZ4=; b=1VH+UnYzm3tpDZEjHgRar9hGCUjU2Kta5p854WcpBczk2qWnGQH8LUkdJytUhkRbDm EiExa5E7yvCApwQqJutdptzxGI+XJVQIJrxCgGqFe4a+hz9B/fLB1/SkbJhBpotHCcKi GtB8aiE+rV/A3DsXcm49rqZjIg1Zjwj0LQ5fI2BSADxzshmpmISJjnCphCUBWQPeRCUf gO+zrYCPygoWOyUjYXBU4IO4tCSeft+P7NmHC4UIKAoeZPEwwcg3+qmTVO5c1HVoTmko VH+F4OlhX30rtaEHIIG4246Z1FqKqGco/9imEI5ps4QaaM8z8U6qIHKiAlKPd9terHcV ZOIQ== X-Gm-Message-State: AOAM5330fNaYrzMJTuYaEv7MFNwa5c2g3pBymEe0Ik/G+Ib1mRmGr+An kHmLLT0ZiyX33remvHj0vOtePHV9761Tz6t3h1c= X-Google-Smtp-Source: ABdhPJzIrF4RQxOepwiQDeOarh65fq//wgbM5LDo7bwOD+UWYA70CVSqPO8EBAL06DKxo/8AXVRCBMJP2rm3OGyWQm4= X-Received: from willmcvicker.c.googlers.com ([fda3:e722:ac3:cc00:24:72f4:c0a8:2dd0]) (user=willmcvicker job=sendgmr) by 2002:ad4:466a:: with SMTP id z10mr328044qvv.7.1632873429872; Tue, 28 Sep 2021 16:57:09 -0700 (PDT) Date: Tue, 28 Sep 2021 23:56:25 +0000 In-Reply-To: <20210928235635.1348330-1-willmcvicker@google.com> Message-Id: <20210928235635.1348330-9-willmcvicker@google.com> Mime-Version: 1.0 References: <20210928235635.1348330-1-willmcvicker@google.com> X-Mailer: git-send-email 2.33.0.685.g46640cef36-goog Subject: [PATCH v2 08/12] pinctrl: samsung: modularize the ARM and ARM64 pinctrls From: Will McVicker To: Russell King , Krzysztof Kozlowski , Catalin Marinas , Will Deacon , Michael Turquette , Stephen Boyd , Sylwester Nawrocki , Tomasz Figa , Chanwoo Choi , Linus Walleij , Alessandro Zummo , Alexandre Belloni , John Stultz , Thomas Gleixner Cc: Lee Jones , Geert Uytterhoeven , Saravana Kannan , Will McVicker , kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-rtc@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org This patch modularizes the Samsung Exynos ARM and ARM64 pinctrl drivers. It creates 2 kernel modules (pending Kconfig changes): 1) pinctrl-samsung.ko: common pinctrl driver for all the samsung pinctrl drivers. 2) pinctrl_exynos.ko: ARM and ARM64 pinctrl driver. Signed-off-by: Will McVicker --- drivers/pinctrl/samsung/Makefile | 13 +-- drivers/pinctrl/samsung/pinctrl-exynos-arm.c | 102 ++++++++++-------- .../pinctrl/samsung/pinctrl-exynos-arm64.c | 73 +++++++------ drivers/pinctrl/samsung/pinctrl-exynos.c | 17 +-- drivers/pinctrl/samsung/pinctrl-samsung.c | 11 +- 5 files changed, 117 insertions(+), 99 deletions(-) diff --git a/drivers/pinctrl/samsung/Makefile b/drivers/pinctrl/samsung/Makefile index ed951df6a112..767ce3357a19 100644 --- a/drivers/pinctrl/samsung/Makefile +++ b/drivers/pinctrl/samsung/Makefile @@ -1,9 +1,10 @@ # SPDX-License-Identifier: GPL-2.0 # Samsung pin control drivers -obj-$(CONFIG_PINCTRL_SAMSUNG) += pinctrl-samsung.o -obj-$(CONFIG_PINCTRL_EXYNOS) += pinctrl-exynos.o -obj-$(CONFIG_PINCTRL_EXYNOS_ARM) += pinctrl-exynos-arm.o -obj-$(CONFIG_PINCTRL_EXYNOS_ARM64) += pinctrl-exynos-arm64.o -obj-$(CONFIG_PINCTRL_S3C24XX) += pinctrl-s3c24xx.o -obj-$(CONFIG_PINCTRL_S3C64XX) += pinctrl-s3c64xx.o +obj-$(CONFIG_PINCTRL_SAMSUNG) += pinctrl-samsung.o +obj-$(CONFIG_PINCTRL_EXYNOS) += pinctrl_exynos.o +pinctrl_exynos-y += pinctrl-exynos.o +pinctrl_exynos-$(CONFIG_PINCTRL_EXYNOS_ARM) += pinctrl-exynos-arm.o +pinctrl_exynos-$(CONFIG_PINCTRL_EXYNOS_ARM64) += pinctrl-exynos-arm64.o +obj-$(CONFIG_PINCTRL_S3C24XX) += pinctrl-s3c24xx.o +obj-$(CONFIG_PINCTRL_S3C64XX) += pinctrl-s3c64xx.o diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm.c index 85ddf49a5188..f3bd8cf1bbb6 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm.c @@ -83,12 +83,12 @@ s5pv210_retention_init(struct samsung_pinctrl_drv_data *drvdata, return ctrl; } -static const struct samsung_retention_data s5pv210_retention_data __initconst = { +static const struct samsung_retention_data s5pv210_retention_data = { .init = s5pv210_retention_init, }; /* pin banks of s5pv210 pin-controller */ -static const struct samsung_pin_bank_data s5pv210_pin_bank[] __initconst = { +static const struct samsung_pin_bank_data s5pv210_pin_bank[] = { /* Must start with EINTG banks, ordered by EINT group number. */ EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpa1", 0x04), @@ -126,7 +126,7 @@ static const struct samsung_pin_bank_data s5pv210_pin_bank[] __initconst = { EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gph3", 0x0c), }; -static const struct samsung_pin_ctrl s5pv210_pin_ctrl[] __initconst = { +static const struct samsung_pin_ctrl s5pv210_pin_ctrl[] = { { /* pin-controller instance 0 data */ .pin_banks = s5pv210_pin_bank, @@ -139,16 +139,17 @@ static const struct samsung_pin_ctrl s5pv210_pin_ctrl[] __initconst = { }, }; -const struct samsung_pinctrl_of_match_data s5pv210_of_data __initconst = { +const struct samsung_pinctrl_of_match_data s5pv210_of_data = { .ctrl = s5pv210_pin_ctrl, .num_ctrl = ARRAY_SIZE(s5pv210_pin_ctrl), }; +EXPORT_SYMBOL_GPL(s5pv210_of_data); /* Pad retention control code for accessing PMU regmap */ static atomic_t exynos_shared_retention_refcnt; /* pin banks of exynos3250 pin-controller 0 */ -static const struct samsung_pin_bank_data exynos3250_pin_banks0[] __initconst = { +static const struct samsung_pin_bank_data exynos3250_pin_banks0[] = { /* Must start with EINTG banks, ordered by EINT group number. */ EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), @@ -160,7 +161,7 @@ static const struct samsung_pin_bank_data exynos3250_pin_banks0[] __initconst = }; /* pin banks of exynos3250 pin-controller 1 */ -static const struct samsung_pin_bank_data exynos3250_pin_banks1[] __initconst = { +static const struct samsung_pin_bank_data exynos3250_pin_banks1[] = { /* Must start with EINTG banks, ordered by EINT group number. */ EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpe0"), EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpe1"), @@ -196,7 +197,7 @@ static const u32 exynos3250_retention_regs[] = { S5P_PAD_RET_SPI_OPTION, }; -static const struct samsung_retention_data exynos3250_retention_data __initconst = { +static const struct samsung_retention_data exynos3250_retention_data = { .regs = exynos3250_retention_regs, .nr_regs = ARRAY_SIZE(exynos3250_retention_regs), .value = EXYNOS_WAKEUP_FROM_LOWPWR, @@ -208,7 +209,7 @@ static const struct samsung_retention_data exynos3250_retention_data __initconst * Samsung pinctrl driver data for Exynos3250 SoC. Exynos3250 SoC includes * two gpio/pin-mux/pinconfig controllers. */ -static const struct samsung_pin_ctrl exynos3250_pin_ctrl[] __initconst = { +static const struct samsung_pin_ctrl exynos3250_pin_ctrl[] = { { /* pin-controller instance 0 data */ .pin_banks = exynos3250_pin_banks0, @@ -229,13 +230,14 @@ static const struct samsung_pin_ctrl exynos3250_pin_ctrl[] __initconst = { }, }; -const struct samsung_pinctrl_of_match_data exynos3250_of_data __initconst = { +const struct samsung_pinctrl_of_match_data exynos3250_of_data = { .ctrl = exynos3250_pin_ctrl, .num_ctrl = ARRAY_SIZE(exynos3250_pin_ctrl), }; +EXPORT_SYMBOL_GPL(exynos3250_of_data); /* pin banks of exynos4210 pin-controller 0 */ -static const struct samsung_pin_bank_data exynos4210_pin_banks0[] __initconst = { +static const struct samsung_pin_bank_data exynos4210_pin_banks0[] = { /* Must start with EINTG banks, ordered by EINT group number. */ EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), @@ -256,7 +258,7 @@ static const struct samsung_pin_bank_data exynos4210_pin_banks0[] __initconst = }; /* pin banks of exynos4210 pin-controller 1 */ -static const struct samsung_pin_bank_data exynos4210_pin_banks1[] __initconst = { +static const struct samsung_pin_bank_data exynos4210_pin_banks1[] = { /* Must start with EINTG banks, ordered by EINT group number. */ EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpj0", 0x00), EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpj1", 0x04), @@ -281,7 +283,7 @@ static const struct samsung_pin_bank_data exynos4210_pin_banks1[] __initconst = }; /* pin banks of exynos4210 pin-controller 2 */ -static const struct samsung_pin_bank_data exynos4210_pin_banks2[] __initconst = { +static const struct samsung_pin_bank_data exynos4210_pin_banks2[] = { /* Must start with EINTG banks, ordered by EINT group number. */ EXYNOS_PIN_BANK_EINTN(7, 0x000, "gpz"), }; @@ -296,7 +298,7 @@ static const u32 exynos4_retention_regs[] = { S5P_PAD_RET_EBIB_OPTION, }; -static const struct samsung_retention_data exynos4_retention_data __initconst = { +static const struct samsung_retention_data exynos4_retention_data = { .regs = exynos4_retention_regs, .nr_regs = ARRAY_SIZE(exynos4_retention_regs), .value = EXYNOS_WAKEUP_FROM_LOWPWR, @@ -309,7 +311,7 @@ static const u32 exynos4_audio_retention_regs[] = { S5P_PAD_RET_MAUDIO_OPTION, }; -static const struct samsung_retention_data exynos4_audio_retention_data __initconst = { +static const struct samsung_retention_data exynos4_audio_retention_data = { .regs = exynos4_audio_retention_regs, .nr_regs = ARRAY_SIZE(exynos4_audio_retention_regs), .value = EXYNOS_WAKEUP_FROM_LOWPWR, @@ -320,7 +322,7 @@ static const struct samsung_retention_data exynos4_audio_retention_data __initco * Samsung pinctrl driver data for Exynos4210 SoC. Exynos4210 SoC includes * three gpio/pin-mux/pinconfig controllers. */ -static const struct samsung_pin_ctrl exynos4210_pin_ctrl[] __initconst = { +static const struct samsung_pin_ctrl exynos4210_pin_ctrl[] = { { /* pin-controller instance 0 data */ .pin_banks = exynos4210_pin_banks0, @@ -346,13 +348,14 @@ static const struct samsung_pin_ctrl exynos4210_pin_ctrl[] __initconst = { }, }; -const struct samsung_pinctrl_of_match_data exynos4210_of_data __initconst = { +const struct samsung_pinctrl_of_match_data exynos4210_of_data = { .ctrl = exynos4210_pin_ctrl, .num_ctrl = ARRAY_SIZE(exynos4210_pin_ctrl), }; +EXPORT_SYMBOL_GPL(exynos4210_of_data); /* pin banks of exynos4x12 pin-controller 0 */ -static const struct samsung_pin_bank_data exynos4x12_pin_banks0[] __initconst = { +static const struct samsung_pin_bank_data exynos4x12_pin_banks0[] = { /* Must start with EINTG banks, ordered by EINT group number. */ EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), @@ -370,7 +373,7 @@ static const struct samsung_pin_bank_data exynos4x12_pin_banks0[] __initconst = }; /* pin banks of exynos4x12 pin-controller 1 */ -static const struct samsung_pin_bank_data exynos4x12_pin_banks1[] __initconst = { +static const struct samsung_pin_bank_data exynos4x12_pin_banks1[] = { /* Must start with EINTG banks, ordered by EINT group number. */ EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08), EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c), @@ -398,13 +401,13 @@ static const struct samsung_pin_bank_data exynos4x12_pin_banks1[] __initconst = }; /* pin banks of exynos4x12 pin-controller 2 */ -static const struct samsung_pin_bank_data exynos4x12_pin_banks2[] __initconst = { +static const struct samsung_pin_bank_data exynos4x12_pin_banks2[] = { /* Must start with EINTG banks, ordered by EINT group number. */ EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00), }; /* pin banks of exynos4x12 pin-controller 3 */ -static const struct samsung_pin_bank_data exynos4x12_pin_banks3[] __initconst = { +static const struct samsung_pin_bank_data exynos4x12_pin_banks3[] = { /* Must start with EINTG banks, ordered by EINT group number. */ EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00), EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04), @@ -417,7 +420,7 @@ static const struct samsung_pin_bank_data exynos4x12_pin_banks3[] __initconst = * Samsung pinctrl driver data for Exynos4x12 SoC. Exynos4x12 SoC includes * four gpio/pin-mux/pinconfig controllers. */ -static const struct samsung_pin_ctrl exynos4x12_pin_ctrl[] __initconst = { +static const struct samsung_pin_ctrl exynos4x12_pin_ctrl[] = { { /* pin-controller instance 0 data */ .pin_banks = exynos4x12_pin_banks0, @@ -453,13 +456,14 @@ static const struct samsung_pin_ctrl exynos4x12_pin_ctrl[] __initconst = { }, }; -const struct samsung_pinctrl_of_match_data exynos4x12_of_data __initconst = { +const struct samsung_pinctrl_of_match_data exynos4x12_of_data = { .ctrl = exynos4x12_pin_ctrl, .num_ctrl = ARRAY_SIZE(exynos4x12_pin_ctrl), }; +EXPORT_SYMBOL_GPL(exynos4x12_of_data); /* pin banks of exynos5250 pin-controller 0 */ -static const struct samsung_pin_bank_data exynos5250_pin_banks0[] __initconst = { +static const struct samsung_pin_bank_data exynos5250_pin_banks0[] = { /* Must start with EINTG banks, ordered by EINT group number. */ EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), @@ -489,7 +493,7 @@ static const struct samsung_pin_bank_data exynos5250_pin_banks0[] __initconst = }; /* pin banks of exynos5250 pin-controller 1 */ -static const struct samsung_pin_bank_data exynos5250_pin_banks1[] __initconst = { +static const struct samsung_pin_bank_data exynos5250_pin_banks1[] = { /* Must start with EINTG banks, ordered by EINT group number. */ EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00), EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04), @@ -503,7 +507,7 @@ static const struct samsung_pin_bank_data exynos5250_pin_banks1[] __initconst = }; /* pin banks of exynos5250 pin-controller 2 */ -static const struct samsung_pin_bank_data exynos5250_pin_banks2[] __initconst = { +static const struct samsung_pin_bank_data exynos5250_pin_banks2[] = { /* Must start with EINTG banks, ordered by EINT group number. */ EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00), EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04), @@ -513,7 +517,7 @@ static const struct samsung_pin_bank_data exynos5250_pin_banks2[] __initconst = }; /* pin banks of exynos5250 pin-controller 3 */ -static const struct samsung_pin_bank_data exynos5250_pin_banks3[] __initconst = { +static const struct samsung_pin_bank_data exynos5250_pin_banks3[] = { /* Must start with EINTG banks, ordered by EINT group number. */ EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00), }; @@ -522,7 +526,7 @@ static const struct samsung_pin_bank_data exynos5250_pin_banks3[] __initconst = * Samsung pinctrl driver data for Exynos5250 SoC. Exynos5250 SoC includes * four gpio/pin-mux/pinconfig controllers. */ -static const struct samsung_pin_ctrl exynos5250_pin_ctrl[] __initconst = { +static const struct samsung_pin_ctrl exynos5250_pin_ctrl[] = { { /* pin-controller instance 0 data */ .pin_banks = exynos5250_pin_banks0, @@ -558,13 +562,14 @@ static const struct samsung_pin_ctrl exynos5250_pin_ctrl[] __initconst = { }, }; -const struct samsung_pinctrl_of_match_data exynos5250_of_data __initconst = { +const struct samsung_pinctrl_of_match_data exynos5250_of_data = { .ctrl = exynos5250_pin_ctrl, .num_ctrl = ARRAY_SIZE(exynos5250_pin_ctrl), }; +EXPORT_SYMBOL_GPL(exynos5250_of_data); /* pin banks of exynos5260 pin-controller 0 */ -static const struct samsung_pin_bank_data exynos5260_pin_banks0[] __initconst = { +static const struct samsung_pin_bank_data exynos5260_pin_banks0[] = { /* Must start with EINTG banks, ordered by EINT group number. */ EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpa0", 0x00), EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpa1", 0x04), @@ -590,7 +595,7 @@ static const struct samsung_pin_bank_data exynos5260_pin_banks0[] __initconst = }; /* pin banks of exynos5260 pin-controller 1 */ -static const struct samsung_pin_bank_data exynos5260_pin_banks1[] __initconst = { +static const struct samsung_pin_bank_data exynos5260_pin_banks1[] = { /* Must start with EINTG banks, ordered by EINT group number. */ EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpc0", 0x00), EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpc1", 0x04), @@ -600,7 +605,7 @@ static const struct samsung_pin_bank_data exynos5260_pin_banks1[] __initconst = }; /* pin banks of exynos5260 pin-controller 2 */ -static const struct samsung_pin_bank_data exynos5260_pin_banks2[] __initconst = { +static const struct samsung_pin_bank_data exynos5260_pin_banks2[] = { /* Must start with EINTG banks, ordered by EINT group number. */ EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00), EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04), @@ -610,7 +615,7 @@ static const struct samsung_pin_bank_data exynos5260_pin_banks2[] __initconst = * Samsung pinctrl driver data for Exynos5260 SoC. Exynos5260 SoC includes * three gpio/pin-mux/pinconfig controllers. */ -static const struct samsung_pin_ctrl exynos5260_pin_ctrl[] __initconst = { +static const struct samsung_pin_ctrl exynos5260_pin_ctrl[] = { { /* pin-controller instance 0 data */ .pin_banks = exynos5260_pin_banks0, @@ -636,13 +641,14 @@ static const struct samsung_pin_ctrl exynos5260_pin_ctrl[] __initconst = { }, }; -const struct samsung_pinctrl_of_match_data exynos5260_of_data __initconst = { +const struct samsung_pinctrl_of_match_data exynos5260_of_data = { .ctrl = exynos5260_pin_ctrl, .num_ctrl = ARRAY_SIZE(exynos5260_pin_ctrl), }; +EXPORT_SYMBOL_GPL(exynos5260_of_data); /* pin banks of exynos5410 pin-controller 0 */ -static const struct samsung_pin_bank_data exynos5410_pin_banks0[] __initconst = { +static const struct samsung_pin_bank_data exynos5410_pin_banks0[] = { /* Must start with EINTG banks, ordered by EINT group number. */ EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), @@ -682,7 +688,7 @@ static const struct samsung_pin_bank_data exynos5410_pin_banks0[] __initconst = }; /* pin banks of exynos5410 pin-controller 1 */ -static const struct samsung_pin_bank_data exynos5410_pin_banks1[] __initconst = { +static const struct samsung_pin_bank_data exynos5410_pin_banks1[] = { /* Must start with EINTG banks, ordered by EINT group number. */ EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpj0", 0x00), EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpj1", 0x04), @@ -696,7 +702,7 @@ static const struct samsung_pin_bank_data exynos5410_pin_banks1[] __initconst = }; /* pin banks of exynos5410 pin-controller 2 */ -static const struct samsung_pin_bank_data exynos5410_pin_banks2[] __initconst = { +static const struct samsung_pin_bank_data exynos5410_pin_banks2[] = { /* Must start with EINTG banks, ordered by EINT group number. */ EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00), EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04), @@ -706,7 +712,7 @@ static const struct samsung_pin_bank_data exynos5410_pin_banks2[] __initconst = }; /* pin banks of exynos5410 pin-controller 3 */ -static const struct samsung_pin_bank_data exynos5410_pin_banks3[] __initconst = { +static const struct samsung_pin_bank_data exynos5410_pin_banks3[] = { /* Must start with EINTG banks, ordered by EINT group number. */ EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00), }; @@ -715,7 +721,7 @@ static const struct samsung_pin_bank_data exynos5410_pin_banks3[] __initconst = * Samsung pinctrl driver data for Exynos5410 SoC. Exynos5410 SoC includes * four gpio/pin-mux/pinconfig controllers. */ -static const struct samsung_pin_ctrl exynos5410_pin_ctrl[] __initconst = { +static const struct samsung_pin_ctrl exynos5410_pin_ctrl[] = { { /* pin-controller instance 0 data */ .pin_banks = exynos5410_pin_banks0, @@ -748,13 +754,14 @@ static const struct samsung_pin_ctrl exynos5410_pin_ctrl[] __initconst = { }, }; -const struct samsung_pinctrl_of_match_data exynos5410_of_data __initconst = { +const struct samsung_pinctrl_of_match_data exynos5410_of_data = { .ctrl = exynos5410_pin_ctrl, .num_ctrl = ARRAY_SIZE(exynos5410_pin_ctrl), }; +EXPORT_SYMBOL_GPL(exynos5410_of_data); /* pin banks of exynos5420 pin-controller 0 */ -static const struct samsung_pin_bank_data exynos5420_pin_banks0[] __initconst = { +static const struct samsung_pin_bank_data exynos5420_pin_banks0[] = { /* Must start with EINTG banks, ordered by EINT group number. */ EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpy7", 0x00), EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), @@ -764,7 +771,7 @@ static const struct samsung_pin_bank_data exynos5420_pin_banks0[] __initconst = }; /* pin banks of exynos5420 pin-controller 1 */ -static const struct samsung_pin_bank_data exynos5420_pin_banks1[] __initconst = { +static const struct samsung_pin_bank_data exynos5420_pin_banks1[] = { /* Must start with EINTG banks, ordered by EINT group number. */ EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpc0", 0x00), EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc1", 0x04), @@ -782,7 +789,7 @@ static const struct samsung_pin_bank_data exynos5420_pin_banks1[] __initconst = }; /* pin banks of exynos5420 pin-controller 2 */ -static const struct samsung_pin_bank_data exynos5420_pin_banks2[] __initconst = { +static const struct samsung_pin_bank_data exynos5420_pin_banks2[] = { /* Must start with EINTG banks, ordered by EINT group number. */ EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00), EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04), @@ -795,7 +802,7 @@ static const struct samsung_pin_bank_data exynos5420_pin_banks2[] __initconst = }; /* pin banks of exynos5420 pin-controller 3 */ -static const struct samsung_pin_bank_data exynos5420_pin_banks3[] __initconst = { +static const struct samsung_pin_bank_data exynos5420_pin_banks3[] = { /* Must start with EINTG banks, ordered by EINT group number. */ EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), @@ -809,7 +816,7 @@ static const struct samsung_pin_bank_data exynos5420_pin_banks3[] __initconst = }; /* pin banks of exynos5420 pin-controller 4 */ -static const struct samsung_pin_bank_data exynos5420_pin_banks4[] __initconst = { +static const struct samsung_pin_bank_data exynos5420_pin_banks4[] = { /* Must start with EINTG banks, ordered by EINT group number. */ EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00), }; @@ -830,7 +837,7 @@ static const u32 exynos5420_retention_regs[] = { EXYNOS5420_PAD_RET_DRAM_COREBLK_OPTION, }; -static const struct samsung_retention_data exynos5420_retention_data __initconst = { +static const struct samsung_retention_data exynos5420_retention_data = { .regs = exynos5420_retention_regs, .nr_regs = ARRAY_SIZE(exynos5420_retention_regs), .value = EXYNOS_WAKEUP_FROM_LOWPWR, @@ -842,7 +849,7 @@ static const struct samsung_retention_data exynos5420_retention_data __initconst * Samsung pinctrl driver data for Exynos5420 SoC. Exynos5420 SoC includes * four gpio/pin-mux/pinconfig controllers. */ -static const struct samsung_pin_ctrl exynos5420_pin_ctrl[] __initconst = { +static const struct samsung_pin_ctrl exynos5420_pin_ctrl[] = { { /* pin-controller instance 0 data */ .pin_banks = exynos5420_pin_banks0, @@ -887,7 +894,8 @@ static const struct samsung_pin_ctrl exynos5420_pin_ctrl[] __initconst = { }, }; -const struct samsung_pinctrl_of_match_data exynos5420_of_data __initconst = { +const struct samsung_pinctrl_of_match_data exynos5420_of_data = { .ctrl = exynos5420_pin_ctrl, .num_ctrl = ARRAY_SIZE(exynos5420_pin_ctrl), }; +EXPORT_SYMBOL_GPL(exynos5420_of_data); diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c index fe5f6046fbd5..9fb658c65b96 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c @@ -62,7 +62,7 @@ static const struct samsung_pin_bank_type exynos850_bank_type_alive = { static atomic_t exynos_shared_retention_refcnt; /* pin banks of exynos5433 pin-controller - ALIVE */ -static const struct samsung_pin_bank_data exynos5433_pin_banks0[] __initconst = { +static const struct samsung_pin_bank_data exynos5433_pin_banks0[] = { /* Must start with EINTG banks, ordered by EINT group number. */ EXYNOS5433_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00), EXYNOS5433_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04), @@ -76,32 +76,32 @@ static const struct samsung_pin_bank_data exynos5433_pin_banks0[] __initconst = }; /* pin banks of exynos5433 pin-controller - AUD */ -static const struct samsung_pin_bank_data exynos5433_pin_banks1[] __initconst = { +static const struct samsung_pin_bank_data exynos5433_pin_banks1[] = { /* Must start with EINTG banks, ordered by EINT group number. */ EXYNOS5433_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00), EXYNOS5433_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04), }; /* pin banks of exynos5433 pin-controller - CPIF */ -static const struct samsung_pin_bank_data exynos5433_pin_banks2[] __initconst = { +static const struct samsung_pin_bank_data exynos5433_pin_banks2[] = { /* Must start with EINTG banks, ordered by EINT group number. */ EXYNOS5433_PIN_BANK_EINTG(2, 0x000, "gpv6", 0x00), }; /* pin banks of exynos5433 pin-controller - eSE */ -static const struct samsung_pin_bank_data exynos5433_pin_banks3[] __initconst = { +static const struct samsung_pin_bank_data exynos5433_pin_banks3[] = { /* Must start with EINTG banks, ordered by EINT group number. */ EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj2", 0x00), }; /* pin banks of exynos5433 pin-controller - FINGER */ -static const struct samsung_pin_bank_data exynos5433_pin_banks4[] __initconst = { +static const struct samsung_pin_bank_data exynos5433_pin_banks4[] = { /* Must start with EINTG banks, ordered by EINT group number. */ EXYNOS5433_PIN_BANK_EINTG(4, 0x000, "gpd5", 0x00), }; /* pin banks of exynos5433 pin-controller - FSYS */ -static const struct samsung_pin_bank_data exynos5433_pin_banks5[] __initconst = { +static const struct samsung_pin_bank_data exynos5433_pin_banks5[] = { /* Must start with EINTG banks, ordered by EINT group number. */ EXYNOS5433_PIN_BANK_EINTG(6, 0x000, "gph1", 0x00), EXYNOS5433_PIN_BANK_EINTG(7, 0x020, "gpr4", 0x04), @@ -112,19 +112,19 @@ static const struct samsung_pin_bank_data exynos5433_pin_banks5[] __initconst = }; /* pin banks of exynos5433 pin-controller - IMEM */ -static const struct samsung_pin_bank_data exynos5433_pin_banks6[] __initconst = { +static const struct samsung_pin_bank_data exynos5433_pin_banks6[] = { /* Must start with EINTG banks, ordered by EINT group number. */ EXYNOS5433_PIN_BANK_EINTG(8, 0x000, "gpf0", 0x00), }; /* pin banks of exynos5433 pin-controller - NFC */ -static const struct samsung_pin_bank_data exynos5433_pin_banks7[] __initconst = { +static const struct samsung_pin_bank_data exynos5433_pin_banks7[] = { /* Must start with EINTG banks, ordered by EINT group number. */ EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00), }; /* pin banks of exynos5433 pin-controller - PERIC */ -static const struct samsung_pin_bank_data exynos5433_pin_banks8[] __initconst = { +static const struct samsung_pin_bank_data exynos5433_pin_banks8[] = { /* Must start with EINTG banks, ordered by EINT group number. */ EXYNOS5433_PIN_BANK_EINTG(6, 0x000, "gpv7", 0x00), EXYNOS5433_PIN_BANK_EINTG(5, 0x020, "gpb0", 0x04), @@ -146,7 +146,7 @@ static const struct samsung_pin_bank_data exynos5433_pin_banks8[] __initconst = }; /* pin banks of exynos5433 pin-controller - TOUCH */ -static const struct samsung_pin_bank_data exynos5433_pin_banks9[] __initconst = { +static const struct samsung_pin_bank_data exynos5433_pin_banks9[] = { /* Must start with EINTG banks, ordered by EINT group number. */ EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00), }; @@ -165,7 +165,7 @@ static const u32 exynos5433_retention_regs[] = { EXYNOS5433_PAD_RETENTION_FSYSGENIO_OPTION, }; -static const struct samsung_retention_data exynos5433_retention_data __initconst = { +static const struct samsung_retention_data exynos5433_retention_data = { .regs = exynos5433_retention_regs, .nr_regs = ARRAY_SIZE(exynos5433_retention_regs), .value = EXYNOS_WAKEUP_FROM_LOWPWR, @@ -178,7 +178,7 @@ static const u32 exynos5433_audio_retention_regs[] = { EXYNOS5433_PAD_RETENTION_AUD_OPTION, }; -static const struct samsung_retention_data exynos5433_audio_retention_data __initconst = { +static const struct samsung_retention_data exynos5433_audio_retention_data = { .regs = exynos5433_audio_retention_regs, .nr_regs = ARRAY_SIZE(exynos5433_audio_retention_regs), .value = EXYNOS_WAKEUP_FROM_LOWPWR, @@ -192,7 +192,7 @@ static const u32 exynos5433_fsys_retention_regs[] = { EXYNOS5433_PAD_RETENTION_MMC2_OPTION, }; -static const struct samsung_retention_data exynos5433_fsys_retention_data __initconst = { +static const struct samsung_retention_data exynos5433_fsys_retention_data = { .regs = exynos5433_fsys_retention_regs, .nr_regs = ARRAY_SIZE(exynos5433_fsys_retention_regs), .value = EXYNOS_WAKEUP_FROM_LOWPWR, @@ -203,7 +203,7 @@ static const struct samsung_retention_data exynos5433_fsys_retention_data __init * Samsung pinctrl driver data for Exynos5433 SoC. Exynos5433 SoC includes * ten gpio/pin-mux/pinconfig controllers. */ -static const struct samsung_pin_ctrl exynos5433_pin_ctrl[] __initconst = { +static const struct samsung_pin_ctrl exynos5433_pin_ctrl[] = { { /* pin-controller instance 0 data */ .pin_banks = exynos5433_pin_banks0, @@ -288,13 +288,14 @@ static const struct samsung_pin_ctrl exynos5433_pin_ctrl[] __initconst = { }, }; -const struct samsung_pinctrl_of_match_data exynos5433_of_data __initconst = { +const struct samsung_pinctrl_of_match_data exynos5433_of_data = { .ctrl = exynos5433_pin_ctrl, .num_ctrl = ARRAY_SIZE(exynos5433_pin_ctrl), }; +EXPORT_SYMBOL_GPL(exynos5433_of_data); /* pin banks of exynos7 pin-controller - ALIVE */ -static const struct samsung_pin_bank_data exynos7_pin_banks0[] __initconst = { +static const struct samsung_pin_bank_data exynos7_pin_banks0[] = { /* Must start with EINTG banks, ordered by EINT group number. */ EXYNOS_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00), EXYNOS_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04), @@ -303,7 +304,7 @@ static const struct samsung_pin_bank_data exynos7_pin_banks0[] __initconst = { }; /* pin banks of exynos7 pin-controller - BUS0 */ -static const struct samsung_pin_bank_data exynos7_pin_banks1[] __initconst = { +static const struct samsung_pin_bank_data exynos7_pin_banks1[] = { /* Must start with EINTG banks, ordered by EINT group number. */ EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00), EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc0", 0x04), @@ -323,37 +324,37 @@ static const struct samsung_pin_bank_data exynos7_pin_banks1[] __initconst = { }; /* pin banks of exynos7 pin-controller - NFC */ -static const struct samsung_pin_bank_data exynos7_pin_banks2[] __initconst = { +static const struct samsung_pin_bank_data exynos7_pin_banks2[] = { /* Must start with EINTG banks, ordered by EINT group number. */ EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00), }; /* pin banks of exynos7 pin-controller - TOUCH */ -static const struct samsung_pin_bank_data exynos7_pin_banks3[] __initconst = { +static const struct samsung_pin_bank_data exynos7_pin_banks3[] = { /* Must start with EINTG banks, ordered by EINT group number. */ EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00), }; /* pin banks of exynos7 pin-controller - FF */ -static const struct samsung_pin_bank_data exynos7_pin_banks4[] __initconst = { +static const struct samsung_pin_bank_data exynos7_pin_banks4[] = { /* Must start with EINTG banks, ordered by EINT group number. */ EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpg4", 0x00), }; /* pin banks of exynos7 pin-controller - ESE */ -static const struct samsung_pin_bank_data exynos7_pin_banks5[] __initconst = { +static const struct samsung_pin_bank_data exynos7_pin_banks5[] = { /* Must start with EINTG banks, ordered by EINT group number. */ EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpv7", 0x00), }; /* pin banks of exynos7 pin-controller - FSYS0 */ -static const struct samsung_pin_bank_data exynos7_pin_banks6[] __initconst = { +static const struct samsung_pin_bank_data exynos7_pin_banks6[] = { /* Must start with EINTG banks, ordered by EINT group number. */ EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpr4", 0x00), }; /* pin banks of exynos7 pin-controller - FSYS1 */ -static const struct samsung_pin_bank_data exynos7_pin_banks7[] __initconst = { +static const struct samsung_pin_bank_data exynos7_pin_banks7[] = { /* Must start with EINTG banks, ordered by EINT group number. */ EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpr0", 0x00), EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpr1", 0x04), @@ -362,7 +363,7 @@ static const struct samsung_pin_bank_data exynos7_pin_banks7[] __initconst = { }; /* pin banks of exynos7 pin-controller - BUS1 */ -static const struct samsung_pin_bank_data exynos7_pin_banks8[] __initconst = { +static const struct samsung_pin_bank_data exynos7_pin_banks8[] = { /* Must start with EINTG banks, ordered by EINT group number. */ EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpf0", 0x00), EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpf1", 0x04), @@ -376,13 +377,13 @@ static const struct samsung_pin_bank_data exynos7_pin_banks8[] __initconst = { EXYNOS_PIN_BANK_EINTG(3, 0x140, "gpv6", 0x24), }; -static const struct samsung_pin_bank_data exynos7_pin_banks9[] __initconst = { +static const struct samsung_pin_bank_data exynos7_pin_banks9[] = { /* Must start with EINTG banks, ordered by EINT group number. */ EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00), EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04), }; -static const struct samsung_pin_ctrl exynos7_pin_ctrl[] __initconst = { +static const struct samsung_pin_ctrl exynos7_pin_ctrl[] = { { /* pin-controller instance 0 Alive data */ .pin_banks = exynos7_pin_banks0, @@ -436,13 +437,14 @@ static const struct samsung_pin_ctrl exynos7_pin_ctrl[] __initconst = { }, }; -const struct samsung_pinctrl_of_match_data exynos7_of_data __initconst = { +const struct samsung_pinctrl_of_match_data exynos7_of_data = { .ctrl = exynos7_pin_ctrl, .num_ctrl = ARRAY_SIZE(exynos7_pin_ctrl), }; +EXPORT_SYMBOL_GPL(exynos7_of_data); /* pin banks of exynos850 pin-controller 0 (ALIVE) */ -static const struct samsung_pin_bank_data exynos850_pin_banks0[] __initconst = { +static const struct samsung_pin_bank_data exynos850_pin_banks0[] = { /* Must start with EINTG banks, ordered by EINT group number. */ EXYNOS850_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00), EXYNOS850_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04), @@ -453,7 +455,7 @@ static const struct samsung_pin_bank_data exynos850_pin_banks0[] __initconst = { }; /* pin banks of exynos850 pin-controller 1 (CMGP) */ -static const struct samsung_pin_bank_data exynos850_pin_banks1[] __initconst = { +static const struct samsung_pin_bank_data exynos850_pin_banks1[] = { /* Must start with EINTG banks, ordered by EINT group number. */ EXYNOS850_PIN_BANK_EINTW(1, 0x000, "gpm0", 0x00), EXYNOS850_PIN_BANK_EINTW(1, 0x020, "gpm1", 0x04), @@ -466,27 +468,27 @@ static const struct samsung_pin_bank_data exynos850_pin_banks1[] __initconst = { }; /* pin banks of exynos850 pin-controller 2 (AUD) */ -static const struct samsung_pin_bank_data exynos850_pin_banks2[] __initconst = { +static const struct samsung_pin_bank_data exynos850_pin_banks2[] = { /* Must start with EINTG banks, ordered by EINT group number. */ EXYNOS850_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00), EXYNOS850_PIN_BANK_EINTG(5, 0x020, "gpb1", 0x04), }; /* pin banks of exynos850 pin-controller 3 (HSI) */ -static const struct samsung_pin_bank_data exynos850_pin_banks3[] __initconst = { +static const struct samsung_pin_bank_data exynos850_pin_banks3[] = { /* Must start with EINTG banks, ordered by EINT group number. */ EXYNOS850_PIN_BANK_EINTG(6, 0x000, "gpf2", 0x00), }; /* pin banks of exynos850 pin-controller 4 (CORE) */ -static const struct samsung_pin_bank_data exynos850_pin_banks4[] __initconst = { +static const struct samsung_pin_bank_data exynos850_pin_banks4[] = { /* Must start with EINTG banks, ordered by EINT group number. */ EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpf0", 0x00), EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpf1", 0x04), }; /* pin banks of exynos850 pin-controller 5 (PERI) */ -static const struct samsung_pin_bank_data exynos850_pin_banks5[] __initconst = { +static const struct samsung_pin_bank_data exynos850_pin_banks5[] = { /* Must start with EINTG banks, ordered by EINT group number. */ EXYNOS850_PIN_BANK_EINTG(2, 0x000, "gpg0", 0x00), EXYNOS850_PIN_BANK_EINTG(6, 0x020, "gpp0", 0x04), @@ -499,7 +501,7 @@ static const struct samsung_pin_bank_data exynos850_pin_banks5[] __initconst = { EXYNOS850_PIN_BANK_EINTG(6, 0x100, "gpc1", 0x20), }; -static const struct samsung_pin_ctrl exynos850_pin_ctrl[] __initconst = { +static const struct samsung_pin_ctrl exynos850_pin_ctrl[] = { { /* pin-controller instance 0 ALIVE data */ .pin_banks = exynos850_pin_banks0, @@ -534,7 +536,8 @@ static const struct samsung_pin_ctrl exynos850_pin_ctrl[] __initconst = { }, }; -const struct samsung_pinctrl_of_match_data exynos850_of_data __initconst = { +const struct samsung_pinctrl_of_match_data exynos850_of_data = { .ctrl = exynos850_pin_ctrl, .num_ctrl = ARRAY_SIZE(exynos850_pin_ctrl), }; +EXPORT_SYMBOL_GPL(exynos850_of_data); diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c index 0489c899b401..628c6e94d08c 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -207,7 +208,7 @@ static void exynos_irq_release_resources(struct irq_data *irqd) /* * irq_chip for gpio interrupts. */ -static const struct exynos_irq_chip exynos_gpio_irq_chip __initconst = { +static const struct exynos_irq_chip exynos_gpio_irq_chip = { .chip = { .name = "exynos_gpio_irq_chip", .irq_unmask = exynos_irq_unmask, @@ -275,7 +276,7 @@ struct exynos_eint_gpio_save { * exynos_eint_gpio_init() - setup handling of external gpio interrupts. * @d: driver data of samsung pinctrl driver. */ -__init int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d) +int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d) { struct samsung_pin_bank *bank; struct device *dev = d->dev; @@ -399,7 +400,7 @@ static u32 eint_wake_mask_value = EXYNOS_EINT_WAKEUP_MASK_DISABLED; /* * irq_chip for wakeup interrupts */ -static const struct exynos_irq_chip s5pv210_wkup_irq_chip __initconst = { +static const struct exynos_irq_chip s5pv210_wkup_irq_chip = { .chip = { .name = "s5pv210_wkup_irq_chip", .irq_unmask = exynos_irq_unmask, @@ -419,7 +420,7 @@ static const struct exynos_irq_chip s5pv210_wkup_irq_chip __initconst = { .set_eint_wakeup_mask = s5pv210_pinctrl_set_eint_wakeup_mask, }; -static const struct exynos_irq_chip exynos4210_wkup_irq_chip __initconst = { +static const struct exynos_irq_chip exynos4210_wkup_irq_chip = { .chip = { .name = "exynos4210_wkup_irq_chip", .irq_unmask = exynos_irq_unmask, @@ -438,7 +439,7 @@ static const struct exynos_irq_chip exynos4210_wkup_irq_chip __initconst = { .set_eint_wakeup_mask = exynos_pinctrl_set_eint_wakeup_mask, }; -static const struct exynos_irq_chip exynos7_wkup_irq_chip __initconst = { +static const struct exynos_irq_chip exynos7_wkup_irq_chip = { .chip = { .name = "exynos7_wkup_irq_chip", .irq_unmask = exynos_irq_unmask, @@ -521,7 +522,7 @@ static void exynos_irq_demux_eint16_31(struct irq_desc *desc) * exynos_eint_wkup_init() - setup handling of external wakeup interrupts. * @d: driver data of samsung pinctrl driver. */ -__init int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d) +int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d) { struct device *dev = d->dev; struct device_node *wkup_np = NULL; @@ -760,3 +761,7 @@ exynos_retention_init(struct samsung_pinctrl_drv_data *drvdata, return ctrl; } + +MODULE_DESCRIPTION("Pinctrl common driver for Exynos, S3C24XX, and S3C64XX SoCs"); +MODULE_AUTHOR("Thomas Abraham "); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c index 2a0fc63516f1..7a5f1363d0d1 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.c +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -1299,8 +1300,8 @@ static struct platform_driver samsung_pinctrl_driver = { }, }; -static int __init samsung_pinctrl_drv_register(void) -{ - return platform_driver_register(&samsung_pinctrl_driver); -} -postcore_initcall(samsung_pinctrl_drv_register); +module_platform_driver(samsung_pinctrl_driver); + +MODULE_DESCRIPTION("Pinctrl common driver for Exynos, S3C24XX, and S3C64XX SoCs"); +MODULE_AUTHOR("Thomas Abraham "); +MODULE_LICENSE("GPL v2"); From patchwork Tue Sep 28 23:56:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William McVicker X-Patchwork-Id: 12524135 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BF804C433FE for ; Tue, 28 Sep 2021 23:57:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AAF5161159 for ; Tue, 28 Sep 2021 23:57:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243511AbhI1X7N (ORCPT ); Tue, 28 Sep 2021 19:59:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43186 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243468AbhI1X66 (ORCPT ); Tue, 28 Sep 2021 19:58:58 -0400 Received: from mail-pl1-x64a.google.com (mail-pl1-x64a.google.com [IPv6:2607:f8b0:4864:20::64a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 952C9C0613E9 for ; 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Tue, 28 Sep 2021 16:57:12 -0700 (PDT) Date: Tue, 28 Sep 2021 23:56:26 +0000 In-Reply-To: <20210928235635.1348330-1-willmcvicker@google.com> Message-Id: <20210928235635.1348330-10-willmcvicker@google.com> Mime-Version: 1.0 References: <20210928235635.1348330-1-willmcvicker@google.com> X-Mailer: git-send-email 2.33.0.685.g46640cef36-goog Subject: [PATCH v2 09/12] pinctrl: samsung: set PINCTRL_EXYNOS and PINCTRL_SAMSUNG as tristate From: Will McVicker To: Russell King , Krzysztof Kozlowski , Catalin Marinas , Will Deacon , Michael Turquette , Stephen Boyd , Sylwester Nawrocki , Tomasz Figa , Chanwoo Choi , Linus Walleij , Alessandro Zummo , Alexandre Belloni , John Stultz , Thomas Gleixner Cc: Lee Jones , Geert Uytterhoeven , Saravana Kannan , Will McVicker , kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-rtc@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Make PINCTRL_EXYNOS and PINCTRL_SAMSUNG tristate so that we can compile them as modules. Also don't have ARCH_EXYNOS directly select them, but use "default y if ARCH_EXYNOS || ARCH_S5PV210" instead. Signed-off-by: Will McVicker --- arch/arm/mach-exynos/Kconfig | 1 - arch/arm/mach-s5pv210/Kconfig | 1 - arch/arm64/Kconfig.platforms | 1 - drivers/pinctrl/samsung/Kconfig | 5 +++-- 4 files changed, 3 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 01b8e8b8d95d..afc8cd062605 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -22,7 +22,6 @@ menuconfig ARCH_EXYNOS select HAVE_S3C2410_I2C if I2C select HAVE_S3C_RTC if RTC_CLASS select PINCTRL - select PINCTRL_EXYNOS select PM_GENERIC_DOMAINS if PM select S5P_DEV_MFC select SAMSUNG_MC diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig index 3d7e0b5739d8..62b90dda571f 100644 --- a/arch/arm/mach-s5pv210/Kconfig +++ b/arch/arm/mach-s5pv210/Kconfig @@ -14,7 +14,6 @@ config ARCH_S5PV210 select HAVE_S3C2410_I2C if I2C select HAVE_S3C_RTC if RTC_CLASS select PINCTRL - select PINCTRL_EXYNOS select SOC_SAMSUNG help Samsung S5PV210/S5PC110 series based systems diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index e6d4abadacd8..67f60cc3c723 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -95,7 +95,6 @@ config ARCH_EXYNOS select EXYNOS_PMU select HAVE_S3C_RTC if RTC_CLASS select PINCTRL - select PINCTRL_EXYNOS select PM_GENERIC_DOMAINS if PM select SOC_SAMSUNG help diff --git a/drivers/pinctrl/samsung/Kconfig b/drivers/pinctrl/samsung/Kconfig index dfd805e76862..caeb865cfa21 100644 --- a/drivers/pinctrl/samsung/Kconfig +++ b/drivers/pinctrl/samsung/Kconfig @@ -3,15 +3,16 @@ # Samsung Pin control drivers # config PINCTRL_SAMSUNG - bool + tristate "Pinctrl common driver for Exynos, S3C24XX, and S3C64XX SoCs" if COMPILE_TEST depends on OF_GPIO select PINMUX select PINCONF config PINCTRL_EXYNOS - bool "Pinctrl common driver part for Samsung Exynos SoCs" + tristate "Pinctrl common driver part for Samsung Exynos ARM and ARM64 SoCs" depends on OF_GPIO depends on ARCH_EXYNOS || ARCH_S5PV210 || COMPILE_TEST + default y if (ARCH_EXYNOS || ARCH_S5PV210) select PINCTRL_SAMSUNG select PINCTRL_EXYNOS_ARM if ARM && (ARCH_EXYNOS || ARCH_S5PV210) select PINCTRL_EXYNOS_ARM64 if ARM64 && ARCH_EXYNOS From patchwork Tue Sep 28 23:56:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William McVicker X-Patchwork-Id: 12524139 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 608AFC43219 for ; Tue, 28 Sep 2021 23:57:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4C49F61157 for ; Tue, 28 Sep 2021 23:57:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243563AbhI1X7Q (ORCPT ); Tue, 28 Sep 2021 19:59:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43216 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243396AbhI1X7D (ORCPT ); Tue, 28 Sep 2021 19:59:03 -0400 Received: from mail-pg1-x549.google.com (mail-pg1-x549.google.com [IPv6:2607:f8b0:4864:20::549]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B2F23C061767 for ; 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Tue, 28 Sep 2021 16:57:14 -0700 (PDT) Date: Tue, 28 Sep 2021 23:56:27 +0000 In-Reply-To: <20210928235635.1348330-1-willmcvicker@google.com> Message-Id: <20210928235635.1348330-11-willmcvicker@google.com> Mime-Version: 1.0 References: <20210928235635.1348330-1-willmcvicker@google.com> X-Mailer: git-send-email 2.33.0.685.g46640cef36-goog Subject: [PATCH v2 10/12] soc: samsung: pmu: modularize the Exynos ARMv8 PMU driver From: Will McVicker To: Russell King , Krzysztof Kozlowski , Catalin Marinas , Will Deacon , Michael Turquette , Stephen Boyd , Sylwester Nawrocki , Tomasz Figa , Chanwoo Choi , Linus Walleij , Alessandro Zummo , Alexandre Belloni , John Stultz , Thomas Gleixner Cc: Lee Jones , Geert Uytterhoeven , Saravana Kannan , Will McVicker , kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-rtc@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org In order to only modularize the Exynos ARMv8 PMU driver, we have to split it up from the ARM PMU driver. So make the following Kconfig changes: * EXYNOS_PMU -> EXYNOS_PMU_ARM64 * EXYNOS_PMU_ARM_DRIVERS -> EXYNOS_PMU_ARM This patch also includes the necessary modularization changes. Lastly, have EXYNOS_PMU_ARM64 use "default y if ARCH_EXYNOS && ARM64" instead of having ARCH_EXYNOS select it directly. Signed-off-by: Will McVicker --- arch/arm/mach-exynos/Kconfig | 2 +- arch/arm64/Kconfig.platforms | 1 - drivers/soc/samsung/Kconfig | 15 +++++++++------ drivers/soc/samsung/Makefile | 8 +++++--- drivers/soc/samsung/exynos-pmu.c | 13 +++++++------ drivers/soc/samsung/exynos-pmu.h | 2 +- include/linux/soc/samsung/exynos-pmu.h | 2 +- 7 files changed, 24 insertions(+), 19 deletions(-) diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index afc8cd062605..e97e1d8f7b00 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -13,7 +13,7 @@ menuconfig ARCH_EXYNOS select ARM_GIC select EXYNOS_IRQ_COMBINER select EXYNOS_THERMAL - select EXYNOS_PMU + select EXYNOS_PMU_ARM select EXYNOS_SROM select EXYNOS_PM_DOMAINS if PM_GENERIC_DOMAINS select GPIOLIB diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 67f60cc3c723..e5e4b9b2fb97 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -92,7 +92,6 @@ config ARCH_BRCMSTB config ARCH_EXYNOS bool "ARMv8 based Samsung Exynos SoC family" select EXYNOS_PM_DOMAINS if PM_GENERIC_DOMAINS - select EXYNOS_PMU select HAVE_S3C_RTC if RTC_CLASS select PINCTRL select PM_GENERIC_DOMAINS if PM diff --git a/drivers/soc/samsung/Kconfig b/drivers/soc/samsung/Kconfig index d3746415be72..fdf1162ec98b 100644 --- a/drivers/soc/samsung/Kconfig +++ b/drivers/soc/samsung/Kconfig @@ -23,15 +23,18 @@ config EXYNOS_CHIPID Support for Samsung Exynos SoC ChipID and Adaptive Supply Voltage. This driver can also be built as module (exynos_chipid). -config EXYNOS_PMU - bool "Exynos PMU controller driver" if COMPILE_TEST - depends on ARCH_EXYNOS || ((ARM || ARM64) && COMPILE_TEST) - select EXYNOS_PMU_ARM_DRIVERS if ARM && ARCH_EXYNOS +config EXYNOS_PMU_ARM64 + tristate "Exynos PMU controller driver" + depends on ARCH_EXYNOS || (ARM64 && COMPILE_TEST) + default y if (ARCH_EXYNOS && ARM64) + help + Support for Samsung Exynos ARMv8 PMU controller. This driver can be + built-in or as a module (exynos-pmu). # There is no need to enable these drivers for ARMv8 -config EXYNOS_PMU_ARM_DRIVERS +config EXYNOS_PMU_ARM bool "Exynos PMU ARMv7-specific driver extensions" if COMPILE_TEST - depends on EXYNOS_PMU + depends on ARCH_EXYNOS || (ARM && COMPILE_TEST) config EXYNOS_PM_DOMAINS bool "Exynos PM domains" if COMPILE_TEST diff --git a/drivers/soc/samsung/Makefile b/drivers/soc/samsung/Makefile index 2ae4bea804cf..cd55c72a052d 100644 --- a/drivers/soc/samsung/Makefile +++ b/drivers/soc/samsung/Makefile @@ -4,10 +4,12 @@ obj-$(CONFIG_EXYNOS_ASV_ARM) += exynos5422-asv.o obj-$(CONFIG_EXYNOS_CHIPID) += exynos_chipid.o exynos_chipid-y += exynos-chipid.o exynos-asv.o -obj-$(CONFIG_EXYNOS_PMU) += exynos-pmu.o +obj-$(CONFIG_EXYNOS_PMU_ARM64) += exynos-pmu.o + +obj-$(CONFIG_EXYNOS_PMU_ARM) += exynos-pmu32.o +exynos-pmu32-y += exynos-pmu.o exynos3250-pmu.o \ + exynos4-pmu.o exynos5250-pmu.o exynos5420-pmu.o -obj-$(CONFIG_EXYNOS_PMU_ARM_DRIVERS) += exynos3250-pmu.o exynos4-pmu.o \ - exynos5250-pmu.o exynos5420-pmu.o obj-$(CONFIG_EXYNOS_PM_DOMAINS) += pm_domains.o obj-$(CONFIG_EXYNOS_REGULATOR_COUPLER) += exynos-regulator-coupler.o diff --git a/drivers/soc/samsung/exynos-pmu.c b/drivers/soc/samsung/exynos-pmu.c index a18c93a4646c..3dd0219c908c 100644 --- a/drivers/soc/samsung/exynos-pmu.c +++ b/drivers/soc/samsung/exynos-pmu.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -63,7 +64,7 @@ void exynos_sys_powerdown_conf(enum sys_powerdown mode) * Split the data between ARM architectures because it is relatively big * and useless on other arch. */ -#ifdef CONFIG_EXYNOS_PMU_ARM_DRIVERS +#ifdef CONFIG_EXYNOS_PMU_ARM #define exynos_pmu_data_arm_ptr(data) (&data) #else #define exynos_pmu_data_arm_ptr(data) NULL @@ -154,9 +155,9 @@ static struct platform_driver exynos_pmu_driver = { .probe = exynos_pmu_probe, }; -static int __init exynos_pmu_init(void) -{ - return platform_driver_register(&exynos_pmu_driver); +module_platform_driver(exynos_pmu_driver); -} -postcore_initcall(exynos_pmu_init); +MODULE_DESCRIPTION("Exynos PMU controller driver"); +MODULE_AUTHOR("Marek Szyprowski "); +MODULE_AUTHOR("Krzysztof Kozlowski "); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/soc/samsung/exynos-pmu.h b/drivers/soc/samsung/exynos-pmu.h index 5e851f32307e..4a7f03c79dd0 100644 --- a/drivers/soc/samsung/exynos-pmu.h +++ b/drivers/soc/samsung/exynos-pmu.h @@ -28,7 +28,7 @@ struct exynos_pmu_data { extern void __iomem *pmu_base_addr; -#ifdef CONFIG_EXYNOS_PMU_ARM_DRIVERS +#ifdef CONFIG_EXYNOS_PMU_ARM /* list of all exported SoC specific data */ extern const struct exynos_pmu_data exynos3250_pmu_data; extern const struct exynos_pmu_data exynos4210_pmu_data; diff --git a/include/linux/soc/samsung/exynos-pmu.h b/include/linux/soc/samsung/exynos-pmu.h index a4f5516cc956..d7317e0902b8 100644 --- a/include/linux/soc/samsung/exynos-pmu.h +++ b/include/linux/soc/samsung/exynos-pmu.h @@ -19,7 +19,7 @@ enum sys_powerdown { }; extern void exynos_sys_powerdown_conf(enum sys_powerdown mode); -#ifdef CONFIG_EXYNOS_PMU +#if IS_ENABLED(CONFIG_EXYNOS_PMU_ARM64) || IS_ENABLED(CONFIG_EXYNOS_PMU_ARM) extern struct regmap *exynos_get_pmu_regmap(void); #else static inline struct regmap *exynos_get_pmu_regmap(void) From patchwork Tue Sep 28 23:56:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William McVicker X-Patchwork-Id: 12524141 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0789DC433EF for ; Tue, 28 Sep 2021 23:57:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EAFBE613A0 for ; Tue, 28 Sep 2021 23:57:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243383AbhI1X7Q (ORCPT ); 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Tue, 28 Sep 2021 16:57:16 -0700 (PDT) Date: Tue, 28 Sep 2021 23:56:28 +0000 In-Reply-To: <20210928235635.1348330-1-willmcvicker@google.com> Message-Id: <20210928235635.1348330-12-willmcvicker@google.com> Mime-Version: 1.0 References: <20210928235635.1348330-1-willmcvicker@google.com> X-Mailer: git-send-email 2.33.0.685.g46640cef36-goog Subject: [PATCH v2 11/12] soc: samsung: pm_domains: modularize EXYNOS_PM_DOMAINS From: Will McVicker To: Russell King , Krzysztof Kozlowski , Catalin Marinas , Will Deacon , Michael Turquette , Stephen Boyd , Sylwester Nawrocki , Tomasz Figa , Chanwoo Choi , Linus Walleij , Alessandro Zummo , Alexandre Belloni , John Stultz , Thomas Gleixner Cc: Lee Jones , Geert Uytterhoeven , Saravana Kannan , Will McVicker , kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-rtc@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Convert the Exynos PM Domains driver into a module. This includes setting EXYNOS_PM_DOMAINS as tristate and removing it from being auto-selected by ARCH_EXYNOS. Instead, the config will use "default y if ARCH_EXYNOS" which allows us to set it to a module via the defconfig now. Signed-off-by: Will McVicker --- arch/arm/mach-exynos/Kconfig | 1 - arch/arm64/Kconfig.platforms | 1 - drivers/soc/samsung/Kconfig | 3 ++- drivers/soc/samsung/pm_domains.c | 12 +++++++----- 4 files changed, 9 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index e97e1d8f7b00..2ad19a08bf06 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -15,7 +15,6 @@ menuconfig ARCH_EXYNOS select EXYNOS_THERMAL select EXYNOS_PMU_ARM select EXYNOS_SROM - select EXYNOS_PM_DOMAINS if PM_GENERIC_DOMAINS select GPIOLIB select HAVE_ARM_ARCH_TIMER if ARCH_EXYNOS5 select HAVE_ARM_SCU if SMP diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index e5e4b9b2fb97..e44d5e9f5058 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -91,7 +91,6 @@ config ARCH_BRCMSTB config ARCH_EXYNOS bool "ARMv8 based Samsung Exynos SoC family" - select EXYNOS_PM_DOMAINS if PM_GENERIC_DOMAINS select HAVE_S3C_RTC if RTC_CLASS select PINCTRL select PM_GENERIC_DOMAINS if PM diff --git a/drivers/soc/samsung/Kconfig b/drivers/soc/samsung/Kconfig index fdf1162ec98b..e4743c29f73c 100644 --- a/drivers/soc/samsung/Kconfig +++ b/drivers/soc/samsung/Kconfig @@ -37,8 +37,9 @@ config EXYNOS_PMU_ARM depends on ARCH_EXYNOS || (ARM && COMPILE_TEST) config EXYNOS_PM_DOMAINS - bool "Exynos PM domains" if COMPILE_TEST + tristate "Exynos PM domains" depends on (ARCH_EXYNOS && PM_GENERIC_DOMAINS) || COMPILE_TEST + default y if ARCH_EXYNOS config SAMSUNG_PM_DEBUG bool "Samsung PM Suspend debug" diff --git a/drivers/soc/samsung/pm_domains.c b/drivers/soc/samsung/pm_domains.c index 5ec0c13f0aaf..6144733fa3c2 100644 --- a/drivers/soc/samsung/pm_domains.c +++ b/drivers/soc/samsung/pm_domains.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -160,8 +161,9 @@ static struct platform_driver exynos_pd_driver = { } }; -static __init int exynos4_pm_init_power_domain(void) -{ - return platform_driver_register(&exynos_pd_driver); -} -core_initcall(exynos4_pm_init_power_domain); +module_platform_driver(exynos_pd_driver); + +MODULE_DESCRIPTION("Exynos PM domains driver"); +MODULE_AUTHOR("Marek Szyprowski "); +MODULE_AUTHOR("Krzysztof Kozlowski "); +MODULE_LICENSE("GPL v2"); From patchwork Tue Sep 28 23:56:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William McVicker X-Patchwork-Id: 12524143 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3ABD0C433FE for ; Tue, 28 Sep 2021 23:57:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 21FD661159 for ; Tue, 28 Sep 2021 23:57:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243601AbhI1X7U (ORCPT ); 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Also, one less config to keep track of! Signed-off-by: Will McVicker Acked-by: Alexandre Belloni --- arch/arm/Kconfig | 1 - arch/arm/mach-exynos/Kconfig | 1 - arch/arm/mach-s5pv210/Kconfig | 1 - arch/arm64/Kconfig.platforms | 1 - drivers/rtc/Kconfig | 10 ++-------- 5 files changed, 2 insertions(+), 12 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index fc196421b2ce..5ed6b5de981e 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -475,7 +475,6 @@ config ARCH_S3C24XX select GPIOLIB select GENERIC_IRQ_MULTI_HANDLER select HAVE_S3C2410_I2C if I2C - select HAVE_S3C_RTC if RTC_CLASS select NEED_MACH_IO_H select S3C2410_WATCHDOG select SAMSUNG_ATAGS diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 2ad19a08bf06..8b72a70b6c43 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -19,7 +19,6 @@ menuconfig ARCH_EXYNOS select HAVE_ARM_ARCH_TIMER if ARCH_EXYNOS5 select HAVE_ARM_SCU if SMP select HAVE_S3C2410_I2C if I2C - select HAVE_S3C_RTC if RTC_CLASS select PINCTRL select PM_GENERIC_DOMAINS if PM select S5P_DEV_MFC diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig index 62b90dda571f..681823687018 100644 --- a/arch/arm/mach-s5pv210/Kconfig +++ b/arch/arm/mach-s5pv210/Kconfig @@ -12,7 +12,6 @@ config ARCH_S5PV210 select CLKSRC_SAMSUNG_PWM select GPIOLIB select HAVE_S3C2410_I2C if I2C - select HAVE_S3C_RTC if RTC_CLASS select PINCTRL select SOC_SAMSUNG help diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index e44d5e9f5058..02c8637d3f09 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -91,7 +91,6 @@ config ARCH_BRCMSTB config ARCH_EXYNOS bool "ARMv8 based Samsung Exynos SoC family" - select HAVE_S3C_RTC if RTC_CLASS select PINCTRL select PM_GENERIC_DOMAINS if PM select SOC_SAMSUNG diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index e1bc5214494e..7208eeb8459a 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -1404,16 +1404,10 @@ config RTC_DRV_OMAP This driver can also be built as a module, if so, module will be called rtc-omap. -config HAVE_S3C_RTC - bool - help - This will include RTC support for Samsung SoCs. If - you want to include RTC support for any machine, kindly - select this in the respective mach-XXXX/Kconfig file. - config RTC_DRV_S3C tristate "Samsung S3C series SoC RTC" - depends on ARCH_S3C64XX || HAVE_S3C_RTC || COMPILE_TEST + depends on ARCH_EXYNOS || ARCH_S3C64XX || ARCH_S3C24XX || ARCH_S5PV210 || \ + COMPILE_TEST help RTC (Realtime Clock) driver for the clock inbuilt into the Samsung S3C24XX series of SoCs. This can provide periodic