From patchwork Sat Oct 2 00:59:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Stach X-Patchwork-Id: 12531833 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4E064C433EF for ; Sat, 2 Oct 2021 01:02:28 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 07A026115A for ; Sat, 2 Oct 2021 01:02:28 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 07A026115A Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=5sFuCdyGPrgqb1ODD9dfV9R914HRgbzxwQOPeZ9Bpko=; b=p2uD7pP94CeVhf KUqoJ7aZQ7ZF9OZ82uMnKFEuOW6vBYB+p6H98ze4eui42l4Zsb0NSXmu72aZmuOrg/eqv1joE4BgB e1MEPdtM+uN2wIf+ceaiq0u/afjn94uOWtDxKEjK9QhuvgTYD5t2/MV+oASmQnj9J3MKMKR2KdUHK LrOeivvqhe4uHLpdgJkB8taIxFuiEQar3pTgGTpeyV99ebOYop28OA4VDalWzcdnc01gMYZ8teI8v xQb/ezcJ2tqU6TlXLFYrEB9Iz8y5vZYGILBDjwtyrYc+5lvtsB+mWXHBrbmgqKiiiGPueEOxwOZrY VBgUoKew31umb8e+NwzA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mWTNz-001aGA-SA; Sat, 02 Oct 2021 01:00:19 +0000 Received: from metis.ext.pengutronix.de ([2001:67c:670:201:290:27ff:fe1d:cc33]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mWTNl-001a7o-8h for linux-arm-kernel@lists.infradead.org; Sat, 02 Oct 2021 01:00:06 +0000 Received: from dude03.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::39]) by metis.ext.pengutronix.de with esmtp (Exim 4.92) (envelope-from ) id 1mWTNe-0005o6-6V; Sat, 02 Oct 2021 02:59:58 +0200 From: Lucas Stach To: Shawn Guo Cc: Rob Herring , Fabio Estevam , NXP Linux Team , Adam Ford , Frieder Schrempf , Marek Vasut , Tim Harvey , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@pengutronix.de, patchwork-lst@pengutronix.de Subject: [PATCH v5 01/18] Revert "soc: imx: gpcv2: move reset assert after requesting domain power up" Date: Sat, 2 Oct 2021 02:59:37 +0200 Message-Id: <20211002005954.1367653-2-l.stach@pengutronix.de> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211002005954.1367653-1-l.stach@pengutronix.de> References: <20211002005954.1367653-1-l.stach@pengutronix.de> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2a0a:edc0:0:1101:1d::39 X-SA-Exim-Mail-From: l.stach@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211001_180005_381176_13CCCC36 X-CRM114-Status: GOOD ( 13.83 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This reverts commit a77ebdd9f553. It turns out that the VPU domain has no different requirements, even though the downstream ATF implementation seems to suggest otherwise. Powering on the domain with the reset asserted works fine. As the changed sequence has caused sporadic issues with the GPU domains, just revert the change to go back to the working sequence. Cc: # 5.14 Signed-off-by: Lucas Stach Acked-by: Peng Fan Tested-by: Adam Ford #imx8mm-beacon --- drivers/soc/imx/gpcv2.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index 34a9ac1f2b9b..8b7a01773aec 100644 --- a/drivers/soc/imx/gpcv2.c +++ b/drivers/soc/imx/gpcv2.c @@ -244,6 +244,8 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd) goto out_regulator_disable; } + reset_control_assert(domain->reset); + if (domain->bits.pxx) { /* request the domain to power up */ regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PUP_REQ, @@ -266,8 +268,6 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd) GPC_PGC_CTRL_PCR); } - reset_control_assert(domain->reset); - /* delay for reset to propagate */ udelay(5); From patchwork Sat Oct 2 00:59:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Stach X-Patchwork-Id: 12531841 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 32179C433EF for ; Sat, 2 Oct 2021 01:03:02 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id F37B161A81 for ; Sat, 2 Oct 2021 01:03:01 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org F37B161A81 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=XKuZWWzsiZZF5+Db6Dnp34pLoHh3ELAcIE064sBVx8I=; b=tmqJjgchraZ4Tg JNYAwdVhpaNFUPCGrkslgOb9IHFlWwoedzV4avtx93+X2qq/GmSTzrJEpOeFzX5JBpC1NmuqgCkn2 VDlRs2fy3xgSGnNJj9GaSt/lTYY/ImegKK8qRdJHOvFlETuD8b+xAIN2congP6Fu6hy/afjxVOUa+ ar61Ar9Ql2Q8aTFka+4WC4u/hz6DgWpu0KTl51p3iCpGXoQamjJ771Cbk6vV56qtTOWMw7ErJWIue HqM3jT6kr0JgO0lNWK/uZzKQ8KnjXpSyQaaB7VQTxdazEXBMk1TStxKmAQpxZqF9qTLwL+xTZ+xwY Zv8FrFMPzcARsuhNw4oQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mWTOT-001aKz-58; Sat, 02 Oct 2021 01:00:49 +0000 Received: from metis.ext.pengutronix.de ([2001:67c:670:201:290:27ff:fe1d:cc33]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mWTNl-001a7s-LN for linux-arm-kernel@lists.infradead.org; Sat, 02 Oct 2021 01:00:08 +0000 Received: from dude03.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::39]) by metis.ext.pengutronix.de with esmtp (Exim 4.92) (envelope-from ) id 1mWTNe-0005o6-UT; Sat, 02 Oct 2021 02:59:59 +0200 From: Lucas Stach To: Shawn Guo Cc: Rob Herring , Fabio Estevam , NXP Linux Team , Adam Ford , Frieder Schrempf , Marek Vasut , Tim Harvey , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@pengutronix.de, patchwork-lst@pengutronix.de Subject: [PATCH v5 02/18] soc: imx: gpcv2: Turn domain->pgc into bitfield Date: Sat, 2 Oct 2021 02:59:38 +0200 Message-Id: <20211002005954.1367653-3-l.stach@pengutronix.de> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211002005954.1367653-1-l.stach@pengutronix.de> References: <20211002005954.1367653-1-l.stach@pengutronix.de> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2a0a:edc0:0:1101:1d::39 X-SA-Exim-Mail-From: l.stach@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211001_180005_910862_908BDA73 X-CRM114-Status: GOOD ( 17.21 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Marek Vasut There is currently the MX8MM GPU domain, which is in fact a composite domain for both GPU2D and GPU3D. To correctly configure this domain, it is necessary to control both GPC_PGC_nCTRL(GPU_2D) and GPC_PGC_nCTRL(GPU_3D) at the same time. This is currently not possible. Turn the domain->pgc from value into bitfield and use for_each_set_bit() to iterate over all bits set in domain->pgc when configuring GPC_PGC_nCTRL register array. This way it is possible to configure all GPC_PGC_nCTRL registers required in a particular domain. This is a preparatory patch, no functional change. Signed-off-by: Marek Vasut Signed-off-by: Lucas Stach Reviewed-by: Peng Fan --- v2 (Lucas Stach): - rebase on top of reverted reset sequence change - also convert i.MX8MN domains --- drivers/soc/imx/gpcv2.c | 72 ++++++++++++++++++++++------------------- 1 file changed, 38 insertions(+), 34 deletions(-) diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index 8b7a01773aec..c7826ce92f0d 100644 --- a/drivers/soc/imx/gpcv2.c +++ b/drivers/soc/imx/gpcv2.c @@ -192,7 +192,7 @@ struct imx_pgc_domain { struct clk_bulk_data *clks; int num_clks; - unsigned int pgc; + unsigned long pgc; const struct { u32 pxx; @@ -220,7 +220,7 @@ to_imx_pgc_domain(struct generic_pm_domain *genpd) static int imx_pgc_power_up(struct generic_pm_domain *genpd) { struct imx_pgc_domain *domain = to_imx_pgc_domain(genpd); - u32 reg_val; + u32 reg_val, pgc; int ret; ret = pm_runtime_get_sync(domain->dev); @@ -264,8 +264,10 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd) } /* disable power control */ - regmap_clear_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc), - GPC_PGC_CTRL_PCR); + for_each_set_bit(pgc, &domain->pgc, 32) { + regmap_clear_bits(domain->regmap, GPC_PGC_CTRL(pgc), + GPC_PGC_CTRL_PCR); + } } /* delay for reset to propagate */ @@ -311,7 +313,7 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd) static int imx_pgc_power_down(struct generic_pm_domain *genpd) { struct imx_pgc_domain *domain = to_imx_pgc_domain(genpd); - u32 reg_val; + u32 reg_val, pgc; int ret; /* Enable reset clocks for all devices in the domain */ @@ -338,8 +340,10 @@ static int imx_pgc_power_down(struct generic_pm_domain *genpd) if (domain->bits.pxx) { /* enable power control */ - regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc), - GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR); + for_each_set_bit(pgc, &domain->pgc, 32) { + regmap_update_bits(domain->regmap, GPC_PGC_CTRL(pgc), + GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR); + } /* request the domain to power down */ regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PDN_REQ, @@ -389,7 +393,7 @@ static const struct imx_pgc_domain imx7_pgc_domains[] = { .map = IMX7_MIPI_PHY_A_CORE_DOMAIN, }, .voltage = 1000000, - .pgc = IMX7_PGC_MIPI, + .pgc = BIT(IMX7_PGC_MIPI), }, [IMX7_POWER_DOMAIN_PCIE_PHY] = { @@ -401,7 +405,7 @@ static const struct imx_pgc_domain imx7_pgc_domains[] = { .map = IMX7_PCIE_PHY_A_CORE_DOMAIN, }, .voltage = 1000000, - .pgc = IMX7_PGC_PCIE, + .pgc = BIT(IMX7_PGC_PCIE), }, [IMX7_POWER_DOMAIN_USB_HSIC_PHY] = { @@ -413,7 +417,7 @@ static const struct imx_pgc_domain imx7_pgc_domains[] = { .map = IMX7_USB_HSIC_PHY_A_CORE_DOMAIN, }, .voltage = 1200000, - .pgc = IMX7_PGC_USB_HSIC, + .pgc = BIT(IMX7_PGC_USB_HSIC), }, }; @@ -448,7 +452,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = { .pxx = IMX8M_MIPI_SW_Pxx_REQ, .map = IMX8M_MIPI_A53_DOMAIN, }, - .pgc = IMX8M_PGC_MIPI, + .pgc = BIT(IMX8M_PGC_MIPI), }, [IMX8M_POWER_DOMAIN_PCIE1] = { @@ -459,7 +463,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = { .pxx = IMX8M_PCIE1_SW_Pxx_REQ, .map = IMX8M_PCIE1_A53_DOMAIN, }, - .pgc = IMX8M_PGC_PCIE1, + .pgc = BIT(IMX8M_PGC_PCIE1), }, [IMX8M_POWER_DOMAIN_USB_OTG1] = { @@ -470,7 +474,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = { .pxx = IMX8M_OTG1_SW_Pxx_REQ, .map = IMX8M_OTG1_A53_DOMAIN, }, - .pgc = IMX8M_PGC_OTG1, + .pgc = BIT(IMX8M_PGC_OTG1), }, [IMX8M_POWER_DOMAIN_USB_OTG2] = { @@ -481,7 +485,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = { .pxx = IMX8M_OTG2_SW_Pxx_REQ, .map = IMX8M_OTG2_A53_DOMAIN, }, - .pgc = IMX8M_PGC_OTG2, + .pgc = BIT(IMX8M_PGC_OTG2), }, [IMX8M_POWER_DOMAIN_DDR1] = { @@ -492,7 +496,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = { .pxx = IMX8M_DDR1_SW_Pxx_REQ, .map = IMX8M_DDR2_A53_DOMAIN, }, - .pgc = IMX8M_PGC_DDR1, + .pgc = BIT(IMX8M_PGC_DDR1), }, [IMX8M_POWER_DOMAIN_GPU] = { @@ -505,7 +509,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = { .hskreq = IMX8M_GPU_HSK_PWRDNREQN, .hskack = IMX8M_GPU_HSK_PWRDNACKN, }, - .pgc = IMX8M_PGC_GPU, + .pgc = BIT(IMX8M_PGC_GPU), }, [IMX8M_POWER_DOMAIN_VPU] = { @@ -518,7 +522,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = { .hskreq = IMX8M_VPU_HSK_PWRDNREQN, .hskack = IMX8M_VPU_HSK_PWRDNACKN, }, - .pgc = IMX8M_PGC_VPU, + .pgc = BIT(IMX8M_PGC_VPU), }, [IMX8M_POWER_DOMAIN_DISP] = { @@ -531,7 +535,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = { .hskreq = IMX8M_DISP_HSK_PWRDNREQN, .hskack = IMX8M_DISP_HSK_PWRDNACKN, }, - .pgc = IMX8M_PGC_DISP, + .pgc = BIT(IMX8M_PGC_DISP), }, [IMX8M_POWER_DOMAIN_MIPI_CSI1] = { @@ -542,7 +546,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = { .pxx = IMX8M_MIPI_CSI1_SW_Pxx_REQ, .map = IMX8M_MIPI_CSI1_A53_DOMAIN, }, - .pgc = IMX8M_PGC_MIPI_CSI1, + .pgc = BIT(IMX8M_PGC_MIPI_CSI1), }, [IMX8M_POWER_DOMAIN_MIPI_CSI2] = { @@ -553,7 +557,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = { .pxx = IMX8M_MIPI_CSI2_SW_Pxx_REQ, .map = IMX8M_MIPI_CSI2_A53_DOMAIN, }, - .pgc = IMX8M_PGC_MIPI_CSI2, + .pgc = BIT(IMX8M_PGC_MIPI_CSI2), }, [IMX8M_POWER_DOMAIN_PCIE2] = { @@ -564,7 +568,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = { .pxx = IMX8M_PCIE2_SW_Pxx_REQ, .map = IMX8M_PCIE2_A53_DOMAIN, }, - .pgc = IMX8M_PGC_PCIE2, + .pgc = BIT(IMX8M_PGC_PCIE2), }, }; @@ -627,7 +631,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { .pxx = IMX8MM_PCIE_SW_Pxx_REQ, .map = IMX8MM_PCIE_A53_DOMAIN, }, - .pgc = IMX8MM_PGC_PCIE, + .pgc = BIT(IMX8MM_PGC_PCIE), }, [IMX8MM_POWER_DOMAIN_OTG1] = { @@ -638,7 +642,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { .pxx = IMX8MM_OTG1_SW_Pxx_REQ, .map = IMX8MM_OTG1_A53_DOMAIN, }, - .pgc = IMX8MM_PGC_OTG1, + .pgc = BIT(IMX8MM_PGC_OTG1), }, [IMX8MM_POWER_DOMAIN_OTG2] = { @@ -649,7 +653,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { .pxx = IMX8MM_OTG2_SW_Pxx_REQ, .map = IMX8MM_OTG2_A53_DOMAIN, }, - .pgc = IMX8MM_PGC_OTG2, + .pgc = BIT(IMX8MM_PGC_OTG2), }, [IMX8MM_POWER_DOMAIN_GPUMIX] = { @@ -662,7 +666,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { .hskreq = IMX8MM_GPUMIX_HSK_PWRDNREQN, .hskack = IMX8MM_GPUMIX_HSK_PWRDNACKN, }, - .pgc = IMX8MM_PGC_GPUMIX, + .pgc = BIT(IMX8MM_PGC_GPUMIX), }, [IMX8MM_POWER_DOMAIN_GPU] = { @@ -675,7 +679,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { .hskreq = IMX8MM_GPU_HSK_PWRDNREQN, .hskack = IMX8MM_GPU_HSK_PWRDNACKN, }, - .pgc = IMX8MM_PGC_GPU2D, + .pgc = BIT(IMX8MM_PGC_GPU2D), }, [IMX8MM_POWER_DOMAIN_VPUMIX] = { @@ -688,7 +692,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { .hskreq = IMX8MM_VPUMIX_HSK_PWRDNREQN, .hskack = IMX8MM_VPUMIX_HSK_PWRDNACKN, }, - .pgc = IMX8MM_PGC_VPUMIX, + .pgc = BIT(IMX8MM_PGC_VPUMIX), }, [IMX8MM_POWER_DOMAIN_VPUG1] = { @@ -699,7 +703,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { .pxx = IMX8MM_VPUG1_SW_Pxx_REQ, .map = IMX8MM_VPUG1_A53_DOMAIN, }, - .pgc = IMX8MM_PGC_VPUG1, + .pgc = BIT(IMX8MM_PGC_VPUG1), }, [IMX8MM_POWER_DOMAIN_VPUG2] = { @@ -710,7 +714,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { .pxx = IMX8MM_VPUG2_SW_Pxx_REQ, .map = IMX8MM_VPUG2_A53_DOMAIN, }, - .pgc = IMX8MM_PGC_VPUG2, + .pgc = BIT(IMX8MM_PGC_VPUG2), }, [IMX8MM_POWER_DOMAIN_VPUH1] = { @@ -721,7 +725,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { .pxx = IMX8MM_VPUH1_SW_Pxx_REQ, .map = IMX8MM_VPUH1_A53_DOMAIN, }, - .pgc = IMX8MM_PGC_VPUH1, + .pgc = BIT(IMX8MM_PGC_VPUH1), }, [IMX8MM_POWER_DOMAIN_DISPMIX] = { @@ -734,7 +738,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { .hskreq = IMX8MM_DISPMIX_HSK_PWRDNREQN, .hskack = IMX8MM_DISPMIX_HSK_PWRDNACKN, }, - .pgc = IMX8MM_PGC_DISPMIX, + .pgc = BIT(IMX8MM_PGC_DISPMIX), }, [IMX8MM_POWER_DOMAIN_MIPI] = { @@ -745,7 +749,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { .pxx = IMX8MM_MIPI_SW_Pxx_REQ, .map = IMX8MM_MIPI_A53_DOMAIN, }, - .pgc = IMX8MM_PGC_MIPI, + .pgc = BIT(IMX8MM_PGC_MIPI), }, }; @@ -812,7 +816,7 @@ static const struct imx_pgc_domain imx8mn_pgc_domains[] = { .pxx = IMX8MN_OTG1_SW_Pxx_REQ, .map = IMX8MN_OTG1_A53_DOMAIN, }, - .pgc = IMX8MN_PGC_OTG1, + .pgc = BIT(IMX8MN_PGC_OTG1), }, [IMX8MN_POWER_DOMAIN_GPUMIX] = { @@ -825,7 +829,7 @@ static const struct imx_pgc_domain imx8mn_pgc_domains[] = { .hskreq = IMX8MN_GPUMIX_HSK_PWRDNREQN, .hskack = IMX8MN_GPUMIX_HSK_PWRDNACKN, }, - .pgc = IMX8MN_PGC_GPUMIX, + .pgc = BIT(IMX8MN_PGC_GPUMIX), }, }; From patchwork Sat Oct 2 00:59:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Stach X-Patchwork-Id: 12531837 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 954D4C433EF for ; Sat, 2 Oct 2021 01:02:44 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5CC1761AEE for ; Sat, 2 Oct 2021 01:02:44 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 5CC1761AEE Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=X9MjO2X9WKzIVokB5mQVFY7KyYufHQoDl3+XpXLHIMg=; b=WawLUah9TzYdHC +CQda2x81kdxvWMyOlT/OFIJdggaRtXJMhjlktssRwOvof5McL0znciZVchKgpf5e0KPnV8xosI0S MJPlr08NfhrxVZwmjq3DHyLqV8xQf3ZW2IVKLd+XGjKl5XLi6ZdQNtp8uTpLKNPKm8q2EsYXH0VqH Ps5bkSi+b1KXeoqoRDHIY+o95dP+3C6nBa5s883LC6B4uTE41JI9tks0nRF6YG4Bd4jP+uleqWD4l IriOXjNJQ2mABkAJiq/ZheH1e7L+m0KGDzucm0TDu3rQk1oFcTQCrDNYDTpf06Bt5NYyD/Y81glky GPu41kaO1PJrwT2UFyvA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mWTO9-001aHb-Cw; Sat, 02 Oct 2021 01:00:29 +0000 Received: from metis.ext.pengutronix.de ([2001:67c:670:201:290:27ff:fe1d:cc33]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mWTNm-001a8U-Ir for linux-arm-kernel@lists.infradead.org; Sat, 02 Oct 2021 01:00:07 +0000 Received: from dude03.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::39]) by metis.ext.pengutronix.de with esmtp (Exim 4.92) (envelope-from ) id 1mWTNf-0005o6-Lv; Sat, 02 Oct 2021 02:59:59 +0200 From: Lucas Stach To: Shawn Guo Cc: Rob Herring , Fabio Estevam , NXP Linux Team , Adam Ford , Frieder Schrempf , Marek Vasut , Tim Harvey , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@pengutronix.de, patchwork-lst@pengutronix.de Subject: [PATCH v5 03/18] soc: imx: gpcv2: Set both GPC_PGC_nCTRL(GPU_2D|GPU_3D) for MX8MM GPU domain Date: Sat, 2 Oct 2021 02:59:39 +0200 Message-Id: <20211002005954.1367653-4-l.stach@pengutronix.de> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211002005954.1367653-1-l.stach@pengutronix.de> References: <20211002005954.1367653-1-l.stach@pengutronix.de> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2a0a:edc0:0:1101:1d::39 X-SA-Exim-Mail-From: l.stach@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211001_180006_684017_E8D66A1A X-CRM114-Status: GOOD ( 13.97 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Marek Vasut To bring up the MX8MM GPU domain, it is necessary to configure both GPC_PGC_nCTRL(GPU_2D) and GPC_PGC_nCTRL(GPU_3D) registers. Without this configuration, the system might hang on boot when bringing up the GPU power domain. This is sporadically observed on multiple disparate systems. Add the GPU3D bit into MX8MM GPU domain pgc bitfield, so that both GPC_PGC_nCTRL(GPU_2D) and GPC_PGC_nCTRL(GPU_3D) registers are configured when bringing up the GPU domain. This fixes the sporadic hang. Signed-off-by: Marek Vasut Signed-off-by: Lucas Stach Reviewed-by: Peng Fan --- drivers/soc/imx/gpcv2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index c7826ce92f0d..2c43e74db0be 100644 --- a/drivers/soc/imx/gpcv2.c +++ b/drivers/soc/imx/gpcv2.c @@ -679,7 +679,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { .hskreq = IMX8MM_GPU_HSK_PWRDNREQN, .hskack = IMX8MM_GPU_HSK_PWRDNACKN, }, - .pgc = BIT(IMX8MM_PGC_GPU2D), + .pgc = BIT(IMX8MM_PGC_GPU2D) | BIT(IMX8MM_PGC_GPU3D), }, [IMX8MM_POWER_DOMAIN_VPUMIX] = { From patchwork Sat Oct 2 00:59:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Stach X-Patchwork-Id: 12531839 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D5CF2C433EF for ; Sat, 2 Oct 2021 01:02:48 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 93E1661AEE for ; Sat, 2 Oct 2021 01:02:48 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 93E1661AEE Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=+V6I0Ytqrq6aAk2QHXw/xo1XdOLcCOfaQOyhUZ1eSvw=; b=WCLs6QKRES2Ggu 5M2JGN2Aa51L8dgksw0hdeeJg4MI2RndFRzBoD0aywLXQHJQpKxufIwzt+s9zGD6caiVMVa3Fcyuw iGK8zyiK+dpuRvky3ZOn1LdpXNtiPh5tbsYDM5rTgvVfq6nHGhA3sio8NtGoq5sZ4gst9UqdS7Lld QoTOXW4uTconpq+s4u0H/iZa4CGvPVmJ9xwpcUF86lcrKnHrotNhKYwwiFQvZj09ouxWKlPjcZznR biBwDhKPR6345JTP/8QJQ3cuUFNZ0yd5L5gcFPXDBP8k7ZrejJ+kJ+n6JFd0VxGfIbGcc4FQqYEni hsSgKTBjrvRG76Ci0T/A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mWTOJ-001aIy-0q; Sat, 02 Oct 2021 01:00:39 +0000 Received: from metis.ext.pengutronix.de ([2001:67c:670:201:290:27ff:fe1d:cc33]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mWTNm-001a8W-LP for linux-arm-kernel@lists.infradead.org; Sat, 02 Oct 2021 01:00:08 +0000 Received: from dude03.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::39]) by metis.ext.pengutronix.de with esmtp (Exim 4.92) (envelope-from ) id 1mWTNg-0005o6-DN; Sat, 02 Oct 2021 03:00:00 +0200 From: Lucas Stach To: Shawn Guo Cc: Rob Herring , Fabio Estevam , NXP Linux Team , Adam Ford , Frieder Schrempf , Marek Vasut , Tim Harvey , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@pengutronix.de, patchwork-lst@pengutronix.de Subject: [PATCH v5 04/18] soc: imx: gpcv2: add lockdep annotation Date: Sat, 2 Oct 2021 02:59:40 +0200 Message-Id: <20211002005954.1367653-5-l.stach@pengutronix.de> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211002005954.1367653-1-l.stach@pengutronix.de> References: <20211002005954.1367653-1-l.stach@pengutronix.de> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2a0a:edc0:0:1101:1d::39 X-SA-Exim-Mail-From: l.stach@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211001_180006_749115_CC43741F X-CRM114-Status: GOOD ( 12.04 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Some of the GPCv2 power domains are nested inside each other without visibility to lockdep at the genpd level, as they are in separate driver instances and don't have a parent/child power-domain relationship. Add a subclass annotation to the nested domains to let lockdep know that it is okay to take the genpd lock in a nested fashion. Signed-off-by: Lucas Stach Reviewed-by: Peng Fan --- drivers/soc/imx/gpcv2.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index 2c43e74db0be..35f26f57d1ac 100644 --- a/drivers/soc/imx/gpcv2.c +++ b/drivers/soc/imx/gpcv2.c @@ -898,6 +898,10 @@ static int imx_pgc_domain_probe(struct platform_device *pdev) goto out_domain_unmap; } + if (IS_ENABLED(CONFIG_LOCKDEP) && + of_property_read_bool(domain->dev->of_node, "power-domains")) + lockdep_set_subclass(&domain->genpd.mlock, 1); + ret = of_genpd_add_provider_simple(domain->dev->of_node, &domain->genpd); if (ret) { From patchwork Sat Oct 2 00:59:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Stach X-Patchwork-Id: 12531845 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 105A1C433F5 for ; Sat, 2 Oct 2021 01:03:20 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C9FB061AEE for ; Sat, 2 Oct 2021 01:03:19 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org C9FB061AEE Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=15UgjJ98XyRsG33BCS1z+7r6in/S3PUGBpdjAjWcAFA=; b=F3YOfaXE0WWA4O li09Yh8KcW8NR2l8qcJUltskXchMnAGz37Awv/B5WkxZTOjC+ZdoQBvQ2WcpBwUkMWGeIC76OCs29 gaWN6/CSF+FP5Vw7N8aQMxzJO05Wl1i6YdpxsMtDiDxenfYBinv9PAZMK/i6R73FadTdlTxaVMyaU qfRDjmosgZa2Cdwqqg5qnDU3xn511OaSAhGlibQHF+cRDqbMdveXesqAn+UwhuICqnfV9mZJSOLRm K3Ur/SBqHoEKS+mWPl6ANToSaqsnc+kK5KrYmFKbwkcsIWP9qdUmTgmRWOHQPN7zrRl2Z67q5TlVn suM743mMsX/35nF70hVQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mWTOd-001aOK-FW; Sat, 02 Oct 2021 01:00:59 +0000 Received: from metis.ext.pengutronix.de ([2001:67c:670:201:290:27ff:fe1d:cc33]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mWTNn-001a9C-Hu for linux-arm-kernel@lists.infradead.org; Sat, 02 Oct 2021 01:00:09 +0000 Received: from dude03.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::39]) by metis.ext.pengutronix.de with esmtp (Exim 4.92) (envelope-from ) id 1mWTNh-0005o6-4n; Sat, 02 Oct 2021 03:00:01 +0200 From: Lucas Stach To: Shawn Guo Cc: Rob Herring , Fabio Estevam , NXP Linux Team , Adam Ford , Frieder Schrempf , Marek Vasut , Tim Harvey , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@pengutronix.de, patchwork-lst@pengutronix.de Subject: [PATCH v5 05/18] soc: imx: gpcv2: add domain option to keep domain clocks enabled Date: Sat, 2 Oct 2021 02:59:41 +0200 Message-Id: <20211002005954.1367653-6-l.stach@pengutronix.de> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211002005954.1367653-1-l.stach@pengutronix.de> References: <20211002005954.1367653-1-l.stach@pengutronix.de> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2a0a:edc0:0:1101:1d::39 X-SA-Exim-Mail-From: l.stach@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211001_180007_614052_382C7549 X-CRM114-Status: GOOD ( 14.92 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Some of the MIX domains are using clocks to drive the bus bridges. Those must be enabled at all times, as long as the domain is powered up and they don't have any other consumer than the power domain. Add an option to keep the clocks attached to a domain enabled as long as the domain is power up and only disable them after the domain is powered down. Signed-off-by: Lucas Stach Reviewed-by: Peng Fan --- drivers/soc/imx/gpcv2.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index 35f26f57d1ac..c3b1d2580963 100644 --- a/drivers/soc/imx/gpcv2.c +++ b/drivers/soc/imx/gpcv2.c @@ -202,6 +202,7 @@ struct imx_pgc_domain { } bits; const int voltage; + const bool keep_clocks; struct device *dev; }; @@ -295,7 +296,8 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd) } /* Disable reset clocks for all devices in the domain */ - clk_bulk_disable_unprepare(domain->num_clks, domain->clks); + if (!domain->keep_clocks) + clk_bulk_disable_unprepare(domain->num_clks, domain->clks); return 0; @@ -317,10 +319,12 @@ static int imx_pgc_power_down(struct generic_pm_domain *genpd) int ret; /* Enable reset clocks for all devices in the domain */ - ret = clk_bulk_prepare_enable(domain->num_clks, domain->clks); - if (ret) { - dev_err(domain->dev, "failed to enable reset clocks\n"); - return ret; + if (!domain->keep_clocks) { + ret = clk_bulk_prepare_enable(domain->num_clks, domain->clks); + if (ret) { + dev_err(domain->dev, "failed to enable reset clocks\n"); + return ret; + } } /* request the ADB400 to power down */ From patchwork Sat Oct 2 00:59:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Stach X-Patchwork-Id: 12531843 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 20698C433FE for ; Sat, 2 Oct 2021 01:03:20 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DD3FF61A81 for ; Sat, 2 Oct 2021 01:03:19 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org DD3FF61A81 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=kCHAoJmm+vweCD++IpbJuuwRF6Qui0nttFk51xXAuAI=; b=zXPDr1tBSm/3KH e9BenENqdYrZlOAv8G+YGMr6uoA1yvhqC323boAddy6z9SI8o1nqgPIhsriUnKUNLjzPX/rU2VQ5K d3fGaVpNVbmt0uCKoM70K4QBfD4i5xkKaTBA5XoOI8zpg9slAFH3IvRhcu8gUHi72GemZxWP6wvAZ U6DcPb454P46iuQ/cSoYQcWEMGvWpC1Al1V78W1n094wXD9mVVz+j2eX92MJahXjTzzJr6nakHtvY BBhbtUKb4LbR6G/VuCgJC689TSmc/i987C2Q/O7fNW6Q3st6WS+9Akik9lK6/IsQPyHtAmRTSTDZ1 0MdIiKgK8D9W4qsFhb+A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mWTOo-001aSo-UA; Sat, 02 Oct 2021 01:01:11 +0000 Received: from metis.ext.pengutronix.de ([2001:67c:670:201:290:27ff:fe1d:cc33]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mWTNo-001aA5-AG for linux-arm-kernel@lists.infradead.org; Sat, 02 Oct 2021 01:00:09 +0000 Received: from dude03.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::39]) by metis.ext.pengutronix.de with esmtp (Exim 4.92) (envelope-from ) id 1mWTNh-0005o6-Ss; Sat, 02 Oct 2021 03:00:01 +0200 From: Lucas Stach To: Shawn Guo Cc: Rob Herring , Fabio Estevam , NXP Linux Team , Adam Ford , Frieder Schrempf , Marek Vasut , Tim Harvey , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@pengutronix.de, patchwork-lst@pengutronix.de Subject: [PATCH v5 06/18] soc: imx: gpcv2: keep i.MX8M* bus clocks enabled Date: Sat, 2 Oct 2021 02:59:42 +0200 Message-Id: <20211002005954.1367653-7-l.stach@pengutronix.de> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211002005954.1367653-1-l.stach@pengutronix.de> References: <20211002005954.1367653-1-l.stach@pengutronix.de> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2a0a:edc0:0:1101:1d::39 X-SA-Exim-Mail-From: l.stach@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211001_180008_383873_615F56D2 X-CRM114-Status: GOOD ( 10.10 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Annotate the domains with bus clocks to keep those clocks enabled as long as the domain is active. Signed-off-by: Lucas Stach Reviewed-by: Peng Fan --- drivers/soc/imx/gpcv2.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index c3b1d2580963..adf297c2d2af 100644 --- a/drivers/soc/imx/gpcv2.c +++ b/drivers/soc/imx/gpcv2.c @@ -527,6 +527,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = { .hskack = IMX8M_VPU_HSK_PWRDNACKN, }, .pgc = BIT(IMX8M_PGC_VPU), + .keep_clocks = true, }, [IMX8M_POWER_DOMAIN_DISP] = { @@ -625,6 +626,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { .hskreq = IMX8MM_HSIO_HSK_PWRDNREQN, .hskack = IMX8MM_HSIO_HSK_PWRDNACKN, }, + .keep_clocks = true, }, [IMX8MM_POWER_DOMAIN_PCIE] = { @@ -671,6 +673,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { .hskack = IMX8MM_GPUMIX_HSK_PWRDNACKN, }, .pgc = BIT(IMX8MM_PGC_GPUMIX), + .keep_clocks = true, }, [IMX8MM_POWER_DOMAIN_GPU] = { @@ -697,6 +700,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { .hskack = IMX8MM_VPUMIX_HSK_PWRDNACKN, }, .pgc = BIT(IMX8MM_PGC_VPUMIX), + .keep_clocks = true, }, [IMX8MM_POWER_DOMAIN_VPUG1] = { @@ -743,6 +747,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { .hskack = IMX8MM_DISPMIX_HSK_PWRDNACKN, }, .pgc = BIT(IMX8MM_PGC_DISPMIX), + .keep_clocks = true, }, [IMX8MM_POWER_DOMAIN_MIPI] = { @@ -810,6 +815,7 @@ static const struct imx_pgc_domain imx8mn_pgc_domains[] = { .hskreq = IMX8MN_HSIO_HSK_PWRDNREQN, .hskack = IMX8MN_HSIO_HSK_PWRDNACKN, }, + .keep_clocks = true, }, [IMX8MN_POWER_DOMAIN_OTG1] = { From patchwork Sat Oct 2 00:59:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Stach X-Patchwork-Id: 12531847 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 131C3C433F5 for ; Sat, 2 Oct 2021 01:03:35 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C062A61A81 for ; Sat, 2 Oct 2021 01:03:34 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org C062A61A81 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; 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Sat, 02 Oct 2021 01:00:10 +0000 Received: from dude03.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::39]) by metis.ext.pengutronix.de with esmtp (Exim 4.92) (envelope-from ) id 1mWTNi-0005o6-Ku; Sat, 02 Oct 2021 03:00:02 +0200 From: Lucas Stach To: Shawn Guo Cc: Rob Herring , Fabio Estevam , NXP Linux Team , Adam Ford , Frieder Schrempf , Marek Vasut , Tim Harvey , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@pengutronix.de, patchwork-lst@pengutronix.de Subject: [PATCH v5 07/18] soc: imx: gpcv2: support system suspend/resume Date: Sat, 2 Oct 2021 02:59:43 +0200 Message-Id: <20211002005954.1367653-8-l.stach@pengutronix.de> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211002005954.1367653-1-l.stach@pengutronix.de> References: <20211002005954.1367653-1-l.stach@pengutronix.de> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2a0a:edc0:0:1101:1d::39 X-SA-Exim-Mail-From: l.stach@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211001_180008_944689_A47FF689 X-CRM114-Status: GOOD ( 18.49 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Our usage of runtime PM to control the hierarchy of power domains is slightly unusual and means that powering up a domain may fail in early system resume, as runtime PM is still disallowed at this stage. However the system suspend/resume path takes care of powering down/up the power domains in the order defined by the device parent/child and power-domain provider/consumer hierarachy. So we can just runtime resume all our power-domain devices to allow the power-up to work properly in the resume path. System suspend will still disable all domains as intended. Signed-off-by: Lucas Stach Acked-by: Peng Fan --- drivers/soc/imx/gpcv2.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index adf297c2d2af..811e9d29a079 100644 --- a/drivers/soc/imx/gpcv2.c +++ b/drivers/soc/imx/gpcv2.c @@ -948,6 +948,36 @@ static int imx_pgc_domain_remove(struct platform_device *pdev) return 0; } +#ifdef CONFIG_PM_SLEEP +static int imx_pgc_domain_suspend(struct device *dev) +{ + int ret; + + /* + * This may look strange, but is done so the generic PM_SLEEP code + * can power down our domain and more importantly power it up again + * after resume, without tripping over our usage of runtime PM to + * power up/down the nested domains. + */ + ret = pm_runtime_get_sync(dev); + if (ret < 0) { + pm_runtime_put_noidle(dev); + return ret; + } + + return 0; +} + +static int imx_pgc_domain_resume(struct device *dev) +{ + return pm_runtime_put(dev); +} +#endif + +static const struct dev_pm_ops imx_pgc_domain_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(imx_pgc_domain_suspend, imx_pgc_domain_resume) +}; + static const struct platform_device_id imx_pgc_domain_id[] = { { "imx-pgc-domain", }, { }, @@ -956,6 +986,7 @@ static const struct platform_device_id imx_pgc_domain_id[] = { static struct platform_driver imx_pgc_domain_driver = { .driver = { .name = "imx-pgc", + .pm = &imx_pgc_domain_pm_ops, }, .probe = imx_pgc_domain_probe, .remove = imx_pgc_domain_remove, From patchwork Sat Oct 2 00:59:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Stach X-Patchwork-Id: 12531851 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1EE96C433F5 for ; Sat, 2 Oct 2021 01:04:04 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E434561A81 for ; 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Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mWTPb-001ata-LE; Sat, 02 Oct 2021 01:01:59 +0000 Received: from metis.ext.pengutronix.de ([2001:67c:670:201:290:27ff:fe1d:cc33]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mWTNp-001aB7-HG for linux-arm-kernel@lists.infradead.org; Sat, 02 Oct 2021 01:00:11 +0000 Received: from dude03.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::39]) by metis.ext.pengutronix.de with esmtp (Exim 4.92) (envelope-from ) id 1mWTNj-0005o6-Cw; Sat, 02 Oct 2021 03:00:03 +0200 From: Lucas Stach To: Shawn Guo Cc: Rob Herring , Fabio Estevam , NXP Linux Team , Adam Ford , Frieder Schrempf , Marek Vasut , Tim Harvey , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@pengutronix.de, patchwork-lst@pengutronix.de Subject: [PATCH v5 08/18] dt-bindings: soc: add binding for i.MX8MM VPU blk-ctrl Date: Sat, 2 Oct 2021 02:59:44 +0200 Message-Id: <20211002005954.1367653-9-l.stach@pengutronix.de> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211002005954.1367653-1-l.stach@pengutronix.de> References: <20211002005954.1367653-1-l.stach@pengutronix.de> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2a0a:edc0:0:1101:1d::39 X-SA-Exim-Mail-From: l.stach@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211001_180009_609683_A46CBFB6 X-CRM114-Status: GOOD ( 13.42 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This adds the DT binding for the i.MX8MM VPU blk-ctrl. Signed-off-by: Lucas Stach Reviewed-by: Rob Herring --- .../soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml | 76 +++++++++++++++++++ 1 file changed, 76 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml new file mode 100644 index 000000000000..26487daa64d9 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8MM VPU blk-ctrl + +maintainers: + - Lucas Stach + +description: + The i.MX8MM VPU blk-ctrl is a top-level peripheral providing access to + the NoC and ensuring proper power sequencing of the VPU peripherals + located in the VPU domain of the SoC. + +properties: + compatible: + items: + - const: fsl,imx8mm-vpu-blk-ctrl + - const: syscon + + reg: + maxItems: 1 + + '#power-domain-cells': + const: 1 + + power-domains: + minItems: 4 + maxItems: 4 + + power-domain-names: + items: + - const: bus + - const: g1 + - const: g2 + - const: h1 + + clocks: + minItems: 3 + maxItems: 3 + + clock-names: + items: + - const: g1 + - const: g2 + - const: h1 + +required: + - compatible + - reg + - power-domains + - power-domain-names + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + + vpu_blk_ctrl: blk-ctrl@38330000 { + compatible = "fsl,imx8mm-vpu-blk-ctrl", "syscon"; + reg = <0x38330000 0x100>; + power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>, + <&pgc_vpu_g2>, <&pgc_vpu_h1>; + power-domain-names = "bus", "g1", "g2", "h1"; + clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>, + <&clk IMX8MM_CLK_VPU_G2_ROOT>, + <&clk IMX8MM_CLK_VPU_H1_ROOT>; + clock-names = "g1", "g2", "h1"; + #power-domain-cells = <1>; + }; From patchwork Sat Oct 2 00:59:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Stach X-Patchwork-Id: 12531849 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6D4DCC433EF for ; Sat, 2 Oct 2021 01:04:02 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3343161AEE for ; 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Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mWTPN-001alI-0O; Sat, 02 Oct 2021 01:01:45 +0000 Received: from metis.ext.pengutronix.de ([2001:67c:670:201:290:27ff:fe1d:cc33]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mWTNp-001aB9-In for linux-arm-kernel@lists.infradead.org; Sat, 02 Oct 2021 01:00:10 +0000 Received: from dude03.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::39]) by metis.ext.pengutronix.de with esmtp (Exim 4.92) (envelope-from ) id 1mWTNk-0005o6-4a; Sat, 02 Oct 2021 03:00:04 +0200 From: Lucas Stach To: Shawn Guo Cc: Rob Herring , Fabio Estevam , NXP Linux Team , Adam Ford , Frieder Schrempf , Marek Vasut , Tim Harvey , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@pengutronix.de, patchwork-lst@pengutronix.de Subject: [PATCH v5 09/18] dt-bindings: power: imx8mm: add defines for VPU blk-ctrl domains Date: Sat, 2 Oct 2021 02:59:45 +0200 Message-Id: <20211002005954.1367653-10-l.stach@pengutronix.de> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211002005954.1367653-1-l.stach@pengutronix.de> References: <20211002005954.1367653-1-l.stach@pengutronix.de> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2a0a:edc0:0:1101:1d::39 X-SA-Exim-Mail-From: l.stach@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211001_180009_652868_63C3CF00 X-CRM114-Status: UNSURE ( 9.74 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This adds the defines for the power domains provided by the VPU blk-ctrl. Signed-off-by: Lucas Stach Acked-by: Rob Herring --- include/dt-bindings/power/imx8mm-power.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/dt-bindings/power/imx8mm-power.h b/include/dt-bindings/power/imx8mm-power.h index fc9c2e16aadc..38b0a56fd7d0 100644 --- a/include/dt-bindings/power/imx8mm-power.h +++ b/include/dt-bindings/power/imx8mm-power.h @@ -19,4 +19,8 @@ #define IMX8MM_POWER_DOMAIN_DISPMIX 10 #define IMX8MM_POWER_DOMAIN_MIPI 11 +#define IMX8MM_VPUBLK_PD_G1 0 +#define IMX8MM_VPUBLK_PD_G2 1 +#define IMX8MM_VPUBLK_PD_H1 2 + #endif From patchwork Sat Oct 2 00:59:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Stach X-Patchwork-Id: 12531855 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 743E4C433EF for ; Sat, 2 Oct 2021 01:05:19 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3F10A61AEE for ; Sat, 2 Oct 2021 01:05:19 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 3F10A61AEE Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=cWsKp0jNT0Ho4xSg9CLxga+x4Fbu4MSE2APfzcfdqv0=; b=43Uingvzhwg9RI cTslH0tiCSTiB8WBPJ6D80ZeuC16lQRYjwb8okVFGp6Y4O5L8pApEyZhbDah3mN+EDHZGHwKrcLde FdHOAWu0ZMV9DHevcVbldhW6tNkZUS8lbWODMQhx5qOyBBapCAr9OAmvIPO422uJQcbrNxMf+byKT O1gZMRrwMs5X/MJN31Hd/UINMIArRCHPdkA/LEgNV4bQfc6UZ3tzj/sGYefCR0pyTPUeVW24tXBz3 wab2EV+Tan+MZftmWZ3zp+2Y884hRxM46DOJ4H26f0VP87KpJntuTpV6p0+taxippHKJzw7Chdu1y /xtqXEnotRd+M4uCQuyw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mWTQk-001bc3-Eg; Sat, 02 Oct 2021 01:03:10 +0000 Received: from metis.ext.pengutronix.de ([2001:67c:670:201:290:27ff:fe1d:cc33]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mWTNr-001aCY-O8 for linux-arm-kernel@lists.infradead.org; Sat, 02 Oct 2021 01:00:14 +0000 Received: from dude03.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::39]) by metis.ext.pengutronix.de with esmtp (Exim 4.92) (envelope-from ) id 1mWTNk-0005o6-SG; Sat, 02 Oct 2021 03:00:04 +0200 From: Lucas Stach To: Shawn Guo Cc: Rob Herring , Fabio Estevam , NXP Linux Team , Adam Ford , Frieder Schrempf , Marek Vasut , Tim Harvey , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@pengutronix.de, patchwork-lst@pengutronix.de Subject: [PATCH v5 10/18] soc: imx: add i.MX8M blk-ctrl driver Date: Sat, 2 Oct 2021 02:59:46 +0200 Message-Id: <20211002005954.1367653-11-l.stach@pengutronix.de> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211002005954.1367653-1-l.stach@pengutronix.de> References: <20211002005954.1367653-1-l.stach@pengutronix.de> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2a0a:edc0:0:1101:1d::39 X-SA-Exim-Mail-From: l.stach@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211001_180012_146883_DF16221A X-CRM114-Status: GOOD ( 35.58 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This adds a driver for the blk-ctrl blocks found in the i.MX8M* line of SoCs. The blk-ctrl is a top-level peripheral located in the various *MIX power domains and interacts with the GPC power controller to provide the peripherals in the power domain access to the NoC and ensures that those peripherals are properly reset when their respective power domain is brought back to life. Software needs to do different things to make the bus handshake happen after the GPC *MIX domain is powered up and before it is powered down. As the requirements are quite different between the various blk-ctrls there is a callback function provided to hook in the proper sequence. The peripheral domains are quite uniform, they handle the soft clock enables and resets in the blk-ctrl address space and sequencing with the upstream GPC power domains. Signed-off-by: Lucas Stach Acked-by: Frieder Schrempf Reviewed-by: Philipp Zabel --- This commit includes the full code to drive the VPUMIX domain on the i.MX8MM, as the skeleton driver would probably be harder to review without the context provided by one blk-ctrl implementation. Other blk-ctrl implementations will follow, based on this overall structure. v4: - fix commit message typos - fix superfluous whitespace - constify clk_names more v5: - add missing 'm' in the imx8mm_* structure names --- drivers/soc/imx/Makefile | 1 + drivers/soc/imx/imx8m-blk-ctrl.c | 453 +++++++++++++++++++++++++++++++ 2 files changed, 454 insertions(+) create mode 100644 drivers/soc/imx/imx8m-blk-ctrl.c diff --git a/drivers/soc/imx/Makefile b/drivers/soc/imx/Makefile index 078dc918f4f3..8a707077914c 100644 --- a/drivers/soc/imx/Makefile +++ b/drivers/soc/imx/Makefile @@ -5,3 +5,4 @@ endif obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o obj-$(CONFIG_IMX_GPCV2_PM_DOMAINS) += gpcv2.o obj-$(CONFIG_SOC_IMX8M) += soc-imx8m.o +obj-$(CONFIG_SOC_IMX8M) += imx8m-blk-ctrl.o diff --git a/drivers/soc/imx/imx8m-blk-ctrl.c b/drivers/soc/imx/imx8m-blk-ctrl.c new file mode 100644 index 000000000000..f8db0ebd02c3 --- /dev/null +++ b/drivers/soc/imx/imx8m-blk-ctrl.c @@ -0,0 +1,453 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2021 Pengutronix, Lucas Stach + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define BLK_SFT_RSTN 0x0 +#define BLK_CLK_EN 0x4 + +struct imx8m_blk_ctrl_domain; + +struct imx8m_blk_ctrl { + struct device *dev; + struct notifier_block power_nb; + struct device *bus_power_dev; + struct regmap *regmap; + struct imx8m_blk_ctrl_domain *domains; + struct genpd_onecell_data onecell_data; +}; + +struct imx8m_blk_ctrl_domain_data { + const char *name; + const char * const *clk_names; + int num_clks; + const char *gpc_name; + u32 rst_mask; + u32 clk_mask; +}; + +#define DOMAIN_MAX_CLKS 3 + +struct imx8m_blk_ctrl_domain { + struct generic_pm_domain genpd; + const struct imx8m_blk_ctrl_domain_data *data; + struct clk_bulk_data clks[DOMAIN_MAX_CLKS]; + struct device *power_dev; + struct imx8m_blk_ctrl *bc; +}; + +struct imx8m_blk_ctrl_data { + int max_reg; + notifier_fn_t power_notifier_fn; + const struct imx8m_blk_ctrl_domain_data *domains; + int num_domains; +}; + +static inline struct imx8m_blk_ctrl_domain * +to_imx8m_blk_ctrl_domain(struct generic_pm_domain *genpd) +{ + return container_of(genpd, struct imx8m_blk_ctrl_domain, genpd); +} + +static int imx8m_blk_ctrl_power_on(struct generic_pm_domain *genpd) +{ + struct imx8m_blk_ctrl_domain *domain = to_imx8m_blk_ctrl_domain(genpd); + const struct imx8m_blk_ctrl_domain_data *data = domain->data; + struct imx8m_blk_ctrl *bc = domain->bc; + int ret; + + /* make sure bus domain is awake */ + ret = pm_runtime_get_sync(bc->bus_power_dev); + if (ret < 0) { + pm_runtime_put_noidle(bc->bus_power_dev); + dev_err(bc->dev, "failed to power up bus domain\n"); + return ret; + } + + /* put devices into reset */ + regmap_clear_bits(bc->regmap, BLK_SFT_RSTN, data->rst_mask); + + /* enable upstream and blk-ctrl clocks to allow reset to propagate */ + ret = clk_bulk_prepare_enable(data->num_clks, domain->clks); + if (ret) { + dev_err(bc->dev, "failed to enable clocks\n"); + goto bus_put; + } + regmap_set_bits(bc->regmap, BLK_CLK_EN, data->clk_mask); + + /* power up upstream GPC domain */ + ret = pm_runtime_get_sync(domain->power_dev); + if (ret < 0) { + dev_err(bc->dev, "failed to power up peripheral domain\n"); + goto clk_disable; + } + + /* wait for reset to propagate */ + udelay(5); + + /* release reset */ + regmap_set_bits(bc->regmap, BLK_SFT_RSTN, data->rst_mask); + + /* disable upstream clocks */ + clk_bulk_disable_unprepare(data->num_clks, domain->clks); + + return 0; + +clk_disable: + clk_bulk_disable_unprepare(data->num_clks, domain->clks); +bus_put: + pm_runtime_put(bc->bus_power_dev); + + return ret; +} + +static int imx8m_blk_ctrl_power_off(struct generic_pm_domain *genpd) +{ + struct imx8m_blk_ctrl_domain *domain = to_imx8m_blk_ctrl_domain(genpd); + const struct imx8m_blk_ctrl_domain_data *data = domain->data; + struct imx8m_blk_ctrl *bc = domain->bc; + + /* put devices into reset and disable clocks */ + regmap_clear_bits(bc->regmap, BLK_SFT_RSTN, data->rst_mask); + regmap_clear_bits(bc->regmap, BLK_CLK_EN, data->clk_mask); + + /* power down upstream GPC domain */ + pm_runtime_put(domain->power_dev); + + /* allow bus domain to suspend */ + pm_runtime_put(bc->bus_power_dev); + + return 0; +} + +static struct generic_pm_domain * +imx8m_blk_ctrl_xlate(struct of_phandle_args *args, void *data) +{ + struct genpd_onecell_data *onecell_data = data; + unsigned int index = args->args[0]; + + if (args->args_count != 1 || + index > onecell_data->num_domains) + return ERR_PTR(-EINVAL); + + return onecell_data->domains[index]; +} + +static struct lock_class_key blk_ctrl_genpd_lock_class; + +static int imx8m_blk_ctrl_probe(struct platform_device *pdev) +{ + const struct imx8m_blk_ctrl_data *bc_data; + struct device *dev = &pdev->dev; + struct imx8m_blk_ctrl *bc; + void __iomem *base; + int i, ret; + + struct regmap_config regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + }; + + bc = devm_kzalloc(dev, sizeof(*bc), GFP_KERNEL); + if (!bc) + return -ENOMEM; + + bc->dev = dev; + + bc_data = of_device_get_match_data(dev); + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + regmap_config.max_register = bc_data->max_reg; + bc->regmap = devm_regmap_init_mmio(dev, base, ®map_config); + if (IS_ERR(bc->regmap)) + return dev_err_probe(dev, PTR_ERR(bc->regmap), + "failed to init regmap\n"); + + bc->domains = devm_kcalloc(dev, bc_data->num_domains, + sizeof(struct imx8m_blk_ctrl_domain), + GFP_KERNEL); + if (!bc->domains) + return -ENOMEM; + + bc->onecell_data.num_domains = bc_data->num_domains; + bc->onecell_data.xlate = imx8m_blk_ctrl_xlate; + bc->onecell_data.domains = + devm_kcalloc(dev, bc_data->num_domains, + sizeof(struct generic_pm_domain *), GFP_KERNEL); + if (!bc->onecell_data.domains) + return -ENOMEM; + + bc->bus_power_dev = genpd_dev_pm_attach_by_name(dev, "bus"); + if (IS_ERR(bc->bus_power_dev)) + return dev_err_probe(dev, PTR_ERR(bc->bus_power_dev), + "failed to attach power domain\n"); + + for (i = 0; i < bc_data->num_domains; i++) { + const struct imx8m_blk_ctrl_domain_data *data = &bc_data->domains[i]; + struct imx8m_blk_ctrl_domain *domain = &bc->domains[i]; + int j; + + domain->data = data; + + for (j = 0; j < data->num_clks; j++) + domain->clks[j].id = data->clk_names[j]; + + ret = devm_clk_bulk_get(dev, data->num_clks, domain->clks); + if (ret) { + dev_err_probe(dev, ret, "failed to get clock\n"); + goto cleanup_pds; + } + + domain->power_dev = + dev_pm_domain_attach_by_name(dev, data->gpc_name); + if (IS_ERR(domain->power_dev)) { + dev_err_probe(dev, PTR_ERR(domain->power_dev), + "failed to attach power domain\n"); + ret = PTR_ERR(domain->power_dev); + goto cleanup_pds; + } + + domain->genpd.name = data->name; + domain->genpd.power_on = imx8m_blk_ctrl_power_on; + domain->genpd.power_off = imx8m_blk_ctrl_power_off; + domain->bc = bc; + + ret = pm_genpd_init(&domain->genpd, NULL, true); + if (ret) { + dev_err_probe(dev, ret, "failed to init power domain\n"); + dev_pm_domain_detach(domain->power_dev, true); + goto cleanup_pds; + } + + /* + * We use runtime PM to trigger power on/off of the upstream GPC + * domain, as a strict hierarchical parent/child power domain + * setup doesn't allow us to meet the sequencing requirements. + * This means we have nested locking of genpd locks, without the + * nesting being visible at the genpd level, so we need a + * separate lock class to make lockdep aware of the fact that + * this are separate domain locks that can be nested without a + * self-deadlock. + */ + lockdep_set_class(&domain->genpd.mlock, + &blk_ctrl_genpd_lock_class); + + bc->onecell_data.domains[i] = &domain->genpd; + } + + ret = of_genpd_add_provider_onecell(dev->of_node, &bc->onecell_data); + if (ret) { + dev_err_probe(dev, ret, "failed to add power domain provider\n"); + goto cleanup_pds; + } + + bc->power_nb.notifier_call = bc_data->power_notifier_fn; + ret = dev_pm_genpd_add_notifier(bc->bus_power_dev, &bc->power_nb); + if (ret) { + dev_err_probe(dev, ret, "failed to add power notifier\n"); + goto cleanup_provider; + } + + dev_set_drvdata(dev, bc); + + return 0; + +cleanup_provider: + of_genpd_del_provider(dev->of_node); +cleanup_pds: + for (i--; i >= 0; i--) { + pm_genpd_remove(&bc->domains[i].genpd); + dev_pm_domain_detach(bc->domains[i].power_dev, true); + } + + dev_pm_domain_detach(bc->bus_power_dev, true); + + return ret; +} + +static int imx8m_blk_ctrl_remove(struct platform_device *pdev) +{ + struct imx8m_blk_ctrl *bc = dev_get_drvdata(&pdev->dev); + int i; + + of_genpd_del_provider(pdev->dev.of_node); + + for (i = 0; bc->onecell_data.num_domains; i++) { + struct imx8m_blk_ctrl_domain *domain = &bc->domains[i]; + + pm_genpd_remove(&domain->genpd); + dev_pm_domain_detach(domain->power_dev, true); + } + + dev_pm_genpd_remove_notifier(bc->bus_power_dev); + + dev_pm_domain_detach(bc->bus_power_dev, true); + + return 0; +} + +#ifdef CONFIG_PM_SLEEP +static int imx8m_blk_ctrl_suspend(struct device *dev) +{ + struct imx8m_blk_ctrl *bc = dev_get_drvdata(dev); + int ret, i; + + /* + * This may look strange, but is done so the generic PM_SLEEP code + * can power down our domains and more importantly power them up again + * after resume, without tripping over our usage of runtime PM to + * control the upstream GPC domains. Things happen in the right order + * in the system suspend/resume paths due to the device parent/child + * hierarchy. + */ + ret = pm_runtime_get_sync(bc->bus_power_dev); + if (ret < 0) { + pm_runtime_put_noidle(bc->bus_power_dev); + return ret; + } + + for (i = 0; i < bc->onecell_data.num_domains; i++) { + struct imx8m_blk_ctrl_domain *domain = &bc->domains[i]; + + ret = pm_runtime_get_sync(domain->power_dev); + if (ret < 0) { + pm_runtime_put_noidle(domain->power_dev); + goto out_fail; + } + } + + return 0; + +out_fail: + for (i--; i >= 0; i--) + pm_runtime_put(bc->domains[i].power_dev); + + pm_runtime_put(bc->bus_power_dev); + + return ret; +} + +static int imx8m_blk_ctrl_resume(struct device *dev) +{ + struct imx8m_blk_ctrl *bc = dev_get_drvdata(dev); + int i; + + for (i = 0; i < bc->onecell_data.num_domains; i++) + pm_runtime_put(bc->domains[i].power_dev); + + pm_runtime_put(bc->bus_power_dev); + + return 0; +} +#endif + +static const struct dev_pm_ops imx8m_blk_ctrl_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(imx8m_blk_ctrl_suspend, imx8m_blk_ctrl_resume) +}; + +static int imx8mm_vpu_power_notifier(struct notifier_block *nb, + unsigned long action, void *data) +{ + struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl, + power_nb); + + if (action != GENPD_NOTIFY_ON && action != GENPD_NOTIFY_PRE_OFF) + return NOTIFY_OK; + + /* + * The ADB in the VPUMIX domain has no separate reset and clock + * enable bits, but is ungated together with the VPU clocks. To + * allow the handshake with the GPC to progress we put the VPUs + * in reset and ungate the clocks. + */ + regmap_clear_bits(bc->regmap, BLK_SFT_RSTN, BIT(0) | BIT(1) | BIT(2)); + regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(0) | BIT(1) | BIT(2)); + + if (action == GENPD_NOTIFY_ON) { + /* + * On power up we have no software backchannel to the GPC to + * wait for the ADB handshake to happen, so we just delay for a + * bit. On power down the GPC driver waits for the handshake. + */ + udelay(5); + + /* set "fuse" bits to enable the VPUs */ + regmap_set_bits(bc->regmap, 0x8, 0xffffffff); + regmap_set_bits(bc->regmap, 0xc, 0xffffffff); + regmap_set_bits(bc->regmap, 0x10, 0xffffffff); + regmap_set_bits(bc->regmap, 0x14, 0xffffffff); + } + + return NOTIFY_OK; +} + +static const struct imx8m_blk_ctrl_domain_data imx8mm_vpu_blk_ctl_domain_data[] = { + [IMX8MM_VPUBLK_PD_G1] = { + .name = "vpublk-g1", + .clk_names = (const char *[]){ "g1", }, + .num_clks = 1, + .gpc_name = "g1", + .rst_mask = BIT(1), + .clk_mask = BIT(1), + }, + [IMX8MM_VPUBLK_PD_G2] = { + .name = "vpublk-g2", + .clk_names = (const char *[]){ "g2", }, + .num_clks = 1, + .gpc_name = "g2", + .rst_mask = BIT(0), + .clk_mask = BIT(0), + }, + [IMX8MM_VPUBLK_PD_H1] = { + .name = "vpublk-h1", + .clk_names = (const char *[]){ "h1", }, + .num_clks = 1, + .gpc_name = "h1", + .rst_mask = BIT(2), + .clk_mask = BIT(2), + }, +}; + +static const struct imx8m_blk_ctrl_data imx8mm_vpu_blk_ctl_dev_data = { + .max_reg = 0x18, + .power_notifier_fn = imx8mm_vpu_power_notifier, + .domains = imx8mm_vpu_blk_ctl_domain_data, + .num_domains = ARRAY_SIZE(imx8mm_vpu_blk_ctl_domain_data), +}; + +static const struct of_device_id imx8m_blk_ctrl_of_match[] = { + { + .compatible = "fsl,imx8mm-vpu-blk-ctrl", + .data = &imx8mm_vpu_blk_ctl_dev_data + }, { + /* Sentinel */ + } +}; +MODULE_DEVICE_TABLE(of, imx8m_blk_ctrl_of_match); + +static struct platform_driver imx8m_blk_ctrl_driver = { + .probe = imx8m_blk_ctrl_probe, + .remove = imx8m_blk_ctrl_remove, + .driver = { + .name = "imx8m-blk-ctrl", + .pm = &imx8m_blk_ctrl_pm_ops, + .of_match_table = imx8m_blk_ctrl_of_match, + }, +}; +module_platform_driver(imx8m_blk_ctrl_driver); From patchwork Sat Oct 2 00:59:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Stach X-Patchwork-Id: 12531853 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AE62EC433FE for ; Sat, 2 Oct 2021 01:04:34 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7FA1061A81 for ; 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Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mWTPv-001b5H-Mr; Sat, 02 Oct 2021 01:02:20 +0000 Received: from metis.ext.pengutronix.de ([2001:67c:670:201:290:27ff:fe1d:cc33]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mWTNr-001aCX-MS for linux-arm-kernel@lists.infradead.org; Sat, 02 Oct 2021 01:00:13 +0000 Received: from dude03.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::39]) by metis.ext.pengutronix.de with esmtp (Exim 4.92) (envelope-from ) id 1mWTNl-0005o6-Jd; Sat, 02 Oct 2021 03:00:05 +0200 From: Lucas Stach To: Shawn Guo Cc: Rob Herring , Fabio Estevam , NXP Linux Team , Adam Ford , Frieder Schrempf , Marek Vasut , Tim Harvey , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@pengutronix.de, patchwork-lst@pengutronix.de Subject: [PATCH v5 11/18] dt-bindings: soc: add binding for i.MX8MM DISP blk-ctrl Date: Sat, 2 Oct 2021 02:59:47 +0200 Message-Id: <20211002005954.1367653-12-l.stach@pengutronix.de> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211002005954.1367653-1-l.stach@pengutronix.de> References: <20211002005954.1367653-1-l.stach@pengutronix.de> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2a0a:edc0:0:1101:1d::39 X-SA-Exim-Mail-From: l.stach@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211001_180011_779530_6E4EB8A8 X-CRM114-Status: GOOD ( 13.47 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This adds the DT binding for the i.MX8MM VPU blk-ctrl. Signed-off-by: Lucas Stach Reviewed-by: Rob Herring --- .../soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml | 94 +++++++++++++++++++ 1 file changed, 94 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml new file mode 100644 index 000000000000..ecd86cfb3da4 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8MM DISP blk-ctrl + +maintainers: + - Lucas Stach + +description: + The i.MX8MM DISP blk-ctrl is a top-level peripheral providing access to + the NoC and ensuring proper power sequencing of the display and MIPI CSI + peripherals located in the DISP domain of the SoC. + +properties: + compatible: + items: + - const: fsl,imx8mm-disp-blk-ctrl + - const: syscon + + reg: + maxItems: 1 + + '#power-domain-cells': + const: 1 + + power-domains: + minItems: 5 + maxItems: 5 + + power-domain-names: + items: + - const: bus + - const: csi-bridge + - const: lcdif + - const: mipi-dsi + - const: mipi-csi + + clocks: + minItems: 10 + maxItems: 10 + + clock-names: + items: + - const: csi-bridge-axi + - const: csi-bridge-apb + - const: csi-bridge-core + - const: lcdif-axi + - const: lcdif-apb + - const: lcdif-pix + - const: dsi-pclk + - const: dsi-ref + - const: csi-aclk + - const: csi-pclk + +required: + - compatible + - reg + - power-domains + - power-domain-names + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + + disp_blk_ctl: blk_ctrl@32e28000 { + compatible = "fsl,imx8mm-disp-blk-ctrl", "syscon"; + reg = <0x32e28000 0x100>; + power-domains = <&pgc_dispmix>, <&pgc_dispmix>, <&pgc_dispmix>, + <&pgc_mipi>, <&pgc_mipi>; + power-domain-names = "bus", "csi-bridge", "lcdif", + "mipi-dsi", "mipi-csi"; + clocks = <&clk IMX8MM_CLK_DISP_AXI_ROOT>, + <&clk IMX8MM_CLK_DISP_APB_ROOT>, + <&clk IMX8MM_CLK_CSI1_ROOT>, + <&clk IMX8MM_CLK_DISP_AXI_ROOT>, + <&clk IMX8MM_CLK_DISP_APB_ROOT>, + <&clk IMX8MM_CLK_DISP_ROOT>, + <&clk IMX8MM_CLK_DSI_CORE>, + <&clk IMX8MM_CLK_DSI_PHY_REF>, + <&clk IMX8MM_CLK_CSI1_CORE>, + <&clk IMX8MM_CLK_CSI1_PHY_REF>; + clock-names = "csi-bridge-axi", "csi-bridge-apb", "csi-bridge-core", + "lcdif-axi", "lcdif-apb", "lcdif-pix", "dsi-pclk", + "dsi-ref", "csi-aclk", "csi-pclk"; + #power-domain-cells = <1>; + }; From patchwork Sat Oct 2 00:59:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Stach X-Patchwork-Id: 12531857 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EC223C433EF for ; Sat, 2 Oct 2021 01:06:06 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B352461AEE for ; Sat, 2 Oct 2021 01:06:06 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org B352461AEE Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=4qjL53+zxdoHzmTwfEE8rdSOM6gqUmankctFKWCsBPI=; b=5GQR/BATTerel0 HeZXQvifjbePN1LtTHONXuZ0UE4suYZpFgdXc2mtf5uo5wagdzqqQZ3w27o66iiyjV1m3AMq6tYwA DN7XVi27hB4uA7lz1lSUtQyTpEN3Rt9kHg08U5TIFrRbzzJ5pQJsxTNFuNbGEywiwNs/W2ST+FHWN 232OqATNDfHh0SjCBFtqoKJ9ayHCxnZrB9u+2PYuF3Kjc4IKi+nmOpy8ZkH69z2JiUlLyaRvvU+pb a3C5HP5lppNJtGE2SKrgSre4/OfeLvMqWvw5elDrldi3Dz3UER6UsxdqmnGU+I+jnjW9RA3Jksibf O0BQeP6q3emKeunyrEdQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mWTRQ-001c4r-UF; Sat, 02 Oct 2021 01:03:54 +0000 Received: from metis.ext.pengutronix.de ([2001:67c:670:201:290:27ff:fe1d:cc33]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mWTNt-001aDN-76 for linux-arm-kernel@lists.infradead.org; Sat, 02 Oct 2021 01:00:14 +0000 Received: from dude03.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::39]) by metis.ext.pengutronix.de with esmtp (Exim 4.92) (envelope-from ) id 1mWTNm-0005o6-Aq; Sat, 02 Oct 2021 03:00:06 +0200 From: Lucas Stach To: Shawn Guo Cc: Rob Herring , Fabio Estevam , NXP Linux Team , Adam Ford , Frieder Schrempf , Marek Vasut , Tim Harvey , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@pengutronix.de, patchwork-lst@pengutronix.de Subject: [PATCH v5 12/18] dt-bindings: power: imx8mm: add defines for DISP blk-ctrl domains Date: Sat, 2 Oct 2021 02:59:48 +0200 Message-Id: <20211002005954.1367653-13-l.stach@pengutronix.de> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211002005954.1367653-1-l.stach@pengutronix.de> References: <20211002005954.1367653-1-l.stach@pengutronix.de> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2a0a:edc0:0:1101:1d::39 X-SA-Exim-Mail-From: l.stach@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211001_180013_328501_BE74A663 X-CRM114-Status: UNSURE ( 9.63 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This adds the defines for the power domains provided by the DISP blk-ctrl. Signed-off-by: Lucas Stach Acked-by: Rob Herring --- v4: Change naming to be consistent with the VPUBLK domains. --- include/dt-bindings/power/imx8mm-power.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/dt-bindings/power/imx8mm-power.h b/include/dt-bindings/power/imx8mm-power.h index 38b0a56fd7d0..648938f24c8e 100644 --- a/include/dt-bindings/power/imx8mm-power.h +++ b/include/dt-bindings/power/imx8mm-power.h @@ -23,4 +23,9 @@ #define IMX8MM_VPUBLK_PD_G2 1 #define IMX8MM_VPUBLK_PD_H1 2 +#define IMX8MM_DISPBLK_PD_CSI_BRIDGE 0 +#define IMX8MM_DISPBLK_PD_LCDIF 1 +#define IMX8MM_DISPBLK_PD_MIPI_DSI 2 +#define IMX8MM_DISPBLK_PD_MIPI_CSI 3 + #endif From patchwork Sat Oct 2 00:59:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Stach X-Patchwork-Id: 12531859 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 97C06C433EF for ; Sat, 2 Oct 2021 01:06:29 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 63AF961A81 for ; Sat, 2 Oct 2021 01:06:29 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 63AF961A81 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=LVehE9iyklWQBLFWYDaFGhidR7ycez+dirLf9hN+uqw=; b=AgeyA7QXQeDA+t cFy+xUdVxoaVFcZU2aLdP9edkzFs972g/RonDhsUfc/ILhvy3fP/MmF4JvM1qEoa8pX9NYVKp7FJN aBcUf66xdZ7XxQ7khj8VqtgYEUdZ/mjXY/rs7gwtnFapMuaPnsj5qcLOHosBy1x+4swCreCs/GoO0 vc9yttzQWxBks3FAZxHI+eLu4kLSFaQfsjLEGKu8bTY6Ow5hkTFo58uB8T3po9+rd5g/vNsRUTSBb VSjmGMQ/HaeOTngT1c0L5vqaQHN7QrYopBs2edF934CDWeU5tApLw9JNuhzIjEdZe0BXNJs0vat6s dS5s3bVzJkzKNJHAOeqw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mWTRx-001cOl-60; Sat, 02 Oct 2021 01:04:25 +0000 Received: from metis.ext.pengutronix.de ([2001:67c:670:201:290:27ff:fe1d:cc33]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mWTNt-001aDO-8B for linux-arm-kernel@lists.infradead.org; Sat, 02 Oct 2021 01:00:14 +0000 Received: from dude03.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::39]) by metis.ext.pengutronix.de with esmtp (Exim 4.92) (envelope-from ) id 1mWTNn-0005o6-2G; Sat, 02 Oct 2021 03:00:07 +0200 From: Lucas Stach To: Shawn Guo Cc: Rob Herring , Fabio Estevam , NXP Linux Team , Adam Ford , Frieder Schrempf , Marek Vasut , Tim Harvey , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@pengutronix.de, patchwork-lst@pengutronix.de Subject: [PATCH v5 13/18] soc: imx: imx8m-blk-ctrl: add DISP blk-ctrl Date: Sat, 2 Oct 2021 02:59:49 +0200 Message-Id: <20211002005954.1367653-14-l.stach@pengutronix.de> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211002005954.1367653-1-l.stach@pengutronix.de> References: <20211002005954.1367653-1-l.stach@pengutronix.de> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2a0a:edc0:0:1101:1d::39 X-SA-Exim-Mail-From: l.stach@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211001_180013_352874_59776C6D X-CRM114-Status: GOOD ( 16.78 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This adds the description for the i.MX8MM disp blk-ctrl. Signed-off-by: Lucas Stach Reviewed-by: Peng Fan --- v5: add missing 'm' in the imx8mm_* structure names --- drivers/soc/imx/imx8m-blk-ctrl.c | 70 ++++++++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/drivers/soc/imx/imx8m-blk-ctrl.c b/drivers/soc/imx/imx8m-blk-ctrl.c index f8db0ebd02c3..e172d295c441 100644 --- a/drivers/soc/imx/imx8m-blk-ctrl.c +++ b/drivers/soc/imx/imx8m-blk-ctrl.c @@ -431,11 +431,81 @@ static const struct imx8m_blk_ctrl_data imx8mm_vpu_blk_ctl_dev_data = { .num_domains = ARRAY_SIZE(imx8mm_vpu_blk_ctl_domain_data), }; +static int imx8mm_disp_power_notifier(struct notifier_block *nb, + unsigned long action, void *data) +{ + struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl, + power_nb); + + if (action != GENPD_NOTIFY_ON && action != GENPD_NOTIFY_PRE_OFF) + return NOTIFY_OK; + + /* Enable bus clock and deassert bus reset */ + regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(12)); + regmap_set_bits(bc->regmap, BLK_SFT_RSTN, BIT(6)); + + /* + * On power up we have no software backchannel to the GPC to + * wait for the ADB handshake to happen, so we just delay for a + * bit. On power down the GPC driver waits for the handshake. + */ + if (action == GENPD_NOTIFY_ON) + udelay(5); + + + return NOTIFY_OK; +} + +static const struct imx8m_blk_ctrl_domain_data imx8mm_disp_blk_ctl_domain_data[] = { + [IMX8MM_DISPBLK_PD_CSI_BRIDGE] = { + .name = "dispblk-csi-bridge", + .clk_names = (const char *[]){ "csi-bridge-axi", "csi-bridge-apb", + "csi-bridge-core", }, + .num_clks = 3, + .gpc_name = "csi-bridge", + .rst_mask = BIT(0) | BIT(1) | BIT(2), + .clk_mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5), + }, + [IMX8MM_DISPBLK_PD_LCDIF] = { + .name = "dispblk-lcdif", + .clk_names = (const char *[]){ "lcdif-axi", "lcdif-apb", "lcdif-pix", }, + .num_clks = 3, + .gpc_name = "lcdif", + .clk_mask = BIT(6) | BIT(7), + }, + [IMX8MM_DISPBLK_PD_MIPI_DSI] = { + .name = "dispblk-mipi-dsi", + .clk_names = (const char *[]){ "dsi-pclk", "dsi-ref", }, + .num_clks = 2, + .gpc_name = "mipi-dsi", + .rst_mask = BIT(5), + .clk_mask = BIT(8) | BIT(9), + }, + [IMX8MM_DISPBLK_PD_MIPI_CSI] = { + .name = "dispblk-mipi-csi", + .clk_names = (const char *[]){ "csi-aclk", "csi-pclk" }, + .num_clks = 2, + .gpc_name = "mipi-csi", + .rst_mask = BIT(3) | BIT(4), + .clk_mask = BIT(10) | BIT(11), + }, +}; + +static const struct imx8m_blk_ctrl_data imx8mm_disp_blk_ctl_dev_data = { + .max_reg = 0x2c, + .power_notifier_fn = imx8mm_disp_power_notifier, + .domains = imx8mm_disp_blk_ctl_domain_data, + .num_domains = ARRAY_SIZE(imx8mm_disp_blk_ctl_domain_data), +}; + static const struct of_device_id imx8m_blk_ctrl_of_match[] = { { .compatible = "fsl,imx8mm-vpu-blk-ctrl", .data = &imx8mm_vpu_blk_ctl_dev_data }, { + .compatible = "fsl,imx8mm-disp-blk-ctrl", + .data = &imx8mm_disp_blk_ctl_dev_data + } ,{ /* Sentinel */ } }; From patchwork Sat Oct 2 00:59:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Stach X-Patchwork-Id: 12531861 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1E2A9C433F5 for ; Sat, 2 Oct 2021 01:07:15 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E1BD461A81 for ; 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Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mWTSQ-001chf-Ry; Sat, 02 Oct 2021 01:04:55 +0000 Received: from metis.ext.pengutronix.de ([2001:67c:670:201:290:27ff:fe1d:cc33]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mWTNt-001aDX-Rh for linux-arm-kernel@lists.infradead.org; Sat, 02 Oct 2021 01:00:15 +0000 Received: from dude03.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::39]) by metis.ext.pengutronix.de with esmtp (Exim 4.92) (envelope-from ) id 1mWTNn-0005o6-Py; Sat, 02 Oct 2021 03:00:07 +0200 From: Lucas Stach To: Shawn Guo Cc: Rob Herring , Fabio Estevam , NXP Linux Team , Adam Ford , Frieder Schrempf , Marek Vasut , Tim Harvey , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@pengutronix.de, patchwork-lst@pengutronix.de Subject: [PATCH v5 14/18] arm64: dts: imx8mm: add GPC node Date: Sat, 2 Oct 2021 02:59:50 +0200 Message-Id: <20211002005954.1367653-15-l.stach@pengutronix.de> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211002005954.1367653-1-l.stach@pengutronix.de> References: <20211002005954.1367653-1-l.stach@pengutronix.de> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2a0a:edc0:0:1101:1d::39 X-SA-Exim-Mail-From: l.stach@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211001_180013_915233_ACAE6CCB X-CRM114-Status: GOOD ( 11.06 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add the DT node for the GPC, including all the PGC power domains, some of them are not fully functional yet, as they require interaction with the blk-ctrls to properly power up/down the peripherals. Signed-off-by: Lucas Stach --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 107 ++++++++++++++++++++++ 1 file changed, 107 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index 2f632e8ca388..83185b70dd46 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -7,6 +7,8 @@ #include #include #include +#include +#include #include #include "imx8mm-pinfunc.h" @@ -610,6 +612,111 @@ src: reset-controller@30390000 { interrupts = ; #reset-cells = <1>; }; + + gpc: gpc@303a0000 { + compatible = "fsl,imx8mm-gpc"; + reg = <0x303a0000 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + interrupt-controller; + #interrupt-cells = <3>; + + pgc { + #address-cells = <1>; + #size-cells = <0>; + + pgc_hsiomix: power-domain@0 { + #power-domain-cells = <0>; + reg = ; + clocks = <&clk IMX8MM_CLK_USB_BUS>; + assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; + }; + + pgc_pcie: power-domain@1 { + #power-domain-cells = <0>; + reg = ; + power-domains = <&pgc_hsiomix>; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>; + }; + + pgc_otg1: power-domain@2 { + #power-domain-cells = <0>; + reg = ; + power-domains = <&pgc_hsiomix>; + }; + + pgc_otg2: power-domain@3 { + #power-domain-cells = <0>; + reg = ; + power-domains = <&pgc_hsiomix>; + }; + + pgc_gpumix: power-domain@4 { + #power-domain-cells = <0>; + reg = ; + clocks = <&clk IMX8MM_CLK_GPU_BUS_ROOT>, + <&clk IMX8MM_CLK_GPU_AHB>; + assigned-clocks = <&clk IMX8MM_CLK_GPU_AXI>, + <&clk IMX8MM_CLK_GPU_AHB>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>, + <&clk IMX8MM_SYS_PLL1_800M>; + assigned-clock-rates = <800000000>, <400000000>; + }; + + pgc_gpu: power-domain@5 { + #power-domain-cells = <0>; + reg = ; + clocks = <&clk IMX8MM_CLK_GPU_AHB>, + <&clk IMX8MM_CLK_GPU_BUS_ROOT>, + <&clk IMX8MM_CLK_GPU2D_ROOT>, + <&clk IMX8MM_CLK_GPU3D_ROOT>; + resets = <&src IMX8MQ_RESET_GPU_RESET>; + power-domains = <&pgc_gpumix>; + }; + + pgc_vpumix: power-domain@6 { + #power-domain-cells = <0>; + reg = ; + clocks = <&clk IMX8MM_CLK_VPU_DEC_ROOT>; + assigned-clocks = <&clk IMX8MM_CLK_VPU_BUS>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>; + resets = <&src IMX8MQ_RESET_VPU_RESET>; + }; + + pgc_vpu_g1: power-domain@7 { + #power-domain-cells = <0>; + reg = ; + }; + + pgc_vpu_g2: power-domain@8 { + #power-domain-cells = <0>; + reg = ; + }; + + pgc_vpu_h1: power-domain@9 { + #power-domain-cells = <0>; + reg = ; + }; + + pgc_dispmix: power-domain@10 { + #power-domain-cells = <0>; + reg = ; + clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>, + <&clk IMX8MM_CLK_DISP_AXI_ROOT>; + assigned-clocks = <&clk IMX8MM_CLK_DISP_AXI>, + <&clk IMX8MM_CLK_DISP_APB>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>, + <&clk IMX8MM_SYS_PLL1_800M>; + assigned-clock-rates = <500000000>, <200000000>; + }; + + pgc_mipi: power-domain@11 { + #power-domain-cells = <0>; + reg = ; + }; + }; + }; }; aips2: bus@30400000 { From patchwork Sat Oct 2 00:59:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Stach X-Patchwork-Id: 12531863 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EB069C433F5 for ; Sat, 2 Oct 2021 01:07:43 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A824561AEE for ; Sat, 2 Oct 2021 01:07:43 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org A824561AEE Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; 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Sat, 02 Oct 2021 01:00:15 +0000 Received: from dude03.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::39]) by metis.ext.pengutronix.de with esmtp (Exim 4.92) (envelope-from ) id 1mWTNo-0005o6-HW; Sat, 02 Oct 2021 03:00:08 +0200 From: Lucas Stach To: Shawn Guo Cc: Rob Herring , Fabio Estevam , NXP Linux Team , Adam Ford , Frieder Schrempf , Marek Vasut , Tim Harvey , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@pengutronix.de, patchwork-lst@pengutronix.de Subject: [PATCH v5 15/18] arm64: dts: imx8mm: put USB controllers into power-domains Date: Sat, 2 Oct 2021 02:59:51 +0200 Message-Id: <20211002005954.1367653-16-l.stach@pengutronix.de> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211002005954.1367653-1-l.stach@pengutronix.de> References: <20211002005954.1367653-1-l.stach@pengutronix.de> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2a0a:edc0:0:1101:1d::39 X-SA-Exim-Mail-From: l.stach@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211001_180014_252912_98E74638 X-CRM114-Status: GOOD ( 10.67 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Now that we have support for the power domain controller on the i.MX8MM we can put the USB controllers in their respective power domains to allow them to power down the PHY when possible. Signed-off-by: Lucas Stach --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index 83185b70dd46..d8c53ffb5fff 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -1078,6 +1078,7 @@ usbotg1: usb@32e40000 { assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; phys = <&usbphynop1>; fsl,usbmisc = <&usbmisc1 0>; + power-domains = <&pgc_otg1>; status = "disabled"; }; @@ -1097,6 +1098,7 @@ usbotg2: usb@32e50000 { assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; phys = <&usbphynop2>; fsl,usbmisc = <&usbmisc2 0>; + power-domains = <&pgc_otg2>; status = "disabled"; }; From patchwork Sat Oct 2 00:59:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Stach X-Patchwork-Id: 12531865 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 99C4DC433F5 for ; Sat, 2 Oct 2021 01:08:31 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 68A3861AEE for ; Sat, 2 Oct 2021 01:08:31 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 68A3861AEE Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=s937ziMaAYuVSgOI0TQeKXMfUhjHVZdTJZhPiUxN7Q4=; b=T98XTT7mR1Ih+T cV683JxJml6+Zda+qIR0179R2zd2WWvmx57drF9z22GkP+7psKSkSlUixcqVij0zPEVFT8D8iPbOo CngzEy4nvsCihYa1ZsAWUDZIIG2/bRYjAQgcR3XnmMhJ4OwYARlVD/HDXtlufpl0NXUOGv4kxNs3d GIZoMVuxny/OgixOSaLTmizK2zcCmSuyKvh3WMsmT4+Ygw+QaZJTvSu/wdfBDSiqIDHQHpI/EK8qy OXMwgYdbBDskVkz9gZb3RzOYnnnU2Y30UBv2kGbXW9qZe5B+l/ooyvA2R49KvYtsnbdUmsBqPN3qA iEHye8rjwkF5A8A5Zp0g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mWTTp-001dRb-FU; Sat, 02 Oct 2021 01:06:22 +0000 Received: from metis.ext.pengutronix.de ([2001:67c:670:201:290:27ff:fe1d:cc33]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mWTNv-001aEJ-37 for linux-arm-kernel@lists.infradead.org; Sat, 02 Oct 2021 01:00:16 +0000 Received: from dude03.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::39]) by metis.ext.pengutronix.de with esmtp (Exim 4.92) (envelope-from ) id 1mWTNp-0005o6-9g; Sat, 02 Oct 2021 03:00:09 +0200 From: Lucas Stach To: Shawn Guo Cc: Rob Herring , Fabio Estevam , NXP Linux Team , Adam Ford , Frieder Schrempf , Marek Vasut , Tim Harvey , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@pengutronix.de, patchwork-lst@pengutronix.de Subject: [PATCH v5 16/18] arm64: dts: imx8mm: Add GPU nodes for 2D and 3D core Date: Sat, 2 Oct 2021 02:59:52 +0200 Message-Id: <20211002005954.1367653-17-l.stach@pengutronix.de> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211002005954.1367653-1-l.stach@pengutronix.de> References: <20211002005954.1367653-1-l.stach@pengutronix.de> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2a0a:edc0:0:1101:1d::39 X-SA-Exim-Mail-From: l.stach@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211001_180015_163425_0980DA4B X-CRM114-Status: GOOD ( 12.89 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Frieder Schrempf According to the documents, the i.MX8M-Mini features a GC320 and a GCNanoUltra GPU core. Etnaviv detects them as: etnaviv-gpu 38000000.gpu: model: GC600, revision: 4653 etnaviv-gpu 38008000.gpu: model: GC520, revision: 5341 This seems to work fine more or less without any changes to the HWDB, which still might be needed in the future to correct some features, etc. [lst]: Added power domains and switched clock assignments to the new clock defines used for the composite clocks, instead of relying on the backwards compat defines. Signed-off-by: Frieder Schrempf Signed-off-by: Lucas Stach --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 31 +++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index d8c53ffb5fff..6009e54266f0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -1139,6 +1139,37 @@ gpmi: nand-controller@33002000{ status = "disabled"; }; + gpu_3d: gpu@38000000 { + compatible = "vivante,gc"; + reg = <0x38000000 0x8000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_GPU_AHB>, + <&clk IMX8MM_CLK_GPU_BUS_ROOT>, + <&clk IMX8MM_CLK_GPU3D_ROOT>, + <&clk IMX8MM_CLK_GPU3D_ROOT>; + clock-names = "reg", "bus", "core", "shader"; + assigned-clocks = <&clk IMX8MM_CLK_GPU3D_CORE>, + <&clk IMX8MM_GPU_PLL_OUT>; + assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>; + assigned-clock-rates = <0>, <1000000000>; + power-domains = <&pgc_gpu>; + }; + + gpu_2d: gpu@38008000 { + compatible = "vivante,gc"; + reg = <0x38008000 0x8000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_GPU_AHB>, + <&clk IMX8MM_CLK_GPU_BUS_ROOT>, + <&clk IMX8MM_CLK_GPU2D_ROOT>; + clock-names = "reg", "bus", "core"; + assigned-clocks = <&clk IMX8MM_CLK_GPU2D_CORE>, + <&clk IMX8MM_GPU_PLL_OUT>; + assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>; + assigned-clock-rates = <0>, <1000000000>; + power-domains = <&pgc_gpu>; + }; + gic: interrupt-controller@38800000 { compatible = "arm,gic-v3"; reg = <0x38800000 0x10000>, /* GIC Dist */ From patchwork Sat Oct 2 00:59:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Stach X-Patchwork-Id: 12531875 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3FDDAC433F5 for ; Sat, 2 Oct 2021 01:10:14 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C248A6108E for ; Sat, 2 Oct 2021 01:10:13 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org C248A6108E Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=nxvj7RmXsiRM7nJKO/OF2LPa6Azht0ev79SKD9gHRSE=; b=37GJ87mMNCiQok 0CVq0NRqYZg5l7QfFsBJmVAXN7IIv0AMqkEt1BgRBdyfA9V5+lqpIlJfJPvhz3koX8lcpiNtIuKpI GORRfdsuHuMLjk4ioQbHs0gfVyGE+mJPP6rjeYe96RqBO4COUZDkpyZkkK5EdZheI3BnCvLO+l72j bTMvMYrAu6DAxVHu+SsfNN5m6dtvUdXxOD7R5lhfTOFuXXPVzT5lWOTjS3PBF7rwKkr5YDneVXEWK 4rz4g6XyQX5eQxpw3SR1B0qfWw5OJ1/8B41PLbj5i37Tps26RlJnx/1k8cdox9llM7s03P1Aewgue oGJLpup7sC/SobM8IwVw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mWTUw-001dzR-GY; Sat, 02 Oct 2021 01:07:31 +0000 Received: from metis.ext.pengutronix.de ([2001:67c:670:201:290:27ff:fe1d:cc33]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mWTNv-001aEj-Qi for linux-arm-kernel@lists.infradead.org; Sat, 02 Oct 2021 01:00:17 +0000 Received: from dude03.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::39]) by metis.ext.pengutronix.de with esmtp (Exim 4.92) (envelope-from ) id 1mWTNq-0005o6-1J; Sat, 02 Oct 2021 03:00:10 +0200 From: Lucas Stach To: Shawn Guo Cc: Rob Herring , Fabio Estevam , NXP Linux Team , Adam Ford , Frieder Schrempf , Marek Vasut , Tim Harvey , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@pengutronix.de, patchwork-lst@pengutronix.de Subject: [PATCH v5 17/18] arm64: dts: imx8mm: add VPU blk-ctrl Date: Sat, 2 Oct 2021 02:59:53 +0200 Message-Id: <20211002005954.1367653-18-l.stach@pengutronix.de> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211002005954.1367653-1-l.stach@pengutronix.de> References: <20211002005954.1367653-1-l.stach@pengutronix.de> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2a0a:edc0:0:1101:1d::39 X-SA-Exim-Mail-From: l.stach@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211001_180015_903282_6BB5A63B X-CRM114-Status: GOOD ( 10.18 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add the DT node for the VPU blk-ctrl. With this in place the VPU power domains are fully functional. Signed-off-by: Lucas Stach --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index 6009e54266f0..f4a97bd8b7ad 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -1170,6 +1170,19 @@ gpu_2d: gpu@38008000 { power-domains = <&pgc_gpu>; }; + vpu_blk_ctrl: blk-ctrl@38330000 { + compatible = "fsl,imx8mm-vpu-blk-ctrl", "syscon"; + reg = <0x38330000 0x100>; + power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>, + <&pgc_vpu_g2>, <&pgc_vpu_h1>; + power-domain-names = "bus", "g1", "g2", "h1"; + clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>, + <&clk IMX8MM_CLK_VPU_G2_ROOT>, + <&clk IMX8MM_CLK_VPU_H1_ROOT>; + clock-names = "g1", "g2", "h1"; + #power-domain-cells = <1>; + }; + gic: interrupt-controller@38800000 { compatible = "arm,gic-v3"; reg = <0x38800000 0x10000>, /* GIC Dist */ From patchwork Sat Oct 2 00:59:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Stach X-Patchwork-Id: 12531877 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B30ABC433EF for ; Sat, 2 Oct 2021 01:10:54 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 803A361AF0 for ; Sat, 2 Oct 2021 01:10:54 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 803A361AF0 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=HDrGBB/pGg3hIjB57P8IPiEgLgJdgjnArtJVXtgJ3+M=; b=F6wl5QsC3ZfWO3 SQj4RtB6Dwr0YSbU2RbjW2bomcJeQiKddPN8S7XZaBG9N0GYElPbvipsFk/SRnJyL6zOhBGSeJSWy bfr4+Fc9a6Z5FilQW+8X25Zh4GFPt+VBWkJQ3yu67wzh9poijXQOl4FxMGdGCqC3yxjokeKL2sL8A jVXNCU2IrH2D9VnhKxvwHUcEzg1OGpFGaNz/4zAh2NZWXJrvvu/isMAWF4vZsaV+/TE9wX8y7vxrJ oUwB/WIqodVBn4xEcsRVOaz1zjdvm7cmpFzgoCjHqriHL50P/FatDp7BS6EwYFJ3mMQeFi4mVAcpz x+e25l60eqWpw2vIGdjg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mWTVv-001eRE-5a; Sat, 02 Oct 2021 01:08:31 +0000 Received: from metis.ext.pengutronix.de ([2001:67c:670:201:290:27ff:fe1d:cc33]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mWTNx-001aFX-3D for linux-arm-kernel@lists.infradead.org; Sat, 02 Oct 2021 01:00:18 +0000 Received: from dude03.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::39]) by metis.ext.pengutronix.de with esmtp (Exim 4.92) (envelope-from ) id 1mWTNq-0005o6-Pl; Sat, 02 Oct 2021 03:00:10 +0200 From: Lucas Stach To: Shawn Guo Cc: Rob Herring , Fabio Estevam , NXP Linux Team , Adam Ford , Frieder Schrempf , Marek Vasut , Tim Harvey , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@pengutronix.de, patchwork-lst@pengutronix.de Subject: [PATCH v5 18/18] arm64: dts: imx8mm: add DISP blk-ctrl Date: Sat, 2 Oct 2021 02:59:54 +0200 Message-Id: <20211002005954.1367653-19-l.stach@pengutronix.de> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211002005954.1367653-1-l.stach@pengutronix.de> References: <20211002005954.1367653-1-l.stach@pengutronix.de> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2a0a:edc0:0:1101:1d::39 X-SA-Exim-Mail-From: l.stach@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211001_180017_162315_491032A7 X-CRM114-Status: UNSURE ( 9.80 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add the DT node for the DISP blk-ctrl. With this in place the display/mipi power domains are fully functional. Signed-off-by: Lucas Stach --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 27 +++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index f4a97bd8b7ad..c2f3f118f82e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -1068,6 +1068,33 @@ aips4: bus@32c00000 { #size-cells = <1>; ranges = <0x32c00000 0x32c00000 0x400000>; + disp_blk_ctrl: blk-ctrl@32e28000 { + compatible = "fsl,imx8mm-disp-blk-ctrl", "syscon"; + reg = <0x32e28000 0x100>; + power-domains = <&pgc_dispmix>, <&pgc_dispmix>, + <&pgc_dispmix>, <&pgc_mipi>, + <&pgc_mipi>; + power-domain-names = "bus", "csi-bridge", + "lcdif", "mipi-dsi", + "mipi-csi"; + clocks = <&clk IMX8MM_CLK_DISP_AXI_ROOT>, + <&clk IMX8MM_CLK_DISP_APB_ROOT>, + <&clk IMX8MM_CLK_CSI1_ROOT>, + <&clk IMX8MM_CLK_DISP_AXI_ROOT>, + <&clk IMX8MM_CLK_DISP_APB_ROOT>, + <&clk IMX8MM_CLK_DISP_ROOT>, + <&clk IMX8MM_CLK_DSI_CORE>, + <&clk IMX8MM_CLK_DSI_PHY_REF>, + <&clk IMX8MM_CLK_CSI1_CORE>, + <&clk IMX8MM_CLK_CSI1_PHY_REF>; + clock-names = "csi-bridge-axi","csi-bridge-apb", + "csi-bridge-core", "lcdif-axi", + "lcdif-apb", "lcdif-pix", + "dsi-pclk", "dsi-ref", + "csi-aclk", "csi-pclk"; + #power-domain-cells = <1>; + }; + usbotg1: usb@32e40000 { compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; reg = <0x32e40000 0x200>;