From patchwork Mon Oct 4 20:19:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephan Gerhold X-Patchwork-Id: 12534755 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 45678C433F5 for ; Mon, 4 Oct 2021 20:24:22 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 05FD6613D2 for ; Mon, 4 Oct 2021 20:24:22 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 05FD6613D2 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gerhold.net Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=jsv9igunRnOyzdrQxl4Q8ptN8AdL23M6ULsq9rRr5eg=; b=vevPlIyM9vzAAa 2SUZ8AJW8gsXR8M35JLC+ardRIfI4C8Gn3PcH4pVxegTl7m4jZLeFhTkS8Ls6oQeU4mbR3M87yHgY 1oo4lNyYzgLxpMjgO0pawNNZmuehUFGkJFCgy5rUy4xJZJOn/VPDrQQ5Xz+mqDnzSiMrzz06kiZFB XA+UgPKv+og6t7sbP1bIUWwceOsDF6l9umHYx57ZAVb8rOeQzmn3R8tliQtgVr2MEsjAAwWK+8uNp 25rrFQh7wXH0eWtcHTz8X7LiAz5V6kkgXbcqtIpqwMiaW13SMgxTfMLkUL1nbvBdtRTAY8PKO284N jfmk7etb6cj6uhmvAJAA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mXUTS-007xfF-Ph; Mon, 04 Oct 2021 20:22:10 +0000 Received: from mo4-p01-ob.smtp.rzone.de ([81.169.146.164]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mXUTE-007xbQ-HQ for linux-arm-kernel@lists.infradead.org; Mon, 04 Oct 2021 20:21:58 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1633378910; s=strato-dkim-0002; d=gerhold.net; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Cc:Date: From:Subject:Sender; bh=888nFMWcvrfj90T6Q6xm9ej51dNHQS2mIKNKGw+gxLM=; b=nu5KzGk1Zc7OCdX8RuY5rsxuOW80be4c6Z8Fx5MAlge1c+cvNjLqfIqFOwU2VyaCEq iWG9qcVCG468YnEmnPN1Z43m79BkDpAZkMV7hnTPTC7OaBmoEIB+dKGI+Xfj3hAUByPw Z6nepeXg5N2TO66hU3bTI9ZxMmsx0ezlLJBRJvTZf0LsFR+yG6PgRUOfCtikNmEu65vA gMVT0XHpbplO2x9Pq+8dm+MBdmwBlccesz5d9RXL7nc2nA0b2wvpn3CjvVJSv12nIIBp 3+9DPXgMtRhtA/d0ZVSmYCLij8GuKvboa+sHDjzUifjgce9k7cRX+eBdjC4jZQhgqFc5 4gNA== Authentication-Results: strato.com; dkim=none X-RZG-AUTH: ":P3gBZUipdd93FF5ZZvYFPugejmSTVR2nRPhVORvLd4SsytBXTbAOHjRHIhr2eFePxBA=" X-RZG-CLASS-ID: mo00 Received: from droid.. by smtp.strato.de (RZmta 47.33.8 DYNA|AUTH) with ESMTPSA id 301038x94KLoKQl (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256 bits)) (Client did not present a certificate); Mon, 4 Oct 2021 22:21:50 +0200 (CEST) From: Stephan Gerhold To: Bjorn Andersson Cc: Andy Gross , linux-arm-msm@vger.kernel.org, Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, Stephan Gerhold Subject: [PATCH v2 01/15] arm64: dts: qcom: Add device tree for Samsung Galaxy S4 Mini Value Edition Date: Mon, 4 Oct 2021 22:19:07 +0200 Message-Id: <20211004201921.18526-2-stephan@gerhold.net> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211004201921.18526-1-stephan@gerhold.net> References: <20211004201921.18526-1-stephan@gerhold.net> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211004_132156_920868_1D554488 X-CRM114-Status: GOOD ( 25.86 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The Samsung Galaxy S4 Mini Value Edition is an updated version of the original S4 Mini based on MSM8916. It is similar to the other Samsung devices based on MSM8916 with only a few minor differences. The device tree contains initial support for the S4 Mini Value Edition with: - UART - eMMC/SD card (needs quirk for some reason) - Buttons - Vibrator - WiFi/Bluetooth (WCNSS) - USB Unfortunately, the S4 Mini VE was released with outdated 32-bit only firmware and never received any update from Samsung. Since the 32-bit TrustZone firmware is signed there seems to be no way currently to actually boot this device tree on arm64 Linux at the moment. :( However, it is possible to use this device tree by compiling an ARM32 kernel instead. The device tree can be easily built on ARM32 with an #include and it works really well there. To avoid confusion for others it is still better to add this device tree on arm64. Otherwise it's easy to forget to update this one when making some changes that affect all MSM8916 devices. Maybe someone finds a way to boot ARM64 Linux on this device at some point. In this case I expect that this device tree can be simply used as-is. Signed-off-by: Stephan Gerhold --- Changes in v2: - Add missing word in "FIXME: Disable UHS-I modes" comment --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../dts/qcom/msm8916-samsung-serranove.dts | 301 ++++++++++++++++++ 2 files changed, 302 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 8398c0a2150f..6c6efa192a6e 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -15,6 +15,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8910.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a3u-eur.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a5u-eur.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-serranove.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-wingtech-wt88047.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8992-bullhead-rev-101.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8992-msft-lumia-octagon-talkman.dtb diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts new file mode 100644 index 000000000000..013f843aff9c --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts @@ -0,0 +1,301 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright (C) 2019 Stephan Gerhold + +/dts-v1/; + +#include "msm8916-pm8916.dtsi" +#include +#include +#include + +/* + * NOTE: The original firmware from Samsung can only boot ARM32 kernels. + * Unfortunately, the firmware is signed and cannot be replaced easily. + * There seems to be no way to boot ARM64 kernels on this device at the moment, + * even though the hardware would support it. + * + * However, it is possible to use this device tree by compiling an ARM32 kernel + * instead. For clarity and build testing this device tree is maintained next + * to the other MSM8916 device trees. However, it is actually used through + * arch/arm/boot/dts/qcom-msm8916-samsung-serranove.dts + */ + +/ { + model = "Samsung Galaxy S4 Mini Value Edition"; + compatible = "samsung,serranove", "qcom,msm8916"; + + aliases { + serial0 = &blsp1_uart2; + }; + + chosen { + stdout-path = "serial0"; + }; + + reserved-memory { + /* Additional memory used by Samsung firmware modifications */ + tz-apps@85500000 { + reg = <0x0 0x85500000 0x0 0xb00000>; + no-map; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_default>; + + label = "GPIO Buttons"; + + volume-up { + label = "Volume Up"; + gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + home { + label = "Home"; + gpios = <&msmgpio 109 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + gpio-hall-sensor { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_hall_sensor_default>; + + label = "GPIO Hall Effect Sensor"; + + hall-sensor { + label = "Hall Effect Sensor"; + gpios = <&msmgpio 52 GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + linux,can-disable; + }; + }; + + i2c-muic { + compatible = "i2c-gpio"; + sda-gpios = <&msmgpio 105 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&msmgpio 106 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + + pinctrl-names = "default"; + pinctrl-0 = <&muic_i2c_default>; + + #address-cells = <1>; + #size-cells = <0>; + + muic: extcon@14 { + compatible = "siliconmitus,sm5504-muic"; + reg = <0x14>; + + interrupt-parent = <&msmgpio>; + interrupts = <12 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-names = "default"; + pinctrl-0 = <&muic_irq_default>; + }; + }; +}; + +&blsp1_uart2 { + status = "okay"; +}; + +&pm8916_resin { + status = "okay"; + linux,code = ; +}; + +&pm8916_vib { + status = "okay"; +}; + +&pronto { + status = "okay"; + + iris { + compatible = "qcom,wcn3660b"; + }; +}; + +&sdhc_1 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; + pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; +}; + +&sdhc_2 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; + + non-removable; + + /* + * FIXME: Disable UHS-I modes since tuning fails with: + * + * sdhci_msm 7864900.sdhci: mmc1: No tuning point found + * mmc1: tuning execution failed: -5 + * mmc1: error -5 whilst initialising SD card + * + * This is the quirk used on downstream, which suggests this is + * a hardware limitation. However, probing a card using DDR50 works + * (without tuning), so maybe only tuning is broken? + */ + no-1-8-v; +}; + +&usb { + status = "okay"; + extcon = <&muic>, <&muic>; +}; + +&usb_hs_phy { + extcon = <&muic>; +}; + +&smd_rpm_regulators { + vdd_l1_l2_l3-supply = <&pm8916_s3>; + vdd_l4_l5_l6-supply = <&pm8916_s4>; + vdd_l7-supply = <&pm8916_s4>; + + s3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1300000>; + }; + + s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2100000>; + }; + + l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + l4 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l8 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2900000>; + }; + + l9 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + l10 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2800000>; + }; + + l11 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + regulator-allow-set-load; + regulator-system-load = <200000>; + }; + + l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + l13 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + }; + + l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + l16 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + l18 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; +}; + +&msmgpio { + gpio_keys_default: gpio-keys-default { + pins = "gpio107", "gpio109"; + function = "gpio"; + + drive-strength = <2>; + bias-pull-up; + }; + + gpio_hall_sensor_default: gpio-hall-sensor-default { + pins = "gpio52"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + muic_i2c_default: muic-i2c-default { + pins = "gpio105", "gpio106"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + muic_irq_default: muic-irq-default { + pins = "gpio12"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; +}; From patchwork Mon Oct 4 20:19:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephan Gerhold X-Patchwork-Id: 12534757 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2D309C433F5 for ; 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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Like msm8916-samsung-a3u-eur, the S4 Mini VE uses a Zinitix BT541 touch screen. Add it together with the necessary fixed-regulator to the device tree. Signed-off-by: Stephan Gerhold --- Changes in v2: None. --- .../dts/qcom/msm8916-samsung-serranove.dts | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts index 013f843aff9c..aa1326e5d4cb 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts @@ -78,6 +78,19 @@ hall-sensor { }; }; + reg_vdd_tsp: regulator-vdd-tsp { + compatible = "regulator-fixed"; + regulator-name = "vdd_tsp"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&msmgpio 73 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&tsp_en_default>; + }; + i2c-muic { compatible = "i2c-gpio"; sda-gpios = <&msmgpio 105 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; @@ -102,6 +115,27 @@ muic: extcon@14 { }; }; +&blsp_i2c5 { + status = "okay"; + + touchscreen@20 { + compatible = "zinitix,bt541"; + reg = <0x20>; + + interrupt-parent = <&msmgpio>; + interrupts = <13 IRQ_TYPE_EDGE_FALLING>; + + touchscreen-size-x = <540>; + touchscreen-size-y = <960>; + + vdd-supply = <®_vdd_tsp>; + vddo-supply = <&pm8916_l6>; + + pinctrl-names = "default"; + pinctrl-0 = <&tsp_irq_default>; + }; +}; + &blsp1_uart2 { status = "okay"; }; @@ -298,4 +332,20 @@ muic_irq_default: muic-irq-default { drive-strength = <2>; bias-disable; }; + + tsp_en_default: tsp-en-default { + pins = "gpio73"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + tsp_irq_default: tsp-irq-default { + pins = "gpio13"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; }; From patchwork Mon Oct 4 20:19:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephan Gerhold X-Patchwork-Id: 12534765 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 02454C433F5 for ; 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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add the CORERIVER TC360 touch key together with the two necessary fixed regulators for it. Note that for some reason Samsung decided to connect this to GPIOs where no hardware I2C bus is available, so we need to fall back to software bit-banging using i2c-gpio. Signed-off-by: Stephan Gerhold --- Changes in v2: None. --- .../dts/qcom/msm8916-samsung-serranove.dts | 87 +++++++++++++++++++ 1 file changed, 87 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts index aa1326e5d4cb..564f4f6d4f0f 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts @@ -91,6 +91,32 @@ reg_vdd_tsp: regulator-vdd-tsp { pinctrl-0 = <&tsp_en_default>; }; + reg_touch_key: regulator-touch-key { + compatible = "regulator-fixed"; + regulator-name = "touch_key"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + gpio = <&msmgpio 86 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&tkey_en_default>; + }; + + reg_key_led: regulator-key-led { + compatible = "regulator-fixed"; + regulator-name = "key_led"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&msmgpio 60 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&tkey_led_en_default>; + }; + i2c-muic { compatible = "i2c-gpio"; sda-gpios = <&msmgpio 105 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; @@ -113,6 +139,35 @@ muic: extcon@14 { pinctrl-0 = <&muic_irq_default>; }; }; + + i2c-tkey { + compatible = "i2c-gpio"; + sda-gpios = <&msmgpio 16 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&msmgpio 17 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + + pinctrl-names = "default"; + pinctrl-0 = <&tkey_i2c_default>; + + #address-cells = <1>; + #size-cells = <0>; + + touchkey@20 { + compatible = "coreriver,tc360-touchkey"; + reg = <0x20>; + + interrupt-parent = <&msmgpio>; + interrupts = <98 IRQ_TYPE_EDGE_FALLING>; + + vcc-supply = <®_touch_key>; + vdd-supply = <®_key_led>; + vddio-supply = <&pm8916_l6>; + + linux,keycodes = ; + + pinctrl-names = "default"; + pinctrl-0 = <&tkey_default>; + }; + }; }; &blsp_i2c5 { @@ -333,6 +388,38 @@ muic_irq_default: muic-irq-default { bias-disable; }; + tkey_default: tkey-default { + pins = "gpio98"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + tkey_en_default: tkey-en-default { + pins = "gpio86"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + tkey_i2c_default: tkey-i2c-default { + pins = "gpio16", "gpio17"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + tkey_led_en_default: tkey-led-en-default { + pins = "gpio60"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + tsp_en_default: tsp-en-default { pins = "gpio73"; function = "gpio"; From patchwork Mon Oct 4 20:19:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephan Gerhold X-Patchwork-Id: 12534759 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 74AB8C433F5 for ; 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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add the STMicroelectronics LSM6DS3 IMU that is used in the S4 Mini VE to the device tree. Signed-off-by: Stephan Gerhold --- Changes in v2: None. --- .../dts/qcom/msm8916-samsung-serranove.dts | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts index 564f4f6d4f0f..2280b2e4b09f 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts @@ -170,6 +170,21 @@ touchkey@20 { }; }; +&blsp_i2c2 { + status = "okay"; + + imu@6b { + compatible = "st,lsm6ds3"; + reg = <0x6b>; + + interrupt-parent = <&msmgpio>; + interrupts = <115 IRQ_TYPE_EDGE_RISING>; + + pinctrl-names = "default"; + pinctrl-0 = <&imu_irq_default>; + }; +}; + &blsp_i2c5 { status = "okay"; @@ -372,6 +387,14 @@ gpio_hall_sensor_default: gpio-hall-sensor-default { bias-disable; }; + imu_irq_default: imu-irq-default { + pins = "gpio115"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + muic_i2c_default: muic-i2c-default { pins = "gpio105", "gpio106"; function = "gpio"; From patchwork Mon Oct 4 20:19:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephan Gerhold X-Patchwork-Id: 12534763 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DC516C433F5 for ; Mon, 4 Oct 2021 20:25:18 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id AA6C56140B for ; Mon, 4 Oct 2021 20:25:18 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org AA6C56140B Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gerhold.net Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; 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Mon, 04 Oct 2021 20:21:59 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1633378912; s=strato-dkim-0002; d=gerhold.net; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Cc:Date: From:Subject:Sender; bh=ea+Sy+mMXz74lRddtGM5fpGU44ERmjDH2rPdXRR4quU=; b=W8qn4Q0EyDg8OJa1LBVIsCFsMtKm+SPS70fiRed9tXensM0iF1gO/Jo0GzUAruEqfY xzu8GVgN37TO1IfnlJNaXfvuwPgGn1WCvjXmxvQGfhLMoM6RekEMn8AElxSxgY/6WRMM gWoot1ZRBtK0FhILSyDP9N+jGZkK4vzw+1CD6Ne+BE6knbDCjNYrTGaplrsaYh+GJhZb yUOU6LlWyIt/aLzw6fcmYfAzesQL39U7hGlh1xGNz5VVjDgmXLavyUpkVBNUc+4jxVOl Y+XkPNsUuvrVC0cGcZnj708YDdf0QY+/NfRgTbunJ2MDhiyAHwVEtHEAcxz50vFxxbHT RsLg== Authentication-Results: strato.com; dkim=none X-RZG-AUTH: ":P3gBZUipdd93FF5ZZvYFPugejmSTVR2nRPhVORvLd4SsytBXTbAOHjRHIhr2eFePxBA=" X-RZG-CLASS-ID: mo00 Received: from droid.. by smtp.strato.de (RZmta 47.33.8 DYNA|AUTH) with ESMTPSA id 301038x94KLpKQp (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256 bits)) (Client did not present a certificate); Mon, 4 Oct 2021 22:21:51 +0200 (CEST) From: Stephan Gerhold To: Bjorn Andersson Cc: Andy Gross , linux-arm-msm@vger.kernel.org, Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, Stephan Gerhold Subject: [PATCH v2 05/15] arm64: dts: qcom: msm8916-samsung-serranove: Add rt5033 battery Date: Mon, 4 Oct 2021 22:19:11 +0200 Message-Id: <20211004201921.18526-6-stephan@gerhold.net> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211004201921.18526-1-stephan@gerhold.net> References: <20211004201921.18526-1-stephan@gerhold.net> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211004_132157_150009_D462A8AA X-CRM114-Status: UNSURE ( 9.79 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Like the Samsung Galaxy A3/A5, the S4 Mini VE uses a Richtek RT5033 PMIC as battery fuel gauge, charger, flash LED and for some regulators. For now, only add the fuel gauge/battery device to the device tree, so we can check the remaining battery percentage. The other RT5033 drivers need some more work first before they can be used properly. Signed-off-by: Stephan Gerhold --- Changes in v2: None. --- .../dts/qcom/msm8916-samsung-serranove.dts | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts index 2280b2e4b09f..3ef00bdc043e 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts @@ -185,6 +185,21 @@ imu@6b { }; }; +&blsp_i2c4 { + status = "okay"; + + battery@35 { + compatible = "richtek,rt5033-battery"; + reg = <0x35>; + + interrupt-parent = <&msmgpio>; + interrupts = <121 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-names = "default"; + pinctrl-0 = <&fg_alert_default>; + }; +}; + &blsp_i2c5 { status = "okay"; @@ -371,6 +386,14 @@ l18 { }; &msmgpio { + fg_alert_default: fg-alert-default { + pins = "gpio121"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + gpio_keys_default: gpio-keys-default { pins = "gpio107", "gpio109"; function = "gpio"; From patchwork Mon Oct 4 20:19:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephan Gerhold X-Patchwork-Id: 12534761 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7C56BC433F5 for ; Mon, 4 Oct 2021 20:25:09 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 483CC6140B for ; Mon, 4 Oct 2021 20:25:09 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 483CC6140B Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gerhold.net Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; 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Mon, 04 Oct 2021 20:22:00 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1633378912; s=strato-dkim-0002; d=gerhold.net; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Cc:Date: From:Subject:Sender; bh=BNocBK4U1HyTaxyN3VYb2yfK5aJOaCFqjEMeLHlV25E=; b=X/95LHhnc+kTdg+7tBN1vZVklTHr1sXMlxDaVoCt3T73doSBLH42egK1bULCMjkN39 wdmT2wckB+r7297JlCVEdJZpMFWWysiRkNM6hcJwsOlMMtOpxRNbt/zjzTrNb5LTGJWb KMoOm8jojKAnR2fNVZqb/U7Mr+M0n+h9dOOF8DHhWfbNjChsFMQVbFPai5teyW7AFe0P wBclHRrDCnPZR2rte8APn/d+4JpVB/gfECkoRrxFSUtPyRbGnAIHt0toZWZoT5mEaHhc PxuRwBntveNN6CgR5nB4Pe1OaTMPb17bKKrmAdyVis5EmEceLE+miNLQABJT9Gu5vml6 HiIA== Authentication-Results: strato.com; dkim=none X-RZG-AUTH: ":P3gBZUipdd93FF5ZZvYFPugejmSTVR2nRPhVORvLd4SsytBXTbAOHjRHIhr2eFePxBA=" X-RZG-CLASS-ID: mo00 Received: from droid.. by smtp.strato.de (RZmta 47.33.8 DYNA|AUTH) with ESMTPSA id 301038x94KLqKQq (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256 bits)) (Client did not present a certificate); Mon, 4 Oct 2021 22:21:52 +0200 (CEST) From: Stephan Gerhold To: Bjorn Andersson Cc: Andy Gross , linux-arm-msm@vger.kernel.org, Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, Stephan Gerhold Subject: [PATCH v2 06/15] arm64: dts: qcom: msm8916-samsung-serranove: Add NFC Date: Mon, 4 Oct 2021 22:19:12 +0200 Message-Id: <20211004201921.18526-7-stephan@gerhold.net> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211004201921.18526-1-stephan@gerhold.net> References: <20211004201921.18526-1-stephan@gerhold.net> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211004_132157_478625_D843D575 X-CRM114-Status: GOOD ( 11.59 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The LTE version of the S4 Mini VE has a NXP PN547, which is supported by the nxp-nci-i2c driver in mainline. It seems to detect NFC tags using "nfctool" just fine, although more testing is difficult given there seem to be very few useful applications making use of the Linux NFC subsystem. :( Note that for some reason Samsung decided to connect the I2C pins to GPIOs where no hardware I2C bus is available, so we need to fall back to software bit-banging with i2c-gpio. Signed-off-by: Stephan Gerhold --- Changes in v2: None. --- .../dts/qcom/msm8916-samsung-serranove.dts | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts index 3ef00bdc043e..a78f87a5bf4f 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts @@ -168,6 +168,32 @@ touchkey@20 { pinctrl-0 = <&tkey_default>; }; }; + + i2c-nfc { + compatible = "i2c-gpio"; + sda-gpios = <&msmgpio 0 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&msmgpio 1 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + + pinctrl-names = "default"; + pinctrl-0 = <&nfc_i2c_default>; + + #address-cells = <1>; + #size-cells = <0>; + + nfc@2b { + compatible = "nxp,pn547", "nxp,nxp-nci-i2c"; + reg = <0x2b>; + + interrupt-parent = <&msmgpio>; + interrupts = <21 IRQ_TYPE_EDGE_RISING>; + + enable-gpios = <&msmgpio 20 GPIO_ACTIVE_HIGH>; + firmware-gpios = <&msmgpio 49 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&nfc_default>; + }; + }; }; &blsp_i2c2 { @@ -434,6 +460,30 @@ muic_irq_default: muic-irq-default { bias-disable; }; + nfc_default: nfc-default { + pins = "gpio20", "gpio49"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + + irq { + pins = "gpio21"; + function = "gpio"; + + drive-strength = <2>; + bias-pull-down; + }; + }; + + nfc_i2c_default: nfc-i2c-default { + pins = "gpio0", "gpio1"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + tkey_default: tkey-default { pins = "gpio98"; function = "gpio"; From patchwork Mon Oct 4 20:49:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephan Gerhold X-Patchwork-Id: 12534785 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 86BB0C433EF for ; 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Note that since ARM64 is the main supported architecture for MSM8916 this is only intended for testing and for devices where signed firmware does not allow booting ARM64 kernels. Signed-off-by: Stephan Gerhold --- Changes in v2: Simplify wording a bit --- arch/arm/mach-qcom/Kconfig | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/mach-qcom/Kconfig b/arch/arm/mach-qcom/Kconfig index 1772eccb5caf..466acc4a5e0c 100644 --- a/arch/arm/mach-qcom/Kconfig +++ b/arch/arm/mach-qcom/Kconfig @@ -21,6 +21,16 @@ config ARCH_MSM8X60 bool "Enable support for MSM8X60" select CLKSRC_QCOM +config ARCH_MSM8916 + bool "Enable support for MSM8916" + select HAVE_ARM_ARCH_TIMER + help + Enable support for the Qualcomm Snapdragon 410 (MSM8916/APQ8016). + + Note that ARM64 is the main supported architecture for MSM8916. + The ARM32 option is intended for a few devices with signed firmware + that does not allow booting ARM64 kernels. + config ARCH_MSM8960 bool "Enable support for MSM8960" select CLKSRC_QCOM From patchwork Mon Oct 4 20:49:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephan Gerhold X-Patchwork-Id: 12534779 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 93C7FC433F5 for ; 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b=EXmT3EsYWO5E58t24n3RyLuxOCocuaNf+UZ8+6K/smj6WeWAFfgcjWQVSjIBaGZXZ6 Ev9AqbWA6630d0dfUvRx6kLv0yAuhztGzzAP4UOKSN6juTxCUc8h8UcAXiXEMikUvyPm ZQoiY7gLan4KDGIlzvdlXKY2IM4vpqJqlC4pmWF605JLBuYG+MM2bx2Oj1riiAwPV8yA ioQNoMn+wBSreK+EsakCW+GpFpjUYclxmy9jw7om21UilwhHo2rgHP5JYGF7bLXmT0KJ uNUx9EvicFzunXzdtwvusuejgwlY1OpZuPpBsdezfKA4Xf6BSLnr0YSnG5B7UvqIxzKx caDA== Authentication-Results: strato.com; dkim=none X-RZG-AUTH: ":P3gBZUipdd93FF5ZZvYFPugejmSTVR2nRPhVORvLd4SsytBXTbAOHjRHIhr2eFePxBA=" X-RZG-CLASS-ID: mo00 Received: from droid.. by smtp.strato.de (RZmta 47.33.8 DYNA|AUTH) with ESMTPSA id 301038x94Kp8KSl (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256 bits)) (Client did not present a certificate); Mon, 4 Oct 2021 22:51:08 +0200 (CEST) From: Stephan Gerhold To: Bjorn Andersson Cc: Andy Gross , linux-arm-msm@vger.kernel.org, Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, Stephan Gerhold Subject: [PATCH v2 08/15] dt-bindings: arm: cpus: Document qcom, msm8916-smp enable-method Date: Mon, 4 Oct 2021 22:49:48 +0200 Message-Id: <20211004204955.21077-8-stephan@gerhold.net> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211004201921.18526-1-stephan@gerhold.net> References: <20211004201921.18526-1-stephan@gerhold.net> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211004_135112_211882_8E7A2A6A X-CRM114-Status: GOOD ( 15.15 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Since MSM8916 is an ARM v8 64-bit SoC the CPU cores are normally booted using "psci" or "spin-table". Unfortunately, some devices come with signed 32-bit-only firmware without ARM64 and PSCI support. This setup is easy to support since it's very similar to older 32-bit only Qualcomm SoCs (e.g. MSM8226) and only requires adding a few new definitions to already existing drivers. Document the qcom,msm8916-smp enable-method. It is actually just an alias of qcom,msm8226-smp since it should be implemented identically. The enable-method is only valid on ARM32 and must not be used on ARM64. Signed-off-by: Stephan Gerhold Reviewed-by: Rob Herring --- Changes in v2: - Clarify that this is only supposed to be used on ARM 32-bit (Add comment to commit message and DT schema) The "see above for ARM v8 64-bit" comment refers to this a few lines above in the DT schema: # On ARM v8 64-bit this property is required - enum: - psci - spin-table --- Documentation/devicetree/bindings/arm/cpus.yaml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index 11e3e09da2e5..6a95b2a76bdc 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -211,6 +211,8 @@ properties: - qcom,kpss-acc-v1 - qcom,kpss-acc-v2 - qcom,msm8226-smp + # Only valid on ARM 32-bit, see above for ARM v8 64-bit + - qcom,msm8916-smp - renesas,apmu - renesas,r9a06g032-smp - rockchip,rk3036-smp @@ -295,7 +297,8 @@ properties: Specifies the ACC* node associated with this CPU. Required for systems that have an "enable-method" property - value of "qcom,kpss-acc-v1", "qcom,kpss-acc-v2" or "qcom,msm8226-smp" + value of "qcom,kpss-acc-v1", "qcom,kpss-acc-v2", "qcom,msm8226-smp" + or "qcom,msm8916-smp". * arm/msm/qcom,kpss-acc.txt From patchwork Mon Oct 4 20:49:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephan Gerhold X-Patchwork-Id: 12534781 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7D130C433EF for ; Mon, 4 Oct 2021 20:52:48 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 417FE61360 for ; Mon, 4 Oct 2021 20:52:48 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 417FE61360 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gerhold.net Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=92WQySubhRHlzhFUHE4Wcilkszbp8Agjs6KCciG5fYM=; b=unaH1uh1GmZmhC s8OrdwwH6ceadlZkCroQ/01HOuTWbOz0/ajyRswOpnvaRrF8Nf0BMIewRQpXE+cVJd6DxpFmvF26X qrCsXZWS4QPDdMOzR3PidLFDeOdFeHUPjHyCQ3/hzpgR5qf4XcQFjU2VyMRaXFaNsKFaTfEL2SV0+ Z/I8/ICx/FCfvpE14bS4e2L57JqrERhHCm1c3iq0w3Jid2k1pJahu2EkXm3jW0QdKow/cMIxNFoh0 WPPpWjSIV/8Q6UYdsEEg5wPKu5pbEOXry8fDMaW4OzOHimRWzIXkfOMFO72UewKxxgws4+qyiPIpv vuMeOXAHch5+js7dycRA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mXUvm-00849z-Pb; Mon, 04 Oct 2021 20:51:26 +0000 Received: from mo4-p03-ob.smtp.rzone.de ([81.169.146.174]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mXUvd-00840r-JR for linux-arm-kernel@lists.infradead.org; Mon, 04 Oct 2021 20:51:19 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1633380672; s=strato-dkim-0002; d=gerhold.net; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Cc:Date: From:Subject:Sender; bh=cHGij+gAQJh8yR9ykjR0K1Im3U3PsRCreY04KgR25+M=; b=OZZT9zOmXMma2xhPzb5OEwOHz/23MZ782XwCWfwT9XgL9AJGtOWSKsKsuWH1UiCH8X 73w1ynvGpQu1eXG7mssZkZgvnQSbBysY+mBBvNPSXBuXKsYGgRDloG6jIHL3LSlC9EX/ XM6MBn5Y5uJVUG9o7J1LPTONCifs3+5UPLfF65bA68Iu4VyzirEZoyrBxi2Oimj4Np0N E4/DhTz7XR87Q1uWWvTZJNCFVrO2BMXN1zXGvWYG77oMB7fij0wwXnqkx+vWHCcaqinA TzQvcii2DvuHyfn2NqRMq58hfrkQct706+LoQVWtQl9CxK/WqMMXOVlOuZOeuSSgdcnF mgMQ== Authentication-Results: strato.com; dkim=none X-RZG-AUTH: ":P3gBZUipdd93FF5ZZvYFPugejmSTVR2nRPhVORvLd4SsytBXTbAOHjRHIhr2eFePxBA=" X-RZG-CLASS-ID: mo00 Received: from droid.. by smtp.strato.de (RZmta 47.33.8 DYNA|AUTH) with ESMTPSA id 301038x94KpBKSm (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256 bits)) (Client did not present a certificate); Mon, 4 Oct 2021 22:51:11 +0200 (CEST) From: Stephan Gerhold To: Bjorn Andersson Cc: Andy Gross , linux-arm-msm@vger.kernel.org, Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, Stephan Gerhold Subject: [PATCH v2 09/15] ARM: qcom: Add qcom, msm8916-smp enable-method identical to MSM8226 Date: Mon, 4 Oct 2021 22:49:49 +0200 Message-Id: <20211004204955.21077-9-stephan@gerhold.net> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211004201921.18526-1-stephan@gerhold.net> References: <20211004201921.18526-1-stephan@gerhold.net> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211004_135117_805372_2C7D2DB0 X-CRM114-Status: UNSURE ( 9.75 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Unfortunately, some MSM8916 devices have signed firmware without ARM64 and PSCI support and can therefore only boot ARM32 Linux. The ARM Cortex-A53 cores should be actually booted exactly like the Cortex-A7 cores on MSM8226, so just add an alias for the existing code. Signed-off-by: Stephan Gerhold --- Changes in v2: Clarify commit message very slightly --- arch/arm/mach-qcom/platsmp.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-qcom/platsmp.c b/arch/arm/mach-qcom/platsmp.c index 60496554c6dd..58a4228455ce 100644 --- a/arch/arm/mach-qcom/platsmp.c +++ b/arch/arm/mach-qcom/platsmp.c @@ -385,6 +385,7 @@ static const struct smp_operations qcom_smp_cortex_a7_ops __initconst = { #endif }; CPU_METHOD_OF_DECLARE(qcom_smp_msm8226, "qcom,msm8226-smp", &qcom_smp_cortex_a7_ops); +CPU_METHOD_OF_DECLARE(qcom_smp_msm8916, "qcom,msm8916-smp", &qcom_smp_cortex_a7_ops); static const struct smp_operations qcom_smp_kpssv1_ops __initconst = { .smp_prepare_cpus = qcom_smp_prepare_cpus, From patchwork Mon Oct 4 20:49:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephan Gerhold X-Patchwork-Id: 12534783 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9DBACC433F5 for ; Mon, 4 Oct 2021 20:52:58 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 694E061357 for ; Mon, 4 Oct 2021 20:52:58 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 694E061357 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gerhold.net Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=gKmcHaoV/O//o7OgrnoF0m++Tc36AeSmOSrIM1OT0Us=; b=pyjdy6gvOpfq2r rvSiGWyA6lJy7XkH3Vk2OZgzyOB97DI7h7lRaJeeMGPobiVtXr3VPc2XxOccP7cxMqehzDbxkgdZY t4yEfz7cGYIXE/VTIw/50bvc5Sj8735GcdtEEKXvbRgQsf1LBoNtzxp3UIFINIiIW4TfEdpYmCzeU rznMoTU4pYz626T5Muc12Hx3TrMoNGMkJgQAup03Ld95FBstPxdFl2nQT0AiSTLTzrpek916IERSK JjNJ5YTmEUsR3d/n/cAyAm4GSv4wqLNz+8aH1rV5pX3Zqgbt0HbNuVQQ+e+o2+lVsPhbg7z4cihjp kIGD7MY67icK2eSs2EKQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mXUvx-0084Ds-Il; Mon, 04 Oct 2021 20:51:37 +0000 Received: from mo4-p03-ob.smtp.rzone.de ([85.215.255.103]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mXUve-00841I-6R for linux-arm-kernel@lists.infradead.org; Mon, 04 Oct 2021 20:51:19 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1633380674; s=strato-dkim-0002; d=gerhold.net; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Cc:Date: From:Subject:Sender; bh=P3pJe8UTWqOR4oauZ6Y2fQM+55nPWxe9V8KCULIJ8Os=; b=CbBFa8iPw8NwTAiwQd9BtEUy50z+lxvvQRhSGBM0fH1FEBOwNsy3oy7S9mffOlA2Zh iTLWJcRYdXXe5BwMYyyVx+Niy+HR3sfcyIaEbYPjD+blB9vT4J6nX7JTxYzpta0lm/dj rdBLBY6UdX3Ce4uWsqoRgqojIm9H9r+BtDLGP+UWoef0TcabgOBFCLXUhuNVRlbwrl75 sgV8AxyO4XwEo/4+7IjvGbHoiqif6nYI5+k3FR8uTiyQlVYlI4EDQn4wUM7o59kZwNas C0BWBJkvedE1X3akzZNUwVOmw+rnAuWwNe5ufeluU24AsGu0krqE+h5+AYhLN6Xe42aG musQ== Authentication-Results: strato.com; dkim=none X-RZG-AUTH: ":P3gBZUipdd93FF5ZZvYFPugejmSTVR2nRPhVORvLd4SsytBXTbAOHjRHIhr2eFePxBA=" X-RZG-CLASS-ID: mo00 Received: from droid.. by smtp.strato.de (RZmta 47.33.8 DYNA|AUTH) with ESMTPSA id 301038x94KpEKSn (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256 bits)) (Client did not present a certificate); Mon, 4 Oct 2021 22:51:14 +0200 (CEST) From: Stephan Gerhold To: Bjorn Andersson Cc: Andy Gross , linux-arm-msm@vger.kernel.org, Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, Rob Herring , Stephan Gerhold Subject: [PATCH v2 10/15] dt-bindings: soc: qcom: spm: Document qcom, msm8916-saw2-v3.0-cpu Date: Mon, 4 Oct 2021 22:49:50 +0200 Message-Id: <20211004204955.21077-10-stephan@gerhold.net> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211004201921.18526-1-stephan@gerhold.net> References: <20211004201921.18526-1-stephan@gerhold.net> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211004_135118_410254_7CDEBD3D X-CRM114-Status: UNSURE ( 8.15 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Document the qcom,msm8916-saw2-v3.0-cpu compatible that is needed for cpuidle for MSM8916 on some devices with signed firmware which is only capable of booting ARM32 kernels without PSCI. Acked-by: Rob Herring Signed-off-by: Stephan Gerhold --- Changes in v2: Add Rob's Acked-by --- Documentation/devicetree/bindings/soc/qcom/qcom,spm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,spm.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,spm.yaml index d68c002527fa..07d2d5398345 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,spm.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,spm.yaml @@ -22,6 +22,7 @@ properties: - qcom,sdm660-silver-saw2-v4.1-l2 - qcom,msm8998-gold-saw2-v4.1-l2 - qcom,msm8998-silver-saw2-v4.1-l2 + - qcom,msm8916-saw2-v3.0-cpu - qcom,msm8226-saw2-v2.1-cpu - qcom,msm8974-saw2-v2.1-cpu - qcom,apq8084-saw2-v2.1-cpu From patchwork Mon Oct 4 20:49:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephan Gerhold X-Patchwork-Id: 12534787 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0060EC433EF for ; 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Link: https://lore.kernel.org/linux-arm-msm/1429314549-6730-5-git-send-email-lina.iyer@linaro.org/ Signed-off-by: Lina Iyer [stephan: rebase patch and fix conflicts] Signed-off-by: Stephan Gerhold --- Changes in v2: None. Like for qcom,msm8916-smp and qcom,msm8226-smp, this is actually pretty much identical to the MSM8226 configuration except for the new v3.0 register offsets. --- drivers/soc/qcom/spm.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/soc/qcom/spm.c b/drivers/soc/qcom/spm.c index 2961a89d929c..f831420b7fd4 100644 --- a/drivers/soc/qcom/spm.c +++ b/drivers/soc/qcom/spm.c @@ -67,6 +67,25 @@ static const struct spm_reg_data spm_reg_8998_silver_l2 = { .avs_limit = 0x4200420, }; +static const u16 spm_reg_offset_v3_0[SPM_REG_NR] = { + [SPM_REG_CFG] = 0x08, + [SPM_REG_SPM_CTL] = 0x30, + [SPM_REG_DLY] = 0x34, + [SPM_REG_SEQ_ENTRY] = 0x400, +}; + +/* SPM register data for 8916 */ +static const struct spm_reg_data spm_reg_8916_cpu = { + .reg_offset = spm_reg_offset_v3_0, + .spm_cfg = 0x1, + .spm_dly = 0x3C102800, + .seq = { 0x60, 0x03, 0x60, 0x0B, 0x0F, 0x20, 0x10, 0x80, 0x30, 0x90, + 0x5B, 0x60, 0x03, 0x60, 0x3B, 0x76, 0x76, 0x0B, 0x94, 0x5B, + 0x80, 0x10, 0x26, 0x30, 0x0F }, + .start_index[PM_SLEEP_MODE_STBY] = 0, + .start_index[PM_SLEEP_MODE_SPC] = 5, +}; + static const u16 spm_reg_offset_v2_1[SPM_REG_NR] = { [SPM_REG_CFG] = 0x08, [SPM_REG_SPM_CTL] = 0x30, @@ -176,6 +195,8 @@ static const struct of_device_id spm_match_table[] = { .data = &spm_reg_660_silver_l2 }, { .compatible = "qcom,msm8226-saw2-v2.1-cpu", .data = &spm_reg_8226_cpu }, + { .compatible = "qcom,msm8916-saw2-v3.0-cpu", + .data = &spm_reg_8916_cpu }, { .compatible = "qcom,msm8974-saw2-v2.1-cpu", .data = &spm_reg_8974_8084_cpu }, { .compatible = "qcom,msm8998-gold-saw2-v4.1-l2", From patchwork Mon Oct 4 20:49:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephan Gerhold X-Patchwork-Id: 12534789 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E7E23C433EF for ; Mon, 4 Oct 2021 20:53:35 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id AFBEB61357 for ; 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dkim=none X-RZG-AUTH: ":P3gBZUipdd93FF5ZZvYFPugejmSTVR2nRPhVORvLd4SsytBXTbAOHjRHIhr2eFePxBA=" X-RZG-CLASS-ID: mo00 Received: from droid.. by smtp.strato.de (RZmta 47.33.8 DYNA|AUTH) with ESMTPSA id 301038x94KpIKSp (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256 bits)) (Client did not present a certificate); Mon, 4 Oct 2021 22:51:18 +0200 (CEST) From: Stephan Gerhold To: Bjorn Andersson Cc: Andy Gross , linux-arm-msm@vger.kernel.org, Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, Stephan Gerhold Subject: [PATCH v2 12/15] firmware: qcom: scm: Add support for MC boot address API Date: Mon, 4 Oct 2021 22:49:52 +0200 Message-Id: <20211004204955.21077-12-stephan@gerhold.net> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211004201921.18526-1-stephan@gerhold.net> References: <20211004201921.18526-1-stephan@gerhold.net> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211004_135121_838175_1FC59AB2 X-CRM114-Status: GOOD ( 23.90 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org It looks like the old QCOM_SCM_BOOT_SET_ADDR API is broken on some MSM8916 firmware versions that implement the newer SMC32 calling convention. It just returns -EINVAL no matter which arguments are being passed. This does not cause any problems downstream because it first tries to use the new multi-cluster API replacement which is working fine. Implement support for the multi-cluster variant of the SCM call by attempting it first but still fallback to the old call in case of an error. Also, to be absolutely sure only use the multi-cluster variant with the SMC calling convention since older platforms should not need this. Signed-off-by: Stephan Gerhold --- Changes in v2: None. The diff generated by Git is a bit hard to read sadly, what I did essentially is: 1. Add __qcom_scm_set_boot_addr_mc() 2. Rename original qcom_scm_set_cold/warm_boot_addr() to static __qcom_scm_set_cold/warm_boot_addr() 3. Make new qcom_scm_set_cold/warm_boot_addr() call __qcom_scm_set_boot_addr_mc() first and then fall back to the old __qcom_scm_set_cold/warm_boot_addr() as before --- drivers/firmware/qcom_scm.c | 84 +++++++++++++++++++++++++++++-------- drivers/firmware/qcom_scm.h | 4 ++ 2 files changed, 71 insertions(+), 17 deletions(-) diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c index a861033616ee..75506a1bbcfc 100644 --- a/drivers/firmware/qcom_scm.c +++ b/drivers/firmware/qcom_scm.c @@ -17,6 +17,8 @@ #include #include +#include + #include "qcom_scm.h" static bool download_mode = IS_ENABLED(CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT); @@ -260,15 +262,36 @@ static bool __qcom_scm_is_call_available(struct device *dev, u32 svc_id, return ret ? false : !!res.result[0]; } -/** - * qcom_scm_set_warm_boot_addr() - Set the warm boot address for cpus - * @entry: Entry point function for the cpus - * @cpus: The cpumask of cpus that will use the entry point - * - * Set the Linux entry point for the SCM to transfer control to when coming - * out of a power down. CPU power down may be executed on cpuidle or hotplug. - */ -int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus) +static int __qcom_scm_set_boot_addr_mc(void *entry, const cpumask_t *cpus, + unsigned int flags) +{ + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_BOOT, + .cmd = QCOM_SCM_BOOT_SET_ADDR_MC, + .owner = ARM_SMCCC_OWNER_SIP, + .arginfo = QCOM_SCM_ARGS(6), + }; + unsigned int cpu; + u64 map; + + /* Need a device for DMA of the additional arguments */ + if (!__scm || __get_convention() == SMC_CONVENTION_LEGACY) + return -EOPNOTSUPP; + + desc.args[0] = virt_to_phys(entry); + for_each_cpu(cpu, cpus) { + map = cpu_logical_map(cpu); + desc.args[1] |= BIT(MPIDR_AFFINITY_LEVEL(map, 0)); + desc.args[2] |= BIT(MPIDR_AFFINITY_LEVEL(map, 1)); + desc.args[3] |= BIT(MPIDR_AFFINITY_LEVEL(map, 2)); + } + desc.args[4] = ~0ULL; /* Reserved for affinity level 3 */ + desc.args[5] = flags; + + return qcom_scm_call(__scm->dev, &desc, NULL); +} + +static int __qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus) { int ret; int flags = 0; @@ -304,17 +327,28 @@ int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus) return ret; } -EXPORT_SYMBOL(qcom_scm_set_warm_boot_addr); /** - * qcom_scm_set_cold_boot_addr() - Set the cold boot address for cpus + * qcom_scm_set_warm_boot_addr() - Set the warm boot address for cpus * @entry: Entry point function for the cpus * @cpus: The cpumask of cpus that will use the entry point * - * Set the cold boot address of the cpus. Any cpu outside the supported - * range would be removed from the cpu present mask. + * Set the Linux entry point for the SCM to transfer control to when coming + * out of a power down. CPU power down may be executed on cpuidle or hotplug. */ -int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus) +int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus) +{ + if (!cpus || cpumask_empty(cpus)) + return -EINVAL; + + if (__qcom_scm_set_boot_addr_mc(entry, cpus, QCOM_SCM_BOOT_MC_FLAG_WARMBOOT)) + /* Fallback to old SCM call */ + return __qcom_scm_set_warm_boot_addr(entry, cpus); + return 0; +} +EXPORT_SYMBOL(qcom_scm_set_warm_boot_addr); + +static int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus) { int flags = 0; int cpu; @@ -331,9 +365,6 @@ int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus) .owner = ARM_SMCCC_OWNER_SIP, }; - if (!cpus || cpumask_empty(cpus)) - return -EINVAL; - for_each_cpu(cpu, cpus) { if (cpu < ARRAY_SIZE(scm_cb_flags)) flags |= scm_cb_flags[cpu]; @@ -346,6 +377,25 @@ int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus) return qcom_scm_call_atomic(__scm ? __scm->dev : NULL, &desc, NULL); } + +/** + * qcom_scm_set_cold_boot_addr() - Set the cold boot address for cpus + * @entry: Entry point function for the cpus + * @cpus: The cpumask of cpus that will use the entry point + * + * Set the cold boot address of the cpus. Any cpu outside the supported + * range would be removed from the cpu present mask. + */ +int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus) +{ + if (!cpus || cpumask_empty(cpus)) + return -EINVAL; + + if (__qcom_scm_set_boot_addr_mc(entry, cpus, QCOM_SCM_BOOT_MC_FLAG_COLDBOOT)) + /* Fallback to old SCM call */ + return __qcom_scm_set_cold_boot_addr(entry, cpus); + return 0; +} EXPORT_SYMBOL(qcom_scm_set_cold_boot_addr); /** diff --git a/drivers/firmware/qcom_scm.h b/drivers/firmware/qcom_scm.h index d92156ceb3ac..2a6a87b75231 100644 --- a/drivers/firmware/qcom_scm.h +++ b/drivers/firmware/qcom_scm.h @@ -78,8 +78,12 @@ extern int scm_legacy_call(struct device *dev, const struct qcom_scm_desc *desc, #define QCOM_SCM_BOOT_SET_ADDR 0x01 #define QCOM_SCM_BOOT_TERMINATE_PC 0x02 #define QCOM_SCM_BOOT_SET_DLOAD_MODE 0x10 +#define QCOM_SCM_BOOT_SET_ADDR_MC 0x11 #define QCOM_SCM_BOOT_SET_REMOTE_STATE 0x0a #define QCOM_SCM_FLUSH_FLAG_MASK 0x3 +#define QCOM_SCM_BOOT_MC_FLAG_AARCH64 BIT(0) +#define QCOM_SCM_BOOT_MC_FLAG_COLDBOOT BIT(1) +#define QCOM_SCM_BOOT_MC_FLAG_WARMBOOT BIT(2) #define QCOM_SCM_SVC_PIL 0x02 #define QCOM_SCM_PIL_PAS_INIT_IMAGE 0x01 From patchwork Mon Oct 4 20:49:53 2021 Content-Type: text/plain; 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Mon, 04 Oct 2021 20:51:25 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1633380680; s=strato-dkim-0002; d=gerhold.net; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Cc:Date: From:Subject:Sender; bh=4ep6ai6Ln+jJh0LgouoZwvg0x9S3eHBE38lFwTBns3k=; b=m1PZrmuJJaqpQfqSGBIYecbqx2g0LcPB8ncMSb7gt2+GNd1q5qncDKYLtdPdxWPQRU map1kbKZXufcx01CRna6zUeC9E8eRZNHRwvy+0Rk3kixvheRVDQLW7FMVAQ70CmAvdkn PrcaLX4D7mlAWmCyd/E7yTmVsBE1EGQ6bxqSLEJRD207f6bCgvfANrx8posbV/twPrR+ jgfQou/zqkLE7S6N1q5kMgMDoMwez4UcYO5ErenAX3pGN2HbJya3ag4SJF3qyJnFaMQu +HG702+zKaNMTgA/2Qdcg56NLNTiRzoYyf4QOPvDywd+ciGo82FRrGFmRpBslpFuG5+j 8eSQ== Authentication-Results: strato.com; dkim=none X-RZG-AUTH: ":P3gBZUipdd93FF5ZZvYFPugejmSTVR2nRPhVORvLd4SsytBXTbAOHjRHIhr2eFePxBA=" X-RZG-CLASS-ID: mo00 Received: from droid.. by smtp.strato.de (RZmta 47.33.8 DYNA|AUTH) with ESMTPSA id 301038x94KpJKSq (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256 bits)) (Client did not present a certificate); Mon, 4 Oct 2021 22:51:19 +0200 (CEST) From: Stephan Gerhold To: Bjorn Andersson Cc: Andy Gross , linux-arm-msm@vger.kernel.org, Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, Stephan Gerhold Subject: [PATCH v2 13/15] arm64: dts: qcom: msm8916: Add CPU ACC and SAW/SPM Date: Mon, 4 Oct 2021 22:49:53 +0200 Message-Id: <20211004204955.21077-13-stephan@gerhold.net> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211004201921.18526-1-stephan@gerhold.net> References: <20211004201921.18526-1-stephan@gerhold.net> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211004_135123_949847_FD1A27DE X-CRM114-Status: GOOD ( 13.11 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add the device tree nodes necessary for SMP bring-up and cpuidle without PSCI on ARM32. The hardware is typically controlled by the PSCI implementation in the TrustZone firmware and is therefore marked as status = "reserved" by default (from the device tree specification): "Indicates that the device is operational, but should not be used. Typically this is used for devices that are controlled by another software component, such as platform firmware." Since this is part of the MSM8916 SoC it should be added to msm8916.dtsi but in practice these nodes should only get enabled via an extra include on ARM32. This is necessary for some devices with signed firmware which is missing both ARM64 and PSCI support and can therefore only boot ARM32 kernels. Signed-off-by: Stephan Gerhold --- Changes in v2: None. --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 56 +++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 6b06b387b021..3e7e5c9e6f1b 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -124,6 +124,8 @@ CPU0: cpu@0 { #cooling-cells = <2>; power-domains = <&CPU_PD0>; power-domain-names = "psci"; + qcom,acc = <&cpu0_acc>; + qcom,saw = <&cpu0_saw>; }; CPU1: cpu@1 { @@ -137,6 +139,8 @@ CPU1: cpu@1 { #cooling-cells = <2>; power-domains = <&CPU_PD1>; power-domain-names = "psci"; + qcom,acc = <&cpu1_acc>; + qcom,saw = <&cpu1_saw>; }; CPU2: cpu@2 { @@ -150,6 +154,8 @@ CPU2: cpu@2 { #cooling-cells = <2>; power-domains = <&CPU_PD2>; power-domain-names = "psci"; + qcom,acc = <&cpu2_acc>; + qcom,saw = <&cpu2_saw>; }; CPU3: cpu@3 { @@ -163,6 +169,8 @@ CPU3: cpu@3 { #cooling-cells = <2>; power-domains = <&CPU_PD3>; power-domain-names = "psci"; + qcom,acc = <&cpu3_acc>; + qcom,saw = <&cpu3_saw>; }; L2_0: l2-cache { @@ -1877,6 +1885,54 @@ frame@b028000 { status = "disabled"; }; }; + + cpu0_acc: power-manager@b088000 { + compatible = "qcom,msm8916-acc"; + reg = <0x0b088000 0x1000>; + status = "reserved"; /* Controlled by PSCI firmware */ + }; + + cpu0_saw: power-manager@b089000 { + compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2"; + reg = <0x0b089000 0x1000>; + status = "reserved"; /* Controlled by PSCI firmware */ + }; + + cpu1_acc: power-manager@b098000 { + compatible = "qcom,msm8916-acc"; + reg = <0x0b098000 0x1000>; + status = "reserved"; /* Controlled by PSCI firmware */ + }; + + cpu1_saw: power-manager@b099000 { + compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2"; + reg = <0x0b099000 0x1000>; + status = "reserved"; /* Controlled by PSCI firmware */ + }; + + cpu2_acc: power-manager@b0a8000 { + compatible = "qcom,msm8916-acc"; + reg = <0x0b0a8000 0x1000>; + status = "reserved"; /* Controlled by PSCI firmware */ + }; + + cpu2_saw: power-manager@b0a9000 { + compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2"; + reg = <0x0b0a9000 0x1000>; + status = "reserved"; /* Controlled by PSCI firmware */ + }; + + cpu3_acc: power-manager@b0b8000 { + compatible = "qcom,msm8916-acc"; + reg = <0x0b0b8000 0x1000>; + status = "reserved"; /* Controlled by PSCI firmware */ + }; + + cpu3_saw: power-manager@b0b9000 { + compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2"; + reg = <0x0b0b9000 0x1000>; + status = "reserved"; /* Controlled by PSCI firmware */ + }; }; thermal-zones { From patchwork Mon Oct 4 20:49:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephan Gerhold X-Patchwork-Id: 12534847 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4224EC433F5 for ; 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This is meant for devices with signed firmware that does not support PSCI and only allows booting ARM32 kernels. Signed-off-by: Stephan Gerhold --- Changes in v2: Clarify commit message very slightly --- arch/arm/boot/dts/qcom-msm8916-smp.dtsi | 62 +++++++++++++++++++++++++ 1 file changed, 62 insertions(+) create mode 100644 arch/arm/boot/dts/qcom-msm8916-smp.dtsi diff --git a/arch/arm/boot/dts/qcom-msm8916-smp.dtsi b/arch/arm/boot/dts/qcom-msm8916-smp.dtsi new file mode 100644 index 000000000000..36328dbe4212 --- /dev/null +++ b/arch/arm/boot/dts/qcom-msm8916-smp.dtsi @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/ { + cpus { + cpu@0 { + enable-method = "qcom,msm8916-smp"; + }; + cpu@1 { + enable-method = "qcom,msm8916-smp"; + }; + cpu@2 { + enable-method = "qcom,msm8916-smp"; + }; + cpu@3 { + enable-method = "qcom,msm8916-smp"; + }; + + idle-states { + /delete-property/ entry-method; + }; + }; + + psci { + status = "disabled"; + }; +}; + +&CPU_SLEEP_0 { + compatible = "qcom,idle-state-spc"; +}; + +&cpu0_acc { + status = "okay"; +}; + +&cpu0_saw { + status = "okay"; +}; + +&cpu1_acc { + status = "okay"; +}; + +&cpu1_saw { + status = "okay"; +}; + +&cpu2_acc { + status = "okay"; +}; + +&cpu2_saw { + status = "okay"; +}; + +&cpu3_acc { + status = "okay"; +}; + +&cpu3_saw { + status = "okay"; +}; From patchwork Mon Oct 4 20:49:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephan Gerhold X-Patchwork-Id: 12534849 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 52504C433F5 for ; Mon, 4 Oct 2021 20:55:08 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 20BC061360 for ; Mon, 4 Oct 2021 20:55:08 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 20BC061360 Authentication-Results: mail.kernel.org; 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Mon, 4 Oct 2021 22:51:22 +0200 (CEST) From: Stephan Gerhold To: Bjorn Andersson Cc: Andy Gross , linux-arm-msm@vger.kernel.org, Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, Stephan Gerhold Subject: [PATCH v2 15/15] ARM: dts: qcom: msm8916-samsung-serranove: Include dts from arm64 Date: Mon, 4 Oct 2021 22:49:55 +0200 Message-Id: <20211004204955.21077-15-stephan@gerhold.net> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211004201921.18526-1-stephan@gerhold.net> References: <20211004201921.18526-1-stephan@gerhold.net> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211004_135126_336441_482B0B0A X-CRM114-Status: GOOD ( 17.12 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org After adding all necessary support for MSM8916 SMP/cpuidle without PSCI on ARM32, build the Samsung Galaxy S4 Mini VE device tree from the arm64 tree together with the ARM32 include to allow booting this device on ARM32. The approach to include device tree files from other architectures is inspired from e.g. the Raspberry Pi (bcm2711-rpi-4-b.dts) where this is used to build the device tree for both ARM32 and ARM64. Signed-off-by: Stephan Gerhold --- Changes in v2: None. I'm not sure what's the best way to apply this patch... It might be easiest to apply the two ARM32 dts patches to the arm64 branch. (It does not seem to cause any conflicts at the moment...) --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/qcom-msm8916-samsung-serranove.dts | 3 +++ 2 files changed, 4 insertions(+) create mode 100644 arch/arm/boot/dts/qcom-msm8916-samsung-serranove.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 8cb859728bd9..0a53bbd9d7b1 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -960,6 +960,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \ qcom-ipq8064-rb3011.dtb \ qcom-msm8226-samsung-s3ve3g.dtb \ qcom-msm8660-surf.dtb \ + qcom-msm8916-samsung-serranove.dtb \ qcom-msm8960-cdp.dtb \ qcom-msm8974-fairphone-fp2.dtb \ qcom-msm8974-lge-nexus5-hammerhead.dtb \ diff --git a/arch/arm/boot/dts/qcom-msm8916-samsung-serranove.dts b/arch/arm/boot/dts/qcom-msm8916-samsung-serranove.dts new file mode 100644 index 000000000000..dee2c20af355 --- /dev/null +++ b/arch/arm/boot/dts/qcom-msm8916-samsung-serranove.dts @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include "arm64/qcom/msm8916-samsung-serranove.dts" +#include "qcom-msm8916-smp.dtsi"