From patchwork Wed Oct 6 02:47:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xuesong Chen X-Patchwork-Id: 12538411 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A9C06C433F5 for ; Wed, 6 Oct 2021 02:48:45 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6DBC3611CA for ; Wed, 6 Oct 2021 02:48:45 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 6DBC3611CA Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Reply-To:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID: Subject:Cc:To:From:Date:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To: References:List-Owner; bh=StRg3m933eKYEXptxZiViFg2Sy3p6woXRxh5V8TiGkM=; b=fYO G2soAu/jFWvSuW1Ay/jxPJmLSEMQ/fWd/fr5ZMRb70l9sOGTGzxIXapeztYEQXUuyES+NQICKpmR0 kQ0HNZq0sQaK6zAd721kSnXLZoxhrbbOVkWN1hyI0rYxCD9thRoSgQ6ngjOMd2JaysONhOAnfRhri 9pMi3z/BSQEk9pP+gYQiY88wyD0wlblMm2Subciqw/IfbXc8OU+qdUM6yim6ZEkLMbPYqPbBhl/B0 27aNfdrZ5hsT1cI0Arxz5tJye/+Y+08xE3jia6hwqpslOEjmsTw1HkT8GqaNION1dt8GfMgYWbwif 7/dA0wkwqaGNBUUbfI5YziP67lAtZ5Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mXwxa-00CbfI-G2; Wed, 06 Oct 2021 02:47:10 +0000 Received: from out30-45.freemail.mail.aliyun.com ([115.124.30.45]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mXwxW-00Cbe9-9G for linux-arm-kernel@lists.infradead.org; Wed, 06 Oct 2021 02:47:08 +0000 X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R131e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=e01e04426; MF=xuesong.chen@linux.alibaba.com; NM=1; PH=DS; RN=16; SR=0; TI=SMTPD_---0UqhcYh2_1633488420; Received: from localhost(mailfrom:xuesong.chen@linux.alibaba.com fp:SMTPD_---0UqhcYh2_1633488420) by smtp.aliyun-inc.com(127.0.0.1); Wed, 06 Oct 2021 10:47:01 +0800 Date: Wed, 6 Oct 2021 10:47:00 +0800 From: Xuesong Chen To: catalin.marinas@arm.com, lorenzo.pieralisi@arm.com, james.morse@arm.com, will@kernel.org, rafael@kernel.org, tony.luck@intel.com, bp@alien8.de, mingo@redhat.com, bhelgaas@google.com Cc: steve.capper@arm.com, mark.rutland@arm.com, linux-pci@vger.kernel.org, linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, xuesong.chen@linux.alibaba.com Subject: [PATCH 1/2] PCI: MCFG: Consolidate the separate PCI MCFG table entry list Message-ID: MIME-Version: 1.0 Content-Disposition: inline X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211005_194706_524988_4232B43A X-CRM114-Status: GOOD ( 18.07 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: Xuesong Chen Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The PCI MCFG entry list is discrete on x86 and other architectures like arm64 in current implementation, this list variable can be consolidated for unnecessary duplication and other purposes, for example, we can remove some of the 'arch' specific codes in the APEI/EINJ module and re-implement it in a more common arch-agnostic way. Signed-off-by: Xuesong Chen --- arch/x86/include/asm/pci_x86.h | 17 +---------------- arch/x86/pci/mmconfig-shared.c | 2 -- drivers/acpi/pci_mcfg.c | 34 +++++++++++++--------------------- drivers/pci/pci.c | 2 ++ include/linux/pci.h | 17 +++++++++++++++++ 5 files changed, 33 insertions(+), 39 deletions(-) diff --git a/arch/x86/include/asm/pci_x86.h b/arch/x86/include/asm/pci_x86.h index 490411d..1f4257c 100644 --- a/arch/x86/include/asm/pci_x86.h +++ b/arch/x86/include/asm/pci_x86.h @@ -146,20 +146,7 @@ static inline int __init pci_acpi_init(void) extern void pcibios_fixup_irqs(void); /* pci-mmconfig.c */ - -/* "PCI MMCONFIG %04x [bus %02x-%02x]" */ -#define PCI_MMCFG_RESOURCE_NAME_LEN (22 + 4 + 2 + 2) - -struct pci_mmcfg_region { - struct list_head list; - struct resource res; - u64 address; - char __iomem *virt; - u16 segment; - u8 start_bus; - u8 end_bus; - char name[PCI_MMCFG_RESOURCE_NAME_LEN]; -}; +struct pci_mmcfg_region; extern int __init pci_mmcfg_arch_init(void); extern void __init pci_mmcfg_arch_free(void); @@ -174,8 +161,6 @@ extern struct pci_mmcfg_region *__init pci_mmconfig_add(int segment, int start, extern struct list_head pci_mmcfg_list; -#define PCI_MMCFG_BUS_OFFSET(bus) ((bus) << 20) - /* * On AMD Fam10h CPUs, all PCI MMIO configuration space accesses must use * %eax. No other source or target registers may be used. The following diff --git a/arch/x86/pci/mmconfig-shared.c b/arch/x86/pci/mmconfig-shared.c index 758cbfe..0b961fe6 100644 --- a/arch/x86/pci/mmconfig-shared.c +++ b/arch/x86/pci/mmconfig-shared.c @@ -31,8 +31,6 @@ static DEFINE_MUTEX(pci_mmcfg_lock); #define pci_mmcfg_lock_held() lock_is_held(&(pci_mmcfg_lock).dep_map) -LIST_HEAD(pci_mmcfg_list); - static void __init pci_mmconfig_remove(struct pci_mmcfg_region *cfg) { if (cfg->res.parent) diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c index 53cab97..d9506b0 100644 --- a/drivers/acpi/pci_mcfg.c +++ b/drivers/acpi/pci_mcfg.c @@ -13,14 +13,7 @@ #include #include -/* Structure to hold entries from the MCFG table */ -struct mcfg_entry { - struct list_head list; - phys_addr_t addr; - u16 segment; - u8 bus_start; - u8 bus_end; -}; +extern struct list_head pci_mmcfg_list; #ifdef CONFIG_PCI_QUIRKS struct mcfg_fixup { @@ -214,16 +207,13 @@ static void pci_mcfg_apply_quirks(struct acpi_pci_root *root, #endif } -/* List to save MCFG entries */ -static LIST_HEAD(pci_mcfg_list); - int pci_mcfg_lookup(struct acpi_pci_root *root, struct resource *cfgres, const struct pci_ecam_ops **ecam_ops) { const struct pci_ecam_ops *ops = &pci_generic_ecam_ops; struct resource *bus_res = &root->secondary; u16 seg = root->segment; - struct mcfg_entry *e; + struct pci_mmcfg_region *e; struct resource res; /* Use address from _CBA if present, otherwise lookup MCFG */ @@ -233,10 +223,10 @@ int pci_mcfg_lookup(struct acpi_pci_root *root, struct resource *cfgres, /* * We expect the range in bus_res in the coverage of MCFG bus range. */ - list_for_each_entry(e, &pci_mcfg_list, list) { - if (e->segment == seg && e->bus_start <= bus_res->start && - e->bus_end >= bus_res->end) { - root->mcfg_addr = e->addr; + list_for_each_entry(e, &pci_mmcfg_list, list) { + if (e->segment == seg && e->start_bus <= bus_res->start && + e->end_bus >= bus_res->end) { + root->mcfg_addr = e->address; } } @@ -268,7 +258,7 @@ static __init int pci_mcfg_parse(struct acpi_table_header *header) { struct acpi_table_mcfg *mcfg; struct acpi_mcfg_allocation *mptr; - struct mcfg_entry *e, *arr; + struct pci_mmcfg_region *e, *arr; int i, n; if (header->length < sizeof(struct acpi_table_mcfg)) @@ -285,10 +275,12 @@ static __init int pci_mcfg_parse(struct acpi_table_header *header) for (i = 0, e = arr; i < n; i++, mptr++, e++) { e->segment = mptr->pci_segment; - e->addr = mptr->address; - e->bus_start = mptr->start_bus_number; - e->bus_end = mptr->end_bus_number; - list_add(&e->list, &pci_mcfg_list); + e->address = mptr->address; + e->start_bus = mptr->start_bus_number; + e->end_bus = mptr->end_bus_number; + e->res.start = e->address + PCI_MMCFG_BUS_OFFSET(e->start_bus); + e->res.end = e->address + PCI_MMCFG_BUS_OFFSET(e->end_bus + 1) - 1; + list_add(&e->list, &pci_mmcfg_list); } #ifdef CONFIG_PCI_QUIRKS diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index ce2ab62..899004e 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -47,6 +47,8 @@ int pci_pci_problems; EXPORT_SYMBOL(pci_pci_problems); +LIST_HEAD(pci_mmcfg_list); + unsigned int pci_pm_d3hot_delay; static void pci_pme_list_scan(struct work_struct *work); diff --git a/include/linux/pci.h b/include/linux/pci.h index cd8aa6f..71e4c06 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -55,6 +55,23 @@ #define PCI_RESET_PROBE true #define PCI_RESET_DO_RESET false +#define PCI_MMCFG_BUS_OFFSET(bus) ((bus) << 20) + +/* "PCI MMCONFIG %04x [bus %02x-%02x]" */ +#define PCI_MMCFG_RESOURCE_NAME_LEN (22 + 4 + 2 + 2) + +/* pci mcfg region */ +struct pci_mmcfg_region { + struct list_head list; + struct resource res; + u64 address; + char __iomem *virt; + u16 segment; + u8 start_bus; + u8 end_bus; + char name[PCI_MMCFG_RESOURCE_NAME_LEN]; +}; + /* * The PCI interface treats multi-function devices as independent * devices. The slot/function address of each device is encoded From patchwork Wed Oct 6 02:47:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xuesong Chen X-Patchwork-Id: 12538413 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 55E6AC433EF for ; Wed, 6 Oct 2021 02:49:45 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1A17061175 for ; Wed, 6 Oct 2021 02:49:45 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 1A17061175 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Reply-To:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID: Subject:Cc:To:From:Date:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To: References:List-Owner; bh=2HGnrl30lqAAxcnxQsuu28b7xbMZ7qmw/V+ZmhxF8MQ=; b=Z4u CtJ6UB5+rdLGtHWtlJ9Ov8tdVZ8fo3zOcJxFsqrJhiUnRMgWhHJp5LpcVlLbl05FndWWtf7mTmxhy +Ux4P7v5Yf8hrcWeOdlEItvOQKDDgWQZn+Gxud9fa8tbMutmW9jH734FP1vlHccLd0wRY839ZducD vwNrjhRyb/aOL0yDb8rDb1oUwbAWwR7WaJlBGnfbw/Nn7ng0/QA0oLHQPJy/t8eK3j/ijp7Bm6yow JnKGc+vZ/7K8FRxdMeS9uzexYj04wGiKUOKimYIXRECk9BPcTOyjmZd1nEMISnCnA9ft0aU51jGZO RNVVv1WYDv0E1tXBT2gkW6gxy5xfhWA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mXwyI-00Cbnx-PC; Wed, 06 Oct 2021 02:47:54 +0000 Received: from out30-130.freemail.mail.aliyun.com ([115.124.30.130]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mXwyE-00Cbmp-VP for linux-arm-kernel@lists.infradead.org; Wed, 06 Oct 2021 02:47:52 +0000 X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R531e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=e01e04407; MF=xuesong.chen@linux.alibaba.com; NM=1; PH=DS; RN=16; SR=0; TI=SMTPD_---0UqhYNe9_1633488467; Received: from localhost(mailfrom:xuesong.chen@linux.alibaba.com fp:SMTPD_---0UqhYNe9_1633488467) by smtp.aliyun-inc.com(127.0.0.1); Wed, 06 Oct 2021 10:47:48 +0800 Date: Wed, 6 Oct 2021 10:47:47 +0800 From: Xuesong Chen To: catalin.marinas@arm.com, lorenzo.pieralisi@arm.com, james.morse@arm.com, will@kernel.org, rafael@kernel.org, tony.luck@intel.com, bp@alien8.de, mingo@redhat.com, bhelgaas@google.com Cc: steve.capper@arm.com, mark.rutland@arm.com, linux-pci@vger.kernel.org, linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, xuesong.chen@linux.alibaba.com Subject: [PATCH 2/2] ACPI: APEI: Filter the PCI MCFG address with an arch-agnostic method Message-ID: MIME-Version: 1.0 Content-Disposition: inline X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211005_194751_206168_4E472685 X-CRM114-Status: GOOD ( 17.31 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: Xuesong Chen Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The commit d91525eb8ee6 ("ACPI, EINJ: Enhance error injection tolerance level") fixes the issue that the ACPI/APEI can not access the PCI MCFG address on x86 platform, but this issue can also happen on other architectures, for instance, we got below error message on arm64 platform: ... APEI: Can not request [mem 0x50100000-0x50100003] for APEI EINJ Trigger registers ... This patch will try to handle this case in a more common way instead of the original 'arch' specific solution, which will be beneficial to all the APEI-dependent platforms after that. Signed-off-by: Xuesong Chen --- arch/x86/pci/mmconfig-shared.c | 28 ---------------------------- drivers/acpi/apei/apei-base.c | 42 ++++++++++++++++++++++++++---------------- 2 files changed, 26 insertions(+), 44 deletions(-) diff --git a/arch/x86/pci/mmconfig-shared.c b/arch/x86/pci/mmconfig-shared.c index 0b961fe6..12f7d96 100644 --- a/arch/x86/pci/mmconfig-shared.c +++ b/arch/x86/pci/mmconfig-shared.c @@ -605,32 +605,6 @@ static int __init pci_parse_mcfg(struct acpi_table_header *header) return 0; } -#ifdef CONFIG_ACPI_APEI -extern int (*arch_apei_filter_addr)(int (*func)(__u64 start, __u64 size, - void *data), void *data); - -static int pci_mmcfg_for_each_region(int (*func)(__u64 start, __u64 size, - void *data), void *data) -{ - struct pci_mmcfg_region *cfg; - int rc; - - if (list_empty(&pci_mmcfg_list)) - return 0; - - list_for_each_entry(cfg, &pci_mmcfg_list, list) { - rc = func(cfg->res.start, resource_size(&cfg->res), data); - if (rc) - return rc; - } - - return 0; -} -#define set_apei_filter() (arch_apei_filter_addr = pci_mmcfg_for_each_region) -#else -#define set_apei_filter() -#endif - static void __init __pci_mmcfg_init(int early) { pci_mmcfg_reject_broken(early); @@ -665,8 +639,6 @@ void __init pci_mmcfg_early_init(void) else acpi_table_parse(ACPI_SIG_MCFG, pci_parse_mcfg); __pci_mmcfg_init(1); - - set_apei_filter(); } } diff --git a/drivers/acpi/apei/apei-base.c b/drivers/acpi/apei/apei-base.c index c7fdb12..fa65792 100644 --- a/drivers/acpi/apei/apei-base.c +++ b/drivers/acpi/apei/apei-base.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include @@ -34,6 +35,8 @@ #define APEI_PFX "APEI: " +extern struct list_head pci_mmcfg_list; + /* * APEI ERST (Error Record Serialization Table) and EINJ (Error * INJection) interpreter framework. @@ -448,12 +451,26 @@ static int apei_get_nvs_resources(struct apei_resources *resources) return acpi_nvs_for_each_region(apei_get_res_callback, resources); } -int (*arch_apei_filter_addr)(int (*func)(__u64 start, __u64 size, - void *data), void *data); -static int apei_get_arch_resources(struct apei_resources *resources) - +static int apei_filter_mcfg_addr(struct apei_resources *res, + struct apei_resources *mcfg_res) { - return arch_apei_filter_addr(apei_get_res_callback, resources); + int rc = 0; + struct pci_mmcfg_region *cfg; + + if (list_empty(&pci_mmcfg_list)) + return 0; + + apei_resources_init(mcfg_res); + list_for_each_entry(cfg, &pci_mmcfg_list, list) { + rc = apei_res_add(&mcfg_res->iomem, cfg->res.start, resource_size(&cfg->res)); + if (rc) + return rc; + } + + /* filter the mcfg resource from current APEI's */ + rc = apei_resources_sub(res, mcfg_res); + + return rc; } /* @@ -486,15 +503,9 @@ int apei_resources_request(struct apei_resources *resources, if (rc) goto nvs_res_fini; - if (arch_apei_filter_addr) { - apei_resources_init(&arch_res); - rc = apei_get_arch_resources(&arch_res); - if (rc) - goto arch_res_fini; - rc = apei_resources_sub(resources, &arch_res); - if (rc) - goto arch_res_fini; - } + rc = apei_filter_mcfg_addr(resources, &arch_res); + if (rc) + goto arch_res_fini; rc = -EINVAL; list_for_each_entry(res, &resources->iomem, list) { @@ -544,8 +555,7 @@ int apei_resources_request(struct apei_resources *resources, release_mem_region(res->start, res->end - res->start); } arch_res_fini: - if (arch_apei_filter_addr) - apei_resources_fini(&arch_res); + apei_resources_fini(&arch_res); nvs_res_fini: apei_resources_fini(&nvs_resources); return rc;