From patchwork Wed Oct 6 06:12:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 12538675 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5873CC433EF for ; Wed, 6 Oct 2021 06:12:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3BCBB61152 for ; Wed, 6 Oct 2021 06:12:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236115AbhJFGOC (ORCPT ); Wed, 6 Oct 2021 02:14:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35000 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235604AbhJFGOA (ORCPT ); Wed, 6 Oct 2021 02:14:00 -0400 Received: from mail-wr1-x436.google.com (mail-wr1-x436.google.com [IPv6:2a00:1450:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 16AFEC061749; Tue, 5 Oct 2021 23:12:09 -0700 (PDT) Received: by mail-wr1-x436.google.com with SMTP id u18so5249450wrg.5; Tue, 05 Oct 2021 23:12:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lMW4foefc6bEFLqLQ2H0asFN0IF8jIbnNoNDfv9QTpo=; b=e7WgKi5k+F0e4KVHalUl0lt6lYta3FL9Lkj0By+kc+nNmKihLUhm3SfM1xLx5Mu+1l pmpIU2EbRexP0Zqdig9TajTW6ADUosnNfNUn7jtko/sE0jSOW7CQAjioh62b953JLM3O RGxKtsSZzDp3ALgtv7+rUJICwcQ1Kw0khoWA6ggL6mdd6ONsbmq1hxh3+xUrQwqPNvhr GixcQLr9D3DxEhuTsUtzfl9Q/nSI9l2L0wj6A7F0ig2ZBaHJ9gnjIFt4fAGkIuWc4sKS pi1rg3Un8B5QyukJICIWtpFrYvP8i7WIjSpOwd6pkZQWV7F8/hDwDGen/znRoq/CvpLi Cyyw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lMW4foefc6bEFLqLQ2H0asFN0IF8jIbnNoNDfv9QTpo=; b=DX/+yQ1Z55VtOvun3aABPvCS5XKhclJfxhXwG1nN8M/XPk1h1DbmESExV1sMvemehG XTP3uuS33ylN6DAdZGJhUPb9ZclZ/a0+TB7y938rIF/IvJjF2Bksc9Hcep7LSL05unVD GdN0m2a+IMG7I/WsiigDp2pMBg1DcKIaWe2Zs75o+DSWKBl0PRobOCdtnl11XA9QV4Qu AWtaF47qWR1H9T8/Z9taV8TRZ5iYIRnJXFtQDFFc880Da/nA18QJl/jYHTq2Xn0lKYs+ wNvksROgrq3Yx70UOudcZhZsrbtQZSn0vSwe5PICGzXSb4ITkqJGDaudZsI9NBSGdiRY AgKQ== X-Gm-Message-State: AOAM531EQScuVjJjk3TMVUjkW4eqx+Ir784ZVjY3xpXjZV14MmTYOdaW 0gB61Zwu8ofDP0kPqkQa3GI= X-Google-Smtp-Source: ABdhPJzWFOAKHtnF6xn6CskP/tAMoCqT71fSDgdsfiv31c5iXRR6qJf29QeN5a8UFgqEsQWkRwWT0Q== X-Received: by 2002:a05:600c:3b22:: with SMTP id m34mr7622500wms.130.1633500727710; Tue, 05 Oct 2021 23:12:07 -0700 (PDT) Received: from localhost.localdomain (252.red-83-54-181.dynamicip.rima-tde.net. [83.54.181.252]) by smtp.gmail.com with ESMTPSA id e8sm3893071wme.46.2021.10.05.23.12.06 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 05 Oct 2021 23:12:07 -0700 (PDT) From: Sergio Paracuellos To: sboyd@kernel.org Cc: linux-clk@vger.kernel.org, gregkh@linuxfoundation.org, devicetree@vger.kernel.org, robh+dt@kernel.org, linux-staging@lists.linux.dev, neil@brown.name, linux-kernel@vger.kernel.org, john@phrozen.org Subject: [PATCH 1/4] dt-bindings: reset: add dt binding header for Mediatek MT7621 resets Date: Wed, 6 Oct 2021 08:12:01 +0200 Message-Id: <20211006061204.2854-2-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211006061204.2854-1-sergio.paracuellos@gmail.com> References: <20211006061204.2854-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add dt binding header for resets lines in Mediatek MT7621 SoCs. Signed-off-by: Sergio Paracuellos --- include/dt-bindings/reset/mt7621-reset.h | 37 ++++++++++++++++++++++++ 1 file changed, 37 insertions(+) create mode 100644 include/dt-bindings/reset/mt7621-reset.h diff --git a/include/dt-bindings/reset/mt7621-reset.h b/include/dt-bindings/reset/mt7621-reset.h new file mode 100644 index 000000000000..7572c6b41453 --- /dev/null +++ b/include/dt-bindings/reset/mt7621-reset.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2021 Sergio Paracuellos + * Author: Sergio Paracuellos + */ + +#ifndef DT_BINDING_MT7621_RESET_H +#define DT_BINDING_MT7621_RESET_H + +#define MT7621_RST_SYS 0 +#define MT7621_RST_MCM 2 +#define MT7621_RST_HSDMA 5 +#define MT7621_RST_FE 6 +#define MT7621_RST_SPDIFTX 7 +#define MT7621_RST_TIMER 8 +#define MT7621_RST_INT 9 +#define MT7621_RST_MC 10 +#define MT7621_RST_PCM 11 +#define MT7621_RST_PIO 13 +#define MT7621_RST_GDMA 14 +#define MT7621_RST_NFI 15 +#define MT7621_RST_I2C 16 +#define MT7621_RST_I2S 17 +#define MT7621_RST_SPI 18 +#define MT7621_RST_UART1 19 +#define MT7621_RST_UART2 20 +#define MT7621_RST_UART3 21 +#define MT7621_RST_ETH 23 +#define MT7621_RST_PCIE0 24 +#define MT7621_RST_PCIE1 25 +#define MT7621_RST_PCIE2 26 +#define MT7621_RST_AUX_STCK 28 +#define MT7621_RST_CRYPTO 29 +#define MT7621_RST_SDXC 30 +#define MT7621_RST_PPE 31 + +#endif /* DT_BINDING_MT7621_RESET_H */ From patchwork Wed Oct 6 06:12:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 12538677 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 14D58C4332F for ; Wed, 6 Oct 2021 06:12:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 007FC610C8 for ; Wed, 6 Oct 2021 06:12:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235604AbhJFGOG (ORCPT ); Wed, 6 Oct 2021 02:14:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35016 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236878AbhJFGOC (ORCPT ); Wed, 6 Oct 2021 02:14:02 -0400 Received: from mail-wr1-x430.google.com (mail-wr1-x430.google.com [IPv6:2a00:1450:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3AD91C061755; Tue, 5 Oct 2021 23:12:11 -0700 (PDT) Received: by mail-wr1-x430.google.com with SMTP id j8so5207077wro.7; Tue, 05 Oct 2021 23:12:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nNzJU9Y0TN+qNE5qJcuFSRHdr3qJUmf5dCSvTeevenI=; b=ANdB3oFZnXCafq+MQbhJNlRkccq1wVIELxjMlYiX2ZU+wsa/0SDckhCa28iFKISyDO b6aK+IxalKhIZnCeMIXYON9LbmPpSicfaD1i7rO4z0UeF0HqHM/JG+OMWvhmlrwVhhZI ZY4mU+sMEOPIA4aaQHMbMs14KiVZOPwi/AhM/nhveMT4kgIF9sBaiPtsg0cNTsPFcdqq IVvTxtQBCHxqpqBB0wn1C/LS2/2lOM4kVeDgWha6fPcDOF0mWcxwqL2wmp5zv//GsDmS hzgqimSCw5tSa+vC2Gt2KPZI9CjQqHX6aqgxEa42KBlDvTOtyfjlb7ubzM25TjGd+SPQ zCLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nNzJU9Y0TN+qNE5qJcuFSRHdr3qJUmf5dCSvTeevenI=; b=eihGqcalGlXNOmHiP4stBf9JcnAnJTb0dhFRUdrt1XBDj3+23sucSTud8g9LIsox0S zRO5jKvp/A9wokm0XHTsMvnEb5E+SfPj85mYTaDRp/U91W71uWNR0qacjJi+VhVaLIJY ZGC94DlZY3kTccuM7+/hNM1CUVOf5ET1FZm5uO+50Daq2tu72T1pvTT8Zdxmqo5DFQyb M0wZYzRYhQg75AGO5tqMmiMj6Vzj34Pm2ZTRDTOWrsHvIp/FVmL6Hp+jKJ2lsVAxClUE 2HtXhVRxR48cjaYo/AXMHRpRvyVxoA2ejjosupszbj7qdALiVhiUuqTRBTb85RR+c1a/ UEjQ== X-Gm-Message-State: AOAM532hhkMhp58ptGowDyXdmffEgITCVitR0SgQZ0jZtsUqYRPoeLd3 2jK1itLXFsB96L7dCHBzv9w= X-Google-Smtp-Source: ABdhPJzvpHh7Kg9/PSeVa1E2N4RIAT/2jC9jWEdRpAWXy/1jh8Pzr4PTphK0flBGavRG4TUxUC4XXQ== X-Received: by 2002:a7b:cc18:: with SMTP id f24mr7914179wmh.8.1633500728703; Tue, 05 Oct 2021 23:12:08 -0700 (PDT) Received: from localhost.localdomain (252.red-83-54-181.dynamicip.rima-tde.net. [83.54.181.252]) by smtp.gmail.com with ESMTPSA id e8sm3893071wme.46.2021.10.05.23.12.07 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 05 Oct 2021 23:12:08 -0700 (PDT) From: Sergio Paracuellos To: sboyd@kernel.org Cc: linux-clk@vger.kernel.org, gregkh@linuxfoundation.org, devicetree@vger.kernel.org, robh+dt@kernel.org, linux-staging@lists.linux.dev, neil@brown.name, linux-kernel@vger.kernel.org, john@phrozen.org Subject: [PATCH 2/4] dt-bindings: clock: mediatek,mt7621-sysc: add '#reset-cells' property Date: Wed, 6 Oct 2021 08:12:02 +0200 Message-Id: <20211006061204.2854-3-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211006061204.2854-1-sergio.paracuellos@gmail.com> References: <20211006061204.2854-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Make system controller a reset provider for all the peripherals in the MT7621 SoC adding '#reset-cells' property. Signed-off-by: Sergio Paracuellos --- .../bindings/clock/mediatek,mt7621-sysc.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml index 915f84efd763..0c0b0ae5e2ac 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml @@ -22,6 +22,11 @@ description: | The clocks are provided inside a system controller node. + This node is also a reset provider for all the peripherals. + + Reset related bits are defined in: + [2]: . + properties: compatible: items: @@ -37,6 +42,12 @@ properties: clocks. const: 1 + "#reset-cells": + description: + The first cell indicates the reset bit within the register, see + [2] for available resets. + const: 1 + ralink,memctl: $ref: /schemas/types.yaml#/definitions/phandle description: @@ -61,6 +72,7 @@ examples: compatible = "mediatek,mt7621-sysc", "syscon"; reg = <0x0 0x100>; #clock-cells = <1>; + #reset-cells = <1>; ralink,memctl = <&memc>; clock-output-names = "xtal", "cpu", "bus", "50m", "125m", "150m", From patchwork Wed Oct 6 06:12:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 12538679 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1D87BC43217 for ; Wed, 6 Oct 2021 06:12:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0E18E6115A for ; Wed, 6 Oct 2021 06:12:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237320AbhJFGOI (ORCPT ); Wed, 6 Oct 2021 02:14:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35018 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236829AbhJFGOD (ORCPT ); Wed, 6 Oct 2021 02:14:03 -0400 Received: from mail-wr1-x431.google.com (mail-wr1-x431.google.com [IPv6:2a00:1450:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3FB6CC061760; Tue, 5 Oct 2021 23:12:11 -0700 (PDT) Received: by mail-wr1-x431.google.com with SMTP id r10so5180011wra.12; Tue, 05 Oct 2021 23:12:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1KLm/UJPYCVCyNtfvETKNp1rfk93uLu7qVrvjdeZZXs=; b=X44T/lPel1S7KxSPvTnlWaNvJ1OgLA3w4idDroLy+/CMHRs8b8FxJtJ0jERLqJcAEB 7ftKiKQbvLk+/sAceBf8Q933r3fyGtZniOphBQlEkotEGAlvZfJZa0SkmSBfvCPZwrrc A464CHjo3CZLaTPU+ElLSk2W/h6N+s6VKyhVno0NKbH6Odp8CSoOEH2dwEG8QvfED8ih oQWfnW8gI76UUUUn8auaU8+gG6TFec0VGIHI0rx9tY3v5olK0WETJO831d8w/XauNN2M y60TRqWgV3JzpIG08gYixAKu2LEozbmeakBGr/MC6Qjf3pClzLGCCTmY/zfQaG+AFXTc LAtA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1KLm/UJPYCVCyNtfvETKNp1rfk93uLu7qVrvjdeZZXs=; b=g7WgFBo6TCoz4AfQbi2vX5FeJoFJ0PLxuJx/IDHYWux75qNC5SuDU8FHReNlq37Zwn pymTcPSV0rNzyyM96v6ZKs6b57G5Il1rBQU2v07k4OSYm3wxfj8k49n8X0sCNoK8gvqm vaz6hY92K8SfLReGpiHsdJE2FZsmVlBuZNWKhQAXY9Rd4kaT+K4WrX8H+qniJWsdw4k1 07jBCHzCzC5o+A2Pbx+/ezSvRt3EUVqjgf6TdSsjfg8Ygc2jR8R7XpgEwMU+JHOmEbx2 8jS8DDETtcYeCxejgXhhds6TfgPKWEL47g7bWPg2NiDYMZmc2DshiscLrr06pmx13+Gp xSfQ== X-Gm-Message-State: AOAM53284VCKMFXMRSePSAvOCJlqul/5Qk33RRXmmDjJMA6yW4tmZLX3 nvEG3xh7O9Nax/C5U8YXJ/U= X-Google-Smtp-Source: ABdhPJwNea3SPVzx29nCKNcRJnbkZu9QqMxzoIhht6EivaDF2CPB6tfCaL2DTlVZ5t5FLqWhWEgWaw== X-Received: by 2002:adf:e985:: with SMTP id h5mr672621wrm.367.1633500729609; Tue, 05 Oct 2021 23:12:09 -0700 (PDT) Received: from localhost.localdomain (252.red-83-54-181.dynamicip.rima-tde.net. [83.54.181.252]) by smtp.gmail.com with ESMTPSA id e8sm3893071wme.46.2021.10.05.23.12.08 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 05 Oct 2021 23:12:09 -0700 (PDT) From: Sergio Paracuellos To: sboyd@kernel.org Cc: linux-clk@vger.kernel.org, gregkh@linuxfoundation.org, devicetree@vger.kernel.org, robh+dt@kernel.org, linux-staging@lists.linux.dev, neil@brown.name, linux-kernel@vger.kernel.org, john@phrozen.org Subject: [PATCH 3/4] clk: ralink: make system controller node a reset provider Date: Wed, 6 Oct 2021 08:12:03 +0200 Message-Id: <20211006061204.2854-4-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211006061204.2854-1-sergio.paracuellos@gmail.com> References: <20211006061204.2854-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org MT7621 system controller node is already providing the clocks for the whole system but must also serve as a reset provider. Hence, add reset controller related code to the clock driver itself. Signed-off-by: Sergio Paracuellos --- drivers/clk/ralink/clk-mt7621.c | 79 +++++++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/drivers/clk/ralink/clk-mt7621.c b/drivers/clk/ralink/clk-mt7621.c index a2c045390f00..67ccc9582c46 100644 --- a/drivers/clk/ralink/clk-mt7621.c +++ b/drivers/clk/ralink/clk-mt7621.c @@ -11,14 +11,17 @@ #include #include #include +#include #include #include +#include /* Configuration registers */ #define SYSC_REG_SYSTEM_CONFIG0 0x10 #define SYSC_REG_SYSTEM_CONFIG1 0x14 #define SYSC_REG_CLKCFG0 0x2c #define SYSC_REG_CLKCFG1 0x30 +#define SYSC_REG_RESET_CTRL 0x34 #define SYSC_REG_CUR_CLK_STS 0x44 #define MEMC_REG_CPU_PLL 0x648 @@ -398,6 +401,76 @@ static void __init mt7621_clk_init(struct device_node *node) } CLK_OF_DECLARE_DRIVER(mt7621_clk, "mediatek,mt7621-sysc", mt7621_clk_init); +struct mt7621_rst { + struct reset_controller_dev rcdev; + struct regmap *sysc; +}; + +static inline struct mt7621_rst *to_mt7621_rst(struct reset_controller_dev *dev) +{ + return container_of(dev, struct mt7621_rst, rcdev); +} + +static int mt7621_assert_device(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct mt7621_rst *data = to_mt7621_rst(rcdev); + struct regmap *sysc = data->sysc; + + if (id == MT7621_RST_SYS) + return -1; + + return regmap_update_bits(sysc, SYSC_REG_RESET_CTRL, BIT(id), BIT(id)); +} + +static int mt7621_deassert_device(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct mt7621_rst *data = to_mt7621_rst(rcdev); + struct regmap *sysc = data->sysc; + + if (id == MT7621_RST_SYS) + return -1; + + return regmap_update_bits(sysc, SYSC_REG_RESET_CTRL, BIT(id), 0); +} + +static int mt7621_reset_device(struct reset_controller_dev *rcdev, + unsigned long id) +{ + int ret; + + ret = mt7621_assert_device(rcdev, id); + if (ret < 0) + return ret; + + return mt7621_deassert_device(rcdev, id); +} + +static const struct reset_control_ops reset_ops = { + .reset = mt7621_reset_device, + .assert = mt7621_assert_device, + .deassert = mt7621_deassert_device +}; + +static int mt7621_reset_init(struct device *dev, struct regmap *sysc) +{ + struct mt7621_rst *rst_data; + + rst_data = kzalloc(sizeof(*rst_data), GFP_KERNEL); + if (!rst_data) + return -ENOMEM; + + rst_data->sysc = sysc; + rst_data->rcdev.ops = &reset_ops; + rst_data->rcdev.owner = THIS_MODULE; + rst_data->rcdev.nr_resets = 32; + rst_data->rcdev.of_reset_n_cells = 1; + rst_data->rcdev.of_node = dev_of_node(dev); + + return devm_reset_controller_register(dev, &rst_data->rcdev); +} + static int mt7621_clk_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; @@ -424,6 +497,12 @@ static int mt7621_clk_probe(struct platform_device *pdev) return ret; } + ret = mt7621_reset_init(dev, priv->sysc); + if (ret) { + pr_err("Could not init reset controller\n"); + return ret; + } + count = ARRAY_SIZE(mt7621_clks_base) + ARRAY_SIZE(mt7621_fixed_clks) + ARRAY_SIZE(mt7621_gates); clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, count), From patchwork Wed Oct 6 06:12:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 12538681 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 400CFC43219 for ; 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[83.54.181.252]) by smtp.gmail.com with ESMTPSA id e8sm3893071wme.46.2021.10.05.23.12.09 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 05 Oct 2021 23:12:10 -0700 (PDT) From: Sergio Paracuellos To: sboyd@kernel.org Cc: linux-clk@vger.kernel.org, gregkh@linuxfoundation.org, devicetree@vger.kernel.org, robh+dt@kernel.org, linux-staging@lists.linux.dev, neil@brown.name, linux-kernel@vger.kernel.org, john@phrozen.org Subject: [PATCH 4/4] staging: mt7621-dts: align resets with binding documentation Date: Wed, 6 Oct 2021 08:12:04 +0200 Message-Id: <20211006061204.2854-5-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211006061204.2854-1-sergio.paracuellos@gmail.com> References: <20211006061204.2854-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Binding documentation for compatible 'mediatek,mt7621-sysc' has been updated to be used as a reset provider. Align reset related bits and system controller node with binding documentation along the dtsi file. Signed-off-by: Sergio Paracuellos --- drivers/staging/mt7621-dts/mt7621.dtsi | 27 ++++++++++++-------------- 1 file changed, 12 insertions(+), 15 deletions(-) diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi b/drivers/staging/mt7621-dts/mt7621.dtsi index 719ef28171f4..72b99d8b4647 100644 --- a/drivers/staging/mt7621-dts/mt7621.dtsi +++ b/drivers/staging/mt7621-dts/mt7621.dtsi @@ -1,6 +1,7 @@ #include #include #include +#include / { #address-cells = <1>; @@ -59,6 +60,7 @@ sysc: syscon@0 { compatible = "mediatek,mt7621-sysc", "syscon"; reg = <0x0 0x100>; #clock-cells = <1>; + #reset-cells = <1>; ralink,memctl = <&memc>; clock-output-names = "xtal", "cpu", "bus", "50m", "125m", "150m", @@ -88,7 +90,7 @@ i2c: i2c@900 { clocks = <&sysc MT7621_CLK_I2C>; clock-names = "i2c"; - resets = <&rstctrl 16>; + resets = <&sysc MT7621_RST_I2C>; reset-names = "i2c"; #address-cells = <1>; @@ -106,7 +108,7 @@ i2s: i2s@a00 { clocks = <&sysc MT7621_CLK_I2S>; clock-names = "i2s"; - resets = <&rstctrl 17>; + resets = <&sysc MT7621_RST_I2S>; reset-names = "i2s"; interrupt-parent = <&gic>; @@ -151,7 +153,7 @@ spi0: spi@b00 { clocks = <&sysc MT7621_CLK_SPI>; clock-names = "spi"; - resets = <&rstctrl 18>; + resets = <&sysc MT7621_RST_SPI>; reset-names = "spi"; #address-cells = <1>; @@ -167,7 +169,7 @@ gdma: gdma@2800 { clocks = <&sysc MT7621_CLK_GDMA>; clock-names = "gdma"; - resets = <&rstctrl 14>; + resets = <&sysc MT7621_RST_GDMA>; reset-names = "dma"; interrupt-parent = <&gic>; @@ -186,7 +188,7 @@ hsdma: hsdma@7000 { clocks = <&sysc MT7621_CLK_HSDMA>; clock-names = "hsdma"; - resets = <&rstctrl 5>; + resets = <&sysc MT7621_RST_HSDMA>; reset-names = "hsdma"; interrupt-parent = <&gic>; @@ -286,11 +288,6 @@ pinmux { }; }; - rstctrl: rstctrl { - compatible = "ralink,rt2880-reset"; - #reset-cells = <1>; - }; - sdhci: sdhci@1E130000 { status = "disabled"; @@ -383,7 +380,7 @@ ethernet: ethernet@1e100000 { #address-cells = <1>; #size-cells = <0>; - resets = <&rstctrl 6 &rstctrl 23>; + resets = <&sysc MT7621_CLK_FE &sysc MT7621_CLK_ETH>; reset-names = "fe", "eth"; interrupt-parent = <&gic>; @@ -428,7 +425,7 @@ switch0: switch0@0 { #size-cells = <0>; reg = <0>; mediatek,mcm; - resets = <&rstctrl 2>; + resets = <&sysc MT7621_RST_MCM>; reset-names = "mcm"; interrupt-controller; #interrupt-cells = <1>; @@ -514,7 +511,7 @@ pcie@0,0 { #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>; - resets = <&rstctrl 24>; + resets = <&sysc MT7621_RST_PCIE0>; clocks = <&sysc MT7621_CLK_PCIE0>; phys = <&pcie0_phy 1>; phy-names = "pcie-phy0"; @@ -529,7 +526,7 @@ pcie@1,0 { #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>; - resets = <&rstctrl 25>; + resets = <&sysc MT7621_RST_PCIE1>; clocks = <&sysc MT7621_CLK_PCIE1>; phys = <&pcie0_phy 1>; phy-names = "pcie-phy1"; @@ -544,7 +541,7 @@ pcie@2,0 { #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>; - resets = <&rstctrl 26>; + resets = <&sysc MT7621_RST_PCIE2>; clocks = <&sysc MT7621_CLK_PCIE2>; phys = <&pcie2_phy 0>; phy-names = "pcie-phy2";