From patchwork Wed Oct 6 11:23:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 12539223 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F7DBC433EF for ; Wed, 6 Oct 2021 11:23:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EE36661166 for ; Wed, 6 Oct 2021 11:23:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238409AbhJFLZM (ORCPT ); Wed, 6 Oct 2021 07:25:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50530 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238286AbhJFLZC (ORCPT ); Wed, 6 Oct 2021 07:25:02 -0400 Received: from mail-wr1-x42f.google.com (mail-wr1-x42f.google.com [IPv6:2a00:1450:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3E02AC061749; Wed, 6 Oct 2021 04:23:10 -0700 (PDT) Received: by mail-wr1-x42f.google.com with SMTP id v17so7734220wrv.9; Wed, 06 Oct 2021 04:23:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lMW4foefc6bEFLqLQ2H0asFN0IF8jIbnNoNDfv9QTpo=; b=fqdoZhMJ2rxSvh2lAg5TQLQ6khL0EhpVeNi4HptuzUZ1DC3nJNGIPgvplHbMR76SeG tE+zzecpcLnJU5QQF05MnQrHtQbUemmbu1R6HLp8c9S47FR70J57K6ovtyOM65f8M6ih PFZUHsOON6/HLhhmHOHAr6wdjR+GkNljvpSXtIm1QpL5Gti0XljT56KRRtf/G6RsqTFB y6u3ydnPQpjnlIQA2q/9pnH5T2uqARPPc5mY7feGiQRBaP4xeVtbGGn6SjmKuoCTtx06 HVk7gdoqFC7wgyRkwpLkqY46OkBcZh0OnWuNb1pJCr8W6FKR4/G3z7ty99I7PY2w1VYP KZfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lMW4foefc6bEFLqLQ2H0asFN0IF8jIbnNoNDfv9QTpo=; b=2PdPYCZXndpd/kVPuaEpiXvIc2XfJxjeokS0LMTzd9JkDrCF4VdncZZuUKL6y/HqRV 2omdA4X6/W8omr9Wr0L2DtSMfvq67eHZcFcMfKuMiH7bHya6fcBBU4SzWWnbBPnXSUVX AReD+6LfG5Xmsebzxi0Uoymgx2lmlgtcVAtlAEyUCsckEtw4Eu+pgkgpNnfYw+tyGz73 IcyzZnNaTbW31CkCPEZZpAbcrXDKCC01RTBIJKtLd7tdQUCBjxIbBGq2isIxbKLX21L5 fG04HdVesEx0SLz4Ch5iLuv45uZQbuyCUglVFMqwYsTuTIs794a4Mdx4i52DDpGEPUKs i2Wg== X-Gm-Message-State: AOAM532K/33rfdzmrL9urJ3VBhfE1Pp04/8364MgTQEUYUYq9eKOH5NA rO4NKHUsf+4x+fHp0MRS1WSFzJLQgzA= X-Google-Smtp-Source: ABdhPJy9s/UAVv/L8Zfm9yvqWMej5Q+dXlji9BY4WfNy30A6S0GHmbTvPS+EYEKibZtyWtSJQgEwGg== X-Received: by 2002:a7b:c954:: with SMTP id i20mr9314376wml.126.1633519388877; Wed, 06 Oct 2021 04:23:08 -0700 (PDT) Received: from localhost.localdomain (252.red-83-54-181.dynamicip.rima-tde.net. [83.54.181.252]) by smtp.gmail.com with ESMTPSA id e14sm10801985wrw.33.2021.10.06.04.23.08 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 06 Oct 2021 04:23:08 -0700 (PDT) From: Sergio Paracuellos To: sboyd@kernel.org Cc: linux-clk@vger.kernel.org, gregkh@linuxfoundation.org, devicetree@vger.kernel.org, robh+dt@kernel.org, linux-staging@lists.linux.dev, neil@brown.name, linux-kernel@vger.kernel.org, john@phrozen.org Subject: [PATCH v2 1/4] dt-bindings: reset: add dt binding header for Mediatek MT7621 resets Date: Wed, 6 Oct 2021 13:23:03 +0200 Message-Id: <20211006112306.4691-2-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211006112306.4691-1-sergio.paracuellos@gmail.com> References: <20211006112306.4691-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add dt binding header for resets lines in Mediatek MT7621 SoCs. Signed-off-by: Sergio Paracuellos Acked-by: Rob Herring --- include/dt-bindings/reset/mt7621-reset.h | 37 ++++++++++++++++++++++++ 1 file changed, 37 insertions(+) create mode 100644 include/dt-bindings/reset/mt7621-reset.h diff --git a/include/dt-bindings/reset/mt7621-reset.h b/include/dt-bindings/reset/mt7621-reset.h new file mode 100644 index 000000000000..7572c6b41453 --- /dev/null +++ b/include/dt-bindings/reset/mt7621-reset.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2021 Sergio Paracuellos + * Author: Sergio Paracuellos + */ + +#ifndef DT_BINDING_MT7621_RESET_H +#define DT_BINDING_MT7621_RESET_H + +#define MT7621_RST_SYS 0 +#define MT7621_RST_MCM 2 +#define MT7621_RST_HSDMA 5 +#define MT7621_RST_FE 6 +#define MT7621_RST_SPDIFTX 7 +#define MT7621_RST_TIMER 8 +#define MT7621_RST_INT 9 +#define MT7621_RST_MC 10 +#define MT7621_RST_PCM 11 +#define MT7621_RST_PIO 13 +#define MT7621_RST_GDMA 14 +#define MT7621_RST_NFI 15 +#define MT7621_RST_I2C 16 +#define MT7621_RST_I2S 17 +#define MT7621_RST_SPI 18 +#define MT7621_RST_UART1 19 +#define MT7621_RST_UART2 20 +#define MT7621_RST_UART3 21 +#define MT7621_RST_ETH 23 +#define MT7621_RST_PCIE0 24 +#define MT7621_RST_PCIE1 25 +#define MT7621_RST_PCIE2 26 +#define MT7621_RST_AUX_STCK 28 +#define MT7621_RST_CRYPTO 29 +#define MT7621_RST_SDXC 30 +#define MT7621_RST_PPE 31 + +#endif /* DT_BINDING_MT7621_RESET_H */ From patchwork Wed Oct 6 11:23:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 12539221 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 39F44C433EF for ; Wed, 6 Oct 2021 11:23:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1B5D5611B0 for ; Wed, 6 Oct 2021 11:23:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238421AbhJFLZF (ORCPT ); Wed, 6 Oct 2021 07:25:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50540 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238408AbhJFLZD (ORCPT ); Wed, 6 Oct 2021 07:25:03 -0400 Received: from mail-wr1-x42e.google.com (mail-wr1-x42e.google.com [IPv6:2a00:1450:4864:20::42e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 407B4C061755; Wed, 6 Oct 2021 04:23:11 -0700 (PDT) Received: by mail-wr1-x42e.google.com with SMTP id r7so7711745wrc.10; Wed, 06 Oct 2021 04:23:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nNzJU9Y0TN+qNE5qJcuFSRHdr3qJUmf5dCSvTeevenI=; b=DvkR5dgnWDdBS+0qZqDLqptsMrO48mZFBOoVfrhVp1wxj0c0lqbipUlch7OZ2zz6Ju FJ808jczCkC64MPyLQ3ZaKyj+N60OlK4MlMcS+EKYeBqdXvtsec4ES4LUhDg+Cb9igbp P2qfaBhC4M3KEmlyTrfH6d7CZObxFLz7co3AJM8bwypCl6XkaeiexgM2xkaNWqQ6Zqok 56RiOXUbl/GGEhcaCu/ffI6h9/qneYg71jDglCCaVPNfTXtWBPutm9YYGaEGR7Vs+Id1 54sA9MQelc5oQvRlUJ3chptIlSUGFO4LaM/DhnzsUQLB29hbkyQoQahqA3qBJruBF7O7 JtGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nNzJU9Y0TN+qNE5qJcuFSRHdr3qJUmf5dCSvTeevenI=; b=6mJMlM7amgCLkdyWaqibr2soI1dFaHkXtX1d57Ahg5YawItzfK+83E0SiSKIn3Lk+r 820abfz+LkQrnXKFrmvMEl01+vxv5zw2uxZIujEqBkVUuYNIaJ5GdbASOjaDn6zFzJHa eqZShLEgHhK39okNxASKkcEZ0opx7nXfH82ORBAcFYyZQpRugMWTwRxRnk2VLjefXxIL dSbr7fvcRreIwZ+gOcrW63+jjON6LgbzBgE3QRMYywbJVLNxHOeFDFwBeePzuf9aV90z PVamCHnXbwdYrwGZ8Ld/nBzOQ3tmBo8eXzKllQdSlMoMmbIYA/zCnBKJ63RZD6++eQQf npRA== X-Gm-Message-State: AOAM530kdEBIK9Tb8VQlENUUKLiQ632/yVhVAvWCbeF8Rne4mvDg5NSC ZpjNOPyiubC4eLhk4sFrOLU= X-Google-Smtp-Source: ABdhPJxnXLZqC6UG7sG5RazrmyOBoNZVOuzAPL7APxcEs7FsSvkkn735SXc27MC7cXQ47Hksg6RmUg== X-Received: by 2002:adf:e74b:: with SMTP id c11mr26414202wrn.362.1633519389838; Wed, 06 Oct 2021 04:23:09 -0700 (PDT) Received: from localhost.localdomain (252.red-83-54-181.dynamicip.rima-tde.net. [83.54.181.252]) by smtp.gmail.com with ESMTPSA id e14sm10801985wrw.33.2021.10.06.04.23.08 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 06 Oct 2021 04:23:09 -0700 (PDT) From: Sergio Paracuellos To: sboyd@kernel.org Cc: linux-clk@vger.kernel.org, gregkh@linuxfoundation.org, devicetree@vger.kernel.org, robh+dt@kernel.org, linux-staging@lists.linux.dev, neil@brown.name, linux-kernel@vger.kernel.org, john@phrozen.org Subject: [PATCH v2 2/4] dt-bindings: clock: mediatek,mt7621-sysc: add '#reset-cells' property Date: Wed, 6 Oct 2021 13:23:04 +0200 Message-Id: <20211006112306.4691-3-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211006112306.4691-1-sergio.paracuellos@gmail.com> References: <20211006112306.4691-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Make system controller a reset provider for all the peripherals in the MT7621 SoC adding '#reset-cells' property. Signed-off-by: Sergio Paracuellos Acked-by: Rob Herring --- .../bindings/clock/mediatek,mt7621-sysc.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml index 915f84efd763..0c0b0ae5e2ac 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml @@ -22,6 +22,11 @@ description: | The clocks are provided inside a system controller node. + This node is also a reset provider for all the peripherals. + + Reset related bits are defined in: + [2]: . + properties: compatible: items: @@ -37,6 +42,12 @@ properties: clocks. const: 1 + "#reset-cells": + description: + The first cell indicates the reset bit within the register, see + [2] for available resets. + const: 1 + ralink,memctl: $ref: /schemas/types.yaml#/definitions/phandle description: @@ -61,6 +72,7 @@ examples: compatible = "mediatek,mt7621-sysc", "syscon"; reg = <0x0 0x100>; #clock-cells = <1>; + #reset-cells = <1>; ralink,memctl = <&memc>; clock-output-names = "xtal", "cpu", "bus", "50m", "125m", "150m", From patchwork Wed Oct 6 11:23:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 12539225 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4FF47C433FE for ; Wed, 6 Oct 2021 11:23:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3C3F76125F for ; Wed, 6 Oct 2021 11:23:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238393AbhJFLZN (ORCPT ); Wed, 6 Oct 2021 07:25:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50546 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238270AbhJFLZE (ORCPT ); Wed, 6 Oct 2021 07:25:04 -0400 Received: from mail-wr1-x434.google.com (mail-wr1-x434.google.com [IPv6:2a00:1450:4864:20::434]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2AE2EC061749; Wed, 6 Oct 2021 04:23:12 -0700 (PDT) Received: by mail-wr1-x434.google.com with SMTP id r18so7781817wrg.6; Wed, 06 Oct 2021 04:23:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Nw+gRBKSlBdLJR5JCN9jZoWbWkQnZuEzAoNBrLU9lmY=; b=Ww78qLVzY61h+k6gNMOOU3DRQKzM8hQZlLDGESLtWFcvQgE8ZSoINAuxX0WrsdG9N1 aR14p6vPJf/Fn0UL48+vAS3qfIXEXvGBDjH2WXyfFAJ+7Es0Qk1IcM8ySpjoVtgg2+Ws ayPZkEpeZ/sdDSGatogPb4ZQA1wAqb7GIYYW1kIDKrCjjrsZ3GF5G3p3QNFfaWnc98u5 4rgMQdYL6a4O09J+JexBm1PK8ASFcjrR+nad9FTNPM3/W0xuB2VGSRcWR2eohrWIEFjB spHP6Z+aLVWu+ncNPEGMXVpDS0yNN3qi7QtnChYjaRj4W/9QMxrlF7+4nWkBIjO+Y2Jc KUZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Nw+gRBKSlBdLJR5JCN9jZoWbWkQnZuEzAoNBrLU9lmY=; b=Ebxy2++ydNibY4T9FL+KVF1BR9oC3Z7SAexeuigqo4RocK7ItYFpPTF1WeCfeU4x7t lftZpPH6UpX9cKjwWlV4VgSUj8vqf6aHFxyl22B9Uy1m5x1D1c79r3eOBd59eXkaZFXv mnZUcxWCqByPrCZdkuWf/tu29Rb365t8l2aGvAU1I59MK/kLO47YnjjbLnP3OQ4oSQSo H8mpNnG1MSIaCRZ3WQRiFOba0y2jcv6g8dgW0G+OhLZU3K18nbmxJIrakoySZFXmF8Py 0Q8eBgncC9zIS5SFk4PZF0ltylL5ajHDjSevYed02GdyErTMVgIoZE3FFXd+jsbQtQt+ +vkQ== X-Gm-Message-State: AOAM530IEBeA2+qURLItcqCiAbtWsxX1lS4M6zaWXUvY8Uj5DpbsNiAR rkrxmF8OrTWA3wGa7OdFgjM= X-Google-Smtp-Source: ABdhPJyYJhfhOzDvyH7laJTeI5RmyTJlxWWlF2G/04PM0PpJLMb9zaJ286MTQc0nux8IxL8UoEUatQ== X-Received: by 2002:a05:600c:4ec6:: with SMTP id g6mr9304916wmq.95.1633519390776; Wed, 06 Oct 2021 04:23:10 -0700 (PDT) Received: from localhost.localdomain (252.red-83-54-181.dynamicip.rima-tde.net. [83.54.181.252]) by smtp.gmail.com with ESMTPSA id e14sm10801985wrw.33.2021.10.06.04.23.09 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 06 Oct 2021 04:23:10 -0700 (PDT) From: Sergio Paracuellos To: sboyd@kernel.org Cc: linux-clk@vger.kernel.org, gregkh@linuxfoundation.org, devicetree@vger.kernel.org, robh+dt@kernel.org, linux-staging@lists.linux.dev, neil@brown.name, linux-kernel@vger.kernel.org, john@phrozen.org Subject: [PATCH v2 3/4] clk: ralink: make system controller node a reset provider Date: Wed, 6 Oct 2021 13:23:05 +0200 Message-Id: <20211006112306.4691-4-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211006112306.4691-1-sergio.paracuellos@gmail.com> References: <20211006112306.4691-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org MT7621 system controller node is already providing the clocks for the whole system but must also serve as a reset provider. Hence, add reset controller related code to the clock driver itself. Signed-off-by: Sergio Paracuellos --- drivers/clk/ralink/clk-mt7621.c | 79 +++++++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/drivers/clk/ralink/clk-mt7621.c b/drivers/clk/ralink/clk-mt7621.c index a2c045390f00..7a474bb4c877 100644 --- a/drivers/clk/ralink/clk-mt7621.c +++ b/drivers/clk/ralink/clk-mt7621.c @@ -11,14 +11,17 @@ #include #include #include +#include #include #include +#include /* Configuration registers */ #define SYSC_REG_SYSTEM_CONFIG0 0x10 #define SYSC_REG_SYSTEM_CONFIG1 0x14 #define SYSC_REG_CLKCFG0 0x2c #define SYSC_REG_CLKCFG1 0x30 +#define SYSC_REG_RESET_CTRL 0x34 #define SYSC_REG_CUR_CLK_STS 0x44 #define MEMC_REG_CPU_PLL 0x648 @@ -398,6 +401,76 @@ static void __init mt7621_clk_init(struct device_node *node) } CLK_OF_DECLARE_DRIVER(mt7621_clk, "mediatek,mt7621-sysc", mt7621_clk_init); +struct mt7621_rst { + struct reset_controller_dev rcdev; + struct regmap *sysc; +}; + +static struct mt7621_rst *to_mt7621_rst(struct reset_controller_dev *dev) +{ + return container_of(dev, struct mt7621_rst, rcdev); +} + +static int mt7621_assert_device(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct mt7621_rst *data = to_mt7621_rst(rcdev); + struct regmap *sysc = data->sysc; + + if (id == MT7621_RST_SYS) + return -EINVAL; + + return regmap_update_bits(sysc, SYSC_REG_RESET_CTRL, BIT(id), BIT(id)); +} + +static int mt7621_deassert_device(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct mt7621_rst *data = to_mt7621_rst(rcdev); + struct regmap *sysc = data->sysc; + + if (id == MT7621_RST_SYS) + return -EINVAL; + + return regmap_update_bits(sysc, SYSC_REG_RESET_CTRL, BIT(id), 0); +} + +static int mt7621_reset_device(struct reset_controller_dev *rcdev, + unsigned long id) +{ + int ret; + + ret = mt7621_assert_device(rcdev, id); + if (ret < 0) + return ret; + + return mt7621_deassert_device(rcdev, id); +} + +static const struct reset_control_ops reset_ops = { + .reset = mt7621_reset_device, + .assert = mt7621_assert_device, + .deassert = mt7621_deassert_device +}; + +static int mt7621_reset_init(struct device *dev, struct regmap *sysc) +{ + struct mt7621_rst *rst_data; + + rst_data = devm_kzalloc(dev, sizeof(*rst_data), GFP_KERNEL); + if (!rst_data) + return -ENOMEM; + + rst_data->sysc = sysc; + rst_data->rcdev.ops = &reset_ops; + rst_data->rcdev.owner = THIS_MODULE; + rst_data->rcdev.nr_resets = 32; + rst_data->rcdev.of_reset_n_cells = 1; + rst_data->rcdev.of_node = dev_of_node(dev); + + return devm_reset_controller_register(dev, &rst_data->rcdev); +} + static int mt7621_clk_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; @@ -424,6 +497,12 @@ static int mt7621_clk_probe(struct platform_device *pdev) return ret; } + ret = mt7621_reset_init(dev, priv->sysc); + if (ret) { + pr_err("Could not init reset controller\n"); + return ret; + } + count = ARRAY_SIZE(mt7621_clks_base) + ARRAY_SIZE(mt7621_fixed_clks) + ARRAY_SIZE(mt7621_gates); clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, count), From patchwork Wed Oct 6 11:23:06 2021 Content-Type: text/plain; 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[83.54.181.252]) by smtp.gmail.com with ESMTPSA id e14sm10801985wrw.33.2021.10.06.04.23.10 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 06 Oct 2021 04:23:11 -0700 (PDT) From: Sergio Paracuellos To: sboyd@kernel.org Cc: linux-clk@vger.kernel.org, gregkh@linuxfoundation.org, devicetree@vger.kernel.org, robh+dt@kernel.org, linux-staging@lists.linux.dev, neil@brown.name, linux-kernel@vger.kernel.org, john@phrozen.org Subject: [PATCH v2 4/4] staging: mt7621-dts: align resets with binding documentation Date: Wed, 6 Oct 2021 13:23:06 +0200 Message-Id: <20211006112306.4691-5-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211006112306.4691-1-sergio.paracuellos@gmail.com> References: <20211006112306.4691-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Binding documentation for compatible 'mediatek,mt7621-sysc' has been updated to be used as a reset provider. Align reset related bits and system controller node with binding documentation along the dtsi file. Signed-off-by: Sergio Paracuellos --- drivers/staging/mt7621-dts/mt7621.dtsi | 27 ++++++++++++-------------- 1 file changed, 12 insertions(+), 15 deletions(-) diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi b/drivers/staging/mt7621-dts/mt7621.dtsi index 719ef28171f4..72b99d8b4647 100644 --- a/drivers/staging/mt7621-dts/mt7621.dtsi +++ b/drivers/staging/mt7621-dts/mt7621.dtsi @@ -1,6 +1,7 @@ #include #include #include +#include / { #address-cells = <1>; @@ -59,6 +60,7 @@ sysc: syscon@0 { compatible = "mediatek,mt7621-sysc", "syscon"; reg = <0x0 0x100>; #clock-cells = <1>; + #reset-cells = <1>; ralink,memctl = <&memc>; clock-output-names = "xtal", "cpu", "bus", "50m", "125m", "150m", @@ -88,7 +90,7 @@ i2c: i2c@900 { clocks = <&sysc MT7621_CLK_I2C>; clock-names = "i2c"; - resets = <&rstctrl 16>; + resets = <&sysc MT7621_RST_I2C>; reset-names = "i2c"; #address-cells = <1>; @@ -106,7 +108,7 @@ i2s: i2s@a00 { clocks = <&sysc MT7621_CLK_I2S>; clock-names = "i2s"; - resets = <&rstctrl 17>; + resets = <&sysc MT7621_RST_I2S>; reset-names = "i2s"; interrupt-parent = <&gic>; @@ -151,7 +153,7 @@ spi0: spi@b00 { clocks = <&sysc MT7621_CLK_SPI>; clock-names = "spi"; - resets = <&rstctrl 18>; + resets = <&sysc MT7621_RST_SPI>; reset-names = "spi"; #address-cells = <1>; @@ -167,7 +169,7 @@ gdma: gdma@2800 { clocks = <&sysc MT7621_CLK_GDMA>; clock-names = "gdma"; - resets = <&rstctrl 14>; + resets = <&sysc MT7621_RST_GDMA>; reset-names = "dma"; interrupt-parent = <&gic>; @@ -186,7 +188,7 @@ hsdma: hsdma@7000 { clocks = <&sysc MT7621_CLK_HSDMA>; clock-names = "hsdma"; - resets = <&rstctrl 5>; + resets = <&sysc MT7621_RST_HSDMA>; reset-names = "hsdma"; interrupt-parent = <&gic>; @@ -286,11 +288,6 @@ pinmux { }; }; - rstctrl: rstctrl { - compatible = "ralink,rt2880-reset"; - #reset-cells = <1>; - }; - sdhci: sdhci@1E130000 { status = "disabled"; @@ -383,7 +380,7 @@ ethernet: ethernet@1e100000 { #address-cells = <1>; #size-cells = <0>; - resets = <&rstctrl 6 &rstctrl 23>; + resets = <&sysc MT7621_CLK_FE &sysc MT7621_CLK_ETH>; reset-names = "fe", "eth"; interrupt-parent = <&gic>; @@ -428,7 +425,7 @@ switch0: switch0@0 { #size-cells = <0>; reg = <0>; mediatek,mcm; - resets = <&rstctrl 2>; + resets = <&sysc MT7621_RST_MCM>; reset-names = "mcm"; interrupt-controller; #interrupt-cells = <1>; @@ -514,7 +511,7 @@ pcie@0,0 { #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>; - resets = <&rstctrl 24>; + resets = <&sysc MT7621_RST_PCIE0>; clocks = <&sysc MT7621_CLK_PCIE0>; phys = <&pcie0_phy 1>; phy-names = "pcie-phy0"; @@ -529,7 +526,7 @@ pcie@1,0 { #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>; - resets = <&rstctrl 25>; + resets = <&sysc MT7621_RST_PCIE1>; clocks = <&sysc MT7621_CLK_PCIE1>; phys = <&pcie0_phy 1>; phy-names = "pcie-phy1"; @@ -544,7 +541,7 @@ pcie@2,0 { #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>; - resets = <&rstctrl 26>; + resets = <&sysc MT7621_RST_PCIE2>; clocks = <&sysc MT7621_CLK_PCIE2>; phys = <&pcie2_phy 0>; phy-names = "pcie-phy2";