From patchwork Fri Oct 8 00:22:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12543923 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 32CCFC4332F for ; Fri, 8 Oct 2021 00:23:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1D0126121F for ; Fri, 8 Oct 2021 00:23:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242073AbhJHAY6 (ORCPT ); Thu, 7 Oct 2021 20:24:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53300 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241878AbhJHAY5 (ORCPT ); Thu, 7 Oct 2021 20:24:57 -0400 Received: from mail-ed1-x52d.google.com (mail-ed1-x52d.google.com [IPv6:2a00:1450:4864:20::52d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8AE40C061570; Thu, 7 Oct 2021 17:23:02 -0700 (PDT) Received: by mail-ed1-x52d.google.com with SMTP id d3so2210519edp.3; Thu, 07 Oct 2021 17:23:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=4IEdjq+B+/Tu4XXsbREn4Co9QK1TLiWV/cOfOjS1OgI=; b=g9B3BE0sCe0E8cRAzMy4Kz+MwuutHkXGqKqZ+3Lz6EzKBAyNhdFD4dJu/CqOrs8+ep Y974PwQ6F+kXQewdawOIQtJqtMYoGDSpwvw9B2hCii1KoE7ucnpAUebc6YLoXdpBIhLr 35Z/+4hyp92SZv/QrS5250PkCIXLNJELRLyMAzaEnkLRsMQUya1N++7tO6BoDI1slLJk Z5ok1V7/VfpMT0yw2v1MGu5+Zg2jauway5k5coxAOGCaJcfBhhd+RSzqBEKmm9WyGMdR W/CYtaJuVYKVKJonqqoXfZZemKQNjFid3GwpxyirXYZMrd0ymKNmdz7RO+QYip4UIX6S hKGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4IEdjq+B+/Tu4XXsbREn4Co9QK1TLiWV/cOfOjS1OgI=; b=6D+cGdu0BZy8IThwvTpGxEpigOSOkNUzqe45ViqV4tBYHUZ3d0Ec04LHFURN9sQSYn cFHgh0Z2TrJi8eWQQXoJ2zldDNtd9uOrnDBmADhkYEPgbyZ8jcu1JNvlXMTr3WkFzDEO u+/tCM+I0DYkRByDe6KygAYTMIUVYuCXSCP7OPLCFG0o0OOkFYVCyvabY6XIdtAYqwgn 8FcQaVxukNmQlaeSGcucHCqE70mf24MwsuSdQ1y+4GfKu1fSf8PcEYPPtluUJUrIL5Qa ioLTgqK3FYEwjLTOam3pCLJbvf9GAx/AHjNx64GtC8oEdYrS171nj4/zQr4h59k23EuL QQLg== X-Gm-Message-State: AOAM533KmvpyBejJdljJAv8C0qnewMKweCbhQkQYogyHLytLglcaU5Xx bEy5pn6GBzx4UJWSJoZNq98= X-Google-Smtp-Source: ABdhPJw8vnxVHIwn2t96k/cYYUlbnbFlQ75+yZRtho4hY7YTrWhkssazLDtea5spB0naFGGDYgOmig== X-Received: by 2002:a05:6402:3128:: with SMTP id dd8mr10216945edb.383.1633652581034; Thu, 07 Oct 2021 17:23:01 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id ke12sm308592ejc.32.2021.10.07.17.23.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Oct 2021 17:23:00 -0700 (PDT) From: Ansuel Smith To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Heiner Kallweit , Russell King , Ansuel Smith , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [net PATCH v2 01/15] drivers: net: phy: at803x: fix resume for QCA8327 phy Date: Fri, 8 Oct 2021 02:22:11 +0200 Message-Id: <20211008002225.2426-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211008002225.2426-1-ansuelsmth@gmail.com> References: <20211008002225.2426-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org From Documentation phy resume triggers phy reset and restart auto-negotiation. Add a dedicated function to wait reset to finish as it was notice a regression where port sometime are not reliable after a suspend/resume session. The reset wait logic is copied from phy_poll_reset. Add dedicated suspend function to use genphy_suspend only with QCA8337 phy and set only additional debug settings for QCA8327. With more test it was reported that QCA8327 doesn't proprely support this mode and using this cause the unreliability of the switch ports, especially the malfunction of the port0. Fixes: 52a6cdbe43a3 ("net: phy: at803x: add resume/suspend function to qca83xx phy") Signed-off-by: Ansuel Smith --- drivers/net/phy/at803x.c | 69 ++++++++++++++++++++++++++++++++++++---- 1 file changed, 63 insertions(+), 6 deletions(-) diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c index 3feee4d59030..c6c87b82c95c 100644 --- a/drivers/net/phy/at803x.c +++ b/drivers/net/phy/at803x.c @@ -92,9 +92,14 @@ #define AT803X_DEBUG_REG_5 0x05 #define AT803X_DEBUG_TX_CLK_DLY_EN BIT(8) +#define AT803X_DEBUG_REG_HIB_CTRL 0x0b +#define AT803X_DEBUG_HIB_CTRL_SEL_RST_80U BIT(10) +#define AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE BIT(13) + #define AT803X_DEBUG_REG_3C 0x3C #define AT803X_DEBUG_REG_3D 0x3D +#define AT803X_DEBUG_GATE_CLK_IN1000 BIT(6) #define AT803X_DEBUG_REG_1F 0x1F #define AT803X_DEBUG_PLL_ON BIT(2) @@ -1312,6 +1317,58 @@ static int qca83xx_config_init(struct phy_device *phydev) return 0; } +static int qca83xx_resume(struct phy_device *phydev) +{ + int ret, val; + + /* Skip reset if not suspended */ + if (!phydev->suspended) + return 0; + + /* Reinit the port, reset values set by suspend */ + qca83xx_config_init(phydev); + + /* Reset the port on port resume */ + phy_set_bits(phydev, MII_BMCR, BMCR_RESET | BMCR_ANENABLE); + + /* On resume from suspend the switch execute a reset and + * restart auto-negotiation. Wait for reset to complete. + */ + ret = phy_read_poll_timeout(phydev, MII_BMCR, val, !(val & BMCR_RESET), + 50000, 600000, true); + if (ret) + return ret; + + msleep(1); + + return 0; +} + +static int qca83xx_suspend(struct phy_device *phydev) +{ + u16 mask = 0; + + /* Only QCA8337 support actual suspend. + * QCA8327 cause port unreliability when phy suspend + * is set. + */ + if (phydev->drv->phy_id == QCA8337_PHY_ID) { + genphy_suspend(phydev); + } else { + mask |= ~(BMCR_SPEED1000 | BMCR_FULLDPLX); + phy_modify(phydev, MII_BMCR, mask, 0); + } + + at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_3D, + AT803X_DEBUG_GATE_CLK_IN1000, 0); + + at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL, + AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE | + AT803X_DEBUG_HIB_CTRL_SEL_RST_80U, 0); + + return 0; +} + static struct phy_driver at803x_driver[] = { { /* Qualcomm Atheros AR8035 */ @@ -1421,8 +1478,8 @@ static struct phy_driver at803x_driver[] = { .get_sset_count = at803x_get_sset_count, .get_strings = at803x_get_strings, .get_stats = at803x_get_stats, - .suspend = genphy_suspend, - .resume = genphy_resume, + .suspend = qca83xx_suspend, + .resume = qca83xx_resume, }, { /* QCA8327-A from switch QCA8327-AL1A */ .phy_id = QCA8327_A_PHY_ID, @@ -1436,8 +1493,8 @@ static struct phy_driver at803x_driver[] = { .get_sset_count = at803x_get_sset_count, .get_strings = at803x_get_strings, .get_stats = at803x_get_stats, - .suspend = genphy_suspend, - .resume = genphy_resume, + .suspend = qca83xx_suspend, + .resume = qca83xx_resume, }, { /* QCA8327-B from switch QCA8327-BL1A */ .phy_id = QCA8327_B_PHY_ID, @@ -1451,8 +1508,8 @@ static struct phy_driver at803x_driver[] = { .get_sset_count = at803x_get_sset_count, .get_strings = at803x_get_strings, .get_stats = at803x_get_stats, - .suspend = genphy_suspend, - .resume = genphy_resume, + .suspend = qca83xx_suspend, + .resume = qca83xx_resume, }, }; module_phy_driver(at803x_driver); From patchwork Fri Oct 8 00:22:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12543933 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 81151C433FE for ; Fri, 8 Oct 2021 00:23:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6E9DC60F43 for ; Fri, 8 Oct 2021 00:23:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242383AbhJHAZB (ORCPT ); Thu, 7 Oct 2021 20:25:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53304 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241951AbhJHAY6 (ORCPT ); Thu, 7 Oct 2021 20:24:58 -0400 Received: from mail-ed1-x535.google.com (mail-ed1-x535.google.com [IPv6:2a00:1450:4864:20::535]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 89C70C061570; Thu, 7 Oct 2021 17:23:03 -0700 (PDT) Received: by mail-ed1-x535.google.com with SMTP id g8so29580644edt.7; Thu, 07 Oct 2021 17:23:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=HGh5+iB2TULH7hahZSPDz2mxWTqZ/+fE5LlYJVBSwbg=; b=fcdEXW33eOPWvxKwPt8Pk4VYbAUe0dimY8gvmOIutI7hCMyRGRwoO6NUgqrF+94JMl gHdpW8lmS+d4CSRZ9mRZQn7FbDB4usBE4W+M6PgBeWwG+FMiuA39u2LThzsBjZ7hO4dm Y7XgqPtkNRU3ekyaZZXohjwW653ivv55P5VPcNSIzytBrVaQRp6zkOCfroqX++oyYTGw ZsOH0oyaxtD9EhMA3hjg4m5EmZ0i30DTWzzaZyoGRKhjbBbqcSDU1njmP+ArRFyb9bKP NkvwpxXlu/aJbb5pTnDqhDdimxDhqe5JH1OMZtXuFoWeIJJ5OLJm6oi8CVst4PchjLjc RCvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HGh5+iB2TULH7hahZSPDz2mxWTqZ/+fE5LlYJVBSwbg=; b=B08BglOQ/qK6JF/zNmEpdUmFvhZsDIn7H4CZ5Bbj30Z9bUBqsWgTsQg8ppTUeuTzNh bqB7iuCIscH5Y+IfdM1eDiTuj/2fi7P2SYe6MiM1SjtlYe5faEn8rQeIPo0mUsFLG7pJ p40zO9roy18Oc80LLqA8L6Xnz5aPEZw9I7uTh0GiEtabCK8ozFAtzIkgwTimCTEDWqTr MLYFY6Wg0J9CXR5scTbx9TfZ9bvonUz83Ff3HV5ZLMUvEK//w6VjoTjmQzAIYw17s7KG l+Ij6/ASQyFlp0YJce3gksOfu/iZItxICSfr2jvwc2FuAHBtfjhCTdOBxUr+H5ou6MXu OJYA== X-Gm-Message-State: AOAM532nH32fE2EQQQBP6lFMLyWBmGxBvcA150Q+pCjSSs+XtymXNp4W ajJ8/C0eXNe7grLjmmLVM6gV4FfpaYw= X-Google-Smtp-Source: ABdhPJxTzCQQIzNG11JvLDWDYuYmWIyDfZdRwMF4seNbFnt6v8JWJpWL+1Nj0NzfogdLRRtrtnRzyQ== X-Received: by 2002:a17:906:1ed7:: with SMTP id m23mr131987ejj.558.1633652582065; Thu, 07 Oct 2021 17:23:02 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id ke12sm308592ejc.32.2021.10.07.17.23.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Oct 2021 17:23:01 -0700 (PDT) From: Ansuel Smith To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Heiner Kallweit , Russell King , Ansuel Smith , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [net PATCH v2 02/15] drivers: net: phy: at803x: add DAC amplitude fix for 8327 phy Date: Fri, 8 Oct 2021 02:22:12 +0200 Message-Id: <20211008002225.2426-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211008002225.2426-1-ansuelsmth@gmail.com> References: <20211008002225.2426-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org QCA8327 internal phy require DAC amplitude adjustement set to +6% with 100m speed. Also add additional define to report a change of the same reg in QCA8337. (different scope it does set 1000m voltage) Add link_change_notify function to set the proper amplitude adjustement on PHY_RUNNING state and disable on any other state. Fixes: c6bcec0d6928 ("net: phy: at803x: add support for qca 8327 A variant internal phy") Signed-off-by: Ansuel Smith --- drivers/net/phy/at803x.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c index c6c87b82c95c..5208ea8fdd69 100644 --- a/drivers/net/phy/at803x.c +++ b/drivers/net/phy/at803x.c @@ -87,6 +87,8 @@ #define AT803X_PSSR_MR_AN_COMPLETE 0x0200 #define AT803X_DEBUG_REG_0 0x00 +#define QCA8327_DEBUG_MANU_CTRL_EN BIT(2) +#define QCA8337_DEBUG_MANU_CTRL_EN GENMASK(3, 2) #define AT803X_DEBUG_RX_CLK_DLY_EN BIT(15) #define AT803X_DEBUG_REG_5 0x05 @@ -1314,9 +1316,37 @@ static int qca83xx_config_init(struct phy_device *phydev) break; } + /* QCA8327 require DAC amplitude adjustment for 100m set to +6%. + * Disable on init and enable only with 100m speed following + * qca original source code. + */ + if (phydev->drv->phy_id == QCA8327_A_PHY_ID || + phydev->drv->phy_id == QCA8327_B_PHY_ID) + at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, + QCA8327_DEBUG_MANU_CTRL_EN, 0); + return 0; } +static void qca83xx_link_change_notify(struct phy_device *phydev) +{ + /* QCA8337 doesn't require DAC Amplitude adjustement */ + if (phydev->drv->phy_id == QCA8337_PHY_ID) + return; + + /* Set DAC Amplitude adjustment to +6% for 100m on link running */ + if (phydev->state == PHY_RUNNING) { + if (phydev->speed == SPEED_100) + at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, + QCA8327_DEBUG_MANU_CTRL_EN, + QCA8327_DEBUG_MANU_CTRL_EN); + } else { + /* Reset DAC Amplitude adjustment */ + at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, + QCA8327_DEBUG_MANU_CTRL_EN, 0); + } +} + static int qca83xx_resume(struct phy_device *phydev) { int ret, val; @@ -1471,6 +1501,7 @@ static struct phy_driver at803x_driver[] = { .phy_id_mask = QCA8K_PHY_ID_MASK, .name = "Qualcomm Atheros 8337 internal PHY", /* PHY_GBIT_FEATURES */ + .link_change_notify = qca83xx_link_change_notify, .probe = at803x_probe, .flags = PHY_IS_INTERNAL, .config_init = qca83xx_config_init, @@ -1486,6 +1517,7 @@ static struct phy_driver at803x_driver[] = { .phy_id_mask = QCA8K_PHY_ID_MASK, .name = "Qualcomm Atheros 8327-A internal PHY", /* PHY_GBIT_FEATURES */ + .link_change_notify = qca83xx_link_change_notify, .probe = at803x_probe, .flags = PHY_IS_INTERNAL, .config_init = qca83xx_config_init, @@ -1501,6 +1533,7 @@ static struct phy_driver at803x_driver[] = { .phy_id_mask = QCA8K_PHY_ID_MASK, .name = "Qualcomm Atheros 8327-B internal PHY", /* PHY_GBIT_FEATURES */ + .link_change_notify = qca83xx_link_change_notify, .probe = at803x_probe, .flags = PHY_IS_INTERNAL, .config_init = qca83xx_config_init, From patchwork Fri Oct 8 00:22:13 2021 Content-Type: text/plain; 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[93.42.71.246]) by smtp.googlemail.com with ESMTPSA id ke12sm308592ejc.32.2021.10.07.17.23.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Oct 2021 17:23:02 -0700 (PDT) From: Ansuel Smith To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Heiner Kallweit , Russell King , Ansuel Smith , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [net-next PATCH v2 03/15] drivers: net: phy: at803x: enable prefer master for 83xx internal phy Date: Fri, 8 Oct 2021 02:22:13 +0200 Message-Id: <20211008002225.2426-4-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211008002225.2426-1-ansuelsmth@gmail.com> References: <20211008002225.2426-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org From original QCA source code the port was set to prefer master as port type in 1000BASE-T mode. Apply the same settings also here. Signed-off-by: Ansuel Smith Reviewed-by: Andrew Lunn --- drivers/net/phy/at803x.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c index 5208ea8fdd69..402b2096f209 100644 --- a/drivers/net/phy/at803x.c +++ b/drivers/net/phy/at803x.c @@ -1325,6 +1325,9 @@ static int qca83xx_config_init(struct phy_device *phydev) at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, QCA8327_DEBUG_MANU_CTRL_EN, 0); + /* Following original QCA sourcecode set port to prefer master */ + phy_set_bits(phydev, MII_CTRL1000, CTL1000_PREFER_MASTER); + return 0; } From patchwork Fri Oct 8 00:22:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12543937 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AEBADC433EF for ; Fri, 8 Oct 2021 00:23:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 987CD613D5 for ; Fri, 8 Oct 2021 00:23:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242938AbhJHAZV (ORCPT ); Thu, 7 Oct 2021 20:25:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53326 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242261AbhJHAZA (ORCPT ); Thu, 7 Oct 2021 20:25:00 -0400 Received: from mail-ed1-x52f.google.com (mail-ed1-x52f.google.com [IPv6:2a00:1450:4864:20::52f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A78C6C061764; Thu, 7 Oct 2021 17:23:05 -0700 (PDT) Received: by mail-ed1-x52f.google.com with SMTP id i20so13530907edj.10; Thu, 07 Oct 2021 17:23:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=jWWBtH+wZrkZ2ctq6tn3ifU4WdTRaNlmHKqlJkhkyug=; b=WnWxY3WAqda0137VyHHOdDYGwrrjA7jjZHTBbu3Ai4xZhC9NZVLRJhTZlpAvBpN7n8 raQp1K8RzWWevmVzlCMhDRyAmTA31pWZ/5j9UrBw6hRxsG10SmpEfGQVcEuGD2x7nXd1 CQOeyU2P8Ta2/slpOfHZCz+CdEuFiho7gmuBLfnEtreLrXYMg/XgijkIh2I6UcwbeOa7 4N8Y1Z4beaF+SLfa++7+HH0NXJN3WZmkS7oouTomsMHxKxjsp++aYmKtQ1dreS063ZUj ZWWY9yZyQOJAjUuott3TVYmpj4qvuX0nZJFjvzdUxvbLchtv3atruignSOHgKbvke/ai Ufvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jWWBtH+wZrkZ2ctq6tn3ifU4WdTRaNlmHKqlJkhkyug=; b=SugdCzfa0SblBUVBioeOkkhVjw/c62LJLxTrkY3pWc02sVL4tGhfn5rEO3A+pGRQKm C7XE7Tqx3mEK2uiVSqG3jP5k/8EaQLRDsDmOczYMQ/s6b8fmAi2xDRDGC/xM7joGf0Hf kpRw6T778nvCmoFAsTfO+BszP1X2IpSZUtreP3xGnldEESSkekWh0ngjnhun4dpKOVF5 TJGQBnzTk8V/7eHOsNRfyQjMMc4F0LL2leaK7STf8OBEtwYvOuyaWiKVk2E1H+EUg98G Ke/Ko97GJXhoGrGSgtQnA0eJdJsqU9qX0wScnm0Xp098FC9FCl3HsMDDRSQIY0P3Gz9S kt2Q== X-Gm-Message-State: AOAM531WcsqWSjuoopO+mWCLtlkmXRuN3h/3ErM7fHJLAxdR4+nLPp8Q DaACWFUBxMMS3C+QH9wkVvc= X-Google-Smtp-Source: ABdhPJzAi96wM/NDyS/dDFWNlE40h4jz2ETsN6R3NZ9Rw2xfZgMN0tBDA95pr96QqbL2JBBttSJtCA== X-Received: by 2002:a17:906:24c6:: with SMTP id f6mr151180ejb.366.1633652584111; Thu, 07 Oct 2021 17:23:04 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id ke12sm308592ejc.32.2021.10.07.17.23.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Oct 2021 17:23:03 -0700 (PDT) From: Ansuel Smith To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Heiner Kallweit , Russell King , Ansuel Smith , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [net-next PATCH v2 04/15] drivers: net: phy: at803x: better describe debug regs Date: Fri, 8 Oct 2021 02:22:14 +0200 Message-Id: <20211008002225.2426-5-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211008002225.2426-1-ansuelsmth@gmail.com> References: <20211008002225.2426-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Give a name to known debug regs from Documentation instead of using unknown hex values. Signed-off-by: Ansuel Smith Reviewed-by: Andrew Lunn --- drivers/net/phy/at803x.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c index 402b2096f209..f40f17a632ad 100644 --- a/drivers/net/phy/at803x.c +++ b/drivers/net/phy/at803x.c @@ -86,12 +86,12 @@ #define AT803X_PSSR 0x11 /*PHY-Specific Status Register*/ #define AT803X_PSSR_MR_AN_COMPLETE 0x0200 -#define AT803X_DEBUG_REG_0 0x00 +#define AT803X_DEBUG_ANALOG_TEST_CTRL 0x00 #define QCA8327_DEBUG_MANU_CTRL_EN BIT(2) #define QCA8337_DEBUG_MANU_CTRL_EN GENMASK(3, 2) #define AT803X_DEBUG_RX_CLK_DLY_EN BIT(15) -#define AT803X_DEBUG_REG_5 0x05 +#define AT803X_DEBUG_SYSTEM_CTRL_MODE 0x05 #define AT803X_DEBUG_TX_CLK_DLY_EN BIT(8) #define AT803X_DEBUG_REG_HIB_CTRL 0x0b @@ -100,7 +100,7 @@ #define AT803X_DEBUG_REG_3C 0x3C -#define AT803X_DEBUG_REG_3D 0x3D +#define AT803X_DEBUG_REG_GREEN 0x3D #define AT803X_DEBUG_GATE_CLK_IN1000 BIT(6) #define AT803X_DEBUG_REG_1F 0x1F @@ -284,25 +284,25 @@ static int at803x_read_page(struct phy_device *phydev) static int at803x_enable_rx_delay(struct phy_device *phydev) { - return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, 0, + return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0, AT803X_DEBUG_RX_CLK_DLY_EN); } static int at803x_enable_tx_delay(struct phy_device *phydev) { - return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5, 0, + return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0, AT803X_DEBUG_TX_CLK_DLY_EN); } static int at803x_disable_rx_delay(struct phy_device *phydev) { - return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, + return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, AT803X_DEBUG_RX_CLK_DLY_EN, 0); } static int at803x_disable_tx_delay(struct phy_device *phydev) { - return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5, + return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, AT803X_DEBUG_TX_CLK_DLY_EN, 0); } @@ -1300,9 +1300,9 @@ static int qca83xx_config_init(struct phy_device *phydev) switch (switch_revision) { case 1: /* For 100M waveform */ - at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_0, 0x02ea); + at803x_debug_reg_write(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0x02ea); /* Turn on Gigabit clock */ - at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3D, 0x68a0); + at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x68a0); break; case 2: @@ -1310,8 +1310,8 @@ static int qca83xx_config_init(struct phy_device *phydev) fallthrough; case 4: phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_AZ_DEBUG, 0x803f); - at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3D, 0x6860); - at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_5, 0x2c46); + at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x6860); + at803x_debug_reg_write(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0x2c46); at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3C, 0x6000); break; } @@ -1322,7 +1322,7 @@ static int qca83xx_config_init(struct phy_device *phydev) */ if (phydev->drv->phy_id == QCA8327_A_PHY_ID || phydev->drv->phy_id == QCA8327_B_PHY_ID) - at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, + at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, QCA8327_DEBUG_MANU_CTRL_EN, 0); /* Following original QCA sourcecode set port to prefer master */ @@ -1340,12 +1340,12 @@ static void qca83xx_link_change_notify(struct phy_device *phydev) /* Set DAC Amplitude adjustment to +6% for 100m on link running */ if (phydev->state == PHY_RUNNING) { if (phydev->speed == SPEED_100) - at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, + at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, QCA8327_DEBUG_MANU_CTRL_EN, QCA8327_DEBUG_MANU_CTRL_EN); } else { /* Reset DAC Amplitude adjustment */ - at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, + at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, QCA8327_DEBUG_MANU_CTRL_EN, 0); } } @@ -1392,7 +1392,7 @@ static int qca83xx_suspend(struct phy_device *phydev) phy_modify(phydev, MII_BMCR, mask, 0); } - at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_3D, + at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_GREEN, AT803X_DEBUG_GATE_CLK_IN1000, 0); at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL, From patchwork Fri Oct 8 00:22:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12543931 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DFBDCC433F5 for ; Fri, 8 Oct 2021 00:23:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C6B8960F43 for ; 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[93.42.71.246]) by smtp.googlemail.com with ESMTPSA id ke12sm308592ejc.32.2021.10.07.17.23.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Oct 2021 17:23:04 -0700 (PDT) From: Ansuel Smith To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Heiner Kallweit , Russell King , Ansuel Smith , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [net-next PATCH v2 05/15] net: dsa: qca8k: add mac_power_sel support Date: Fri, 8 Oct 2021 02:22:15 +0200 Message-Id: <20211008002225.2426-6-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211008002225.2426-1-ansuelsmth@gmail.com> References: <20211008002225.2426-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Add missing mac power sel support needed for some switch that requires additional setup. ar8327 have a different setup than 8337. Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 27 +++++++++++++++++++++++++++ drivers/net/dsa/qca8k.h | 5 +++++ 2 files changed, 32 insertions(+) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index bda5a9bf4f52..5bce7ac4dea7 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -950,6 +950,29 @@ qca8k_setup_of_rgmii_delay(struct qca8k_priv *priv) return 0; } +static int +qca8k_setup_mac_pwr_sel(struct qca8k_priv *priv) +{ + struct device_node *node = priv->dev->of_node; + u32 mask = 0; + int ret = 0; + + if (of_property_read_bool(node, "qca,rgmii0-1-8v")) + mask |= QCA8K_MAC_PWR_RGMII0_1_8V; + + if (of_property_read_bool(node, "qca,rgmii56-1-8v")) + mask |= QCA8K_MAC_PWR_RGMII1_1_8V; + + if (mask) { + ret = qca8k_rmw(priv, QCA8K_REG_MAC_PWR_SEL, + QCA8K_MAC_PWR_RGMII0_1_8V | + QCA8K_MAC_PWR_RGMII1_1_8V, + mask); + } + + return ret; +} + static int qca8k_setup(struct dsa_switch *ds) { @@ -979,6 +1002,10 @@ qca8k_setup(struct dsa_switch *ds) if (ret) return ret; + ret = qca8k_setup_mac_pwr_sel(priv); + if (ret) + return ret; + /* Enable CPU Port */ ret = qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0, QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN); diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h index ed3b05ad6745..fc7db94cc0c9 100644 --- a/drivers/net/dsa/qca8k.h +++ b/drivers/net/dsa/qca8k.h @@ -100,6 +100,11 @@ #define QCA8K_SGMII_MODE_CTRL_PHY (1 << 22) #define QCA8K_SGMII_MODE_CTRL_MAC (2 << 22) +/* MAC_PWR_SEL registers */ +#define QCA8K_REG_MAC_PWR_SEL 0x0e4 +#define QCA8K_MAC_PWR_RGMII1_1_8V BIT(18) +#define QCA8K_MAC_PWR_RGMII0_1_8V BIT(19) + /* EEE control registers */ #define QCA8K_REG_EEE_CTRL 0x100 #define QCA8K_REG_EEE_CTRL_LPI_EN(_i) ((_i + 1) * 2) From patchwork Fri Oct 8 00:22:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12543929 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9A0E5C433EF for ; Fri, 8 Oct 2021 00:23:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 85DD8610A5 for ; Fri, 8 Oct 2021 00:23:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242786AbhJHAZJ (ORCPT ); Thu, 7 Oct 2021 20:25:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53342 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242209AbhJHAZC (ORCPT ); Thu, 7 Oct 2021 20:25:02 -0400 Received: from mail-ed1-x52f.google.com (mail-ed1-x52f.google.com [IPv6:2a00:1450:4864:20::52f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 910B5C061570; Thu, 7 Oct 2021 17:23:07 -0700 (PDT) Received: by mail-ed1-x52f.google.com with SMTP id v18so29883401edc.11; Thu, 07 Oct 2021 17:23:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=rqO0yPNBy5TWB1TUeZd4pFzS3JsFbEWZgR5hHP+FSk8=; b=gVKHp9xp2Ka5kd3iYD0qfWQnlMHvLiBDUg71dufHUlLBoVcVKLPNqpxt3jTzFovxWT VS5EdjOnbf4BnewZLAX3MHKemC1iscsK/w4u6QQsJPdkWrfi/av021TxxFFXQhTQIey1 35ZI3D1xQerrv4DtcoVfWK/hauZUynO/RWBGM+M+SskjYE21SKHaEeZnYGvr4WiwfmFs 0XwJft9Ut0DxY5dZBxsA6JqRGaouMcnmGY1bLwT6/WKyN8WSl522TsHS08uTdagnS7BX jTsFEbY8BHIhI5qskgg6GIqeFgmzm5/Qy9PP3T1ViuIAH3pLi0cvqduzYMtm//86slMB sINg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rqO0yPNBy5TWB1TUeZd4pFzS3JsFbEWZgR5hHP+FSk8=; b=1TkNJT2hZZfQXddNclWKTj4ukNHRGM48JXw11qBJXXAM4XWsNeSk01DMg4aSktNfKA JGX0rLa3qoUia0exKLOmOMO9YPBkG3lV6Tpv2lvNrJYZlMV8sfYR+CunuiSDT7w0WSdL F+I/0BZcNVtsQKMiSR3Gb/I7Fw03FEBfGcxnXZrMA86SjI2WUvbFT/AXWfldmE7acA+X 4G9t2jXfMDWmI2QaE1qKoSEFvyvHo5Enlt+VJojkLBPi5MBUoxftqxxN5B7RPdaV2fwZ upWX6Mb+T+gb+VUrmtjYmXXIqWKa1iGHNZAF4yULqNRdH/ixV1B2razp2SiGJPlVL1bO xyew== X-Gm-Message-State: AOAM530UcUK5Cn3UtJKW25wWtum25w5CZLbBPipTAVla5mKKLBQq7AG2 b7+N1CiV3dtuuzWHU1w7POY= X-Google-Smtp-Source: ABdhPJyTx6syZ3ET42u53ZhlzuNJDeJjevq5fFXt46yW0HAbEqozQAeZfE1enBikfidqWcBUQ1delQ== X-Received: by 2002:a05:6402:4248:: with SMTP id g8mr10400115edb.91.1633652586094; Thu, 07 Oct 2021 17:23:06 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id ke12sm308592ejc.32.2021.10.07.17.23.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Oct 2021 17:23:05 -0700 (PDT) From: Ansuel Smith To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Heiner Kallweit , Russell King , Ansuel Smith , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [net-next PATCH v2 06/15] dt-bindings: net: dsa: qca8k: document rgmii_1_8v bindings Date: Fri, 8 Oct 2021 02:22:16 +0200 Message-Id: <20211008002225.2426-7-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211008002225.2426-1-ansuelsmth@gmail.com> References: <20211008002225.2426-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Document new qca,rgmii0_1_8v and qca,rgmii56_1_8v needed to setup mac_pwr_sel register for qca8337 switch. Specific the use of this binding that is used only in qca8337 and not in qca8327. Signed-off-by: Ansuel Smith --- Documentation/devicetree/bindings/net/dsa/qca8k.txt | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/net/dsa/qca8k.txt b/Documentation/devicetree/bindings/net/dsa/qca8k.txt index 8c73f67c43ca..9383d6bf2426 100644 --- a/Documentation/devicetree/bindings/net/dsa/qca8k.txt +++ b/Documentation/devicetree/bindings/net/dsa/qca8k.txt @@ -13,6 +13,14 @@ Required properties: Optional properties: - reset-gpios: GPIO to be used to reset the whole device +- qca,rgmii0-1-8v: Set the internal regulator to supply 1.8v for MAC0 port. + This is needed for qca8337 and toggles the supply voltage + from 1.5v to 1.8v. For the specific regs it was observed + that this is needed only for ipq8064 and ipq8065 target. +- qca,rgmii56-1-8v: Set the internal regulator to supply 1.8v for MAC5/6 port. + This is needed for qca8337 and toggles the supply voltage + from 1.5v to 1.8v. For the specific regs it was observed + that this is needed only for ipq8065 target. Subnodes: From patchwork Fri Oct 8 00:22:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12543927 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 27A60C4332F for ; Fri, 8 Oct 2021 00:23:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0FE7761152 for ; Fri, 8 Oct 2021 00:23:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242457AbhJHAZI (ORCPT ); Thu, 7 Oct 2021 20:25:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53324 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242497AbhJHAZD (ORCPT ); Thu, 7 Oct 2021 20:25:03 -0400 Received: from mail-ed1-x52d.google.com (mail-ed1-x52d.google.com [IPv6:2a00:1450:4864:20::52d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 88CEEC06176A; Thu, 7 Oct 2021 17:23:08 -0700 (PDT) Received: by mail-ed1-x52d.google.com with SMTP id y12so16318831eda.4; Thu, 07 Oct 2021 17:23:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=USBq3mBDytFzvMpNFzB7I53AgldzT9pGMAwrnP8ri/M=; b=VWZTTbiJNeU8R7qBvRowwRBG44FXdSoEQg0dNuhrDhW9F8JuZskLCKc7l91cOY/a5a /PwG8WErO/sHpB31cPbpT8QU+t7h5KasK++qtAQI9cI6hupXmnybX3z6eTn7dtd68bp+ pxPDuOsMupqoNrZ9MC3fwjs9agttzhRfZTwyzSFO6x7B/Uka2XuX3PXk/Cb/6fX39Vkc 9Jt8lXkgDKEdH0gbztcNpnMSHQa+U9qm/oZC5tXwoUX0lc5eybjI/VZsBKNQFyKxRvv8 UmywySH2IvBSVOR8IHn+6bJDsVTX7BKDU2b1VddeOn6g12cTRyLTP8nHZO6n5U9vxtNu KlmQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=USBq3mBDytFzvMpNFzB7I53AgldzT9pGMAwrnP8ri/M=; b=lk5JKWzizEnI00+YVIA30ujHt2vyTXU+UiWiXmycuT116xX8xz1N3T9xMI7l8FsZc8 mZ3AL4p6s2UulUCvMsy/Oqs+rJ9+8G6BmuGYFR+GbhEEoveZ846+GyGk200D/1+6wKlN XuB07yIGdzZqv7iGa5aJnu7CdHXVcmCKQhKmlHZqH1ECGg+ci4sUrnRsyS7/1XNJk2mS qMwTgEBi+U3fM8YSsbXTsdObP2G7lLx2xI11KxVpda9hOH84C6idXKn79/GXYtnomtFx gZHbj6efcZjlODyVIs1fk1caOuA6luob1I4dBl9ubltcTrmJL+B984tEHzLuzPa3UlmS krdQ== X-Gm-Message-State: AOAM532pDrhaEal09YLraV+NOhOtZrU5S9JeplWjyyZHZYwhXsaTjnIE ggpdmEJijMwOakcBmLYsmw4= X-Google-Smtp-Source: ABdhPJyH2M+r5qpQKz2JGLX1qgvghOiFWJmyfSmwmk9BHy2BARE1cUGhFUXIPIlrXT+WKlsSBNv2lA== X-Received: by 2002:a05:6402:2793:: with SMTP id b19mr10462345ede.80.1633652587071; Thu, 07 Oct 2021 17:23:07 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id ke12sm308592ejc.32.2021.10.07.17.23.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Oct 2021 17:23:06 -0700 (PDT) From: Ansuel Smith To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Heiner Kallweit , Russell King , Ansuel Smith , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Matthew Hagan Subject: [net-next PATCH v2 07/15] net: dsa: qca8k: add support for mac6_exchange, sgmii falling edge Date: Fri, 8 Oct 2021 02:22:17 +0200 Message-Id: <20211008002225.2426-8-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211008002225.2426-1-ansuelsmth@gmail.com> References: <20211008002225.2426-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Some device set the switch to exchange the mac0 port with mac6 port. Add support for this in the qca8k driver. Also add support for SGMII rx/tx clock falling edge. This is only present for pad0, pad5 and pad6 have these bit reserved from Documentation. Signed-off-by: Matthew Hagan Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 33 +++++++++++++++++++++++++++++++++ drivers/net/dsa/qca8k.h | 3 +++ 2 files changed, 36 insertions(+) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index 5bce7ac4dea7..3a040a3ed58e 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -973,6 +973,34 @@ qca8k_setup_mac_pwr_sel(struct qca8k_priv *priv) return ret; } +static int +qca8k_setup_port0_pad_ctrl_reg(struct qca8k_priv *priv) +{ + struct device_node *node = priv->dev->of_node; + u32 mask = 0; + int ret = 0; + + /* Swap MAC0-MAC6 */ + if (of_property_read_bool(node, "qca,mac6-exchange")) + mask |= QCA8K_PORT0_PAD_CTRL_MAC06_EXCHG; + + /* SGMII Clock phase configuration */ + if (of_property_read_bool(node, "qca,sgmii-rxclk-falling-edge")) + mask |= QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE; + + if (of_property_read_bool(node, "qca,sgmii-txclk-falling-edge")) + mask |= QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE; + + if (mask) + ret = qca8k_rmw(priv, QCA8K_REG_PORT0_PAD_CTRL, + QCA8K_PORT0_PAD_CTRL_MAC06_EXCHG | + QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE | + QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE, + mask); + + return ret; +} + static int qca8k_setup(struct dsa_switch *ds) { @@ -1006,6 +1034,11 @@ qca8k_setup(struct dsa_switch *ds) if (ret) return ret; + /* Configure additional PORT0_PAD_CTRL properties */ + ret = qca8k_setup_port0_pad_ctrl_reg(priv); + if (ret) + return ret; + /* Enable CPU Port */ ret = qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0, QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN); diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h index fc7db94cc0c9..3fded69a6839 100644 --- a/drivers/net/dsa/qca8k.h +++ b/drivers/net/dsa/qca8k.h @@ -35,6 +35,9 @@ #define QCA8K_MASK_CTRL_DEVICE_ID_MASK GENMASK(15, 8) #define QCA8K_MASK_CTRL_DEVICE_ID(x) ((x) >> 8) #define QCA8K_REG_PORT0_PAD_CTRL 0x004 +#define QCA8K_PORT0_PAD_CTRL_MAC06_EXCHG BIT(31) +#define QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE BIT(19) +#define QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE BIT(18) #define QCA8K_REG_PORT5_PAD_CTRL 0x008 #define QCA8K_REG_PORT6_PAD_CTRL 0x00c #define QCA8K_PORT_PAD_RGMII_EN BIT(26) From patchwork Fri Oct 8 00:22:18 2021 Content-Type: text/plain; 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[93.42.71.246]) by smtp.googlemail.com with ESMTPSA id ke12sm308592ejc.32.2021.10.07.17.23.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Oct 2021 17:23:07 -0700 (PDT) From: Ansuel Smith To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Heiner Kallweit , Russell King , Ansuel Smith , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Matthew Hagan Subject: [net-next PATCH v2 08/15] dt-bindings: net: dsa: qca8k: Add MAC swap and clock phase properties Date: Fri, 8 Oct 2021 02:22:18 +0200 Message-Id: <20211008002225.2426-9-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211008002225.2426-1-ansuelsmth@gmail.com> References: <20211008002225.2426-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Add names and decriptions of additional PORT0_PAD_CTRL properties. Document new binding qca,mac6_exchange that exchange the mac0 port with mac6. qca,sgmii-(rx|tx)clk-falling-edge are for setting the respective clock phase to failling edge. Signed-off-by: Matthew Hagan Signed-off-by: Ansuel Smith --- Documentation/devicetree/bindings/net/dsa/qca8k.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/net/dsa/qca8k.txt b/Documentation/devicetree/bindings/net/dsa/qca8k.txt index 9383d6bf2426..208ee5bc1bbb 100644 --- a/Documentation/devicetree/bindings/net/dsa/qca8k.txt +++ b/Documentation/devicetree/bindings/net/dsa/qca8k.txt @@ -13,6 +13,11 @@ Required properties: Optional properties: - reset-gpios: GPIO to be used to reset the whole device +- qca,mac6-exchange: Internally swap MAC0 with MAC6. +- qca,sgmii-rxclk-falling-edge: Set the receive clock phase to falling edge. + Mostly used in qca8327 with CPU port 0 set to + sgmii. +- qca,sgmii-txclk-falling-edge: Set the transmit clock phase to falling edge. - qca,rgmii0-1-8v: Set the internal regulator to supply 1.8v for MAC0 port. This is needed for qca8337 and toggles the supply voltage from 1.5v to 1.8v. For the specific regs it was observed From patchwork Fri Oct 8 00:22:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12543939 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DFCF3C4332F for ; Fri, 8 Oct 2021 00:23:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CC61760F43 for ; Fri, 8 Oct 2021 00:23:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242997AbhJHAZZ (ORCPT ); Thu, 7 Oct 2021 20:25:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53334 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242642AbhJHAZF (ORCPT ); Thu, 7 Oct 2021 20:25:05 -0400 Received: from mail-ed1-x530.google.com (mail-ed1-x530.google.com [IPv6:2a00:1450:4864:20::530]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B78E1C061570; Thu, 7 Oct 2021 17:23:10 -0700 (PDT) Received: by mail-ed1-x530.google.com with SMTP id i20so13531486edj.10; Thu, 07 Oct 2021 17:23:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=A7NLR81J3K/d4wqEfrshrrHqYxKBxx0VTZbNQWYxYys=; b=cRnOMixkGAmSanFD6EyEIfXqU8w8IGgyIV6bonGoYy7ZnWBcKz9zRyNPajNlfXhNwg RUpPlh5DPPEDKXM9obJds3wsQfAArYwfOBQ1tH0wU5gWjIycTmiRgyBmZVpU/xtM/nN/ Zyaq2qUp7m0dPZP/3fA1zuwGorDeTViA5Lko44sD5iJox2GqvfrSz+p7L1xwra8zONlV 2AJ5hwWKRM7B/8PYrNBz/vi/mLGAHSUOcVFi5p5asGQfXnYBCKRaazOSpCM9oMQPxREt BQ0LaDcZozAVTf5Y6ElO4khThx9UVvPJ7wRIUNCK4v8YoEW0aAR2v6BpG7i7cm6QoLst 4R/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=A7NLR81J3K/d4wqEfrshrrHqYxKBxx0VTZbNQWYxYys=; b=Y6o6nl2KDwYQvjjSlFmV2fF/l5i8AAX5JbEdaW92KwIIv6BknysrrC8/IxqzRh1JMX L6NsgEfOqT3LcHeW6/IkQ05buY+sYJf+QvUdoY6+w1Ccw9JhXMZzF5lyegWsV9LUr/zG xVVdcif8fYCWKjZPyECw3rNxPlydESgsIxvAzqNnLzmkixglza0yuUsGfWTTS89FZsfX TyYxgak0+CRCZBnUdZy6Y686+FM98qqLuwPD5ZVnAzmKpDszV9Lqn8VA1vfoKsKB9ElE dnZLDguvH83ci8OLTC6AdA36vqdA1uvl7zxLeBWhQbMLSn10M2n54sf1AXNL5tbaGoEw w9Mg== X-Gm-Message-State: AOAM532UPprj7MhhtxHnmUdQsr1wUnp07KOT4MP//8T0FHJXcG9N6g+D teoiEhb36ha83V9ycYFqTgU= X-Google-Smtp-Source: ABdhPJzigErsVfgazb4ZZeSoCuf0ne2ideo7dxNzkn2tU0UOOcD1mQBl6bWE8npXCOj/l2FQRep6kg== X-Received: by 2002:a50:e005:: with SMTP id e5mr10374998edl.211.1633652589226; Thu, 07 Oct 2021 17:23:09 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id ke12sm308592ejc.32.2021.10.07.17.23.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Oct 2021 17:23:08 -0700 (PDT) From: Ansuel Smith To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Heiner Kallweit , Russell King , Ansuel Smith , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [net-next PATCH v2 09/15] net: dsa: qca8k: move rgmii delay detection to phylink mac_config Date: Fri, 8 Oct 2021 02:22:19 +0200 Message-Id: <20211008002225.2426-10-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211008002225.2426-1-ansuelsmth@gmail.com> References: <20211008002225.2426-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Future proof commit. This switch have 2 CPU port and one valid configuration is first CPU port set to sgmii and second CPU port set to regmii-id. The current implementation detects delay only for CPU port zero set to rgmii and doesn't count any delay set in a secondary CPU port. Drop the current delay scan function and move it to the phylink mac_config to generilize and implicitly add support for secondary CPU port set to rgmii-id. Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 122 +++++++++++++++------------------------- drivers/net/dsa/qca8k.h | 2 - 2 files changed, 45 insertions(+), 79 deletions(-) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index 3a040a3ed58e..05ecec4ebc01 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -888,68 +888,6 @@ qca8k_setup_mdio_bus(struct qca8k_priv *priv) return 0; } -static int -qca8k_setup_of_rgmii_delay(struct qca8k_priv *priv) -{ - struct device_node *port_dn; - phy_interface_t mode; - struct dsa_port *dp; - u32 val; - - /* CPU port is already checked */ - dp = dsa_to_port(priv->ds, 0); - - port_dn = dp->dn; - - /* Check if port 0 is set to the correct type */ - of_get_phy_mode(port_dn, &mode); - if (mode != PHY_INTERFACE_MODE_RGMII_ID && - mode != PHY_INTERFACE_MODE_RGMII_RXID && - mode != PHY_INTERFACE_MODE_RGMII_TXID) { - return 0; - } - - switch (mode) { - case PHY_INTERFACE_MODE_RGMII_ID: - case PHY_INTERFACE_MODE_RGMII_RXID: - if (of_property_read_u32(port_dn, "rx-internal-delay-ps", &val)) - val = 2; - else - /* Switch regs accept value in ns, convert ps to ns */ - val = val / 1000; - - if (val > QCA8K_MAX_DELAY) { - dev_err(priv->dev, "rgmii rx delay is limited to a max value of 3ns, setting to the max value"); - val = 3; - } - - priv->rgmii_rx_delay = val; - /* Stop here if we need to check only for rx delay */ - if (mode != PHY_INTERFACE_MODE_RGMII_ID) - break; - - fallthrough; - case PHY_INTERFACE_MODE_RGMII_TXID: - if (of_property_read_u32(port_dn, "tx-internal-delay-ps", &val)) - val = 1; - else - /* Switch regs accept value in ns, convert ps to ns */ - val = val / 1000; - - if (val > QCA8K_MAX_DELAY) { - dev_err(priv->dev, "rgmii tx delay is limited to a max value of 3ns, setting to the max value"); - val = 3; - } - - priv->rgmii_tx_delay = val; - break; - default: - return 0; - } - - return 0; -} - static int qca8k_setup_mac_pwr_sel(struct qca8k_priv *priv) { @@ -1026,10 +964,6 @@ qca8k_setup(struct dsa_switch *ds) if (ret) return ret; - ret = qca8k_setup_of_rgmii_delay(priv); - if (ret) - return ret; - ret = qca8k_setup_mac_pwr_sel(priv); if (ret) return ret; @@ -1201,7 +1135,8 @@ qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, const struct phylink_link_state *state) { struct qca8k_priv *priv = ds->priv; - u32 reg, val; + struct dsa_port *dp; + u32 reg, val, delay; int ret; switch (port) { @@ -1252,17 +1187,50 @@ qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, case PHY_INTERFACE_MODE_RGMII_ID: case PHY_INTERFACE_MODE_RGMII_TXID: case PHY_INTERFACE_MODE_RGMII_RXID: - /* RGMII_ID needs internal delay. This is enabled through - * PORT5_PAD_CTRL for all ports, rather than individual port - * registers + dp = dsa_to_port(ds, port); + val = QCA8K_PORT_PAD_RGMII_EN; + + if (state->interface == PHY_INTERFACE_MODE_RGMII_ID || + state->interface == PHY_INTERFACE_MODE_RGMII_TXID) { + if (of_property_read_u32(dp->dn, "tx-internal-delay-ps", &delay)) + delay = 1; + else + /* Switch regs accept value in ns, convert ps to ns */ + delay = delay / 1000; + + if (delay > QCA8K_MAX_DELAY) { + dev_err(priv->dev, "rgmii tx delay is limited to a max value of 3ns, setting to the max value"); + delay = 3; + } + + val |= QCA8K_PORT_PAD_RGMII_TX_DELAY(delay) | + QCA8K_PORT_PAD_RGMII_TX_DELAY_EN; + } + + if (state->interface == PHY_INTERFACE_MODE_RGMII_ID || + state->interface == PHY_INTERFACE_MODE_RGMII_RXID) { + if (of_property_read_u32(dp->dn, "rx-internal-delay-ps", &delay)) + delay = 2; + else + /* Switch regs accept value in ns, convert ps to ns */ + delay = delay / 1000; + + if (delay > QCA8K_MAX_DELAY) { + dev_err(priv->dev, "rgmii rx delay is limited to a max value of 3ns, setting to the max value"); + delay = 3; + } + + val |= QCA8K_PORT_PAD_RGMII_RX_DELAY(delay) | + QCA8K_PORT_PAD_RGMII_RX_DELAY_EN; + } + + /* Set RGMII delay based on the selected values */ + qca8k_write(priv, reg, val); + + /* QCA8337 requires to set rgmii rx delay for all ports. + * This is enabled through PORT5_PAD_CTRL for all ports, + * rather than individual port registers. */ - qca8k_write(priv, reg, - QCA8K_PORT_PAD_RGMII_EN | - QCA8K_PORT_PAD_RGMII_TX_DELAY(priv->rgmii_tx_delay) | - QCA8K_PORT_PAD_RGMII_RX_DELAY(priv->rgmii_rx_delay) | - QCA8K_PORT_PAD_RGMII_TX_DELAY_EN | - QCA8K_PORT_PAD_RGMII_RX_DELAY_EN); - /* QCA8337 requires to set rgmii rx delay */ if (priv->switch_id == QCA8K_ID_QCA8337) qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL, QCA8K_PORT_PAD_RGMII_RX_DELAY_EN); diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h index 3fded69a6839..a36ef43e3847 100644 --- a/drivers/net/dsa/qca8k.h +++ b/drivers/net/dsa/qca8k.h @@ -261,8 +261,6 @@ struct qca8k_match_data { struct qca8k_priv { u8 switch_id; u8 switch_revision; - u8 rgmii_tx_delay; - u8 rgmii_rx_delay; bool legacy_phy_port_mapping; struct regmap *regmap; struct mii_bus *bus; From patchwork Fri Oct 8 00:22:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12543941 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E9249C433EF for ; Fri, 8 Oct 2021 00:23:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D8E886109F for ; Fri, 8 Oct 2021 00:23:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243016AbhJHAZ0 (ORCPT ); Thu, 7 Oct 2021 20:25:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53368 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242668AbhJHAZG (ORCPT ); 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[93.42.71.246]) by smtp.googlemail.com with ESMTPSA id ke12sm308592ejc.32.2021.10.07.17.23.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Oct 2021 17:23:09 -0700 (PDT) From: Ansuel Smith To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Heiner Kallweit , Russell King , Ansuel Smith , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [net-next PATCH v2 10/15] net: dsa: qca8k: add explicit SGMII PLL enable Date: Fri, 8 Oct 2021 02:22:20 +0200 Message-Id: <20211008002225.2426-11-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211008002225.2426-1-ansuelsmth@gmail.com> References: <20211008002225.2426-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Support enabling PLL on the SGMII CPU port. Some device require this special configuration or no traffic is transmitted and the switch doesn't work at all. A dedicated binding is added to the CPU node port to apply the correct reg on mac config. Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index 05ecec4ebc01..8917bb154e8f 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -1237,6 +1237,8 @@ qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, break; case PHY_INTERFACE_MODE_SGMII: case PHY_INTERFACE_MODE_1000BASEX: + dp = dsa_to_port(ds, port); + /* Enable SGMII on the port */ qca8k_write(priv, reg, QCA8K_PORT_PAD_SGMII_EN); @@ -1255,8 +1257,11 @@ qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, if (ret) return; - val |= QCA8K_SGMII_EN_PLL | QCA8K_SGMII_EN_RX | - QCA8K_SGMII_EN_TX | QCA8K_SGMII_EN_SD; + val |= QCA8K_SGMII_EN_SD; + + if (of_property_read_bool(dp->dn, "qca,sgmii-enable-pll")) + val |= QCA8K_SGMII_EN_PLL | QCA8K_SGMII_EN_RX | + QCA8K_SGMII_EN_TX; if (dsa_is_cpu_port(ds, port)) { /* CPU port, we're talking to the CPU MAC, be a PHY */ From patchwork Fri Oct 8 00:22:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12543943 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 88D68C433EF for ; Fri, 8 Oct 2021 00:23:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 71223610A5 for ; Fri, 8 Oct 2021 00:23:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242755AbhJHAZf (ORCPT ); Thu, 7 Oct 2021 20:25:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53326 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242778AbhJHAZJ (ORCPT ); Thu, 7 Oct 2021 20:25:09 -0400 Received: from mail-ed1-x52c.google.com (mail-ed1-x52c.google.com [IPv6:2a00:1450:4864:20::52c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B141FC061773; Thu, 7 Oct 2021 17:23:12 -0700 (PDT) Received: by mail-ed1-x52c.google.com with SMTP id y12so16319308eda.4; Thu, 07 Oct 2021 17:23:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=7JaUG9XOtD68taTwa7qpisFGXs4Xezjwxb6ClFFnC0M=; b=ScpPoxpotHZlf9VuAI4voqjYT+NUhg90FxRgRfuK5XJmBbpC4hXlSR75ZMIYcTxTbc Bb5ew/CTOj3nUrwbxe3xZfwxlK+JfRAwT1xHq4IxqrMLFUdAOEkhJ4JYdI156Rj59Q1h N6v98812LbSeWUqUVaRA1RfZAtBbYfZUNwkV2EeEFrjBjupzqBCnDiyz7bIpMlcQWqah g3AG/ZmX33ReOrvxRVxA6UXQnlvexdrPlNnESTWXeLREqJMjIDkfdxudAD4B9uqIGP+L UDtg5zApNtEI7+L/lfZPvhAcWfOCPfEQjgnZ4hRsCriID4rOw/QdQQXwQbZnTQR1OGQt QQUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7JaUG9XOtD68taTwa7qpisFGXs4Xezjwxb6ClFFnC0M=; b=3s8GeAv0Ad5O95lJA7vzlun2oRscBjPr3ST1aJ4bHLbk7HTPYgsd3BEsDkF69xQeqx yLgxO9emUHRe26cvMkpEiJxn3rjhM7xCRn9E3pgYAOnrOR1+rmg7aBZ91Pl3yeaobo3/ oN3hh/WCLB4W9AwJGxzNCsPEKj7+Z1TbrnHJvCUUkOgRvPyrV24TvU09DqhuE8iSTDPD 1NMbI0+HtFWUGyLapvXr30wkzv7HafPNwlw7an1UnLBL4d+zgVIZ5CwkJaHvHRAoUgWC fFQ/TcR1/6rVrqcxL4ysrQFD2DSi+o0+FKGXXokGZNeIF4yzxHnaBgqovv7ZAH5iaZwv HZfQ== X-Gm-Message-State: AOAM532zNcZ8WGffa24n/C0aK5m7P+RB+qLU3/ywB9TNFe33Ase33x9/ goszOlsz0in9av9r3SuXMq46mkrl0OM= X-Google-Smtp-Source: ABdhPJzK7UKENaG96vxEfsfv4vQaH6ehc41I0AWUu9arPTJohl2Qgr7xzvxfsTnqmPqj7ioFapDYqw== X-Received: by 2002:a17:906:b183:: with SMTP id w3mr146748ejy.394.1633652591212; Thu, 07 Oct 2021 17:23:11 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id ke12sm308592ejc.32.2021.10.07.17.23.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Oct 2021 17:23:11 -0700 (PDT) From: Ansuel Smith To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Heiner Kallweit , Russell King , Ansuel Smith , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [net-next PATCH v2 11/15] dt-bindings: net: dsa: qca8k: Document qca,sgmii-enable-pll Date: Fri, 8 Oct 2021 02:22:21 +0200 Message-Id: <20211008002225.2426-12-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211008002225.2426-1-ansuelsmth@gmail.com> References: <20211008002225.2426-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Document qca,sgmii-enable-pll binding used in the CPU nodes to enable SGMII PLL on MAC config. Signed-off-by: Ansuel Smith --- Documentation/devicetree/bindings/net/dsa/qca8k.txt | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/net/dsa/qca8k.txt b/Documentation/devicetree/bindings/net/dsa/qca8k.txt index 208ee5bc1bbb..b9cccb657373 100644 --- a/Documentation/devicetree/bindings/net/dsa/qca8k.txt +++ b/Documentation/devicetree/bindings/net/dsa/qca8k.txt @@ -50,6 +50,12 @@ A CPU port node has the following optional node: managed entity. See Documentation/devicetree/bindings/net/fixed-link.txt for details. +- qca,sgmii-enable-pll : For SGMII CPU port, explicitly enable PLL, TX and RX + chain along with Signal Detection. + This should NOT be enabled for qca8327. + This can be required for qca8337 switch with revision 2. + With CPU port set to sgmii and qca8337 it is advised + to set this unless a communication problem is observed. For QCA8K the 'fixed-link' sub-node supports only the following properties: From patchwork Fri Oct 8 00:22:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12543945 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2C635C433F5 for ; Fri, 8 Oct 2021 00:23:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 173F5610A5 for ; Fri, 8 Oct 2021 00:23:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243190AbhJHAZk (ORCPT ); Thu, 7 Oct 2021 20:25:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53390 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242802AbhJHAZK (ORCPT ); Thu, 7 Oct 2021 20:25:10 -0400 Received: from mail-ed1-x52b.google.com (mail-ed1-x52b.google.com [IPv6:2a00:1450:4864:20::52b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BF23BC061779; Thu, 7 Oct 2021 17:23:13 -0700 (PDT) Received: by mail-ed1-x52b.google.com with SMTP id v18so29884115edc.11; Thu, 07 Oct 2021 17:23:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=9uS71E8R2dcbKXKSJMiz2qaBGN/UiL7YlhIAGtErbh4=; b=TvnBELhUFH7M074UI9ELiFkQzKjPmp+Z2dbbLI/k0E76Fqscg6wLkgdf8FSZ7aomqf rF27yUI4jnW2WCAfRRMaloL4sZ/AkA6KajIQINc/i7qOhC4jHUc3THeD4pv0XXfTDqlg zOTkPoyC6Yp0HpYUyw/9ERgADm7l+H0h3VZJBVgT8DoRjCEeTlZ9LswMQ6LfOddQ90Uh LHeiPuNz4QCW3o8Bn8PUWeQrS/NZRU+PAPqZOZSa8lcVxWJkBAtj0ddXUxL7PTDl4+i+ bsOg6hLzqb8DPBG4ltkYMfm3WAuW8EkOXcojZga90pGlPaQlU1/lAm/nIUGONdH85SR0 R0dg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9uS71E8R2dcbKXKSJMiz2qaBGN/UiL7YlhIAGtErbh4=; b=bJxvVo4SEnzssPhsB34sKvueoMr4HoDsIIbbZeYe6ADM+pwm771cIlTaEcZTTNKNbl kqI4vNu0G1Da86cZnX52RlLD7zjGZmgmHNTkgJv35wrjKP7+w5lInvRPJLXthqel2Jls iLtPhJRqf50VrwFpTwWI0NUWhweLYq0MtX+kxJNM7VtXQnh0k5FcOR7E34y2lE/0tvU9 FnSpJR7aeK3ffTpvNDnMHn9iz8WEbl+k0KyGc7STZGygOCJtDUinjErJPPSzPWLeDu8i ZjYbuQVXzbeQUrM38dM39Y/K0QYHna9YFkLKXL86rKBYzIzkJRo+k8vlvaFYCEtDs1Pz nqRg== X-Gm-Message-State: AOAM5335hFYJXWVN/JFsG5p+B7kIMz3lbiZ8JK23ecHtk3fnFSoEyc4b aNPZSDH4mNFhbRMPqG1JdGE= X-Google-Smtp-Source: ABdhPJz2QVbpshW8m/ONmVawn2kizV1P4AIa3BMZJunQkiVPMdAQ8ydpfTitq3YYCaBGQ5V1I0YHfw== X-Received: by 2002:a17:906:480a:: with SMTP id w10mr165033ejq.262.1633652592162; Thu, 07 Oct 2021 17:23:12 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id ke12sm308592ejc.32.2021.10.07.17.23.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Oct 2021 17:23:11 -0700 (PDT) From: Ansuel Smith To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Heiner Kallweit , Russell King , Ansuel Smith , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [net-next PATCH v2 12/15] drivers: net: dsa: qca8k: add support for pws config reg Date: Fri, 8 Oct 2021 02:22:22 +0200 Message-Id: <20211008002225.2426-13-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211008002225.2426-1-ansuelsmth@gmail.com> References: <20211008002225.2426-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Some qca8327 switch require to force the ignore of power on sel strapping. Some switch require to set the led open drain mode in regs instead of using strapping. While most of the device implements this using the correct way using pin strapping, there are still some broken device that require to be set using sw regs. Introduce a new binding and support these special configuration. As led open drain require to ignore pin strapping to work, the probe fails with EINVAL error with incorrect configuration. Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 39 +++++++++++++++++++++++++++++++++++++++ drivers/net/dsa/qca8k.h | 6 ++++++ 2 files changed, 45 insertions(+) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index 8917bb154e8f..0dc921cfb8c6 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -939,6 +939,41 @@ qca8k_setup_port0_pad_ctrl_reg(struct qca8k_priv *priv) return ret; } +static int +qca8k_setup_of_pws_reg(struct qca8k_priv *priv) +{ + struct device_node *node = priv->dev->of_node; + u32 val = 0; + int ret; + + /* QCA8327 require to set to the correct mode. + * His bigger brother QCA8328 have the 172 pin layout. + * Should be applied by default but we set this just to make sure. + */ + if (priv->switch_id == QCA8K_ID_QCA8327) { + ret = qca8k_rmw(priv, QCA8K_REG_PWS, QCA8327_PWS_PACKAGE148_EN, + QCA8327_PWS_PACKAGE148_EN); + if (ret) + return ret; + } + + if (of_property_read_bool(node, "qca,ignore-power-on-sel")) + val |= QCA8K_PWS_POWER_ON_SEL; + + if (of_property_read_bool(node, "qca,led-open-drain")) { + if (!(val & QCA8K_PWS_POWER_ON_SEL)) { + dev_err(priv->dev, "qca,led-open-drain require qca,ignore-power-on-sel to be set."); + return -EINVAL; + } + + val |= QCA8K_PWS_LED_OPEN_EN_CSR; + } + + return qca8k_rmw(priv, QCA8K_REG_PWS, + QCA8K_PWS_LED_OPEN_EN_CSR | QCA8K_PWS_POWER_ON_SEL, + val); +} + static int qca8k_setup(struct dsa_switch *ds) { @@ -964,6 +999,10 @@ qca8k_setup(struct dsa_switch *ds) if (ret) return ret; + ret = qca8k_setup_of_pws_reg(priv); + if (ret) + return ret; + ret = qca8k_setup_mac_pwr_sel(priv); if (ret) return ret; diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h index a36ef43e3847..2c98b133ec4f 100644 --- a/drivers/net/dsa/qca8k.h +++ b/drivers/net/dsa/qca8k.h @@ -48,6 +48,12 @@ #define QCA8K_MAX_DELAY 3 #define QCA8K_PORT_PAD_SGMII_EN BIT(7) #define QCA8K_REG_PWS 0x010 +#define QCA8K_PWS_POWER_ON_SEL BIT(31) +/* This reg is only valid for QCA832x and toggle the package + * type from 176 pin (by default) to 148 pin used on QCA8327 + */ +#define QCA8327_PWS_PACKAGE148_EN BIT(30) +#define QCA8K_PWS_LED_OPEN_EN_CSR BIT(24) #define QCA8K_PWS_SERDES_AEN_DIS BIT(7) #define QCA8K_REG_MODULE_EN 0x030 #define QCA8K_MODULE_EN_MIB BIT(0) From patchwork Fri Oct 8 00:22:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12543947 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BDC12C43219 for ; Fri, 8 Oct 2021 00:23:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A65A461354 for ; Fri, 8 Oct 2021 00:23:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243225AbhJHAZl (ORCPT ); Thu, 7 Oct 2021 20:25:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53318 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242801AbhJHAZK (ORCPT ); Thu, 7 Oct 2021 20:25:10 -0400 Received: from mail-ed1-x531.google.com (mail-ed1-x531.google.com [IPv6:2a00:1450:4864:20::531]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 983B8C06177A; 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[93.42.71.246]) by smtp.googlemail.com with ESMTPSA id ke12sm308592ejc.32.2021.10.07.17.23.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Oct 2021 17:23:12 -0700 (PDT) From: Ansuel Smith To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Heiner Kallweit , Russell King , Ansuel Smith , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [net-next PATCH v2 13/15] dt-bindings: net: dsa: qca8k: document open drain binding Date: Fri, 8 Oct 2021 02:22:23 +0200 Message-Id: <20211008002225.2426-14-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211008002225.2426-1-ansuelsmth@gmail.com> References: <20211008002225.2426-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Document new binding qca,power_on_sel used to enable Power-on-strapping select reg and qca,led_open_drain to set led to open drain mode. Signed-off-by: Ansuel Smith --- Documentation/devicetree/bindings/net/dsa/qca8k.txt | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Documentation/devicetree/bindings/net/dsa/qca8k.txt b/Documentation/devicetree/bindings/net/dsa/qca8k.txt index b9cccb657373..9fb4db65907e 100644 --- a/Documentation/devicetree/bindings/net/dsa/qca8k.txt +++ b/Documentation/devicetree/bindings/net/dsa/qca8k.txt @@ -13,6 +13,17 @@ Required properties: Optional properties: - reset-gpios: GPIO to be used to reset the whole device +- qca,ignore-power-on-sel: Ignore power on pin strapping to configure led open + drain or eeprom presence. This is needed for broken + device that have wrong configuration or when the oem + decided to not use pin strapping and fallback to sw + regs. +- qca,led-open-drain: Set leds to open-drain mode. This require the + qca,ignore-power-on-sel to be set or the driver will fail + to probe. This is needed if the oem doesn't use pin + strapping to set this mode and prefer to set it using sw + regs. The pin strapping related to led open drain mode is + the pin B68 for QCA832x and B49 for QCA833x - qca,mac6-exchange: Internally swap MAC0 with MAC6. - qca,sgmii-rxclk-falling-edge: Set the receive clock phase to falling edge. Mostly used in qca8327 with CPU port 0 set to From patchwork Fri Oct 8 00:22:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12543949 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 55CF6C433FE for ; Fri, 8 Oct 2021 00:23:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 40D4A610C7 for ; Fri, 8 Oct 2021 00:23:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243253AbhJHAZo (ORCPT ); Thu, 7 Oct 2021 20:25:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53336 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242809AbhJHAZK (ORCPT ); Thu, 7 Oct 2021 20:25:10 -0400 Received: from mail-ed1-x52c.google.com (mail-ed1-x52c.google.com [IPv6:2a00:1450:4864:20::52c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7FCB5C061755; Thu, 7 Oct 2021 17:23:15 -0700 (PDT) Received: by mail-ed1-x52c.google.com with SMTP id r18so29607788edv.12; Thu, 07 Oct 2021 17:23:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=BO1dGsbKRvbWMl2fcg8UVPlbMozPNRHZOtkiE2o15Cg=; b=IqE/HnX+Mo3zxnxxC1plciL/Ly9pYmzDh/15pFIatR4oiBQbsfglaOJkD/oL0klyvW BqN5tluUaqM+ayPObM6eZbsADVONAt4Q0WJ1oC43nYM41n87CRzTUtFeOBF19OdDZ218 ptUyfrL8uQNP/zrDnXOWJ5pd7ChkwPHej+O/mTpolu9xOtXEWib9UAoVYkoBtf5fQvyH vEaJVoIDJcW5ZXdunK9SlObP2m9Bm5xXd5naXQfV2GK8cPPfOf2gRPAdM8g8B+ukqb2I dcIZeZCw6etSR/QJkOIfaygeWuj/fe5QYkuqUkrFYmg4/8zhy3XiKcq081l7YqmBOT0f hyLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BO1dGsbKRvbWMl2fcg8UVPlbMozPNRHZOtkiE2o15Cg=; b=hf3bCnKB21eWn2sAeaXBV0rnOCjuCro4uegXdcczAC6cDBMXtViTN+mCi5TEGmhQ16 XpvZ8vwbn6S+74DOWR3Pzws6sjWXj+drzCDIrHtAXB8NM0dLj9fOGaHOjXWYdsN9DVWs d0Ap+oNmDRt4Ko/hTa0oIk65kdFPxVJYyZHqduJ2pBBfCq9HYAnsyVFDjnx9i8zZrH4F 7INL+7C6PG8aYEmNK2MFvNS8RNhEDBf14JKwNMWXas/8/VErlvH0RzaYOfrhJd0fywaO DMZrVROhCxIKAyxJT3jwVlNXDZzpQDEggWOA54ZWD8TkQbiY0Vd348Th8kVkuEPxkV2o cVsw== X-Gm-Message-State: AOAM530+zpuV6g3q1TOSSBU0I+JNexiOVuKuq6MrHg8Z8C7cUVIaIlTG 2Y1BMFxLamhq55UlZt+10qA= X-Google-Smtp-Source: ABdhPJzajTO3bpEEhiwi5OQ77tVTnIJxWbRfIRb8x5mvpl6tWGr/FK1WAn7FPf73PfuXhnHH5BtM9g== X-Received: by 2002:a17:906:31cf:: with SMTP id f15mr163204ejf.272.1633652594024; Thu, 07 Oct 2021 17:23:14 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id ke12sm308592ejc.32.2021.10.07.17.23.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Oct 2021 17:23:13 -0700 (PDT) From: Ansuel Smith To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Heiner Kallweit , Russell King , Ansuel Smith , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [net-next PATCH v2 14/15] drivers: net: dsa: qca8k: add support for QCA8328 Date: Fri, 8 Oct 2021 02:22:24 +0200 Message-Id: <20211008002225.2426-15-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211008002225.2426-1-ansuelsmth@gmail.com> References: <20211008002225.2426-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org QCA8328 switch is the bigger brother of the qca8327. Same regs different chip. Change the function to set the correct pin layout and introduce a new match_data to differentiate the 2 switch as they have the same ID and their internal PHY have the same ID. Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 19 ++++++++++++++++--- drivers/net/dsa/qca8k.h | 1 + 2 files changed, 17 insertions(+), 3 deletions(-) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index 0dc921cfb8c6..aae0cfcd0ce8 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -943,6 +943,7 @@ static int qca8k_setup_of_pws_reg(struct qca8k_priv *priv) { struct device_node *node = priv->dev->of_node; + const struct qca8k_match_data *data; u32 val = 0; int ret; @@ -951,8 +952,14 @@ qca8k_setup_of_pws_reg(struct qca8k_priv *priv) * Should be applied by default but we set this just to make sure. */ if (priv->switch_id == QCA8K_ID_QCA8327) { + data = of_device_get_match_data(priv->dev); + + /* Set the correct package of 148 pin for QCA8327 */ + if (data->reduced_package) + val |= QCA8327_PWS_PACKAGE148_EN; + ret = qca8k_rmw(priv, QCA8K_REG_PWS, QCA8327_PWS_PACKAGE148_EN, - QCA8327_PWS_PACKAGE148_EN); + val); if (ret) return ret; } @@ -1994,7 +2001,12 @@ static int qca8k_resume(struct device *dev) static SIMPLE_DEV_PM_OPS(qca8k_pm_ops, qca8k_suspend, qca8k_resume); -static const struct qca8k_match_data qca832x = { +static const struct qca8k_match_data qca8327 = { + .id = QCA8K_ID_QCA8327, + .reduced_package = true, +}; + +static const struct qca8k_match_data qca8328 = { .id = QCA8K_ID_QCA8327, }; @@ -2003,7 +2015,8 @@ static const struct qca8k_match_data qca833x = { }; static const struct of_device_id qca8k_of_match[] = { - { .compatible = "qca,qca8327", .data = &qca832x }, + { .compatible = "qca,qca8327", .data = &qca8327 }, + { .compatible = "qca,qca8328", .data = &qca8328 }, { .compatible = "qca,qca8334", .data = &qca833x }, { .compatible = "qca,qca8337", .data = &qca833x }, { /* sentinel */ }, diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h index 2c98b133ec4f..2d0c41e8cb75 100644 --- a/drivers/net/dsa/qca8k.h +++ b/drivers/net/dsa/qca8k.h @@ -262,6 +262,7 @@ struct ar8xxx_port_status { struct qca8k_match_data { u8 id; + bool reduced_package; }; struct qca8k_priv { From patchwork Fri Oct 8 00:22:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12543951 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DCB3DC433EF for ; Fri, 8 Oct 2021 00:24:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C6D59610A5 for ; Fri, 8 Oct 2021 00:24:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242791AbhJHAZy (ORCPT ); Thu, 7 Oct 2021 20:25:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53322 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242819AbhJHAZK (ORCPT ); Thu, 7 Oct 2021 20:25:10 -0400 Received: from mail-ed1-x536.google.com (mail-ed1-x536.google.com [IPv6:2a00:1450:4864:20::536]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7731BC061760; Thu, 7 Oct 2021 17:23:16 -0700 (PDT) Received: by mail-ed1-x536.google.com with SMTP id i20so13532203edj.10; Thu, 07 Oct 2021 17:23:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=7jirxa6ab8DNZBierFEzrcZahC2HB0KCCjUjPFf3EW4=; b=ml84SdRkTuctkU728YPxzQBhaMFUp60CeTuF5a3TAh/aLIduNAWF93zSTRusAO/v/5 QJ1UW9k/ykq6w2B99N+Y+TsoRJo5tzrdo8moTBnVkO8cv8CPPVTNX11w6JqrFOWgTPJG yrh3Vidc0Az/pJ77cmtyGg7uvLcsQuwp6svXWkBUqJt6XyUQ/Kw16rAAB8q9tWt274Gb aIPOpsEOrkAXf70IU49gK378ycE18UCEOHje42DLp7kYXVzejSu/cYhVK8vBsgH7A5sh d6bLqS9QUdYUMQyGq4dD3C673LArb0bMov0knMUYjzn39jTMW8tLCLkkb+r3ByBjy/jL 9vpw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7jirxa6ab8DNZBierFEzrcZahC2HB0KCCjUjPFf3EW4=; b=honvZxEHpLlU49brlV5epTZJFj/KX2p6rLYFgNUz22qadHpC7LPurloAdvkMAViWVE aCHgQNcalmeulqPVVms/3xhzsFqwFeZIVzqQHc0Gle118tUiI2xU5j8OYln3pGbzOJ25 AJJHgqVlWYjast0AY9a7+3/bzmz8IbjaaoxQ/m0auUH214RXgL3M+JoQOPL0yIWNysSm NcC9wgJsqjMBHZiV+oey/JRthqV0y4NWZkbE6G+xzPIPEzWFKwPPj6CDp6tFt7OA9lYv Uu+QMUXH+FaG5TDDLt4aEQFLaBON2zjDBd+hZIEazIQt3613FHUh1OVAFwyw/CZQlvWP ZL0w== X-Gm-Message-State: AOAM531WV0wGCY+Aq3+q7vXFOvvs57UDsTDWL/pfHOkhfFYKUcOipVe9 npxI4JHebi0vea+ZdblMeEk= X-Google-Smtp-Source: ABdhPJzCbot7lBz/ZxVq93Zt4RmtGo/NgMhcnAee/2oa/JTtlMjRP+Yo4+1/wHcoDH+4mJaxoOY//A== X-Received: by 2002:a17:906:2816:: with SMTP id r22mr166828ejc.158.1633652594962; Thu, 07 Oct 2021 17:23:14 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id ke12sm308592ejc.32.2021.10.07.17.23.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Oct 2021 17:23:14 -0700 (PDT) From: Ansuel Smith To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Heiner Kallweit , Russell King , Ansuel Smith , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [net-next PATCH v2 15/15] dt-bindings: net: dsa: qca8k: document support for qca8328 Date: Fri, 8 Oct 2021 02:22:25 +0200 Message-Id: <20211008002225.2426-16-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211008002225.2426-1-ansuelsmth@gmail.com> References: <20211008002225.2426-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org QCA8328 is the birrget brother of 8327. Document the new compatible binding. Signed-off-by: Ansuel Smith --- Documentation/devicetree/bindings/net/dsa/qca8k.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/net/dsa/qca8k.txt b/Documentation/devicetree/bindings/net/dsa/qca8k.txt index 9fb4db65907e..0e84500b8db2 100644 --- a/Documentation/devicetree/bindings/net/dsa/qca8k.txt +++ b/Documentation/devicetree/bindings/net/dsa/qca8k.txt @@ -3,6 +3,7 @@ Required properties: - compatible: should be one of: + "qca,qca8328" "qca,qca8327" "qca,qca8334" "qca,qca8337"