From patchwork Fri Oct 8 01:25:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12543973 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 79666C43217 for ; Fri, 8 Oct 2021 01:25:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5B4A56128C for ; Fri, 8 Oct 2021 01:25:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235563AbhJHB1Z (ORCPT ); Thu, 7 Oct 2021 21:27:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38840 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231373AbhJHB1Z (ORCPT ); Thu, 7 Oct 2021 21:27:25 -0400 Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [IPv6:2a00:1450:4864:20::12e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9D423C061570 for ; Thu, 7 Oct 2021 18:25:30 -0700 (PDT) Received: by mail-lf1-x12e.google.com with SMTP id y15so32488739lfk.7 for ; Thu, 07 Oct 2021 18:25:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=D/FnULHtOSn2r5lygapPAHJMuBEtxiZqi9m5HusuZIQ=; b=JpdfMMMWW2nPaI/K2OrZTUJ1ABBi7mYPTEPpP/qdP2k69L9XHKfRXN9EScbtOXHIIk 07oX9fTBSctsN0nS+r9pG3J+QQjq9ZGN2jdR5Js0CgYP75VYCrYTFtd3UAwZxIRQnXrm 5uXbKlOcWcs2fhesulYbaZV+AQOV/fcFCh5LQ1qAyc1b/vTozLhkkx3RuBCeWKhj/ani 3xpPK0QunT7ZB8abxJ4q2DGd567nZNUVTPLIcT4EHcUk/BniG8vMgWd6c31oetZhYZrZ Cc6e4gwqIF3hOwqvuK/Qf6amcnn/xSOtuO3tQ7WiBldAFqPb5wX50d6nARxveyVfQnSM 9iRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=D/FnULHtOSn2r5lygapPAHJMuBEtxiZqi9m5HusuZIQ=; b=vDl5/8X9IWfrMmQTyVjjSxbiEUJBEqO30++XH8ILzBuPWXh9uNjRdhZqOut4VVgpO0 558KLP/HIAk2yfa+r5KUxBSAiwnjaOvway7XuJIwoKcga0TyoHzc8x/5SWYEm4QrMd0H 44YXiIt7l2v/jSGvRXTbwQjle3RRjYK/sfjC54JBdp46Na/3LEUly67/oVjXUztXvwNz ZlUNNqu7Dtj4CmaGw2UM7fmZZPMdqxAmT/K024ci2A5RdN1QPAVELeyQuT5O8vECFqjl Cf4nLPBkBuV+sOxZOffEUZCOt6/g5t1ZMxYIuw/c9+qDuUztJtoFVi8SBRZrknhXdZs9 O9lQ== X-Gm-Message-State: AOAM530bG4hB7rlCz9xT4bHjg9tH+z1GabCj0vNF7Q0NS+iSXOxezX56 mZeVpM1a2cYsBv/sTwIbisvxyrAzOcPvAg== X-Google-Smtp-Source: ABdhPJxZCnso9Ba4OnK+R5zwz6duAbXeXHdnHJgQ+kKF52E2HRWXLur2ym3AS5Zvb3pLATe3JnTDzQ== X-Received: by 2002:a05:651c:d0:: with SMTP id 16mr374187ljr.428.1633656328842; Thu, 07 Oct 2021 18:25:28 -0700 (PDT) Received: from umbar.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id s4sm112875ljp.115.2021.10.07.18.25.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Oct 2021 18:25:28 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Linus Walleij , Rob Herring Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v3 01/25] dt-bindings: pinctrl: qcom,pmic-mpp: Convert qcom pmic mpp bindings to YAML Date: Fri, 8 Oct 2021 04:25:00 +0300 Message-Id: <20211008012524.481877-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211008012524.481877-1-dmitry.baryshkov@linaro.org> References: <20211008012524.481877-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Convert Qualcomm PMIC MPP bindings from .txt to .yaml format. Signed-off-by: Dmitry Baryshkov --- .../bindings/pinctrl/qcom,pmic-mpp.txt | 187 ----------------- .../bindings/pinctrl/qcom,pmic-mpp.yaml | 188 ++++++++++++++++++ 2 files changed, 188 insertions(+), 187 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt deleted file mode 100644 index 5363d44cbb74..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt +++ /dev/null @@ -1,187 +0,0 @@ -Qualcomm PMIC Multi-Purpose Pin (MPP) block - -This binding describes the MPP block(s) found in the 8xxx series -of PMIC's from Qualcomm. - -- compatible: - Usage: required - Value type: - Definition: Should contain one of: - "qcom,pm8018-mpp", - "qcom,pm8019-mpp", - "qcom,pm8038-mpp", - "qcom,pm8058-mpp", - "qcom,pm8821-mpp", - "qcom,pm8841-mpp", - "qcom,pm8916-mpp", - "qcom,pm8917-mpp", - "qcom,pm8921-mpp", - "qcom,pm8941-mpp", - "qcom,pm8950-mpp", - "qcom,pmi8950-mpp", - "qcom,pm8994-mpp", - "qcom,pma8084-mpp", - "qcom,pmi8994-mpp", - - And must contain either "qcom,spmi-mpp" or "qcom,ssbi-mpp" - if the device is on an spmi bus or an ssbi bus respectively. - -- reg: - Usage: required - Value type: - Definition: Register base of the MPP block and length. - -- interrupts: - Usage: required - Value type: - Definition: Must contain an array of encoded interrupt specifiers for - each available MPP - -- gpio-controller: - Usage: required - Value type: - Definition: Mark the device node as a GPIO controller - -- #gpio-cells: - Usage: required - Value type: - Definition: Must be 2; - the first cell will be used to define MPP number and the - second denotes the flags for this MPP - -Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for -a general description of GPIO and interrupt bindings. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -The pin configuration nodes act as a container for an arbitrary number of -subnodes. Each of these subnodes represents some desired configuration for a -pin or a list of pins. This configuration can include the -mux function to select on those pin(s), and various pin configuration -parameters, as listed below. - -SUBNODES: - -The name of each subnode is not important; all subnodes should be enumerated -and processed purely based on their content. - -Each subnode only affects those parameters that are explicitly listed. In -other words, a subnode that lists a mux function but no pin configuration -parameters implies no information about any pin configuration parameters. -Similarly, a pin subnode that describes a pullup parameter implies no -information about e.g. the mux function. - -The following generic properties as defined in pinctrl-bindings.txt are valid -to specify in a pin configuration subnode: - -- pins: - Usage: required - Value type: - Definition: List of MPP pins affected by the properties specified in - this subnode. Valid pins are: - mpp1-mpp4 for pm8841 - mpp1-mpp4 for pm8916 - mpp1-mpp8 for pm8941 - mpp1-mpp4 for pm8950 - mpp1-mpp4 for pmi8950 - mpp1-mpp4 for pma8084 - -- function: - Usage: required - Value type: - Definition: Specify the alternative function to be configured for the - specified pins. Valid values are: - "digital", - "analog", - "sink" - -- bias-disable: - Usage: optional - Value type: - Definition: The specified pins should be configured as no pull. - -- bias-pull-up: - Usage: optional - Value type: - Definition: The specified pins should be configured as pull up. - Valid values are 600, 10000 and 30000 in bidirectional mode - only, i.e. when operating in qcom,analog-mode and input and - outputs are enabled. The hardware ignores the configuration - when operating in other modes. - -- bias-high-impedance: - Usage: optional - Value type: - Definition: The specified pins will put in high-Z mode and disabled. - -- input-enable: - Usage: optional - Value type: - Definition: The specified pins are put in input mode, i.e. their input - buffer is enabled - -- output-high: - Usage: optional - Value type: - Definition: The specified pins are configured in output mode, driven - high. - -- output-low: - Usage: optional - Value type: - Definition: The specified pins are configured in output mode, driven - low. - -- power-source: - Usage: optional - Value type: - Definition: Selects the power source for the specified pins. Valid power - sources are defined in - -- qcom,analog-level: - Usage: optional - Value type: - Definition: Selects the source for analog output. Valued values are - defined in - PMIC_MPP_AOUT_LVL_* - -- qcom,dtest: - Usage: optional - Value type: - Definition: Selects which dtest rail to be routed in the various functions. - Valid values are 1-4 - -- qcom,amux-route: - Usage: optional - Value type: - Definition: Selects the source for analog input. Valid values are - defined in - PMIC_MPP_AMUX_ROUTE_CH5, PMIC_MPP_AMUX_ROUTE_CH6... -- qcom,paired: - Usage: optional - Value type: - Definition: Indicates that the pin should be operating in paired mode. - -Example: - - mpps@a000 { - compatible = "qcom,pm8841-mpp", "qcom,spmi-mpp"; - reg = <0xa000>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <4 0xa0 0 0>, <4 0xa1 0 0>, <4 0xa2 0 0>, <4 0xa3 0 0>; - - pinctrl-names = "default"; - pinctrl-0 = <&pm8841_default>; - - pm8841_default: default { - gpio { - pins = "mpp1", "mpp2", "mpp3", "mpp4"; - function = "digital"; - input-enable; - power-source = ; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml new file mode 100644 index 000000000000..475733cabb02 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml @@ -0,0 +1,188 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,pmic-mpp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm PMIC Multi-Purpose Pin (MPP) block + +maintainers: + - Bjorn Andersson + +description: + This binding describes the MPP block(s) found in the 8xxx series of + PMIC's from Qualcomm. + +properties: + compatible: + items: + - enum: + - qcom,pm8018-mpp + - qcom,pm8019-mpp + - qcom,pm8038-mpp + - qcom,pm8058-mpp + - qcom,pm8821-mpp + - qcom,pm8841-mpp + - qcom,pm8916-mpp + - qcom,pm8917-mpp + - qcom,pm8921-mpp + - qcom,pm8941-mpp + - qcom,pm8950-mpp + - qcom,pmi8950-mpp + - qcom,pm8994-mpp + - qcom,pma8084-mpp + - qcom,pmi8994-mpp + + - enum: + - qcom,spmi-mpp + - qcom,ssbi-mpp + + reg: + maxItems: 1 + + interrupts: + minItems: 1 + maxItems: 12 + description: + Must contain an array of encoded interrupt specifiers for + each available MPP + + gpio-controller: true + gpio-line-names: true + + gpio-ranges: + maxItems: 1 + + '#gpio-cells': + const: 2 + description: + The first cell will be used to define gpio number and the + second denotes the flags for this gpio + +additionalProperties: false + +required: + - compatible + - reg + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +patternProperties: + '-state$': + oneOf: + - $ref: "#/$defs/qcom-pmic-mpp-state" + - patternProperties: + "mpp": + $ref: "#/$defs/qcom-pmic-mpp-state" + additionalProperties: false + +$defs: + qcom-pmic-mpp-state: + type: object + allOf: + - $ref: "pinmux-node.yaml" + - $ref: "pincfg-node.yaml" + properties: + pins: + description: + List of gpio pins affected by the properties specified in + this subnode. Valid pins are + - mpp1-mpp4 for pm8841 + - mpp1-mpp4 for pm8916 + - mpp1-mpp8 for pm8941 + - mpp1-mpp4 for pm8950 + - mpp1-mpp4 for pmi8950 + - mpp1-mpp4 for pma8084 + + items: + pattern: "^mpp([0-9]+)$" + + function: + items: + - enum: + - digital + - analog + - sink + + bias-disable: true + bias-pull-up: true + bias-high-impedance: true + input-enable: true + output-high: true + output-low: true + power-source: true + + qcom,analog-level: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Selects the source for analog output. Valued values are defined in + PMIC_MPP_AOUT_LVL_* + enum: [0, 1, 2, 3, 4, 5, 6, 7] + + qcom,atest: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Selects ATEST rail to route to GPIO when it's + configured in analog-pass-through mode. + enum: [1, 2, 3, 4] + + qcom,dtest: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Selects DTEST rail to route to GPIO when it's + configured as digital input. + enum: [1, 2, 3, 4] + + qcom,amux-route: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Selects the source for analog input. Valid values are defined in + PMIC_MPP_AMUX_ROUTE_CH5, + PMIC_MPP_AMUX_ROUTE_CH6... + enum: [0, 1, 2, 3, 4, 5, 6, 7] + + qcom,paired: + - description: + Indicates that the pin should be operating in paired mode. + + required: + - pins + - function + + additionalProperties: false + +examples: + - | + #include + + pm8841_mpp: mpps@a000 { + compatible = "qcom,pm8841-mpp", "qcom,spmi-mpp"; + reg = <0xa000 0>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pm8841_mpp 0 0 4>; + gpio-line-names = "VDD_PX_BIAS", "WLAN_LED_CTRL", + "BT_LED_CTRL", "GPIO-F"; + interrupts = <4 0xa0 0 0>, <4 0xa1 0 0>, <4 0xa2 0 0>, <4 0xa3 0 0>; + + pinctrl-names = "default"; + pinctrl-0 = <&pm8841_default>; + + mpp1-state { + pins = "mpp1"; + function = "digital"; + input-enable; + power-source = ; + }; + + default-state { + gpio-mpp { + pins = "mpp1", "mpp2", "mpp3", "mpp4"; + function = "digital"; + input-enable; + power-source = ; + }; + }; + }; +... From patchwork Fri Oct 8 01:25:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12543975 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 41A85C4321E for ; Fri, 8 Oct 2021 01:25:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2CF1B61278 for ; Fri, 8 Oct 2021 01:25:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233854AbhJHB10 (ORCPT ); Thu, 7 Oct 2021 21:27:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38846 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234381AbhJHB1Z (ORCPT ); Thu, 7 Oct 2021 21:27:25 -0400 Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 26E78C061760 for ; Thu, 7 Oct 2021 18:25:31 -0700 (PDT) Received: by mail-lf1-x136.google.com with SMTP id z11so24037377lfj.4 for ; Thu, 07 Oct 2021 18:25:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UuQnsS7c2xArKsKKLwccup/8SD8/wP5roqMnNvhNkqg=; b=E13jSEhDxD4rOmzfAZh42wsrEU5QroTrJe8IGz90IyNqilL5ZfYnNbpRIkMGnydBf6 LYh6mizO9LF7BfNBwbkk63mTH7Ac8PXDV/EPqN+i64fALy8FGEPios/OGA8sMxxHNPui cftJq9GH9ry41pP96XMoP8JYWBnXr4sZY2b5VKDRnlSSoH0o5oKnyCLotZLgAe5PnCPm RCqEzEAHVqEp5j6ixqA2s+j9vr7QVJdAh3sHXXAfCUoiixrBwDbeIUGMmpWTEGayjnJU 7WIbVEiyNI5UspvS0sjOJr+gHjbd0SsraF0txpRyWWnpaHtifrC6TYEfNRVo6xqQxY59 bkGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UuQnsS7c2xArKsKKLwccup/8SD8/wP5roqMnNvhNkqg=; b=68AuSnyLnUwK9LIbDFhGVphkhr91tUyxtTsC97cm/2jQaWPjo8p4MvU10jc4MDXz04 kL4F8Uw1mLrF/5eh4sD9FrAjsUTRZuxR00v6W5HEl8WcZnQn8tYAwIE56ucA6+n/Lx4Q pnH3kG9PTojfgf9ES8VVNfpkPFdTwCfD0TROhjCdPhPwxHS16t04hYryiUDdzGhfpfcz +qRQM2g/KCRdqfAyctox82vrgI+06YzULFmFc4IJdcuJk6HmvMga5fiquksJsHncVebC 5eWM8ceNQtbiprgYhI5k3OklPTzCa3p5nkKvjoYzewAP+Di240Wblvje0aRIMpM2egSr 7c+Q== X-Gm-Message-State: AOAM532y9DZmfEey6jsDc/ZzAZ4RCp+bWPb6Ty/DstOErf/aNO6HNwIz irUeuldgsUYaLKYuaIjZzrOHIA== X-Google-Smtp-Source: ABdhPJz6+ZEHinJlcz5hayK+whrKBtIzfUnZfN7/UhuwDZUFCKC8D8+UdtOhAh9m+28HSd41GqLY/w== X-Received: by 2002:ac2:5c48:: with SMTP id s8mr7435912lfp.336.1633656329498; Thu, 07 Oct 2021 18:25:29 -0700 (PDT) Received: from umbar.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id s4sm112875ljp.115.2021.10.07.18.25.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Oct 2021 18:25:29 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Linus Walleij , Rob Herring Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v3 02/25] dt-bindings: mfd: qcom-pm8xxx: add missing child nodes Date: Fri, 8 Oct 2021 04:25:01 +0300 Message-Id: <20211008012524.481877-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211008012524.481877-1-dmitry.baryshkov@linaro.org> References: <20211008012524.481877-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add gpio@[0-9a-f]+, mpps@[0-9a-f]+ and xoadc@[0-9a-f]+ as possible child nodes of qcom,pm8xxx, referencing existint schema files. Schema for other possible nodes does not exist yet. Signed-off-by: Dmitry Baryshkov Reviewed-by: Linus Walleij Reviewed-by: Rob Herring --- .../devicetree/bindings/mfd/qcom-pm8xxx.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/qcom-pm8xxx.yaml b/Documentation/devicetree/bindings/mfd/qcom-pm8xxx.yaml index 9065ec53e643..10021eb7103e 100644 --- a/Documentation/devicetree/bindings/mfd/qcom-pm8xxx.yaml +++ b/Documentation/devicetree/bindings/mfd/qcom-pm8xxx.yaml @@ -38,10 +38,22 @@ properties: interrupt-controller: true patternProperties: + "gpio@[0-9a-f]+$": + type: object + $ref: "../pinctrl/qcom,pmic-gpio.yaml" + + "mpps@[0-9a-f]+$": + type: object + $ref: "../pinctrl/qcom,pmic-mpp.yaml" + "rtc@[0-9a-f]+$": type: object $ref: "../rtc/qcom-pm8xxx-rtc.yaml" + "xoadc@[0-9a-f]+$": + type: object + $ref: "../iio/adc/qcom,pm8018-adc.yaml" + required: - compatible - '#address-cells' From patchwork Fri Oct 8 01:25:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12543977 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A9C43C433FE for ; Fri, 8 Oct 2021 01:25:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 87DFA61381 for ; Fri, 8 Oct 2021 01:25:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235451AbhJHB11 (ORCPT ); Thu, 7 Oct 2021 21:27:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38858 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234381AbhJHB10 (ORCPT ); Thu, 7 Oct 2021 21:27:26 -0400 Received: from mail-lf1-x133.google.com (mail-lf1-x133.google.com [IPv6:2a00:1450:4864:20::133]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CD064C061714 for ; Thu, 7 Oct 2021 18:25:31 -0700 (PDT) Received: by mail-lf1-x133.google.com with SMTP id r19so30680137lfe.10 for ; Thu, 07 Oct 2021 18:25:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=XPJhiyssMgP/Qx7CEDMKniXc51YWsJz5iKb0grR309U=; b=zHkhIrBZsf97wg1GpfqsWTxEcnvewzjvW1ZvTbuX+11eHJpHmbkPgUgxjeIW0Ra5DJ AE6w3pHGdyNVCPo2ikh5V0TVJoftg0TRxJ4M7R5ALH/qmwjP01dN7YbTBDqOnA5CKjrh eyNQd/sh3/8WLyLjHA0zS1R/29dst3pdBHtMQhskY4ZC3lQn3BKtikTWEe625wkWe9eO 4ybVmizrPyFMTKzmghiTACVfYBChfezA8kOg9yRxKQYjRDDWahzLr0ahzalkXMFlGhKv 4sxasp4UvZOoIULwV0DjTVxPxTtkPQNpV2gBr3XuiVzoI3/hoqTMaGsswkSvP1qxPdtw X77w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XPJhiyssMgP/Qx7CEDMKniXc51YWsJz5iKb0grR309U=; b=UNbHBZmP2YXB0usKCqROjKpVnJOBlFy6RqbZe0Jm0F+faQGiZlV7nr9nUiATFrMnli wWyXdc28XHALNiIHtnxWZQm7UEBjz5ZmutsaypMLCh+xhu82OCbVD67A7y3DG1fMOAX5 sXFYSKKeiKjK7v9PlxDTPMUCMb9gE2okH87b3v1qq8zXJ8St5CDc7hSaJjSdOEs7WJjl 84YsCBcD9jI9lbZllGJZcwqQL3Yml/BSBqltkR+wYxo1mY5Jeg5eB1Q1w5UwKtSYRFoX m6dxPWMl5Y2LQREo0jTDleCpn/EP/tGuY6aSGn095R5lG8qmD0azdoAeBDa7XDQpV1VK mvmw== X-Gm-Message-State: AOAM533lJR7TzIRW+sAEmxJ/78NuT2ZpuKxnTxRU+qJprKQRcYnaRKNI wgeIbjccrYyRUOnvNmfKM9ymcg== X-Google-Smtp-Source: ABdhPJzUUrhEF2sHoU6goliUT5IHs3yhFcdNw0i2YUFBJszwRX7KApT2n5LWAONbuXn/yo66Jn/jHQ== X-Received: by 2002:a05:651c:1793:: with SMTP id bn19mr307276ljb.475.1633656330207; Thu, 07 Oct 2021 18:25:30 -0700 (PDT) Received: from umbar.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id s4sm112875ljp.115.2021.10.07.18.25.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Oct 2021 18:25:29 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Linus Walleij , Rob Herring Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v3 03/25] ARM: dts: qcom-apq8064: add gpio-ranges to mpps nodes Date: Fri, 8 Oct 2021 04:25:02 +0300 Message-Id: <20211008012524.481877-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211008012524.481877-1-dmitry.baryshkov@linaro.org> References: <20211008012524.481877-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add gpio-ranges property to mpps device tree nodes, adding the mapping between pinctrl and GPIO pins. Signed-off-by: Dmitry Baryshkov Reviewed-by: Linus Walleij --- arch/arm/boot/dts/qcom-apq8064.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 0b2bed6e7adf..cbc9be8a69cd 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -689,6 +689,7 @@ pm8821_mpps: mpps@50 { <27 IRQ_TYPE_NONE>; gpio-controller; #gpio-cells = <2>; + gpio-ranges = <&pm8821_mpps 0 0 4>; }; }; }; @@ -726,6 +727,7 @@ pm8921_mpps: mpps@50 { reg = <0x50>; gpio-controller; #gpio-cells = <2>; + gpio-ranges = <&pm8921_mpps 0 0 12>; interrupts = <128 IRQ_TYPE_NONE>, <129 IRQ_TYPE_NONE>, From patchwork Fri Oct 8 01:25:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12543979 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9E9A2C43217 for ; Fri, 8 Oct 2021 01:25:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7EECD613A7 for ; Fri, 8 Oct 2021 01:25:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236118AbhJHB12 (ORCPT ); Thu, 7 Oct 2021 21:27:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38846 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234407AbhJHB11 (ORCPT ); Thu, 7 Oct 2021 21:27:27 -0400 Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7695FC061764 for ; Thu, 7 Oct 2021 18:25:32 -0700 (PDT) Received: by mail-lf1-x12c.google.com with SMTP id i24so30954979lfj.13 for ; Thu, 07 Oct 2021 18:25:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=clR0pd2rxG7rsbJsSmT96iRGAfExlfxhlmBSBtDpU+E=; b=cHPcGJugcIEIj7qiruq9EapjU3rzcxhYWG1TXzY5AkX8rE7pjc7vDrHq0+jrce34xn eJiQmKEInBCpIn/R3g4ex0+cBPs5zxxe8FnMcJtdGIKigtycCx0ei6anMchp7kmh6xXM I/t21gX/nAOd1+S8796p1iD6LcTI+3hPYIgJ1nqpU6dg+YLqTfG8KZOyMEvTq5P5ad/8 a0sfRvenRwiQ5BZKKX4KTq8h22WuEt+SMxu+XZNoyTpariS2cuP4pHyXO6NElm32gnEp j4FlqLgczmxO9iIIh+jB3w008Y0qTBH6u3S2YIfGZSsZIShvEytAAyRZ617WTKx40x6J tyog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=clR0pd2rxG7rsbJsSmT96iRGAfExlfxhlmBSBtDpU+E=; b=ySsoiOiXljycK3HAlpNCMjm9jId0RehEGz4rRmGEVVXIlK17w5ju6XfyAYu3YLk2Vd ZtSMuF7NIMZM9ZXOKhN/6y+ueWQRYYOXzv+t9xMXW4Q7rjpbtepBUL1H0yJ2D6Xkg4hT OTVZmvM3L0AOas8H56lfWtY1P6V2enFDGW6egmzZ/fOlotM9hSyLK8X4ea8SNMlrDmHb PteTAyvnOqrz5LhysqZ2ageR/BDxoUnI9O2L4VMC6Tvv2qkWFVfthwcOt/t5EU12tOD0 3te+HxiVMiIK60sLYTukdP4wMxysakgJxLXEjgj+05EZn6I4V5T6fFqQ9J1yQhMj0+cJ KgMQ== X-Gm-Message-State: AOAM531nmTd7RLJBBEHQdPgCYHvXpZvwTZyXWbkaH/jSYvVoXI4di0Fe hBQsapl6iaAF0TCQb9mfpu9dbw== X-Google-Smtp-Source: ABdhPJyGM7o5G0i6hoOpaUrxWb56kXiSMqcM/MjOQzctlUK3zFXekZ7gV0F0bQ7nQglo6H38HlhhcA== X-Received: by 2002:a2e:550:: with SMTP id 77mr377760ljf.478.1633656330786; Thu, 07 Oct 2021 18:25:30 -0700 (PDT) Received: from umbar.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id s4sm112875ljp.115.2021.10.07.18.25.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Oct 2021 18:25:30 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Linus Walleij , Rob Herring Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v3 04/25] ARM: dts: qcom-msm8660: add gpio-ranges to mpps nodes Date: Fri, 8 Oct 2021 04:25:03 +0300 Message-Id: <20211008012524.481877-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211008012524.481877-1-dmitry.baryshkov@linaro.org> References: <20211008012524.481877-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add gpio-ranges property to mpps device tree nodes, adding the mapping between pinctrl and GPIO pins. Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom-msm8660.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi index 480fc08cbe8e..d404d386d392 100644 --- a/arch/arm/boot/dts/qcom-msm8660.dtsi +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi @@ -307,6 +307,7 @@ pm8058_mpps: mpps@50 { reg = <0x50>; gpio-controller; #gpio-cells = <2>; + gpio-ranges = <&pm8058_mpps 0 0 12>; interrupt-parent = <&pm8058>; interrupts = <128 IRQ_TYPE_NONE>, From patchwork Fri Oct 8 01:25:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12543983 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 59C01C43219 for ; Fri, 8 Oct 2021 01:25:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3C51861381 for ; Fri, 8 Oct 2021 01:25:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231233AbhJHB13 (ORCPT ); Thu, 7 Oct 2021 21:27:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38846 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236351AbhJHB11 (ORCPT ); Thu, 7 Oct 2021 21:27:27 -0400 Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [IPv6:2a00:1450:4864:20::130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 03C28C061570 for ; Thu, 7 Oct 2021 18:25:33 -0700 (PDT) Received: by mail-lf1-x130.google.com with SMTP id i24so30955044lfj.13 for ; Thu, 07 Oct 2021 18:25:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kogEQhss8CRQIVqzZR3ldriy2WlhMwjUUX695mLk53A=; b=u/xW+YZM8u0qwKhtsYYmEGHoYpfN2WiGLdRfnfQxGAvmDzsvzr9ESYtWcDelrBtUaN D1Gvg472UeaNp0YpneRi0UwWK92xM0pEOd0fvD2ldwbxEH6We4an3UrYYGXZwgOtwz4c 88QIBcZDRwQht2UrQInbCUT+JE/ovNdgNG8Wi1o4uJvSqITgn7+TsMpMosdPC09A9hoz 06A8DJGc9uF+t86OcBnqbbb/C1sgc5QPOaYvu5Hip66UZ+OA8Pnka1MyHcSbe16xEF2L 5h0yAjn2aauRmCctmpXUUWLb+uRD79ZCui/qUygmrkGeXH8r60Ct70ARWHJi5BNuAE7X idLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kogEQhss8CRQIVqzZR3ldriy2WlhMwjUUX695mLk53A=; b=Sr/9kHHjnSNLc1mGv5/u4F5qSq+faGrxVIRwRld6gbAcOwfIgXXOJdSyUGNjU8IwQ/ HCnaXFoh1VFWj38j4HK4Z90C/Vh2ky8wHnlidfoYEez5cRcDL+BaLIgAQOiuEPb4mQeu o01mNzBUba6GBIKa1V1xJCoinEaqnAga5KUR2g5FLTxKD0Z9fUZ0jY1EWDs16IRr28mC jabC/QSAEEdMMFdym8TVrIELo+5Cqnj2liBzqX39ht82yrhqDpe8dVOcilQUDKrkcBsp 5F5uOQJ3QQXeR2UOxHaHTa00D1NvD4K46GsgmgOqDeHdNJlhV7FVyLFhSzjt6RySXM/6 J2vQ== X-Gm-Message-State: AOAM533TpJmpohkHBb8cm3CqKxOcbgpkJgeOGmwwK9tArIyxXVvaxaX+ lAzRdUM09rmmqiLl8a8p4u+Sdg== X-Google-Smtp-Source: ABdhPJwdrRtLnoRInKY0r/JOimrzZAywVHIFbXWKG8GFNpu/oIQO1O1R5uf+mxzhHovAafByJFJQWA== X-Received: by 2002:a19:48d1:: with SMTP id v200mr7743851lfa.47.1633656331415; Thu, 07 Oct 2021 18:25:31 -0700 (PDT) Received: from umbar.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id s4sm112875ljp.115.2021.10.07.18.25.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Oct 2021 18:25:31 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Linus Walleij , Rob Herring Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v3 05/25] ARM: dts: qcom-pm8841: add gpio-ranges to mpps nodes Date: Fri, 8 Oct 2021 04:25:04 +0300 Message-Id: <20211008012524.481877-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211008012524.481877-1-dmitry.baryshkov@linaro.org> References: <20211008012524.481877-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add gpio-ranges property to mpps device tree nodes, adding the mapping between pinctrl and GPIO pins. Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom-pm8841.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/qcom-pm8841.dtsi b/arch/arm/boot/dts/qcom-pm8841.dtsi index 2fd59c440903..b6066c27732c 100644 --- a/arch/arm/boot/dts/qcom-pm8841.dtsi +++ b/arch/arm/boot/dts/qcom-pm8841.dtsi @@ -15,6 +15,7 @@ pm8841_mpps: mpps@a000 { reg = <0xa000>; gpio-controller; #gpio-cells = <2>; + gpio-ranges = <&pm8841_mpps 0 0 4>; interrupts = <4 0xa0 0 IRQ_TYPE_NONE>, <4 0xa1 0 IRQ_TYPE_NONE>, <4 0xa2 0 IRQ_TYPE_NONE>, From patchwork Fri Oct 8 01:25:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12543981 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E104CC4321E for ; Fri, 8 Oct 2021 01:25:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CB73D61381 for ; Fri, 8 Oct 2021 01:25:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237064AbhJHB1a (ORCPT ); Thu, 7 Oct 2021 21:27:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38870 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234356AbhJHB12 (ORCPT ); Thu, 7 Oct 2021 21:27:28 -0400 Received: from mail-lf1-x12a.google.com (mail-lf1-x12a.google.com [IPv6:2a00:1450:4864:20::12a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 96C58C061762 for ; Thu, 7 Oct 2021 18:25:33 -0700 (PDT) Received: by mail-lf1-x12a.google.com with SMTP id b20so32910845lfv.3 for ; Thu, 07 Oct 2021 18:25:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sE/GeDbmDq0h+hKpjaIbLxWeY1CrCvRz2kO4vU6ead4=; b=mO2BfTUSoOS+QDuI4UVTr2/fdVvyNIeiyheoXP4BVNtgxKbGRRo02bC+aR4iJ+qbYU LgXZbwpzld3il6xvx38o//nNQEkhGY/nuiW4PqGiVzirQKtUqpE70wqxbFwmf4O+WfQC 5RDX2OrqxjiUiyluvf00Kr/qGBIwgLcBQzpuBcUlYWGP2xAe1qQJ0IbyMA15WWm8e7tt aEKFnBcuGPsXknzoKsfQFRQjzCUIy0y1b58IvtX0DVWv5iwHs/DOVLN87ZK8W6jEdd7B BHXw9t0e8vbJVa9bWI03bxlQ4Jw6wy3H6CoWNJKL2iZg2VUlAOkgFUtdHNEAJEuNOkb0 gWjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sE/GeDbmDq0h+hKpjaIbLxWeY1CrCvRz2kO4vU6ead4=; b=LGsArEHym1eEl9CrOEEcOoS9Q8bQF7D+/xt/YNcezqlunLzblo23kPoj6Zb67tb3c+ iAWwgbBn2XeQYM7QUZzWjb5ANom6BTfwmKjexzsnZwEeF46Dime7xLlUGwyAVPbYV+Cg zf1bYq3/JrE5gXKrbq7ijyWu4zQ/BC+OjcLRa0zoV/4OG6pLBHxBJUT0h0OxMGOg0oG6 X11vt9ZHHKc3M8KMGENluNN7pI6kCUo+yKy5bCJK0IklukRgLByyIowvYGw4LL6rBa6a yGizOTpOYB2HNHlpLvyYCJYAa2WxpBpfPSuP2xAM1LkIp2f+oKKxwTLLSDxikZnVdtXy +dtg== X-Gm-Message-State: AOAM531TpQVqKdLdQlSHVRQc1So/YMTULki8UF2OyIp3cL5oDCcs8HKF xt0L1BIzEGVLZJFdpiiQiPLDbg== X-Google-Smtp-Source: ABdhPJzgutI+nOtWdmpQ9mcezQ/G2nxiTvlyG8oRrrXVfiIeglp87+g03CpxJjNQ1om6JPdnlSW72g== X-Received: by 2002:a2e:9c49:: with SMTP id t9mr409209ljj.86.1633656332022; Thu, 07 Oct 2021 18:25:32 -0700 (PDT) Received: from umbar.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id s4sm112875ljp.115.2021.10.07.18.25.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Oct 2021 18:25:31 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Linus Walleij , Rob Herring Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v3 06/25] ARM: dts: qcom-pm8941: add gpio-ranges to mpps nodes Date: Fri, 8 Oct 2021 04:25:05 +0300 Message-Id: <20211008012524.481877-7-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211008012524.481877-1-dmitry.baryshkov@linaro.org> References: <20211008012524.481877-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add gpio-ranges property to mpps device tree nodes, adding the mapping between pinctrl and GPIO pins. Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom-pm8941.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/qcom-pm8941.dtsi b/arch/arm/boot/dts/qcom-pm8941.dtsi index c1f2012d1c8b..cf8daa2fe144 100644 --- a/arch/arm/boot/dts/qcom-pm8941.dtsi +++ b/arch/arm/boot/dts/qcom-pm8941.dtsi @@ -79,6 +79,7 @@ pm8941_mpps: mpps@a000 { reg = <0xa000>; gpio-controller; #gpio-cells = <2>; + gpio-ranges = <&pm8941_mpps 0 0 8>; interrupts = <0 0xa0 0 IRQ_TYPE_NONE>, <0 0xa1 0 IRQ_TYPE_NONE>, <0 0xa2 0 IRQ_TYPE_NONE>, From patchwork Fri Oct 8 01:25:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12543985 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4460FC4167D for ; Fri, 8 Oct 2021 01:25:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 22682613AC for ; Fri, 8 Oct 2021 01:25:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231530AbhJHB1a (ORCPT ); Thu, 7 Oct 2021 21:27:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38884 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231137AbhJHB13 (ORCPT ); Thu, 7 Oct 2021 21:27:29 -0400 Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4C051C061755 for ; Thu, 7 Oct 2021 18:25:34 -0700 (PDT) Received: by mail-lf1-x12c.google.com with SMTP id z11so24037830lfj.4 for ; Thu, 07 Oct 2021 18:25:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=l105OhexlN6YNfKbmvTA4DJELYmmbABapWIiAJPQyxM=; b=y/co2dD2esQ18LGntt0gVHDGfAXcFRT6rLMVqTGdfs+AXzJavXcu4tAN+RYErFH6Dz 2XXGOdR25b2SE8d/tedvc/KOoKcWXmUjt3uzrII9fFB9g+TUNgA0cbJkyhOchnwIX6Uy swz/6suR0pd0O2jPFW7hDf6uR7KnqiW87WZBKJZ/g3EvracbfQHwebvpgibhlqnbhNLw k3E+BdHTo5sC+c4Pqn3jSneKCiOfX9giusz7vyMN9zwTuBCeJiXa6NM066HXo7SaRwWZ MtZMPo356KBZO5F09lb5vK4cXqFshiXb756qfkceMaLIegimsVYL9EBIWjDkSj3rXbbN liZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=l105OhexlN6YNfKbmvTA4DJELYmmbABapWIiAJPQyxM=; b=HZgziIdrtPLv7Grb5ym1m31joFmZCtL/tRTKi4c4jwDZt4BHHt/za/MbuPfVR9VKPW Faw8XNZok9nc3cQb3SSKwbZU5Ep9A3UGzs4+iXd+bZD78Wy+mchIECR3qsMOBgbqZQrj PHyRDzm3dKqDTU0JZOcm//QRIOKvKRzfpED+5daLecs2uy25LRPn5b9J9pdUdhvHT8+Y GjG1PYtnEtrUZ5PRWUf52QTuDhYap+O6YBEeZnsGTRtieDI5cR+KjleN/wsk4yCdzQYB 1/C7BuP0VTYr5D2OsMW1QuujkkqcvIIO2snFvayipcTAgaOjLQnhkr4tByDAb6dfDpnH pG7w== X-Gm-Message-State: AOAM5329OGdsDRIfyn8l9lr3AYIg4QOM0+MRrpyCoec8CQQpIABnS/Ey l6Y4aQH32w+AJHnrQVcKRdsaHg== X-Google-Smtp-Source: ABdhPJwopk30Bc926Mud4VJWcurop+dtnSxECkNEljaY0psvnPvu55RmvcNzZgPlZkT5eE4USvGsvQ== X-Received: by 2002:a05:651c:1589:: with SMTP id h9mr364343ljq.151.1633656332732; Thu, 07 Oct 2021 18:25:32 -0700 (PDT) Received: from umbar.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id s4sm112875ljp.115.2021.10.07.18.25.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Oct 2021 18:25:32 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Linus Walleij , Rob Herring Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v3 07/25] ARM: dts: qcom-pma8084: add gpio-ranges to mpps nodes Date: Fri, 8 Oct 2021 04:25:06 +0300 Message-Id: <20211008012524.481877-8-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211008012524.481877-1-dmitry.baryshkov@linaro.org> References: <20211008012524.481877-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add gpio-ranges property to mpps device tree nodes, adding the mapping between pinctrl and GPIO pins. Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom-pma8084.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/qcom-pma8084.dtsi b/arch/arm/boot/dts/qcom-pma8084.dtsi index e921c5e93a5d..fcee2afe6740 100644 --- a/arch/arm/boot/dts/qcom-pma8084.dtsi +++ b/arch/arm/boot/dts/qcom-pma8084.dtsi @@ -42,6 +42,7 @@ pma8084_mpps: mpps@a000 { reg = <0xa000>; gpio-controller; #gpio-cells = <2>; + gpio-ranges = <&pma8084_mpps 0 0 8>; interrupts = <0 0xa0 0 IRQ_TYPE_NONE>, <0 0xa1 0 IRQ_TYPE_NONE>, <0 0xa2 0 IRQ_TYPE_NONE>, From patchwork Fri Oct 8 01:25:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12543987 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 79726C43217 for ; Fri, 8 Oct 2021 01:25:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 54D0C613AC for ; Fri, 8 Oct 2021 01:25:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231137AbhJHB1b (ORCPT ); Thu, 7 Oct 2021 21:27:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38872 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236805AbhJHB13 (ORCPT ); Thu, 7 Oct 2021 21:27:29 -0400 Received: from mail-lf1-x12f.google.com (mail-lf1-x12f.google.com [IPv6:2a00:1450:4864:20::12f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EC4B7C061769 for ; Thu, 7 Oct 2021 18:25:34 -0700 (PDT) Received: by mail-lf1-x12f.google.com with SMTP id t9so31418415lfd.1 for ; Thu, 07 Oct 2021 18:25:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jPqe703H6IymTOKSZQDO6LX/0zlyxMHngDY3uRoclEk=; b=uJgSuxFdLZN7ePM6wH+96t2n+DPHBqLeAszdom840iKOnzfwFlh2K5EJv5ccn5i5Ay c88gbpvUK06xWacn0aiVry6qdIVO7XPnk7bSUbK58enUzsnhWDrRqXxJ4MNTLdZPMSdn dPaD3f14YTf9RML2mrVyY/I7q3qwi1594f1m8PaxaZJ/BjJP7dTC5YrI5mR3JEZsNgd7 Vc0HHhDOLI2GG3fftoBoEIDBZxFMwzL/JwTg6+pK4xh+KSk3U3yFGxEUNm5adh4SW7VE X0OH61CY+P1x1j22mebXtnvq5ns5NLo+68qXt3ULXVayT1/o+JAuC/YagrWRwIItXrhd dj9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jPqe703H6IymTOKSZQDO6LX/0zlyxMHngDY3uRoclEk=; b=DGNtK7gtN2i++WGyIfTj/oHjusJVvVU52LuO652BP/zQOh+HIIe8hNVFI/rQW90nEj ftCYgY/hTLVgWnlr9UPgL5pcOrr6WUZd2PHUj2/wdWW82dmwKUddfrxsNsHwzPqf5Y8e fFcWSadepuDE0P/ToiKVWlXrlshoAjrsSdrOiGZGduug3IQ4fSTMW46uA316TDnC8/LN RTsAMbBhqluoKqL5gxWMWNeylf/psARg+L+zNGutpNlC8V0F/zRqDx2ue9gsh303ruFD X5YLHFmeMj4mmdZY+YhY+FAp9VmoaX640sLPUxpNeAj1/jPpeOQcKdZpI6f6QgpC23zJ vusA== X-Gm-Message-State: AOAM532B6Fk2rIqQiOcCTxKRFHNY6SxisMcaj7h1Cyw67lRjotBJyu+y IRNZn/sjIev42e0JyxwoiIONYg== X-Google-Smtp-Source: ABdhPJwMxbV0vtkbZvaATJwbz9qAxRs/uR2BDyciy0OSyfS7SqgfG/Kd1ol93HvioqxwiS8XVjW/gQ== X-Received: by 2002:a05:6512:c24:: with SMTP id z36mr6419114lfu.62.1633656333297; Thu, 07 Oct 2021 18:25:33 -0700 (PDT) Received: from umbar.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id s4sm112875ljp.115.2021.10.07.18.25.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Oct 2021 18:25:33 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Linus Walleij , Rob Herring Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v3 08/25] ARM: dts: qcom-mdm9615: add gpio-ranges to mpps node, fix its name Date: Fri, 8 Oct 2021 04:25:07 +0300 Message-Id: <20211008012524.481877-9-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211008012524.481877-1-dmitry.baryshkov@linaro.org> References: <20211008012524.481877-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Rename mpp node to mpps@50 (instead of mpp@50). Also add gpio-ranges property to mpps device tree nodes, adding the mapping between pinctrl and GPIO pins. Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom-mdm9615.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-mdm9615.dtsi b/arch/arm/boot/dts/qcom-mdm9615.dtsi index dda2ceec6591..cfff1a5706ed 100644 --- a/arch/arm/boot/dts/qcom-mdm9615.dtsi +++ b/arch/arm/boot/dts/qcom-mdm9615.dtsi @@ -300,7 +300,7 @@ pwrkey@1c { pull-up; }; - pmicmpp: mpp@50 { + pmicmpp: mpps@50 { compatible = "qcom,pm8018-mpp", "qcom,ssbi-mpp"; interrupt-parent = <&pmicintc>; interrupts = <24 IRQ_TYPE_NONE>, @@ -312,6 +312,7 @@ pmicmpp: mpp@50 { reg = <0x50>; gpio-controller; #gpio-cells = <2>; + gpio-ranges = <&pmicmpp 0 0 6>; }; rtc@11d { From patchwork Fri Oct 8 01:25:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12543989 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 198FCC433FE for ; Fri, 8 Oct 2021 01:25:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 04A0E614C8 for ; Fri, 8 Oct 2021 01:25:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230402AbhJHB1c (ORCPT ); Thu, 7 Oct 2021 21:27:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38902 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238136AbhJHB1a (ORCPT ); Thu, 7 Oct 2021 21:27:30 -0400 Received: from mail-lf1-x129.google.com (mail-lf1-x129.google.com [IPv6:2a00:1450:4864:20::129]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8E746C061762 for ; Thu, 7 Oct 2021 18:25:35 -0700 (PDT) Received: by mail-lf1-x129.google.com with SMTP id b20so32911053lfv.3 for ; Thu, 07 Oct 2021 18:25:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qkMqBx/0+QNy6vnPe5v+Jz8TEUxjmzu64DV0QiSa2s0=; b=ldrtcuLlebPN6CO00igJqAm/YPiO5uQDbTgsbmTHF3MdyXhwR75157DEKb73XBWROL rLvPfpeayyxuYNJ9L4w4lmvr3b6ihp42M3kq8BA9F4U84PQlFZLZJJiyGOvR08ZQAR6A bDTwKHpOmq564aWK5k2AGVUOFuEEQEayQ2uBYmHXatnVeffGnm/jg0hm57FGX5jPfkQy EQuUdbNFr25m5hXS06t/zyBNs32P+YZexrJoMa1UDej7u2k/YrJVAnYba01/Na5NM+Iv RHaymRz0SYpeSfhIF2K9cQn91BbMGDwGayHFVbRjmtXsW2qEgAkDHF2ns79M+Ma6ZqlW 8JvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qkMqBx/0+QNy6vnPe5v+Jz8TEUxjmzu64DV0QiSa2s0=; b=LhqljK4OO4Ey3ub75n/z06OBRX3GnllTeaiPUuFqbXHqQrDZ5F9sERjOtZ97/gNA6/ pA4b6KmE6WRwCdJiCqZrrTCdt+KFLuhsnnDmAu+IAAith3/9SUH5+cofUi4mIYDgqsQf 9ID5GkBFPaXAxwiK8LbNU/lX8L69g9C5AVUzfTohmaPdrXVkygVSs0UUPjfCsujljBQh CgazcjlOa/i1Ps984Jvf2JeqCMSqdCJcco+1NJHe+Uo3lN/PPpRtkjFb4UWEL5v/9G5V MZhy1Wn/dHIJ0VZIiPkC0BIgy/sBm/cpqwbB9IxmKEFVQVjQzhGxU+ONZktUKeGV/GMD MKjw== X-Gm-Message-State: AOAM5322Gi+xsEYDsw3mEQScHu/TISp/wyzzya1RMa0dDTcSLBvN6cuS cFut4D1I26oDLcQdeecNF/QTNQ== X-Google-Smtp-Source: ABdhPJwEya7Yt//DDC9snEcs35LlqhKg12Ly2jycIW8hKh5tNzaUnDnBwup+oIug1i7BD+fdoyJqCg== X-Received: by 2002:a05:651c:1053:: with SMTP id x19mr394867ljm.192.1633656333965; Thu, 07 Oct 2021 18:25:33 -0700 (PDT) Received: from umbar.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id s4sm112875ljp.115.2021.10.07.18.25.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Oct 2021 18:25:33 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Linus Walleij , Rob Herring Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v3 09/25] ARM: dts: qcom-apq8060-dragonboard: fix mpps state names Date: Fri, 8 Oct 2021 04:25:08 +0300 Message-Id: <20211008012524.481877-10-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211008012524.481877-1-dmitry.baryshkov@linaro.org> References: <20211008012524.481877-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The majority of device tree nodes for mpps use xxxx-state as pinctrl nodes. Change names of mpps pinctrl nodes for qcom-apq8060-dragonboard board to follow that pattern. Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom-apq8060-dragonboard.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts index e1189e929ee6..5bedbb902ad5 100644 --- a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts +++ b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts @@ -357,8 +357,8 @@ pinconf { }; mpps@50 { - dragon_cm3605_mpps: cm3605-mpps { - pinconf { + dragon_cm3605_mpps: cm3605-mpps-state { + mpp5 { pins = "mpp5"; function = "analog"; input-enable; From patchwork Fri Oct 8 01:25:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12543991 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1E84CC433FE for ; Fri, 8 Oct 2021 01:25:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0C25E61425 for ; Fri, 8 Oct 2021 01:25:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238136AbhJHB1e (ORCPT ); Thu, 7 Oct 2021 21:27:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38844 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236988AbhJHB1a (ORCPT ); Thu, 7 Oct 2021 21:27:30 -0400 Received: from mail-lf1-x134.google.com (mail-lf1-x134.google.com [IPv6:2a00:1450:4864:20::134]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 38337C061769 for ; Thu, 7 Oct 2021 18:25:36 -0700 (PDT) Received: by mail-lf1-x134.google.com with SMTP id y26so32780706lfa.11 for ; Thu, 07 Oct 2021 18:25:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=N1fDvr411Sym7LpWWuQWuBZ0aeO9/HmmaZ6tC+1sj4g=; b=ZCazwiO1we07+uKMoAa7RwVQbCbUF9UKfbtkFo2Mmk+VOVvy/+ae6BDuvQdyF1EQAL KYMgzbnKSAhN1q/yomhgubVP7RAKJ8ohBxP3ODuboYxgkUrIHzHLNNLBH2Jkgwc+87vz eo+fU8SgS3BuGap2BZSRBQ8BK7l7RLisJ24NkcbeLKbH9CZhx6+/prRvHcJrmEgXT6/V 2UemRyGg5+tq6MtpVEJw26wkd/TCOU4V+9h5obvLDsXuRf7SFD10RVQ+Vetl2yEm2X8i ulMVDu9qWieV7bf32riRWtpHxiRIGTx2Qqf0N2uMmuxkTA9HWJMsqd61D9JPsuqhRfqK JB4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=N1fDvr411Sym7LpWWuQWuBZ0aeO9/HmmaZ6tC+1sj4g=; b=qG/qMQFF4by8/SD6Szu2TW6dXsesRtgz6MN3WNVoIpXyrBVwKYrhIbA6DtxWtrDbip /Y61dmBGHjDisUmgcSg3xbuIdTyfLKWnGW1BqsoeO2m9dnnocqYC7jn8nku6DvQGnL6c bDC5P3iFBrdBA61SH+wvlhdqaZ8AznO9PF6xrWDORtA5j7zcLZ+ZF5vR7mxfryd23Kr1 uPH6XpiHUFtNQxMOOUTK4pY4DQxfm0oqvy9a8hyNcNTeaR8sEsOIAtBFLytzcKr8+nNt lxC0qt3by7im0I4D3XNmDR2VmzS1MtMgaZLmQBY5EG6oyfedCQRc4wH1U20FLFB1Yf7L yAGQ== X-Gm-Message-State: AOAM530nVlcJHETQxxZapXBhodmqQ2aIo3h1eAPOvYQVJVJD2wVE1vD1 fjVMiUKOzKE1m+Z2Cp6y7G3bNA== X-Google-Smtp-Source: ABdhPJy1PwY9wFw5I6HLxquQsYiQDQ7Wz4P9jG7QZ7mH/UqeE2jxqqAPcM4IHoemrhfQ2baaZbT1qA== X-Received: by 2002:a2e:544a:: with SMTP id y10mr338686ljd.323.1633656334612; Thu, 07 Oct 2021 18:25:34 -0700 (PDT) Received: from umbar.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id s4sm112875ljp.115.2021.10.07.18.25.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Oct 2021 18:25:34 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Linus Walleij , Rob Herring Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v3 10/25] arm64: dts: qcom: pm8916: fix mpps device tree node Date: Fri, 8 Oct 2021 04:25:09 +0300 Message-Id: <20211008012524.481877-11-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211008012524.481877-1-dmitry.baryshkov@linaro.org> References: <20211008012524.481877-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add missing "qcom,spmi-mpp" to the compatible list as required by the node description. Also add gpio-ranges property to mpps device tree node, adding the mapping between pinctrl and GPIO pins. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/pm8916.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/pm8916.dtsi b/arch/arm64/boot/dts/qcom/pm8916.dtsi index f931cb0de231..7d9e25dd9e3a 100644 --- a/arch/arm64/boot/dts/qcom/pm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8916.dtsi @@ -91,10 +91,11 @@ rtc@6000 { }; pm8916_mpps: mpps@a000 { - compatible = "qcom,pm8916-mpp"; + compatible = "qcom,pm8916-mpp", "qcom,spmi-mpp"; reg = <0xa000>; gpio-controller; #gpio-cells = <2>; + gpio-ranges = <&pm8916_mpps 0 0 4>; interrupts = <0 0xa0 0 IRQ_TYPE_NONE>, <0 0xa1 0 IRQ_TYPE_NONE>, <0 0xa2 0 IRQ_TYPE_NONE>, From patchwork Fri Oct 8 01:25:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12543993 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7B0AAC433FE for ; Fri, 8 Oct 2021 01:25:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 65FFC61506 for ; Fri, 8 Oct 2021 01:25:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236988AbhJHB1g (ORCPT ); Thu, 7 Oct 2021 21:27:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38912 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237830AbhJHB1b (ORCPT ); Thu, 7 Oct 2021 21:27:31 -0400 Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E2F27C061764 for ; Thu, 7 Oct 2021 18:25:36 -0700 (PDT) Received: by mail-lf1-x12c.google.com with SMTP id n8so30599077lfk.6 for ; Thu, 07 Oct 2021 18:25:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=y8Kd+xfjEORBsc4n3BHzpntVG1Hf41evxmwe7Q2QRKE=; b=lCqUcM67pzlHiAgtQf7DThs1V02qml9XsYsykqJuO9bO4pqrtKSpRNE6Vix9wzFr+i G3e35aULKRtlM1eL6Uba/fti8dmqhRQxfTxAmT1RwFQnv1P/gu9e6G9OsRXIK7+IpzWF TDrRHAHK/v5tglF6Tk3LuK6dazkZLklskVUTODbH0a8owKNzVQC0c8of/tn1mJz41gW2 mM5iT6lG13VEdvQxELS+1jmz0L5halJwMPklKAGhl2+8Wds9B27zBAJLV6ZLfdky9w6c UWJ6w/lfXcYeMQRAF7vJVcQNVPlmheYAI7K/C6ZMpQC8Sg0aDFnSYXrD527DSDGCSxVD SM7g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=y8Kd+xfjEORBsc4n3BHzpntVG1Hf41evxmwe7Q2QRKE=; b=2E+zHL4hTb0+fWfSzh1FywyY3x7weQXfX6IIhNrLNcwd96K43Pmq2zzmsFgmNnmT1j YITxzVYjacyc+e08RYkf4XKjc9MY3LXs0Te2gpyAaeMYmRQ/jrsQ0e1cckoDsS+rxsb2 skK+O4L6dFCmaOuI4Hj77F1trYE2sDSipJheUztxiVuRc9vQoMGG2kISJYp56YpApGvH tbtfimVAyPQ6vUuOCf02j+AZA6q4Z+ei9ahtOQ9uGf0QDF5c3KMEepIPKKZEtHraqo3T W5b/jsbZ82/ReHqaHbgwIEjxYTB77RsifZ/RmDKAAhDzMeWumLfEh9v1ysf1tFvqwzD7 6nww== X-Gm-Message-State: AOAM530aZmcc8LtBTprAUgALTSpB2yBYhnkrJgXR+jJs6Vii1iifCu5g MT9wyLIAorZh71f5zSVYAowxPQ== X-Google-Smtp-Source: ABdhPJwEzudtRN+UIRr5UjSZt36BotkT/oqZHPeRL1+Y8hKKotIxmNoTgLuKsSa/3NgQtg732V8QlQ== X-Received: by 2002:a2e:2f1b:: with SMTP id v27mr357533ljv.448.1633656335324; Thu, 07 Oct 2021 18:25:35 -0700 (PDT) Received: from umbar.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id s4sm112875ljp.115.2021.10.07.18.25.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Oct 2021 18:25:34 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Linus Walleij , Rob Herring Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v3 11/25] arm64: dts: qcom: pm8994: fix mpps device tree node Date: Fri, 8 Oct 2021 04:25:10 +0300 Message-Id: <20211008012524.481877-12-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211008012524.481877-1-dmitry.baryshkov@linaro.org> References: <20211008012524.481877-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add missing "qcom,spmi-mpp" to the compatible list as required by the node description. Also add gpio-ranges property to mpps device tree node, adding the mapping between pinctrl and GPIO pins. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/pm8994.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/pm8994.dtsi b/arch/arm64/boot/dts/qcom/pm8994.dtsi index ad19016df047..88a9d19b60ac 100644 --- a/arch/arm64/boot/dts/qcom/pm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8994.dtsi @@ -119,10 +119,11 @@ pm8994_gpios: gpios@c000 { }; pm8994_mpps: mpps@a000 { - compatible = "qcom,pm8994-mpp"; + compatible = "qcom,pm8994-mpp", "qcom,spmi-mpp"; reg = <0xa000>; gpio-controller; #gpio-cells = <2>; + gpio-ranges = <&pm8994_mpps 0 0 8>; interrupts = <0 0xa0 0 IRQ_TYPE_NONE>, <0 0xa1 0 IRQ_TYPE_NONE>, <0 0xa2 0 IRQ_TYPE_NONE>, From patchwork Fri Oct 8 01:25:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12543995 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0E7B7C433EF for ; Fri, 8 Oct 2021 01:25:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id F07236142A for ; Fri, 8 Oct 2021 01:25:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239061AbhJHB1l (ORCPT ); Thu, 7 Oct 2021 21:27:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38906 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236805AbhJHB1c (ORCPT ); Thu, 7 Oct 2021 21:27:32 -0400 Received: from mail-lf1-x131.google.com (mail-lf1-x131.google.com [IPv6:2a00:1450:4864:20::131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9F99CC061772 for ; Thu, 7 Oct 2021 18:25:37 -0700 (PDT) Received: by mail-lf1-x131.google.com with SMTP id b20so32911285lfv.3 for ; Thu, 07 Oct 2021 18:25:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+kHxD4AyFKHTUkzUIxG/0HGOEUmjqFeIEbITSocdKfU=; b=FnMeBDx4co3rsikNmA1+yvAsBmxVSkiWs5uWbbwykTb4OfQVbqqzyofcLbaA/OeBbU 5lFh3JQm9/xHlSNWM+xdsRNLzzGpKY3s6B0sSE9eU2GB9wZUmHhUTEJEYX1kOya4MV6q L6DpFPTtXVpbVwnhr3bryYfzAUjfRnoUAtw6ofnOu/+RhslY7TUA54T0xBekKxQYKGRK prTgFfgfgau71HWn0+4NAjzNk3yfvqx5JV4yY77kXNJ/ArBufx0hc7zKJ2E9YdsiYJzg VCbEwswd+sq9yDKO2D5o88li6S7B9gJu1lHpH29lOiff0ULC1S2dpxlwCZqnI0U21OqY 4mqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+kHxD4AyFKHTUkzUIxG/0HGOEUmjqFeIEbITSocdKfU=; b=o89GZAKW8PU1NcLyz5dFETxXfxT7s3wqX4uO09rgiFD0t8iQarGfPrsvpwTeynuog4 picJqpCTudD/XI330Y9kvBBbVwCMsrL49kS2PQN3uuQ4W29zbl5XiJ6Nyle2RmyDDOBP 2R4+lI4vcl8TTWbbcNK7jsXAttcmChaBp+zhkFQQS1ZWZ059ccNBrcRXZPqOXBzZQj8T X/Gvcj+XJ7nZ4n881bT55YPoSxcb0kEJKqnXGLX8ymIJ7pt7Wwys8l23SfHqLhVRRt19 xEO4ISMHFrg2BEObQD8beS4Lq4De637KLD7jXulkUtSh2zKHz/vvLANOQ8JkOKucy8eD e5Ww== X-Gm-Message-State: AOAM533tusRA0h4fpfX7K7A1aMJ4MqSZIXDGIbSPyBqhJFHEoD2OAcwz icJTYzL3n7PZbWaQbm9YwQf15Q== X-Google-Smtp-Source: ABdhPJy80doFhzt0+g2B6bpAXm2L2Zu5Oaz1R/LM20rb7sLWCWSe8CY9FhMqcWitOVN9d1RDTYrHrA== X-Received: by 2002:a05:6512:3d13:: with SMTP id d19mr7190869lfv.607.1633656336004; Thu, 07 Oct 2021 18:25:36 -0700 (PDT) Received: from umbar.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id s4sm112875ljp.115.2021.10.07.18.25.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Oct 2021 18:25:35 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Linus Walleij , Rob Herring Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v3 12/25] arm64: dts: qcom: apq8016-sbc: fix mpps state names Date: Fri, 8 Oct 2021 04:25:11 +0300 Message-Id: <20211008012524.481877-13-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211008012524.481877-1-dmitry.baryshkov@linaro.org> References: <20211008012524.481877-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The majority of device tree nodes for mpps use xxxx-state as pinctrl nodes. Change names of mpps pinctrl nodes for the apq8016-sbc board to follow that pattern. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi index f8d8f3e3664e..a250145849cd 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi @@ -809,7 +809,7 @@ &pm8916_mpps { pinctrl-names = "default"; pinctrl-0 = <&ls_exp_gpio_f>; - ls_exp_gpio_f: pm8916-mpp4 { + ls_exp_gpio_f: pm8916-mpp4-state { pins = "mpp4"; function = "digital"; @@ -817,7 +817,7 @@ ls_exp_gpio_f: pm8916-mpp4 { power-source = ; // 1.8V }; - pm8916_mpps_leds: pm8916-mpps-leds { + pm8916_mpps_leds: pm8916-mpps-state { pins = "mpp2", "mpp3"; function = "digital"; From patchwork Fri Oct 8 01:25:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12543997 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F23EEC4321E for ; Fri, 8 Oct 2021 01:25:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DE7076141B for ; Fri, 8 Oct 2021 01:25:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241640AbhJHB1m (ORCPT ); Thu, 7 Oct 2021 21:27:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38868 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234268AbhJHB1d (ORCPT ); Thu, 7 Oct 2021 21:27:33 -0400 Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [IPv6:2a00:1450:4864:20::130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3CCF8C061570 for ; Thu, 7 Oct 2021 18:25:38 -0700 (PDT) Received: by mail-lf1-x130.google.com with SMTP id n8so30599291lfk.6 for ; Thu, 07 Oct 2021 18:25:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=B1tfgMXD/HCZM2/dbxQ/czHnewIDG6QY34tUjSKvwfk=; b=HREMM7YvdSBGH5yCfeBE1GD/MG6qFX3jZvB/hGwR7HZ7db3jFWbR6EjuTL16AfB5UQ koYroB34dm/ZoDXxlxZVaIHC4zdDpnu6Vy7uRPrWOm4t2C6XxRFlKNFN4bTUuSTVTNQY vWACLWBR1Dx5Fz8akQdBCY0VkhkjI8/HeGv+6PNn0pwg170Zq0EUF59oUw3iZN0/fLHe czilOud48xH7CG4PmSkcxH9wRtV9Z1XSRrA24s+ddMsvShtrB0qTXgf9QcU0USltGVH/ 1Do+dge+n5Hnn6CI7GkrIBwFtvS0ZZ7AmfQJzIjXrhHvobw1K1U5m8Eo4xvBONkk8TOi wjZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=B1tfgMXD/HCZM2/dbxQ/czHnewIDG6QY34tUjSKvwfk=; b=5MJL2/lhHd9AoGazBHBz+RR1RQcEgwCvMv+hEtSFLJbE3EGmmmkCzCa02UanBcIsXG FmfkEOIwUvtZ7u7L31879OxyELlJDzX7jvN29+0YrZdiJTXZy/MKSaBvdr4TnzqyFGjs lwSAhyWdB/7YMhOaQObruGEZijjndndclcjqRBzJe2uqpJIeEw+q/PGZPOt4Beo6K5eQ WxKOZeN8Dkm0CafE8XfI1FAfTNsTAeH3zn36PSmIvo9E+YLjNW3jC1/3cWtX3OkcCx3E OKbgha/Ru02xOAfd/DoZaNl+/Yxt2N+pSRLS9nUGeCiNcmMoWgBg9nVrjilsxQYKV8U6 ZEIQ== X-Gm-Message-State: AOAM533sETCEfZ9vqtgoXfuR7R4QueveQKVl16efaarQXbhS8UFWSiYI LH6dA4HvFJX5e8oevCcn3OotHA== X-Google-Smtp-Source: ABdhPJzKdd8/qODtRD3p+6nMYsqC38bIDPZxHTkZ4qvkzYmr0yp6kv6J7YzSEnI+Jxi416yc+t6QVA== X-Received: by 2002:a05:6512:96f:: with SMTP id v15mr7510057lft.455.1633656336652; Thu, 07 Oct 2021 18:25:36 -0700 (PDT) Received: from umbar.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id s4sm112875ljp.115.2021.10.07.18.25.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Oct 2021 18:25:36 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Linus Walleij , Rob Herring Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v3 13/25] pinctrl: qcom: ssbi-mpp: hardcode IRQ counts Date: Fri, 8 Oct 2021 04:25:12 +0300 Message-Id: <20211008012524.481877-14-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211008012524.481877-1-dmitry.baryshkov@linaro.org> References: <20211008012524.481877-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The probing of this driver calls platform_irq_count, which will setup all of the IRQs that are configured in device tree. In preparation for converting this driver to be a hierarchical IRQ chip, hardcode the IRQ count based on the hardware type so that all the IRQs are not configured immediately and are configured on an as-needed basis later in the boot process. This change will also allow for the removal of the interrupts property later in this patch series once the hierarchical IRQ chip support is in. This patch also removes the generic qcom,ssbi-mpp OF match since we don't know the number of pins. All of the existing upstream bindings already include the more-specific binding. Signed-off-by: Dmitry Baryshkov Reviewed-by: Bjorn Andersson --- drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c | 22 ++++++++-------------- 1 file changed, 8 insertions(+), 14 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c b/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c index 92e7f2602847..a90cada1d657 100644 --- a/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c +++ b/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c @@ -733,13 +733,12 @@ static int pm8xxx_pin_populate(struct pm8xxx_mpp *pctrl, } static const struct of_device_id pm8xxx_mpp_of_match[] = { - { .compatible = "qcom,pm8018-mpp" }, - { .compatible = "qcom,pm8038-mpp" }, - { .compatible = "qcom,pm8058-mpp" }, - { .compatible = "qcom,pm8917-mpp" }, - { .compatible = "qcom,pm8821-mpp" }, - { .compatible = "qcom,pm8921-mpp" }, - { .compatible = "qcom,ssbi-mpp" }, + { .compatible = "qcom,pm8018-mpp", .data = (void *) 6 }, + { .compatible = "qcom,pm8038-mpp", .data = (void *) 6 }, + { .compatible = "qcom,pm8058-mpp", .data = (void *) 12 }, + { .compatible = "qcom,pm8821-mpp", .data = (void *) 4 }, + { .compatible = "qcom,pm8917-mpp", .data = (void *) 10 }, + { .compatible = "qcom,pm8921-mpp", .data = (void *) 12 }, { }, }; MODULE_DEVICE_TABLE(of, pm8xxx_mpp_of_match); @@ -750,19 +749,14 @@ static int pm8xxx_mpp_probe(struct platform_device *pdev) struct pinctrl_pin_desc *pins; struct pm8xxx_mpp *pctrl; int ret; - int i, npins; + int i; pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); if (!pctrl) return -ENOMEM; pctrl->dev = &pdev->dev; - npins = platform_irq_count(pdev); - if (!npins) - return -EINVAL; - if (npins < 0) - return npins; - pctrl->npins = npins; + pctrl->npins = (uintptr_t) device_get_match_data(&pdev->dev); pctrl->regmap = dev_get_regmap(pdev->dev.parent, NULL); if (!pctrl->regmap) { From patchwork Fri Oct 8 01:25:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12543999 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8000CC4167D for ; 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Thu, 07 Oct 2021 18:25:37 -0700 (PDT) Received: from umbar.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id s4sm112875ljp.115.2021.10.07.18.25.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Oct 2021 18:25:36 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Linus Walleij , Rob Herring Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v3 14/25] pinctrl: qcom: ssbi-mpp: add support for hierarchical IRQ chip Date: Fri, 8 Oct 2021 04:25:13 +0300 Message-Id: <20211008012524.481877-15-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211008012524.481877-1-dmitry.baryshkov@linaro.org> References: <20211008012524.481877-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org ssbi-mpp did not have any irqchip support so consumers of this in device tree would need to call gpio[d]_to_irq() in order to get the proper IRQ on the underlying PMIC. IRQ chips in device tree should be usable from the start without the consumer having to make an additional call to get the proper IRQ on the parent. This patch adds hierarchical IRQ chip support to the ssbi-mpp code to correct this issue. Signed-off-by: Dmitry Baryshkov Reviewed-by: Bjorn Andersson --- drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c | 111 ++++++++++++++++++++---- 1 file changed, 93 insertions(+), 18 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c b/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c index a90cada1d657..842940594c4a 100644 --- a/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c +++ b/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c @@ -87,7 +87,6 @@ /** * struct pm8xxx_pin_data - dynamic configuration for a pin * @reg: address of the control register - * @irq: IRQ from the PMIC interrupt controller * @mode: operating mode for the pin (digital, analog or current sink) * @input: pin is input * @output: pin is output @@ -103,7 +102,6 @@ */ struct pm8xxx_pin_data { unsigned reg; - int irq; u8 mode; @@ -126,6 +124,7 @@ struct pm8xxx_mpp { struct regmap *regmap; struct pinctrl_dev *pctrl; struct gpio_chip chip; + struct irq_chip irq; struct pinctrl_desc desc; unsigned npins; @@ -148,6 +147,8 @@ static const struct pin_config_item pm8xxx_conf_items[] = { #endif #define PM8XXX_MAX_MPPS 12 +#define PM8XXX_MPP_PHYSICAL_OFFSET 1 + static const char * const pm8xxx_groups[PM8XXX_MAX_MPPS] = { "mpp1", "mpp2", "mpp3", "mpp4", "mpp5", "mpp6", "mpp7", "mpp8", "mpp9", "mpp10", "mpp11", "mpp12", @@ -492,12 +493,16 @@ static int pm8xxx_mpp_get(struct gpio_chip *chip, unsigned offset) struct pm8xxx_mpp *pctrl = gpiochip_get_data(chip); struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; bool state; - int ret; + int ret, irq; if (!pin->input) return !!pin->output_value; - ret = irq_get_irqchip_state(pin->irq, IRQCHIP_STATE_LINE_LEVEL, &state); + irq = chip->to_irq(chip, offset); + if (irq < 0) + return irq; + + ret = irq_get_irqchip_state(irq, IRQCHIP_STATE_LINE_LEVEL, &state); if (!ret) ret = !!state; @@ -524,18 +529,10 @@ static int pm8xxx_mpp_of_xlate(struct gpio_chip *chip, if (flags) *flags = gpio_desc->args[1]; - return gpio_desc->args[0] - 1; + return gpio_desc->args[0] - PM8XXX_MPP_PHYSICAL_OFFSET; } -static int pm8xxx_mpp_to_irq(struct gpio_chip *chip, unsigned offset) -{ - struct pm8xxx_mpp *pctrl = gpiochip_get_data(chip); - struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; - - return pin->irq; -} - #ifdef CONFIG_DEBUG_FS #include @@ -558,7 +555,7 @@ static void pm8xxx_mpp_dbg_show_one(struct seq_file *s, "abus3", }; - seq_printf(s, " mpp%-2d:", offset + 1); + seq_printf(s, " mpp%-2d:", offset + PM8XXX_MPP_PHYSICAL_OFFSET); switch (pin->mode) { case PM8XXX_MPP_DIGITAL: @@ -640,7 +637,6 @@ static const struct gpio_chip pm8xxx_mpp_template = { .get = pm8xxx_mpp_get, .set = pm8xxx_mpp_set, .of_xlate = pm8xxx_mpp_of_xlate, - .to_irq = pm8xxx_mpp_to_irq, .dbg_show = pm8xxx_mpp_dbg_show, .owner = THIS_MODULE, }; @@ -732,6 +728,55 @@ static int pm8xxx_pin_populate(struct pm8xxx_mpp *pctrl, return 0; } +static int pm8xxx_mpp_domain_translate(struct irq_domain *domain, + struct irq_fwspec *fwspec, + unsigned long *hwirq, + unsigned int *type) +{ + struct pm8xxx_mpp *pctrl = container_of(domain->host_data, + struct pm8xxx_mpp, chip); + + if (fwspec->param_count != 2 || + fwspec->param[0] < PM8XXX_MPP_PHYSICAL_OFFSET || + fwspec->param[0] > pctrl->chip.ngpio) + return -EINVAL; + + *hwirq = fwspec->param[0] - PM8XXX_MPP_PHYSICAL_OFFSET; + *type = fwspec->param[1]; + + return 0; +} + +static unsigned int pm8xxx_mpp_child_offset_to_irq(struct gpio_chip *chip, + unsigned int offset) +{ + return offset + PM8XXX_MPP_PHYSICAL_OFFSET; +} + +static int pm8821_mpp_child_to_parent_hwirq(struct gpio_chip *chip, + unsigned int child_hwirq, + unsigned int child_type, + unsigned int *parent_hwirq, + unsigned int *parent_type) +{ + *parent_hwirq = child_hwirq + 24; + *parent_type = child_type; + + return 0; +} + +static int pm8xxx_mpp_child_to_parent_hwirq(struct gpio_chip *chip, + unsigned int child_hwirq, + unsigned int child_type, + unsigned int *parent_hwirq, + unsigned int *parent_type) +{ + *parent_hwirq = child_hwirq + 0x80; + *parent_type = child_type; + + return 0; +} + static const struct of_device_id pm8xxx_mpp_of_match[] = { { .compatible = "qcom,pm8018-mpp", .data = (void *) 6 }, { .compatible = "qcom,pm8038-mpp", .data = (void *) 6 }, @@ -746,7 +791,10 @@ MODULE_DEVICE_TABLE(of, pm8xxx_mpp_of_match); static int pm8xxx_mpp_probe(struct platform_device *pdev) { struct pm8xxx_pin_data *pin_data; + struct irq_domain *parent_domain; + struct device_node *parent_node; struct pinctrl_pin_desc *pins; + struct gpio_irq_chip *girq; struct pm8xxx_mpp *pctrl; int ret; int i; @@ -783,9 +831,6 @@ static int pm8xxx_mpp_probe(struct platform_device *pdev) for (i = 0; i < pctrl->desc.npins; i++) { pin_data[i].reg = SSBI_REG_ADDR_MPP(i); - pin_data[i].irq = platform_get_irq(pdev, i); - if (pin_data[i].irq < 0) - return pin_data[i].irq; ret = pm8xxx_pin_populate(pctrl, &pin_data[i]); if (ret) @@ -816,6 +861,36 @@ static int pm8xxx_mpp_probe(struct platform_device *pdev) pctrl->chip.of_gpio_n_cells = 2; pctrl->chip.label = dev_name(pctrl->dev); pctrl->chip.ngpio = pctrl->npins; + + parent_node = of_irq_find_parent(pctrl->dev->of_node); + if (!parent_node) + return -ENXIO; + + parent_domain = irq_find_host(parent_node); + of_node_put(parent_node); + if (!parent_domain) + return -ENXIO; + + pctrl->irq.name = "ssbi-mpp"; + pctrl->irq.irq_mask_ack = irq_chip_mask_ack_parent; + pctrl->irq.irq_unmask = irq_chip_unmask_parent; + pctrl->irq.irq_set_type = irq_chip_set_type_parent; + pctrl->irq.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE; + + girq = &pctrl->chip.irq; + girq->chip = &pctrl->irq; + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_level_irq; + girq->fwnode = of_node_to_fwnode(pctrl->dev->of_node); + girq->parent_domain = parent_domain; + if (of_device_is_compatible(pdev->dev.of_node, "qcom,pm8821-mpp")) + girq->child_to_parent_hwirq = pm8821_mpp_child_to_parent_hwirq; + else + girq->child_to_parent_hwirq = pm8xxx_mpp_child_to_parent_hwirq; + girq->populate_parent_alloc_arg = gpiochip_populate_parent_fwspec_twocell; + girq->child_offset_to_irq = pm8xxx_mpp_child_offset_to_irq; + girq->child_irq_domain_ops.translate = pm8xxx_mpp_domain_translate; + ret = gpiochip_add_data(&pctrl->chip, pctrl); if (ret) { dev_err(&pdev->dev, "failed register gpiochip\n"); From patchwork Fri Oct 8 01:25:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12544001 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9302DC4167B for ; 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Thu, 07 Oct 2021 18:25:37 -0700 (PDT) Received: from umbar.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id s4sm112875ljp.115.2021.10.07.18.25.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Oct 2021 18:25:37 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Linus Walleij , Rob Herring Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v3 15/25] pinctrl: qcom: spmi-mpp: hardcode IRQ counts Date: Fri, 8 Oct 2021 04:25:14 +0300 Message-Id: <20211008012524.481877-16-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211008012524.481877-1-dmitry.baryshkov@linaro.org> References: <20211008012524.481877-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The probing of this driver calls platform_irq_count, which will setup all of the IRQs that are configured in device tree. In preparation for converting this driver to be a hierarchical IRQ chip, hardcode the IRQ count based on the hardware type so that all the IRQs are not configured immediately and are configured on an as-needed basis later in the boot process. This change will also allow for the removal of the interrupts property later in this patch series once the hierarchical IRQ chip support is in. This patch also removes the generic qcom,spmi-mpp OF match since we don't know the number of pins. All of the existing upstream bindings already include the more-specific binding. Signed-off-by: Dmitry Baryshkov Reviewed-by: Bjorn Andersson --- drivers/pinctrl/qcom/pinctrl-spmi-mpp.c | 25 ++++++++++--------------- 1 file changed, 10 insertions(+), 15 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c index 2da9b5f68f3f..a9f994863126 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c @@ -812,11 +812,7 @@ static int pmic_mpp_probe(struct platform_device *pdev) return ret; } - npins = platform_irq_count(pdev); - if (!npins) - return -EINVAL; - if (npins < 0) - return npins; + npins = (uintptr_t) device_get_match_data(&pdev->dev); BUG_ON(npins > ARRAY_SIZE(pmic_mpp_groups)); @@ -912,16 +908,15 @@ static int pmic_mpp_remove(struct platform_device *pdev) } static const struct of_device_id pmic_mpp_of_match[] = { - { .compatible = "qcom,pm8019-mpp" }, /* 6 MPP's */ - { .compatible = "qcom,pm8841-mpp" }, /* 4 MPP's */ - { .compatible = "qcom,pm8916-mpp" }, /* 4 MPP's */ - { .compatible = "qcom,pm8941-mpp" }, /* 8 MPP's */ - { .compatible = "qcom,pm8950-mpp" }, /* 4 MPP's */ - { .compatible = "qcom,pmi8950-mpp" }, /* 4 MPP's */ - { .compatible = "qcom,pm8994-mpp" }, /* 8 MPP's */ - { .compatible = "qcom,pma8084-mpp" }, /* 8 MPP's */ - { .compatible = "qcom,pmi8994-mpp" }, /* 4 MPP's */ - { .compatible = "qcom,spmi-mpp" }, /* Generic */ + { .compatible = "qcom,pm8019-mpp", .data = (void *) 6 }, + { .compatible = "qcom,pm8841-mpp", .data = (void *) 4 }, + { .compatible = "qcom,pm8916-mpp", .data = (void *) 4 }, + { .compatible = "qcom,pm8941-mpp", .data = (void *) 8 }, + { .compatible = "qcom,pm8950-mpp", .data = (void *) 4 }, + { .compatible = "qcom,pmi8950-mpp", .data = (void *) 4 }, + { .compatible = "qcom,pm8994-mpp", .data = (void *) 8 }, + { .compatible = "qcom,pma8084-mpp", .data = (void *) 8 }, + { .compatible = "qcom,pmi8994-mpp", .data = (void *) 4 }, { }, }; From patchwork Fri Oct 8 01:25:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12544003 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D2606C07EBB for ; Fri, 8 Oct 2021 01:25:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B7E3461506 for ; Fri, 8 Oct 2021 01:25:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238708AbhJHB1o (ORCPT ); Thu, 7 Oct 2021 21:27:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38904 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229529AbhJHB1i (ORCPT ); Thu, 7 Oct 2021 21:27:38 -0400 Received: from mail-lf1-x133.google.com (mail-lf1-x133.google.com [IPv6:2a00:1450:4864:20::133]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 381DDC061775 for ; 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Thu, 07 Oct 2021 18:25:38 -0700 (PDT) Received: from umbar.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id s4sm112875ljp.115.2021.10.07.18.25.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Oct 2021 18:25:38 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Linus Walleij , Rob Herring Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v3 16/25] pinctrl: qcom: spmi-mpp: add support for hierarchical IRQ chip Date: Fri, 8 Oct 2021 04:25:15 +0300 Message-Id: <20211008012524.481877-17-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211008012524.481877-1-dmitry.baryshkov@linaro.org> References: <20211008012524.481877-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org spmi-mpp did not have any irqchip support so consumers of this in device tree would need to call gpio[d]_to_irq() in order to get the proper IRQ on the underlying PMIC. IRQ chips in device tree should be usable from the start without the consumer having to make an additional call to get the proper IRQ on the parent. This patch adds hierarchical IRQ chip support to the spmi-mpp code to correct this issue. Signed-off-by: Dmitry Baryshkov Reviewed-by: Bjorn Andersson --- drivers/pinctrl/qcom/pinctrl-spmi-mpp.c | 86 ++++++++++++++++++++----- 1 file changed, 69 insertions(+), 17 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c index a9f994863126..b80723928b7e 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c @@ -103,7 +103,6 @@ /** * struct pmic_mpp_pad - keep current MPP settings * @base: Address base in SPMI device. - * @irq: IRQ number which this MPP generate. * @is_enabled: Set to false when MPP should be put in high Z state. * @out_value: Cached pin output value. * @output_enabled: Set to true if MPP output logic is enabled. @@ -121,7 +120,6 @@ */ struct pmic_mpp_pad { u16 base; - int irq; bool is_enabled; bool out_value; bool output_enabled; @@ -143,6 +141,7 @@ struct pmic_mpp_state { struct regmap *map; struct pinctrl_dev *ctrl; struct gpio_chip chip; + struct irq_chip irq; }; static const struct pinconf_generic_params pmic_mpp_bindings[] = { @@ -622,16 +621,6 @@ static int pmic_mpp_of_xlate(struct gpio_chip *chip, return gpio_desc->args[0] - PMIC_MPP_PHYSICAL_OFFSET; } -static int pmic_mpp_to_irq(struct gpio_chip *chip, unsigned pin) -{ - struct pmic_mpp_state *state = gpiochip_get_data(chip); - struct pmic_mpp_pad *pad; - - pad = state->ctrl->desc->pins[pin].drv_data; - - return pad->irq; -} - static void pmic_mpp_dbg_show(struct seq_file *s, struct gpio_chip *chip) { struct pmic_mpp_state *state = gpiochip_get_data(chip); @@ -651,7 +640,6 @@ static const struct gpio_chip pmic_mpp_gpio_template = { .request = gpiochip_generic_request, .free = gpiochip_generic_free, .of_xlate = pmic_mpp_of_xlate, - .to_irq = pmic_mpp_to_irq, .dbg_show = pmic_mpp_dbg_show, }; @@ -796,13 +784,53 @@ static int pmic_mpp_populate(struct pmic_mpp_state *state, return 0; } +static int pmic_mpp_domain_translate(struct irq_domain *domain, + struct irq_fwspec *fwspec, + unsigned long *hwirq, + unsigned int *type) +{ + struct pmic_mpp_state *state = container_of(domain->host_data, + struct pmic_mpp_state, + chip); + + if (fwspec->param_count != 2 || + fwspec->param[0] < 1 || fwspec->param[0] > state->chip.ngpio) + return -EINVAL; + + *hwirq = fwspec->param[0] - PMIC_MPP_PHYSICAL_OFFSET; + *type = fwspec->param[1]; + + return 0; +} + +static unsigned int pmic_mpp_child_offset_to_irq(struct gpio_chip *chip, + unsigned int offset) +{ + return offset + PMIC_MPP_PHYSICAL_OFFSET; +} + +static int pmic_mpp_child_to_parent_hwirq(struct gpio_chip *chip, + unsigned int child_hwirq, + unsigned int child_type, + unsigned int *parent_hwirq, + unsigned int *parent_type) +{ + *parent_hwirq = child_hwirq + 0xc0; + *parent_type = child_type; + + return 0; +} + static int pmic_mpp_probe(struct platform_device *pdev) { + struct irq_domain *parent_domain; + struct device_node *parent_node; struct device *dev = &pdev->dev; struct pinctrl_pin_desc *pindesc; struct pinctrl_desc *pctrldesc; struct pmic_mpp_pad *pad, *pads; struct pmic_mpp_state *state; + struct gpio_irq_chip *girq; int ret, npins, i; u32 reg; @@ -857,10 +885,6 @@ static int pmic_mpp_probe(struct platform_device *pdev) pindesc->number = i; pindesc->name = pmic_mpp_groups[i]; - pad->irq = platform_get_irq(pdev, i); - if (pad->irq < 0) - return pad->irq; - pad->base = reg + i * PMIC_MPP_ADDRESS_RANGE; ret = pmic_mpp_populate(state, pad); @@ -880,6 +904,34 @@ static int pmic_mpp_probe(struct platform_device *pdev) if (IS_ERR(state->ctrl)) return PTR_ERR(state->ctrl); + parent_node = of_irq_find_parent(state->dev->of_node); + if (!parent_node) + return -ENXIO; + + parent_domain = irq_find_host(parent_node); + of_node_put(parent_node); + if (!parent_domain) + return -ENXIO; + + state->irq.name = "spmi-mpp", + state->irq.irq_ack = irq_chip_ack_parent, + state->irq.irq_mask = irq_chip_mask_parent, + state->irq.irq_unmask = irq_chip_unmask_parent, + state->irq.irq_set_type = irq_chip_set_type_parent, + state->irq.irq_set_wake = irq_chip_set_wake_parent, + state->irq.flags = IRQCHIP_MASK_ON_SUSPEND, + + girq = &state->chip.irq; + girq->chip = &state->irq; + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_level_irq; + girq->fwnode = of_node_to_fwnode(state->dev->of_node); + girq->parent_domain = parent_domain; + girq->child_to_parent_hwirq = pmic_mpp_child_to_parent_hwirq; + girq->populate_parent_alloc_arg = gpiochip_populate_parent_fwspec_fourcell; + girq->child_offset_to_irq = pmic_mpp_child_offset_to_irq; + girq->child_irq_domain_ops.translate = pmic_mpp_domain_translate; + ret = gpiochip_add_data(&state->chip, state); if (ret) { dev_err(state->dev, "can't add gpio chip\n"); From patchwork Fri Oct 8 01:25:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12544005 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CA0E7C10DC1 for ; Fri, 8 Oct 2021 01:25:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B0C8F61401 for ; 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Thu, 07 Oct 2021 18:25:38 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Linus Walleij , Rob Herring Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v3 17/25] dt-bindings: pinctrl: qcom,pmic-mpp: switch to #interrupt-cells Date: Fri, 8 Oct 2021 04:25:16 +0300 Message-Id: <20211008012524.481877-18-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211008012524.481877-1-dmitry.baryshkov@linaro.org> References: <20211008012524.481877-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Stop specifying individual interrupts properties. Use #interrupt-cells instead as we are switching qcom,spmi-mpp and qcom,ssbi-mpp to hierarchical IRQ setup. Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml index 475733cabb02..35c846f59979 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml @@ -40,12 +40,10 @@ properties: reg: maxItems: 1 - interrupts: - minItems: 1 - maxItems: 12 - description: - Must contain an array of encoded interrupt specifiers for - each available MPP + interrupt-controller: true + + '#interrupt-cells': + const: 2 gpio-controller: true gpio-line-names: true @@ -67,6 +65,7 @@ required: - gpio-controller - '#gpio-cells' - gpio-ranges + - interrupt-controller patternProperties: '-state$': @@ -164,7 +163,8 @@ examples: gpio-ranges = <&pm8841_mpp 0 0 4>; gpio-line-names = "VDD_PX_BIAS", "WLAN_LED_CTRL", "BT_LED_CTRL", "GPIO-F"; - interrupts = <4 0xa0 0 0>, <4 0xa1 0 0>, <4 0xa2 0 0>, <4 0xa3 0 0>; + interrupt-controller; + #interrupt-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pm8841_default>; From patchwork Fri Oct 8 01:25:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12544007 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EBCD7C43219 for ; Fri, 8 Oct 2021 01:25:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D294361371 for ; Fri, 8 Oct 2021 01:25:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242053AbhJHB1q (ORCPT ); Thu, 7 Oct 2021 21:27:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38880 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241740AbhJHB1n (ORCPT ); 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Thu, 07 Oct 2021 18:25:39 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Linus Walleij , Rob Herring Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v3 18/25] ARM: dts: qcom-apq8064: add interrupt controller properties Date: Fri, 8 Oct 2021 04:25:17 +0300 Message-Id: <20211008012524.481877-19-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211008012524.481877-1-dmitry.baryshkov@linaro.org> References: <20211008012524.481877-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Now that the pmic-mpp is a proper hierarchical IRQ chip, add interrupt controller properties ('interrupt-controller' and '#interrupt-cells'). The interrupts property is no longer needed so remove it. Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom-apq8064.dtsi | 21 ++++----------------- 1 file changed, 4 insertions(+), 17 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index cbc9be8a69cd..5aebbeb5eb07 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -683,10 +683,8 @@ pm8821: pmic@1 { pm8821_mpps: mpps@50 { compatible = "qcom,pm8821-mpp", "qcom,ssbi-mpp"; reg = <0x50>; - interrupts = <24 IRQ_TYPE_NONE>, - <25 IRQ_TYPE_NONE>, - <26 IRQ_TYPE_NONE>, - <27 IRQ_TYPE_NONE>; + interrupt-controller; + #interrupt-cells = <2>; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pm8821_mpps 0 0 4>; @@ -728,19 +726,8 @@ pm8921_mpps: mpps@50 { gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pm8921_mpps 0 0 12>; - interrupts = - <128 IRQ_TYPE_NONE>, - <129 IRQ_TYPE_NONE>, - <130 IRQ_TYPE_NONE>, - <131 IRQ_TYPE_NONE>, - <132 IRQ_TYPE_NONE>, - <133 IRQ_TYPE_NONE>, - <134 IRQ_TYPE_NONE>, - <135 IRQ_TYPE_NONE>, - <136 IRQ_TYPE_NONE>, - <137 IRQ_TYPE_NONE>, - <138 IRQ_TYPE_NONE>, - <139 IRQ_TYPE_NONE>; + interrupt-controller; + #interrupt-cells = <2>; }; rtc@11d { From patchwork Fri Oct 8 01:25:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12544011 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AFCB8C10DC2 for ; Fri, 8 Oct 2021 01:25:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9495061401 for ; Fri, 8 Oct 2021 01:25:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241270AbhJHB1r (ORCPT ); Thu, 7 Oct 2021 21:27:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38844 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237830AbhJHB1n (ORCPT ); Thu, 7 Oct 2021 21:27:43 -0400 Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [IPv6:2a00:1450:4864:20::12e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 50A2FC0613EB for ; Thu, 7 Oct 2021 18:25:42 -0700 (PDT) Received: by mail-lf1-x12e.google.com with SMTP id m3so32596688lfu.2 for ; Thu, 07 Oct 2021 18:25:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1ZjqNWJNbpqp+wYhpfPdT4qYlEU1ULLxGhv3FpneW9Y=; b=MAjGzOTWzwVqMXeWy9koSr+ZsvOJydeBaNej7TfaJQ1IipAlHGpmUfBUf4i5PdwHx7 KVdxrTouGB+L8D9aiRcpDk9F3a9MaNyvOO5Uryn9vWNXRua3y4GS3puLmpe4+NJUFM8B YyvRbuhFnTtzd5WIMAX/5hHlnc3CWPW/D/3tmDlb/UJBtKoKWg5zcPlZGekcA5S5kbGL AScuarz5ZALDY6pvdkmaXWBwo2zAe1JFOddgZ4xqqdgttzhOy/S+oFlvtIUG/4bwrWAa NhEDM5bczmzlKMuXGQLfNT/zKqTf2qt9S356jU5uWj4J5L63g7fF5HG+Jv+uZ0lxqOZH GBjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1ZjqNWJNbpqp+wYhpfPdT4qYlEU1ULLxGhv3FpneW9Y=; b=KsLs9uy1DIupdqi/jWdhWIaubAdbKYyRS8+rVLg/mBdAdWw9XKWJ91ZO55DURc8TgR 6WBqcxSu370lN/sCqGKdU3dLf8pCLRpqexGpRcpUgRqcFil/GaMkw7FIkST1adu9y9Ur VQfOGDxSDdWwCxvvvxHujTeKgnmJlLPI8HEDP7Hko7oiT1wGa15LZQC9lT+UdqL6AOT6 L+yn1cwe6nzexwzkqawebc93by/hAcOccfjGrdvNkfDpt2NRABFWdep+Plc11/iCE0YX 5LrB3cMsoQGm3wvN0JRAWpZeFZjvCyxMZzYISW6X9oX2/SOAeewiVgKUsgF9mEV50kqw ao5A== X-Gm-Message-State: AOAM531WZ8qMLn7GjGDi+GZPXfPucBfw13nzYjx0+A9uqQpAXjK4di36 /EWZMfmKtlWf78iUuXkuWqbskVnUcKVHUw== X-Google-Smtp-Source: ABdhPJy8JJ46Ku4Z5WPOF7x7G5kD2M7XtGFMpw+5P+qOlIFiJ2Nhw5VGsgbNR/HtFC3Tt0rfWIE8WA== X-Received: by 2002:a2e:801a:: with SMTP id j26mr355117ljg.175.1633656340592; Thu, 07 Oct 2021 18:25:40 -0700 (PDT) Received: from umbar.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id s4sm112875ljp.115.2021.10.07.18.25.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Oct 2021 18:25:40 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Linus Walleij , Rob Herring Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v3 19/25] ARM: dts: qcom-mdm9615: add interrupt controller properties Date: Fri, 8 Oct 2021 04:25:18 +0300 Message-Id: <20211008012524.481877-20-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211008012524.481877-1-dmitry.baryshkov@linaro.org> References: <20211008012524.481877-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Now that the pmic-mpp is a proper hierarchical IRQ chip, add interrupt controller properties ('interrupt-controller' and '#interrupt-cells'). The interrupts property is no longer needed so remove it. Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom-mdm9615.dtsi | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/qcom-mdm9615.dtsi b/arch/arm/boot/dts/qcom-mdm9615.dtsi index cfff1a5706ed..6e90c5d5a050 100644 --- a/arch/arm/boot/dts/qcom-mdm9615.dtsi +++ b/arch/arm/boot/dts/qcom-mdm9615.dtsi @@ -302,13 +302,8 @@ pwrkey@1c { pmicmpp: mpps@50 { compatible = "qcom,pm8018-mpp", "qcom,ssbi-mpp"; - interrupt-parent = <&pmicintc>; - interrupts = <24 IRQ_TYPE_NONE>, - <25 IRQ_TYPE_NONE>, - <26 IRQ_TYPE_NONE>, - <27 IRQ_TYPE_NONE>, - <28 IRQ_TYPE_NONE>, - <29 IRQ_TYPE_NONE>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x50>; gpio-controller; #gpio-cells = <2>; From patchwork Fri Oct 8 01:25:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12544009 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 41189C4167D for ; Fri, 8 Oct 2021 01:25:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 279DF613A7 for ; Fri, 8 Oct 2021 01:25:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242303AbhJHB1q (ORCPT ); Thu, 7 Oct 2021 21:27:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38904 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235847AbhJHB1n (ORCPT ); Thu, 7 Oct 2021 21:27:43 -0400 Received: from mail-lf1-x12b.google.com (mail-lf1-x12b.google.com [IPv6:2a00:1450:4864:20::12b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D89ECC0613EC for ; Thu, 7 Oct 2021 18:25:42 -0700 (PDT) Received: by mail-lf1-x12b.google.com with SMTP id r19so30681539lfe.10 for ; Thu, 07 Oct 2021 18:25:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tFp/7m8gryHUoq+f87cJCv5Sr9eZMzxJXjwT80w0C30=; b=Tv3hh4qqM6YTzNxLirtrWtJHI2KZWlyziAvAo2x1Fn3mC4o1c/5cqgcDqUEXyEQQfb n/Szj1rkAiH8cT3FlLrbP8mtb36kowJku+OJ9erYxIufpJWBkq8mrtnrFQfy0LELDS+C lMI477cQ3HGoiA9xkVim8SJ3v18Cm7F4GREaj/vyT/IASXUDKtw/EYhyy6qC4zRj2Oss JVVTnWOhPm/O1KhDx58klUyBmaDKvg5lRc2NyLcY1BxfrKdqgRvx1rQP6UNAky76k1Sp qu4hSre2FwLEKmdpEAIMDfWmf5sv9vaJ5GTsxRw1jrD63zb13EXBbCqce3xYIatOUxJd g+aQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tFp/7m8gryHUoq+f87cJCv5Sr9eZMzxJXjwT80w0C30=; b=fVEfbyDDfAzy8eWoIIdoFCEl2hE2+CLgOz3qkDJTo3Guxu0Vnb+uSzgCBKlsTSMjIm l6joHSHx9rk4ZQk4GP77Zj23g9vLOltEcWNSBFRXaOIG4BbqcP70pZ8g0eYVVzK+OrrQ uWm22GFa5xyrVhJJglgnF1S6xXnSQQ8IjO35A2hdFVT4YWWM1UNUZo4WKT/THE9ozNlt QFAiwTNKW4Kdg/PNJM0frCyS+idzPBvvU+d/bOKFjZSR5lFgCNEbSehrIW/Vjhryd6// ezMfeAxmQbDbyBKzR322fPZyuV2+aOjdsFCnN5t8I8tKrIZfCT/Tw6Tf2xggqPq5qvaY 3knA== X-Gm-Message-State: AOAM5308b0SCHCsCU/bFnL0lXEePugg/h5nRrOhr5HK7wCahyL02wjKE d/bGb2d8Vrdm3+kRAenmsf5DZw== X-Google-Smtp-Source: ABdhPJxV89e0kPC/Tpiw58wNVSg5OAz1aGgdQw/L7qiP9anRB9rkUCO885Gbxkb09xyCwG4mUKPH/g== X-Received: by 2002:a2e:a5c8:: with SMTP id n8mr345526ljp.367.1633656341223; Thu, 07 Oct 2021 18:25:41 -0700 (PDT) Received: from umbar.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id s4sm112875ljp.115.2021.10.07.18.25.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Oct 2021 18:25:40 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Linus Walleij , Rob Herring Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v3 20/25] ARM: dts: qcom-msm8660: add interrupt controller properties Date: Fri, 8 Oct 2021 04:25:19 +0300 Message-Id: <20211008012524.481877-21-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211008012524.481877-1-dmitry.baryshkov@linaro.org> References: <20211008012524.481877-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Now that the pmic-mpp is a proper hierarchical IRQ chip, add interrupt controller properties ('interrupt-controller' and '#interrupt-cells'). The interrupts property is no longer needed so remove it. Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom-msm8660.dtsi | 16 ++-------------- 1 file changed, 2 insertions(+), 14 deletions(-) diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi index d404d386d392..21cb58ab68ac 100644 --- a/arch/arm/boot/dts/qcom-msm8660.dtsi +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi @@ -308,20 +308,8 @@ pm8058_mpps: mpps@50 { gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pm8058_mpps 0 0 12>; - interrupt-parent = <&pm8058>; - interrupts = - <128 IRQ_TYPE_NONE>, - <129 IRQ_TYPE_NONE>, - <130 IRQ_TYPE_NONE>, - <131 IRQ_TYPE_NONE>, - <132 IRQ_TYPE_NONE>, - <133 IRQ_TYPE_NONE>, - <134 IRQ_TYPE_NONE>, - <135 IRQ_TYPE_NONE>, - <136 IRQ_TYPE_NONE>, - <137 IRQ_TYPE_NONE>, - <138 IRQ_TYPE_NONE>, - <139 IRQ_TYPE_NONE>; + interrupt-controller; + #interrupt-cells = <2>; }; pwrkey@1c { From patchwork Fri Oct 8 01:25:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12544013 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8DA81C10DCE for ; Fri, 8 Oct 2021 01:25:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7824C61401 for ; Fri, 8 Oct 2021 01:25:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241740AbhJHB1s (ORCPT ); Thu, 7 Oct 2021 21:27:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38916 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241321AbhJHB1o (ORCPT ); Thu, 7 Oct 2021 21:27:44 -0400 Received: from mail-lf1-x129.google.com (mail-lf1-x129.google.com [IPv6:2a00:1450:4864:20::129]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7EF6EC061787 for ; Thu, 7 Oct 2021 18:25:43 -0700 (PDT) Received: by mail-lf1-x129.google.com with SMTP id u18so32213871lfd.12 for ; Thu, 07 Oct 2021 18:25:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=N1AtEgs0cni74U+0HJfUmBYJcZUYOvYv6UrqXbEKgM8=; b=OYTGVh+9G0muxWDccBLrHPtwBPfucZTxBH4t4eZ9mohV21BXeZ2ZO3gaghlFfAWPmb SuHsvOKIuNoVvgV/f/7FgwZbpSIa7FVvRjblsn58Ulvs/D0bfZww3zyFGn60Iw4+lmYf B18MYxzprcS3oLeaJHEhsNv0oU8Fn0QAL2l01okbysqhCxI8Kjn1WKSQ0Ku1QfTzh865 OC6jaFiNl3oyJ5Y+zZlcU/0otipEtjsCzavroELWw1dFC55nWlatMwztBGQsozMXqJDq TRG1MMhkeDspJQRDneNgEpRuQl2SQC4ilTMUc9zkqs9Wng/Xk2g5wboTbkzMP9EekvZs BbhQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=N1AtEgs0cni74U+0HJfUmBYJcZUYOvYv6UrqXbEKgM8=; b=CoODZlCguQu/u+BrMsKas17adqgBgRriPKmcfZW8meQPAVsbI8hN4+yBnXK+FhJqYW Wos2t/lQ7KQPHZ0lpblrBdVm0BnxU6oS2vkhjK9JXIK5Ipll72i1wcfWqbYViDGsum/9 cIPooMLZSBmgO5IQ1cx5xRia74ONT1H8CS4VRXfR8dFNHdpfR1Lex/GUhz5jUhT3BUcY AubtYaA/tpXgwfbdb/lwYFRz53ymkufJQZXXn1d+NezjY7gRw18wrV/EOZbNhuAHpQRR pZ3rSHRAajBsaOJJOTWh1kI+h4HgSV5M1QPB+c3K7J6cxwJUxQP1AIR657aatXwzXD4L fm0Q== X-Gm-Message-State: AOAM5333TCmWi+fhxuvVSGAfy9i9KWFuweboyBcinG+km7f0eIgpLsY1 jJJ6k/gzv6d1Z46x+mSnEEyS4g== X-Google-Smtp-Source: ABdhPJyJIuqxAvjXmvZDZfKOHMAd9yuOmhUqNf+HS/0CpfhKzpcScKzEf+aedI0feSWThIQ5JnfjEw== X-Received: by 2002:a05:6512:3d91:: with SMTP id k17mr7153008lfv.430.1633656341842; Thu, 07 Oct 2021 18:25:41 -0700 (PDT) Received: from umbar.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id s4sm112875ljp.115.2021.10.07.18.25.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Oct 2021 18:25:41 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Linus Walleij , Rob Herring Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v3 21/25] ARM: dts: qcom-pm8841: add interrupt controller properties Date: Fri, 8 Oct 2021 04:25:20 +0300 Message-Id: <20211008012524.481877-22-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211008012524.481877-1-dmitry.baryshkov@linaro.org> References: <20211008012524.481877-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Now that the pmic-mpp is a proper hierarchical IRQ chip, add interrupt controller properties ('interrupt-controller' and '#interrupt-cells'). The interrupts property is no longer needed so remove it. Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom-pm8841.dtsi | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/qcom-pm8841.dtsi b/arch/arm/boot/dts/qcom-pm8841.dtsi index b6066c27732c..2caf71eacb52 100644 --- a/arch/arm/boot/dts/qcom-pm8841.dtsi +++ b/arch/arm/boot/dts/qcom-pm8841.dtsi @@ -16,10 +16,8 @@ pm8841_mpps: mpps@a000 { gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pm8841_mpps 0 0 4>; - interrupts = <4 0xa0 0 IRQ_TYPE_NONE>, - <4 0xa1 0 IRQ_TYPE_NONE>, - <4 0xa2 0 IRQ_TYPE_NONE>, - <4 0xa3 0 IRQ_TYPE_NONE>; + interrupt-controller; + #interrupt-cells = <2>; }; temp-alarm@2400 { From patchwork Fri Oct 8 01:25:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12544019 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5AAADC07EBE for ; Fri, 8 Oct 2021 01:25:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3C4D861529 for ; Fri, 8 Oct 2021 01:25:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236670AbhJHB1u (ORCPT ); Thu, 7 Oct 2021 21:27:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38912 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241994AbhJHB1o (ORCPT ); Thu, 7 Oct 2021 21:27:44 -0400 Received: from mail-lf1-x12a.google.com (mail-lf1-x12a.google.com [IPv6:2a00:1450:4864:20::12a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 399AAC06178C for ; Thu, 7 Oct 2021 18:25:44 -0700 (PDT) Received: by mail-lf1-x12a.google.com with SMTP id m3so32596873lfu.2 for ; Thu, 07 Oct 2021 18:25:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=b0AQXKDQSfjbcdAy/YvhgqCZpI+nhwsFNhGswrbVvuY=; b=IqLbkhJJpNoLsuzCSuQKOqEqDE5uEQm9LmTxRYSVk5AjxAnCdcwJN2saHs67cHAqhD NN/5N4QtCVwaP8V+khw5Veg9lQsxSKZ8RgtWNUNQVaLTdFpVPfKvzULB3u/WpY0d8FwI XEIOUPqkXDsvRbOLrGk9ZsMf1rFr9nH5mSpQ+jOMPAtAXfeAtmGqmv95KfYFj4pFMWyW mzEvgDpa31yiY6OMmSXy1hBYivqznGrGW3vixms5FZqHVIo0pVNPBrROwoXXUHIcIf+u a6LQnGhHJdYLFPF2/+kttysBegZxw4SKWQsy0jOFbHmGuUr9aBbpmbh7W9z0F9XmKqdK BdUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=b0AQXKDQSfjbcdAy/YvhgqCZpI+nhwsFNhGswrbVvuY=; b=heJKZa1pqdbeEwmmzWxPPlBbQC85K8htdB586j6Oyxt0MOruzIEWaMO06uSZ6qyO4j XwdvToz3B+OE50ttoYfWSAWlQdkctfBV6fB0qkh3oQuHKW2RUPjpxpkUD0zLPVhVfRgC rKt0ERwWLwRrVEvAVd3DCBbss3wWBgnv/kUZJf5S7sNTWPyBS2sbjFUWxsHl8E7xtTgu 85tVCRs/QYQvMK3U39OxOkb+/Pi7SgDSvn/D6/JkjYZwKQGBw1Jej5+2v+z+R92c8W8Z 4FhdHMapg170B5EDpPoOvaykSE+iyXsHSss0W6jTlTnf+3sR0SmLeyRuGpKWMOxzCwTS CSIQ== X-Gm-Message-State: AOAM531MkF52qxKN/uvHrM3cQZZgF3lm/mLhr1nU1wcV3hdhTs0+EkKp BLfr0NXDUutCGEGsRZPvmdR9jg== X-Google-Smtp-Source: ABdhPJzN85IyNLdhj7zFxPrE11ApOac+wYFWSm7ukucmYOtwGb+S4pYLo4Mb+JYtDKPys1ZeNH5RWQ== X-Received: by 2002:a05:651c:179a:: with SMTP id bn26mr361065ljb.528.1633656342577; Thu, 07 Oct 2021 18:25:42 -0700 (PDT) Received: from umbar.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id s4sm112875ljp.115.2021.10.07.18.25.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Oct 2021 18:25:42 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Linus Walleij , Rob Herring Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v3 22/25] ARM: dts: qcom-pm8941: add interrupt controller properties Date: Fri, 8 Oct 2021 04:25:21 +0300 Message-Id: <20211008012524.481877-23-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211008012524.481877-1-dmitry.baryshkov@linaro.org> References: <20211008012524.481877-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Now that the pmic-mpp is a proper hierarchical IRQ chip, add interrupt controller properties ('interrupt-controller' and '#interrupt-cells'). The interrupts property is no longer needed so remove it. Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom-pm8941.dtsi | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/qcom-pm8941.dtsi b/arch/arm/boot/dts/qcom-pm8941.dtsi index cf8daa2fe144..da00b8f5eecd 100644 --- a/arch/arm/boot/dts/qcom-pm8941.dtsi +++ b/arch/arm/boot/dts/qcom-pm8941.dtsi @@ -80,14 +80,8 @@ pm8941_mpps: mpps@a000 { gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pm8941_mpps 0 0 8>; - interrupts = <0 0xa0 0 IRQ_TYPE_NONE>, - <0 0xa1 0 IRQ_TYPE_NONE>, - <0 0xa2 0 IRQ_TYPE_NONE>, - <0 0xa3 0 IRQ_TYPE_NONE>, - <0 0xa4 0 IRQ_TYPE_NONE>, - <0 0xa5 0 IRQ_TYPE_NONE>, - <0 0xa6 0 IRQ_TYPE_NONE>, - <0 0xa7 0 IRQ_TYPE_NONE>; + interrupt-controller; + #interrupt-cells = <2>; }; pm8941_temp: temp-alarm@2400 { From patchwork Fri Oct 8 01:25:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12544017 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3D43C10F04 for ; Fri, 8 Oct 2021 01:25:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CF5946138B for ; Fri, 8 Oct 2021 01:25:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241550AbhJHB1v (ORCPT ); Thu, 7 Oct 2021 21:27:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38938 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241462AbhJHB1p (ORCPT ); Thu, 7 Oct 2021 21:27:45 -0400 Received: from mail-lf1-x12d.google.com (mail-lf1-x12d.google.com [IPv6:2a00:1450:4864:20::12d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C4D13C061797 for ; Thu, 7 Oct 2021 18:25:44 -0700 (PDT) Received: by mail-lf1-x12d.google.com with SMTP id y15so32490280lfk.7 for ; Thu, 07 Oct 2021 18:25:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Rl9lijE101nkKuIfXUJz0J1rHJh3GLfZMfhSeNFX708=; b=RqlG/JjJd4k29AASlqtoXzQdegQ0a+3xdtSbdEq2jABLdJiJaTOPLfdbL2hg5zeh1q tvqA0mTagWvk+CgCwwy9JflMkCoMMuEfiRgTNS2XB7vvxC3K+6wiN2Fly9hgUuftn81X hzDnI3lYjjRl4zHnA54MjRBpwRdSYfMteOA/csqMl9NYyjlia8hpQqPv27vymwS2/NkR YtZe2N1qzBfB9bz1JXoi56SttGU+c17/IOMNt2/AxEBrUpKnVbVpW8VKNLzJ6EORbpP5 BMEy7EWgqduLwEV7z9R+mgzAV4ZLuhzKMt1bxa5E/JRh2kiYssGs28Zuy1kF+UZqaJn8 A/Zg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Rl9lijE101nkKuIfXUJz0J1rHJh3GLfZMfhSeNFX708=; b=PPaEeZU5fTDp8bWXGEnLkVItx+9x4ZxjcWH8b2uvHSjlSr6h1tNfM0q8bvaKA6aUi0 7IfdkiAD872ngFCKwHztYyxeqcFHX3qxkMKNj+4Btzr1thHGVZDWtiErj1n550R/j1oP d4Lo18hE61+lCOuWKsESDsRu5SOmZoORwkC+78cSrTsKL03Ob+1N0m99KK+sCynbnfHM I6I5u1LjyLEtIDKUGNfYdrHQlBekL5iqIYCha3/JXwux5QXREiNDvQmycojyn3UazDz0 YC6SfRKfOLfYUygolOKboKJEqaKvALb/0eZx9gqNIPhPmH1etmBH4pDJzjt1Sh1pU9or HK9g== X-Gm-Message-State: AOAM531pAxasErte23Aj+5Oue9O61onMsZQLSrpCEmeT3z6xaL/JnIyh 5Q7brxftUr9lZ6dzaiNgHQMwXA== X-Google-Smtp-Source: ABdhPJwYedEG9raGpnqEQa5sN24WwYPUWIJfrGHPF+D4q72rJZ1gE6oyy5xY0MS755aA2Xr2hRduLA== X-Received: by 2002:a05:651c:905:: with SMTP id e5mr325945ljq.361.1633656343167; Thu, 07 Oct 2021 18:25:43 -0700 (PDT) Received: from umbar.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id s4sm112875ljp.115.2021.10.07.18.25.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Oct 2021 18:25:42 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Linus Walleij , Rob Herring Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v3 23/25] ARM: dts: qcom-pma8084: add interrupt controller properties Date: Fri, 8 Oct 2021 04:25:22 +0300 Message-Id: <20211008012524.481877-24-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211008012524.481877-1-dmitry.baryshkov@linaro.org> References: <20211008012524.481877-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Now that the pmic-mpp is a proper hierarchical IRQ chip, add interrupt controller properties ('interrupt-controller' and '#interrupt-cells'). The interrupts property is no longer needed so remove it. Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom-pma8084.dtsi | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/qcom-pma8084.dtsi b/arch/arm/boot/dts/qcom-pma8084.dtsi index fcee2afe6740..7b8a8d9695da 100644 --- a/arch/arm/boot/dts/qcom-pma8084.dtsi +++ b/arch/arm/boot/dts/qcom-pma8084.dtsi @@ -43,14 +43,8 @@ pma8084_mpps: mpps@a000 { gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pma8084_mpps 0 0 8>; - interrupts = <0 0xa0 0 IRQ_TYPE_NONE>, - <0 0xa1 0 IRQ_TYPE_NONE>, - <0 0xa2 0 IRQ_TYPE_NONE>, - <0 0xa3 0 IRQ_TYPE_NONE>, - <0 0xa4 0 IRQ_TYPE_NONE>, - <0 0xa5 0 IRQ_TYPE_NONE>, - <0 0xa6 0 IRQ_TYPE_NONE>, - <0 0xa7 0 IRQ_TYPE_NONE>; + interrupt-controller; + #interrupt-cells = <2>; }; pma8084_temp: temp-alarm@2400 { From patchwork Fri Oct 8 01:25:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12544015 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BA250C07EBB for ; Fri, 8 Oct 2021 01:25:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9FDE4613A9 for ; Fri, 8 Oct 2021 01:25:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229529AbhJHB1s (ORCPT ); Thu, 7 Oct 2021 21:27:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38942 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239238AbhJHB1p (ORCPT ); Thu, 7 Oct 2021 21:27:45 -0400 Received: from mail-lf1-x134.google.com (mail-lf1-x134.google.com [IPv6:2a00:1450:4864:20::134]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 77B66C061772 for ; Thu, 7 Oct 2021 18:25:45 -0700 (PDT) Received: by mail-lf1-x134.google.com with SMTP id y26so32781696lfa.11 for ; Thu, 07 Oct 2021 18:25:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=eRXNWHuPd38vN0RWOcJ4q4RHGL96UR0p/zcT0YWhKTU=; b=sXE/eokBQnk60sMw5lWBy7jhROc6GuZGLiOdTuXJ6YRADlfelKLdAijTh9GVCPCPh9 X5f2UvW6CMDzqkGyBaA9E/pTjKqxOqXMaBnJxiqkNzCbxnSv/Qi90sD6fjN01SjI6Ldc qsMqDtoHT8VswmMd01z3Fds+in+YbSjA7wV9WQ54W+GQTebOsi+sPuVkd8A+cJPmOk+P Y73mGGD7ec2z/tQZ7Y37BZL0qtVEdH/yZSRVbt0SipTEeINgPdG4bejlX52XxBhvGfaQ 0fKpH7N6iTh9+0L9LmgAHaxtjhwUI6zEYcLsu5Jc/cLnGF+RbHn7MoRLSBQkMFcNorgA NIng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eRXNWHuPd38vN0RWOcJ4q4RHGL96UR0p/zcT0YWhKTU=; b=2AdYIlkxFctKi0yAJUVH+J466mtWW9QvF6pxZXm2fU5N2A+IRwxRzExUqr+laLGeqM e1JPAGTO1vdGqjSeYKS/7OzDhhs9oaZehQyzRaP2qF0OIPCTU84EX/o7/fIBEZIRCOdp PSVVrMJjgXlBJwIxexm+ioYpgB4QlAfpsbImH1UH9+3Ee4PrqHnDZGSy92X7NC9Xv6e+ aiWyoZDpyQsubK8rFin3y0AzgoY387gXBtzpcXRAVx8qbJuo7ohvfAENBkALRxxT9B5t 2kiH1XcmTyz2Q73CnTiOelpPs+Ue+xaNsK3PnBDo+kP3wP9EZEVopNL5DM+UfJNqCDKH rSJQ== X-Gm-Message-State: AOAM533dQ3Jd96pUntxDWlXUVULRkXq4d3G18NQOQmMkPfaoAMECA7GO c9kvso572AytygP9FizheQcSXQ== X-Google-Smtp-Source: ABdhPJzdwYYOHak+ok2LG8aFPMRytg1r0MqaPHeikvw5/pVuEW0puGgbKabv9hmR2usFiGg0yJHryQ== X-Received: by 2002:ac2:54a6:: with SMTP id w6mr7407261lfk.61.1633656343905; Thu, 07 Oct 2021 18:25:43 -0700 (PDT) Received: from umbar.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id s4sm112875ljp.115.2021.10.07.18.25.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Oct 2021 18:25:43 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Linus Walleij , Rob Herring Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v3 24/25] arm64: dts: qcom: pm8916: add interrupt controller properties Date: Fri, 8 Oct 2021 04:25:23 +0300 Message-Id: <20211008012524.481877-25-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211008012524.481877-1-dmitry.baryshkov@linaro.org> References: <20211008012524.481877-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Now that the pmic-mpp is a proper hierarchical IRQ chip, add interrupt controller properties ('interrupt-controller' and '#interrupt-cells'). The interrupts property is no longer needed so remove it. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/pm8916.dtsi | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/pm8916.dtsi b/arch/arm64/boot/dts/qcom/pm8916.dtsi index 7d9e25dd9e3a..55a386d05809 100644 --- a/arch/arm64/boot/dts/qcom/pm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8916.dtsi @@ -96,10 +96,8 @@ pm8916_mpps: mpps@a000 { gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pm8916_mpps 0 0 4>; - interrupts = <0 0xa0 0 IRQ_TYPE_NONE>, - <0 0xa1 0 IRQ_TYPE_NONE>, - <0 0xa2 0 IRQ_TYPE_NONE>, - <0 0xa3 0 IRQ_TYPE_NONE>; + interrupt-controller; + #interrupt-cells = <2>; }; pm8916_gpios: gpios@c000 { From patchwork Fri Oct 8 01:25:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12544021 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 86E65C10DC1 for ; Fri, 8 Oct 2021 01:25:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6AB76613D5 for ; Fri, 8 Oct 2021 01:25:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242269AbhJHB1v (ORCPT ); Thu, 7 Oct 2021 21:27:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38918 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242147AbhJHB1q (ORCPT ); Thu, 7 Oct 2021 21:27:46 -0400 Received: from mail-lf1-x12f.google.com (mail-lf1-x12f.google.com [IPv6:2a00:1450:4864:20::12f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3B9F7C0617AA for ; Thu, 7 Oct 2021 18:25:46 -0700 (PDT) Received: by mail-lf1-x12f.google.com with SMTP id j5so32413955lfg.8 for ; Thu, 07 Oct 2021 18:25:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KFilYJCf+KpWxQtdiRPdV9UvPSg+EjF5wR3x+/r1PaM=; b=b8Kp3IwxAUvtNck1lwmE1eCa2D0sGIsH53MbErRUDrC2x71IDEeSO3vr05y1QVRK4N XakZEvxTVTCJoW6tMZBIYBX/OG+JhezlK5lWV5NOdoQHGX0+rTsfhWvBNBnaVCuW9AyW Zz7ecnwkpFi50/0o52sev5frAGtUqJVwgnOltDFcGy8uO1SJyMd4kfeG1+IcmeaP7Umw XGa+so+3NFhLAaR8YhR6IxjuVSBBRKOw6zjWJnPgHtdJ5cIqNZJLYcPv0WZprgJAD6R5 +6R0XY03fdtOtAGn7S0VZZBkahD0uahB29LjDZlkHKfMFmERBxl4Zx4rsrZ8IpToiGg9 5MHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KFilYJCf+KpWxQtdiRPdV9UvPSg+EjF5wR3x+/r1PaM=; b=gODM3KzGw1RBfQb1Detfud8r4ndcWszZiW6msdGMPP+MrGGxBUXZhDhPwNSsmGisLT Sp8ly9AsQGEK58Mjd7lXuVMYrmdINNIBftuLHo9IdETAUXoz1vUqfkxt9XQ+xqHI8Kep RMZb+2Xb7FrWjE4Gw7zjNZZNafeFi7y6MUBBmgjw4v6nz7SBTWPN8a1BB+ejiGjM+cHv GhyQqs0JLF1a2A9m9ygxIYsza/NrkRysCfLGyv8moy2cGpYCodMoyNoiSWr+35/S/yD5 vsIgVpMjrDr4sin93XxKJE17D8P1vDjnNX36dQeovjcbHCjMO0uBufnpZuk+2b0jJn6t Iq0w== X-Gm-Message-State: AOAM530+cogE81h2IEKO22kFJJFm74UWgXtGlE6/I0skkCMU+Wn3U/25 fIdo2KM3Zhyixrh2AIJZBSoVVw== X-Google-Smtp-Source: ABdhPJxOJu2O2CcCiy90VFNaP0Nc8PeIaVHfboDJZJSdT8OBJFAdj/N6EY6pIN9ZkS0YixLqBwRILA== X-Received: by 2002:a2e:5702:: with SMTP id l2mr373823ljb.370.1633656344600; Thu, 07 Oct 2021 18:25:44 -0700 (PDT) Received: from umbar.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id s4sm112875ljp.115.2021.10.07.18.25.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Oct 2021 18:25:44 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Linus Walleij , Rob Herring Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v3 25/25] arm64: dts: qcom: pm8994: add interrupt controller properties Date: Fri, 8 Oct 2021 04:25:24 +0300 Message-Id: <20211008012524.481877-26-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211008012524.481877-1-dmitry.baryshkov@linaro.org> References: <20211008012524.481877-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Now that the pmic-mpp is a proper hierarchical IRQ chip, add interrupt controller properties ('interrupt-controller' and '#interrupt-cells'). The interrupts property is no longer needed so remove it. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/pm8994.dtsi | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/pm8994.dtsi b/arch/arm64/boot/dts/qcom/pm8994.dtsi index 88a9d19b60ac..5ab46117d737 100644 --- a/arch/arm64/boot/dts/qcom/pm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8994.dtsi @@ -124,14 +124,8 @@ pm8994_mpps: mpps@a000 { gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pm8994_mpps 0 0 8>; - interrupts = <0 0xa0 0 IRQ_TYPE_NONE>, - <0 0xa1 0 IRQ_TYPE_NONE>, - <0 0xa2 0 IRQ_TYPE_NONE>, - <0 0xa3 0 IRQ_TYPE_NONE>, - <0 0xa4 0 IRQ_TYPE_NONE>, - <0 0xa5 0 IRQ_TYPE_NONE>, - <0 0xa6 0 IRQ_TYPE_NONE>, - <0 0xa7 0 IRQ_TYPE_NONE>; + interrupt-controller; + #interrupt-cells = <2>; }; };